v0                 33 arch/alpha/include/asm/mmu_context.h 	register unsigned long v0 __asm__("$0");
v0                 38 arch/alpha/include/asm/mmu_context.h 		: "=r"(v0), "=r"(a0)
v0                 42 arch/alpha/include/asm/mmu_context.h 	return v0;
v0                123 arch/alpha/include/asm/pal.h 	register unsigned long v0 __asm__("$0");
v0                127 arch/alpha/include/asm/pal.h 	    : "=r"(v0), "+r"(a0)
v0                131 arch/alpha/include/asm/pal.h 	return v0;
v0                137 arch/alpha/include/asm/pal.h 	register unsigned long v0 __asm__("$0");
v0                141 arch/alpha/include/asm/pal.h 	    : "=r"(v0), "+r"(a0)
v0                145 arch/alpha/include/asm/pal.h 	return v0;
v0                175 arch/alpha/include/asm/pal.h 	register unsigned long v0 __asm__("$0");
v0                179 arch/alpha/include/asm/pal.h 	    : "=r"(v0), "+r"(a0)
v0                183 arch/alpha/include/asm/pal.h 	return v0;
v0                 19 arch/arm64/lib/xor-neon.c 	register uint64x2_t v0, v1, v2, v3;
v0                 24 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(vld1q_u64(dp1 +  0), vld1q_u64(dp2 +  0));
v0                 30 arch/arm64/lib/xor-neon.c 		vst1q_u64(dp1 +  0, v0);
v0                 47 arch/arm64/lib/xor-neon.c 	register uint64x2_t v0, v1, v2, v3;
v0                 52 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(vld1q_u64(dp1 +  0), vld1q_u64(dp2 +  0));
v0                 58 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(v0, vld1q_u64(dp3 +  0));
v0                 64 arch/arm64/lib/xor-neon.c 		vst1q_u64(dp1 +  0, v0);
v0                 83 arch/arm64/lib/xor-neon.c 	register uint64x2_t v0, v1, v2, v3;
v0                 88 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(vld1q_u64(dp1 +  0), vld1q_u64(dp2 +  0));
v0                 94 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(v0, vld1q_u64(dp3 +  0));
v0                100 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(v0, vld1q_u64(dp4 +  0));
v0                106 arch/arm64/lib/xor-neon.c 		vst1q_u64(dp1 +  0, v0);
v0                128 arch/arm64/lib/xor-neon.c 	register uint64x2_t v0, v1, v2, v3;
v0                133 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(vld1q_u64(dp1 +  0), vld1q_u64(dp2 +  0));
v0                139 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(v0, vld1q_u64(dp3 +  0));
v0                145 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(v0, vld1q_u64(dp4 +  0));
v0                151 arch/arm64/lib/xor-neon.c 		v0 = veorq_u64(v0, vld1q_u64(dp5 +  0));
v0                157 arch/arm64/lib/xor-neon.c 		vst1q_u64(dp1 +  0, v0);
v0                781 arch/ia64/include/asm/pal.h 	u64 v0;
v0                889 arch/ia64/include/asm/pal.h 		features_avail->pal_bus_features_val = iprv.v0;
v0                916 arch/ia64/include/asm/pal.h 		conf->pcci_info_1.pcci1_data      = iprv.v0;
v0                934 arch/ia64/include/asm/pal.h 		prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
v0                935 arch/ia64/include/asm/pal.h 		prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
v0                954 arch/ia64/include/asm/pal.h 		*vector = iprv.v0;
v0                999 arch/ia64/include/asm/pal.h 		*cache_levels = iprv.v0;
v0               1024 arch/ia64/include/asm/pal.h 		*buffer_size = iprv.v0;
v0               1037 arch/ia64/include/asm/pal.h 		*pal_proc_offset = iprv.v0;
v0               1048 arch/ia64/include/asm/pal.h 		*inst_regs = iprv.v0;
v0               1073 arch/ia64/include/asm/pal.h 		*global_unique_addr = iprv.v0;
v0               1083 arch/ia64/include/asm/pal.h 		*platform_base_freq = iprv.v0;
v0               1098 arch/ia64/include/asm/pal.h 		*(u64 *)proc_ratio = iprv.v0;
v0               1116 arch/ia64/include/asm/pal.h 		*cur_policy = iprv.v0;
v0               1163 arch/ia64/include/asm/pal.h 	*pstate_index = iprv.v0;
v0               1206 arch/ia64/include/asm/pal.h 		*pending_vector = iprv.v0;
v0               1228 arch/ia64/include/asm/pal.h 		*size = iprv.v0;
v0               1239 arch/ia64/include/asm/pal.h 		*size = iprv.v0;
v0               1256 arch/ia64/include/asm/pal.h 		*capabilities= iprv.v0;
v0               1270 arch/ia64/include/asm/pal.h 		*capabilities= iprv.v0;
v0               1285 arch/ia64/include/asm/pal.h 		*previous = iprv.v0;
v0               1309 arch/ia64/include/asm/pal.h 		*status = iprv.v0;
v0               1323 arch/ia64/include/asm/pal.h 		*req_size = iprv.v0;
v0               1345 arch/ia64/include/asm/pal.h 		*mem_attrib = iprv.v0 & 0xff;
v0               1358 arch/ia64/include/asm/pal.h 		*bytes_needed = iprv.v0;
v0               1384 arch/ia64/include/asm/pal.h 		pm_info->ppmi_data = iprv.v0;
v0               1419 arch/ia64/include/asm/pal.h 		*features_avail   = iprv.v0;
v0               1458 arch/ia64/include/asm/pal.h 		ptce->base = iprv.v0;
v0               1474 arch/ia64/include/asm/pal.h 		*reg_info_1 = iprv.v0;
v0               1498 arch/ia64/include/asm/pal.h 		*num_phys_stacked = iprv.v0;
v0               1534 arch/ia64/include/asm/pal.h 		*self_test_state = iprv.v0;
v0               1564 arch/ia64/include/asm/pal.h 		pal_min_version->pal_version_val = iprv.v0;
v0               1602 arch/ia64/include/asm/pal.h 		tc_info->pti_val = iprv.v0;
v0               1616 arch/ia64/include/asm/pal.h 		*tr_pages = iprv.v0;
v0               1658 arch/ia64/include/asm/pal.h 		vm_info_1->pvi1_val = iprv.v0;
v0               1681 arch/ia64/include/asm/pal.h 		*vp_info = iprv.v0;
v0               1705 arch/ia64/include/asm/pal.h 		tr_valid->piv_val = iprv.v0;
v0               1790 arch/ia64/include/asm/pal.h 		mapping->overview.overview_data = iprv.v0;
v0               1817 arch/ia64/include/asm/pal.h 		info->num_shared = iprv.v0;
v0                111 arch/ia64/include/asm/sal.h 	unsigned long v0;
v0                708 arch/ia64/include/asm/sal.h 	return isrv.v0;
v0                723 arch/ia64/include/asm/sal.h 	return isrv.v0;
v0                762 arch/ia64/include/asm/sal.h 		*value = isrv.v0;
v0                816 arch/ia64/include/asm/sal.h 		*error_code = isrv.v0;
v0                833 arch/ia64/include/asm/sal.h 		*splid = isrv.v0;
v0                 55 arch/ia64/include/asm/sn/sn_sal.h 	*cookie = rv.v0;
v0               1954 arch/ia64/kernel/mca.c 				"%ld to %ld milliseconds\n", timeout, isrv.v0);
v0               1955 arch/ia64/kernel/mca.c 			timeout = isrv.v0;
v0                 47 arch/ia64/kernel/patch.c 	u64 m0, m1, v0, v1, b0, b1, *b = (u64 *) (insn_addr & -16);
v0                 58 arch/ia64/kernel/patch.c 		v0 = val  << shift; v1 = val >> (64 - shift);
v0                 59 arch/ia64/kernel/patch.c 		b[0] = (b0 & ~m0) | (v0 & m0);
v0                395 arch/ia64/kernel/sal.c 	*ticks_per_second = isrv.v0;
v0                990 arch/ia64/kernel/setup.c 			if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
v0               1592 arch/mips/cavium-octeon/octeon-irq.c 		u32 v0, v1;
v0               1594 arch/mips/cavium-octeon/octeon-irq.c 		r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v0);
v0               1604 arch/mips/cavium-octeon/octeon-irq.c 		base_hwirq = (v0 << 6) | v1;
v0                 30 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dmfc0	v0, CP0_CVMMEMCTL_REG
v0                 32 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dins	v0, $0, 0, 6
v0                 33 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	ori	v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
v0                 34 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dmtc0	v0, CP0_CVMMEMCTL_REG	# Write the cavium mem control register
v0                 35 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dmfc0	v0, CP0_CVMCTL_REG	# Read the cavium control register
v0                 38 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	or  v0, v0, 0x5001
v0                 39 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	xor v0, v0, 0x1001
v0                 43 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	and	v0, v0, v1
v0                 44 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	ori	v0, v0, (6 << 7)
v0                 64 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	or	v0, v0, 0x2000		# Set IPREF bit.
v0                 68 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dmtc0	v0, CP0_CVMCTL_REG
v0                 73 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dli	v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
v0                 74 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dsll	v0, 7
v0                 75 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	beqz	v0, 2f
v0                 76 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 1:	dsubu	v0, 8
v0                 77 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	sd	$0, -32768(v0)
v0                 78 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	bnez	v0, 1b
v0                 80 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	mfc0	v0, CP0_PRID_REG
v0                 81 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	bbit0	v0, 15, 1f
v0                 83 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	and	t1, v0, 0xff00
v0                 84 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dli	v0, 0x9500
v0                 85 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	bge	t1, v0, 1f  # OCTEON III has no DCACHE_ERR_REG COP0
v0                 86 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dli	v0, 0x27
v0                 87 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dmtc0	v0, CP0_DCACHE_ERR_REG
v0                 90 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	rdhwr	v0, $0
v0                119 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	bne t1, v0, octeon_spin_wait_boot
v0                113 arch/mips/include/asm/mach-malta/kernel-entry-init.h 	PTR_LA	v0, 0x9fc00534	/* YAMON print */
v0                114 arch/mips/include/asm/mach-malta/kernel-entry-init.h 	lw	v0, (v0)
v0                117 arch/mips/include/asm/mach-malta/kernel-entry-init.h 	jal	v0
v0                119 arch/mips/include/asm/mach-malta/kernel-entry-init.h 	PTR_LA	v0, 0x9fc00520	/* YAMON exit */
v0                120 arch/mips/include/asm/mach-malta/kernel-entry-init.h 	lw	v0, (v0)
v0                122 arch/mips/include/asm/mach-malta/kernel-entry-init.h 	jal	v0
v0                255 arch/mips/include/asm/stackframe.h 		cfi_st	v0, PT_R2, \docfi
v0                364 arch/mips/include/asm/stackframe.h 		LONG_L	v0, PT_STATUS(sp)
v0                366 arch/mips/include/asm/stackframe.h 		and	v0, v1
v0                367 arch/mips/include/asm/stackframe.h 		or	v0, a0
v0                368 arch/mips/include/asm/stackframe.h 		mtc0	v0, CP0_STATUS
v0                402 arch/mips/include/asm/stackframe.h 		LONG_L	v0, PT_STATUS(sp)
v0                404 arch/mips/include/asm/stackframe.h 		and	v0, v1
v0                405 arch/mips/include/asm/stackframe.h 		or	v0, a0
v0                406 arch/mips/include/asm/stackframe.h 		mtc0	v0, CP0_STATUS
v0                387 arch/mips/kernel/pm-cps.c 		uasm_i_jalr(&p, v0, t0);
v0                586 arch/mips/kernel/pm-cps.c 		uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
v0                 91 arch/s390/include/asm/vx-insn.h 	.ifc \vxr,%v0
v0                 94 arch/x86/platform/uv/bios_uv.c 	u64 v0, v1;
v0                 98 arch/x86/platform/uv/bios_uv.c 				(u64)(&v0), (u64)(&v1), 0, 0);
v0                102 arch/x86/platform/uv/bios_uv.c 	part.val = v0;
v0                 58 drivers/gpu/drm/msm/edp/edp.h void msm_edp_phy_vm_pe_cfg(struct edp_phy *phy, u32 v0, u32 v1);
v0                 62 drivers/gpu/drm/msm/edp/edp_phy.c void msm_edp_phy_vm_pe_cfg(struct edp_phy *phy, u32 v0, u32 v1)
v0                 64 drivers/gpu/drm/msm/edp/edp_phy.c 	edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, v0);
v0                371 drivers/gpu/drm/nouveau/nouveau_abi16.c 		struct nvif_ioctl_v0 v0;
v0                377 drivers/gpu/drm/nouveau/nouveau_abi16.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                378 drivers/gpu/drm/nouveau/nouveau_abi16.c 		switch (args->v0.type) {
v0                392 drivers/gpu/drm/nouveau/nouveau_abi16.c 	if (args->v0.token != ~0ULL) {
v0                393 drivers/gpu/drm/nouveau/nouveau_abi16.c 		if (!(chan = nouveau_abi16_chan(abi16, args->v0.token)))
v0                395 drivers/gpu/drm/nouveau/nouveau_abi16.c 		args->v0.object = nvif_handle(&chan->chan->user);
v0                396 drivers/gpu/drm/nouveau/nouveau_abi16.c 		args->v0.owner  = NVIF_IOCTL_V0_OWNER_ANY;
v0                400 drivers/gpu/drm/nouveau/nouveau_abi16.c 	args->v0.object = nvif_handle(&abi16->device.object);
v0                401 drivers/gpu/drm/nouveau/nouveau_abi16.c 	args->v0.owner  = NVIF_IOCTL_V0_OWNER_ANY;
v0                 78 drivers/gpu/drm/nouveau/nouveau_nvif.c 		struct nvif_notify_req_v0 v0;
v0                 82 drivers/gpu/drm/nouveau/nouveau_nvif.c 	if (length == sizeof(args->v0) && args->v0.version == 0) {
v0                 83 drivers/gpu/drm/nouveau/nouveau_nvif.c 		route = args->v0.route;
v0                 77 drivers/gpu/drm/nouveau/nouveau_usif.c 		struct nvif_notify_rep_v0 v0;
v0                 83 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (length == sizeof(rep->v0) && rep->v0.version == 0) {
v0                 84 drivers/gpu/drm/nouveau/nouveau_usif.c 		if (WARN_ON(!(ntfy = (void *)(unsigned long)rep->v0.token)))
v0                 86 drivers/gpu/drm/nouveau/nouveau_usif.c 		BUG_ON(rep->v0.route != NVDRM_NOTIFY_USIF);
v0                 98 drivers/gpu/drm/nouveau/nouveau_usif.c 	switch (rep->v0.version) {
v0                127 drivers/gpu/drm/nouveau/nouveau_usif.c 		struct nvif_ioctl_ntfy_new_v0 v0;
v0                130 drivers/gpu/drm/nouveau/nouveau_usif.c 		struct nvif_notify_req_v0 v0;
v0                135 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                136 drivers/gpu/drm/nouveau/nouveau_usif.c 		if (usif_notify_find(f, args->v0.index))
v0                147 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, true))) {
v0                148 drivers/gpu/drm/nouveau/nouveau_usif.c 		ntfy->reply = sizeof(struct nvif_notify_rep_v0) + req->v0.reply;
v0                149 drivers/gpu/drm/nouveau/nouveau_usif.c 		ntfy->route = req->v0.route;
v0                150 drivers/gpu/drm/nouveau/nouveau_usif.c 		ntfy->token = req->v0.token;
v0                151 drivers/gpu/drm/nouveau/nouveau_usif.c 		req->v0.route = NVDRM_NOTIFY_USIF;
v0                152 drivers/gpu/drm/nouveau/nouveau_usif.c 		req->v0.token = (unsigned long)(void *)ntfy;
v0                154 drivers/gpu/drm/nouveau/nouveau_usif.c 		req->v0.token = ntfy->token;
v0                155 drivers/gpu/drm/nouveau/nouveau_usif.c 		req->v0.route = ntfy->route;
v0                156 drivers/gpu/drm/nouveau/nouveau_usif.c 		ntfy->handle = args->v0.index;
v0                172 drivers/gpu/drm/nouveau/nouveau_usif.c 		struct nvif_ioctl_ntfy_del_v0 v0;
v0                177 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                178 drivers/gpu/drm/nouveau/nouveau_usif.c 		if (!(ntfy = usif_notify_find(f, args->v0.index)))
v0                195 drivers/gpu/drm/nouveau/nouveau_usif.c 		struct nvif_ioctl_ntfy_del_v0 v0;
v0                200 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                201 drivers/gpu/drm/nouveau/nouveau_usif.c 		if (!(ntfy = usif_notify_find(f, args->v0.index)))
v0                232 drivers/gpu/drm/nouveau/nouveau_usif.c 		struct nvif_ioctl_ntfy_put_v0 v0;
v0                237 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                238 drivers/gpu/drm/nouveau/nouveau_usif.c 		if (!(ntfy = usif_notify_find(f, args->v0.index)))
v0                269 drivers/gpu/drm/nouveau/nouveau_usif.c 		struct nvif_ioctl_new_v0 v0;
v0                278 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                279 drivers/gpu/drm/nouveau/nouveau_usif.c 		object->route = args->v0.route;
v0                280 drivers/gpu/drm/nouveau/nouveau_usif.c 		object->token = args->v0.token;
v0                281 drivers/gpu/drm/nouveau/nouveau_usif.c 		args->v0.route = NVDRM_OBJECT_USIF;
v0                282 drivers/gpu/drm/nouveau/nouveau_usif.c 		args->v0.token = (unsigned long)(void *)object;
v0                284 drivers/gpu/drm/nouveau/nouveau_usif.c 		args->v0.token = object->token;
v0                285 drivers/gpu/drm/nouveau/nouveau_usif.c 		args->v0.route = object->route;
v0                301 drivers/gpu/drm/nouveau/nouveau_usif.c 		struct nvif_ioctl_v0 v0;
v0                312 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (!(ret = nvif_unpack(-ENOSYS, &data, &size, argv->v0, 0, 0, true))) {
v0                314 drivers/gpu/drm/nouveau/nouveau_usif.c 		owner = argv->v0.owner;
v0                315 drivers/gpu/drm/nouveau/nouveau_usif.c 		if (argv->v0.object == 0ULL &&
v0                316 drivers/gpu/drm/nouveau/nouveau_usif.c 		    argv->v0.type != NVIF_IOCTL_V0_DEL)
v0                317 drivers/gpu/drm/nouveau/nouveau_usif.c 			argv->v0.owner = NVDRM_OBJECT_ANY; /* except client */
v0                319 drivers/gpu/drm/nouveau/nouveau_usif.c 			argv->v0.owner = NVDRM_OBJECT_USIF;
v0                327 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (argv->v0.route) {
v0                328 drivers/gpu/drm/nouveau/nouveau_usif.c 		if (ret = -EINVAL, argv->v0.route == 0xff)
v0                336 drivers/gpu/drm/nouveau/nouveau_usif.c 	switch (argv->v0.type) {
v0                356 drivers/gpu/drm/nouveau/nouveau_usif.c 	if (argv->v0.route == NVDRM_OBJECT_USIF) {
v0                357 drivers/gpu/drm/nouveau/nouveau_usif.c 		object = (void *)(unsigned long)argv->v0.token;
v0                358 drivers/gpu/drm/nouveau/nouveau_usif.c 		argv->v0.route = object->route;
v0                359 drivers/gpu/drm/nouveau/nouveau_usif.c 		argv->v0.token = object->token;
v0                360 drivers/gpu/drm/nouveau/nouveau_usif.c 		if (ret == 0 && argv->v0.type == NVIF_IOCTL_V0_DEL) {
v0                365 drivers/gpu/drm/nouveau/nouveau_usif.c 		argv->v0.route = NVIF_IOCTL_V0_ROUTE_HIDDEN;
v0                366 drivers/gpu/drm/nouveau/nouveau_usif.c 		argv->v0.token = 0;
v0                368 drivers/gpu/drm/nouveau/nouveau_usif.c 	argv->v0.owner = owner;
v0                116 drivers/gpu/drm/nouveau/nvif/notify.c 		struct nvif_notify_rep_v0 v0;
v0                120 drivers/gpu/drm/nouveau/nvif/notify.c 	if (length == sizeof(args->v0) && args->v0.version == 0) {
v0                121 drivers/gpu/drm/nouveau/nvif/notify.c 		if (WARN_ON(args->v0.route))
v0                123 drivers/gpu/drm/nouveau/nvif/notify.c 		notify = (void *)(unsigned long)args->v0.token;
v0                 35 drivers/gpu/drm/nouveau/nvif/object.c 		struct nvif_ioctl_v0 v0;
v0                 38 drivers/gpu/drm/nouveau/nvif/object.c 	if (size >= sizeof(*args) && args->v0.version == 0) {
v0                 40 drivers/gpu/drm/nouveau/nvif/object.c 			args->v0.object = nvif_handle(object);
v0                 42 drivers/gpu/drm/nouveau/nvif/object.c 			args->v0.object = 0;
v0                 43 drivers/gpu/drm/nouveau/nvif/object.c 		args->v0.owner = NVIF_IOCTL_V0_OWNER_ANY;
v0                 39 drivers/gpu/drm/nouveau/nvkm/core/client.c 		struct nvif_client_v0 v0;
v0                 44 drivers/gpu/drm/nouveau/nvkm/core/client.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))){
v0                 45 drivers/gpu/drm/nouveau/nvkm/core/client.c 		args->v0.name[sizeof(args->v0.name) - 1] = 0;
v0                 46 drivers/gpu/drm/nouveau/nvkm/core/client.c 		ret = nvkm_client_new(args->v0.name, args->v0.device, NULL,
v0                 77 drivers/gpu/drm/nouveau/nvkm/core/client.c 		struct nvif_notify_rep_v0 v0;
v0                134 drivers/gpu/drm/nouveau/nvkm/core/client.c 		struct nvif_notify_req_v0 v0;
v0                152 drivers/gpu/drm/nouveau/nvkm/core/client.c 	if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, true))) {
v0                154 drivers/gpu/drm/nouveau/nvkm/core/client.c 				   "token %llx\n", req->v0.version,
v0                155 drivers/gpu/drm/nouveau/nvkm/core/client.c 			   req->v0.reply, req->v0.route, req->v0.token);
v0                156 drivers/gpu/drm/nouveau/nvkm/core/client.c 		notify->version = req->v0.version;
v0                157 drivers/gpu/drm/nouveau/nvkm/core/client.c 		notify->size = sizeof(notify->rep.v0);
v0                158 drivers/gpu/drm/nouveau/nvkm/core/client.c 		notify->rep.v0.version = req->v0.version;
v0                159 drivers/gpu/drm/nouveau/nvkm/core/client.c 		notify->rep.v0.route = req->v0.route;
v0                160 drivers/gpu/drm/nouveau/nvkm/core/client.c 		notify->rep.v0.token = req->v0.token;
v0                161 drivers/gpu/drm/nouveau/nvkm/core/client.c 		reply = req->v0.reply;
v0                195 drivers/gpu/drm/nouveau/nvkm/core/client.c 		struct nvif_client_devlist_v0 v0;
v0                200 drivers/gpu/drm/nouveau/nvkm/core/client.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                202 drivers/gpu/drm/nouveau/nvkm/core/client.c 			   args->v0.version, args->v0.count);
v0                203 drivers/gpu/drm/nouveau/nvkm/core/client.c 		if (size == sizeof(args->v0.device[0]) * args->v0.count) {
v0                204 drivers/gpu/drm/nouveau/nvkm/core/client.c 			ret = nvkm_device_list(args->v0.device, args->v0.count);
v0                206 drivers/gpu/drm/nouveau/nvkm/core/client.c 				args->v0.count = ret;
v0                 36 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_nop_v0 v0;
v0                 41 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 42 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		nvif_ioctl(object, "nop vers %lld\n", args->v0.version);
v0                 43 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		args->v0.version = NVIF_VERSION_LATEST;
v0                 54 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_sclass_v0 v0;
v0                 60 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                 62 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.count);
v0                 63 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		if (size != args->v0.count * sizeof(args->v0.oclass[0]))
v0                 68 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			if (i < args->v0.count) {
v0                 69 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 				args->v0.oclass[i].oclass = oclass.base.oclass;
v0                 70 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 				args->v0.oclass[i].minver = oclass.base.minver;
v0                 71 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 				args->v0.oclass[i].maxver = oclass.base.maxver;
v0                 76 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		args->v0.count = i;
v0                 87 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_new_v0 v0;
v0                 94 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                 97 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.handle, args->v0.oclass,
v0                 98 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.route, args->v0.token, args->v0.object);
v0                109 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		oclass.handle = args->v0.handle;
v0                110 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		oclass.route  = args->v0.route;
v0                111 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		oclass.token  = args->v0.token;
v0                112 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		oclass.object = args->v0.object;
v0                118 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	} while (oclass.base.oclass != args->v0.oclass);
v0                169 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_mthd_v0 v0;
v0                174 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                176 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.method);
v0                177 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		ret = nvkm_object_mthd(object, args->v0.method, data, size);
v0                189 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_rd_v0 v0;
v0                199 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                201 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.size, args->v0.addr);
v0                202 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		switch (args->v0.size) {
v0                204 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			ret = nvkm_object_rd08(object, args->v0.addr, &v.b08);
v0                205 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			args->v0.data = v.b08;
v0                208 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			ret = nvkm_object_rd16(object, args->v0.addr, &v.b16);
v0                209 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			args->v0.data = v.b16;
v0                212 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			ret = nvkm_object_rd32(object, args->v0.addr, &v.b32);
v0                213 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			args->v0.data = v.b32;
v0                229 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_wr_v0 v0;
v0                234 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                237 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.size, args->v0.addr,
v0                238 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.data);
v0                242 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	switch (args->v0.size) {
v0                243 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	case 1: return nvkm_object_wr08(object, args->v0.addr, args->v0.data);
v0                244 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	case 2: return nvkm_object_wr16(object, args->v0.addr, args->v0.data);
v0                245 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	case 4: return nvkm_object_wr32(object, args->v0.addr, args->v0.data);
v0                258 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_map_v0 v0;
v0                264 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                265 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		nvif_ioctl(object, "map vers %d\n", args->v0.version);
v0                267 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 				      &args->v0.handle,
v0                268 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 				      &args->v0.length);
v0                270 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			args->v0.type = NVIF_IOCTL_MAP_V0_IO;
v0                272 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			args->v0.type = NVIF_IOCTL_MAP_V0_VA;
v0                301 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_ntfy_new_v0 v0;
v0                307 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                309 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.event);
v0                310 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		ret = nvkm_object_ntfy(object, args->v0.event, &event);
v0                314 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 				args->v0.index = ret;
v0                328 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_ntfy_del_v0 v0;
v0                333 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                335 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.index);
v0                336 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		ret = nvkm_client_notify_del(client, args->v0.index);
v0                347 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_ntfy_get_v0 v0;
v0                352 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                354 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.index);
v0                355 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		ret = nvkm_client_notify_get(client, args->v0.index);
v0                366 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_ntfy_put_v0 v0;
v0                371 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                373 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.index);
v0                374 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		ret = nvkm_client_notify_put(client, args->v0.index);
v0                434 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		struct nvif_ioctl_v0 v0;
v0                441 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                444 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.version, args->v0.type, args->v0.object,
v0                445 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			   args->v0.owner);
v0                446 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		ret = nvkm_ioctl_path(client, args->v0.object, args->v0.type,
v0                447 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 				      data, size, args->v0.owner,
v0                448 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 				      &args->v0.route, &args->v0.token);
v0                 38 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		struct nvif_control_pstate_info_v0 v0;
v0                 44 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 46 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 			   args->v0.version);
v0                 51 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.count = clk->state_nr;
v0                 52 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.ustate_ac = clk->ustate_ac;
v0                 53 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.ustate_dc = clk->ustate_dc;
v0                 54 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.pwrsrc = clk->pwrsrc;
v0                 55 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.pstate = clk->pstate;
v0                 57 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.count = 0;
v0                 58 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.ustate_ac = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;
v0                 59 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.ustate_dc = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;
v0                 60 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.pwrsrc = -ENOSYS;
v0                 61 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN;
v0                 71 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		struct nvif_control_pstate_attr_v0 v0;
v0                 82 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 85 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 			   args->v0.version, args->v0.state, args->v0.index);
v0                 88 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		if (args->v0.state < NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT)
v0                 90 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		if (args->v0.state >= clk->state_nr)
v0                 97 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		if (domain->mname && ++j == args->v0.index)
v0                105 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	if (args->v0.state != NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT) {
v0                107 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 			if (i++ == args->v0.state)
v0                118 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.state = pstate->pstate;
v0                124 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	snprintf(args->v0.name, sizeof(args->v0.name), "%s", domain->mname);
v0                125 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	snprintf(args->v0.unit, sizeof(args->v0.unit), "MHz");
v0                126 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	args->v0.min = lo / domain->mdiv;
v0                127 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	args->v0.max = hi / domain->mdiv;
v0                129 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	args->v0.index = 0;
v0                132 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 			args->v0.index = ++j;
v0                144 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		struct nvif_control_pstate_user_v0 v0;
v0                150 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                153 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 			   args->v0.version, args->v0.ustate, args->v0.pwrsrc);
v0                159 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	if (args->v0.pwrsrc >= 0) {
v0                160 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		ret |= nvkm_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
v0                162 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		ret |= nvkm_clk_ustate(clk, args->v0.ustate, 0);
v0                163 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		ret |= nvkm_clk_ustate(clk, args->v0.ustate, 1);
v0                110 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		struct nv_device_info_v0 v0;
v0                126 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                127 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		nvif_ioctl(object, "device info vers %d\n", args->v0.version);
v0                142 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		args->v0.platform = NV_DEVICE_INFO_V0_IGP;
v0                147 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 			args->v0.platform = NV_DEVICE_INFO_V0_PCI;
v0                150 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 			args->v0.platform = NV_DEVICE_INFO_V0_AGP;
v0                153 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 			args->v0.platform = NV_DEVICE_INFO_V0_PCIE;
v0                156 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 			args->v0.platform = NV_DEVICE_INFO_V0_SOC;
v0                166 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case NV_04: args->v0.family = NV_DEVICE_INFO_V0_TNT; break;
v0                168 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case NV_11: args->v0.family = NV_DEVICE_INFO_V0_CELSIUS; break;
v0                169 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case NV_20: args->v0.family = NV_DEVICE_INFO_V0_KELVIN; break;
v0                170 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case NV_30: args->v0.family = NV_DEVICE_INFO_V0_RANKINE; break;
v0                171 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case NV_40: args->v0.family = NV_DEVICE_INFO_V0_CURIE; break;
v0                172 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case NV_50: args->v0.family = NV_DEVICE_INFO_V0_TESLA; break;
v0                173 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case NV_C0: args->v0.family = NV_DEVICE_INFO_V0_FERMI; break;
v0                174 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case NV_E0: args->v0.family = NV_DEVICE_INFO_V0_KEPLER; break;
v0                175 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case GM100: args->v0.family = NV_DEVICE_INFO_V0_MAXWELL; break;
v0                176 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case GP100: args->v0.family = NV_DEVICE_INFO_V0_PASCAL; break;
v0                177 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case GV100: args->v0.family = NV_DEVICE_INFO_V0_VOLTA; break;
v0                178 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	case TU100: args->v0.family = NV_DEVICE_INFO_V0_TURING; break;
v0                180 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		args->v0.family = 0;
v0                184 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	args->v0.chipset  = device->chipset;
v0                185 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	args->v0.revision = device->chiprev;
v0                187 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		args->v0.ram_size = args->v0.ram_user = fb->ram->size;
v0                189 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		args->v0.ram_size = args->v0.ram_user = 0;
v0                190 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	if (imem && args->v0.ram_size > 0)
v0                191 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		args->v0.ram_user = args->v0.ram_user - imem->reserved;
v0                193 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip));
v0                194 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	strncpy(args->v0.name, device->name, sizeof(args->v0.name));
v0                204 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		struct nv_device_time_v0 v0;
v0                209 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                210 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		nvif_ioctl(object, "device time vers %d\n", args->v0.version);
v0                211 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		args->v0.time = nvkm_timer_read(device->timer);
v0                413 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		struct nv_device_v0 v0;
v0                422 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                424 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 			   args->v0.version, args->v0.device);
v0                440 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	if (args->v0.device != ~0)
v0                441 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		udev->device = nvkm_device_find(args->v0.device);
v0                 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 		struct nvif_notify_head_req_v0 v0;
v0                 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, false))) {
v0                 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 		if (ret = -ENXIO, req->v0.head <= disp->vblank.index_nr) {
v0                 75 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 			notify->index = req->v0.head;
v0                104 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 		struct nvif_notify_conn_req_v0 v0;
v0                109 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, false))) {
v0                112 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 			if (ret = -ENXIO, outp->conn->index == req->v0.conn) {
v0                114 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 					notify->types = req->v0.mask;
v0                115 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 					notify->index = req->v0.conn;
v0                 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c 		struct nv50_disp_base_channel_dma_v0 v0;
v0                 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c 			   args->v0.version, args->v0.pushbuf, args->v0.head);
v0                 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c 		if (!nvkm_head_find(&disp->base, args->v0.head))
v0                 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c 		push = args->v0.pushbuf;
v0                 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c 		head = args->v0.head;
v0                 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c 		struct nv50_disp_core_channel_dma_v0 v0;
v0                 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c 			   args->v0.version, args->v0.pushbuf);
v0                 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c 		push = args->v0.pushbuf;
v0                 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c 		struct nv50_disp_cursor_v0 v0;
v0                 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c 			   args->v0.version, args->v0.head);
v0                 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c 		if (!nvkm_head_find(&disp->base, args->v0.head))
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c 		head = args->v0.head;
v0                 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		struct nv04_disp_scanoutpos_v0 v0;
v0                 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 			   args->v0.version);
v0                 57 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		args->v0.vtotal  = head->arm.vtotal;
v0                 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		args->v0.vblanks = head->arm.vblanks;
v0                 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		args->v0.vblanke = head->arm.vblanke;
v0                 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		args->v0.htotal  = head->arm.htotal;
v0                 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		args->v0.hblanks = head->arm.hblanks;
v0                 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		args->v0.hblanke = head->arm.hblanke;
v0                 68 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		if (!args->v0.vtotal || !args->v0.htotal)
v0                 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		args->v0.time[0] = ktime_to_ns(ktime_get());
v0                 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		head->func->rgpos(head, &args->v0.hline, &args->v0.vline);
v0                 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		args->v0.time[1] = ktime_to_ns(ktime_get());
v0                 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c 		struct nv50_disp_overlay_v0 v0;
v0                 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c 			   args->v0.version, args->v0.head);
v0                 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c 		if (!nvkm_head_find(&disp->base, args->v0.head))
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c 		head = args->v0.head;
v0                 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c 		struct nv50_disp_overlay_channel_dma_v0 v0;
v0                 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c 			   args->v0.version, args->v0.pushbuf, args->v0.head);
v0                 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c 		if (!nvkm_head_find(&disp->base, args->v0.head))
v0                 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c 		push = args->v0.pushbuf;
v0                 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c 		head = args->v0.head;
v0                 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c 		struct nv04_disp_mthd_v0 v0;
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c 			   args->v0.version, args->v0.method, args->v0.head);
v0                 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c 		mthd = args->v0.method;
v0                 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c 		id   = args->v0.head;
v0                 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		struct nv50_disp_mthd_v0 v0;
v0                 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			   args->v0.version, args->v0.method, args->v0.head);
v0                 57 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		mthd = args->v0.method;
v0                 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		hidx = args->v0.head;
v0                 98 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			struct nv50_disp_acquire_v0 v0;
v0                101 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                104 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				args->v0.or = outp->ior->id;
v0                105 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				args->v0.link = outp->ior->asy.link;
v0                116 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			struct nv50_disp_dac_load_v0 v0;
v0                119 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                120 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			if (args->v0.data & 0xfff00000)
v0                125 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			ret = outp->ior->func->sense(outp->ior, args->v0.data);
v0                129 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			args->v0.load = ret;
v0                137 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			struct nv50_disp_sor_hda_eld_v0 v0;
v0                143 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                145 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				   args->v0.version);
v0                154 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		if (size && args->v0.data[0]) {
v0                170 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			struct nv50_disp_sor_hdmi_pwr_v0 v0;
v0                177 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                180 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				   args->v0.version, args->v0.state,
v0                181 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				   args->v0.max_ac_packet, args->v0.rekey,
v0                182 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				   args->v0.scdc);
v0                183 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f)
v0                185 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			if ((args->v0.avi_infoframe_length
v0                186 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			     + args->v0.vendor_infoframe_length) > size)
v0                189 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			if ((args->v0.avi_infoframe_length
v0                190 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			     + args->v0.vendor_infoframe_length) < size)
v0                193 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			avi_size = args->v0.avi_infoframe_length;
v0                195 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			vendor_size = args->v0.vendor_infoframe_length;
v0                202 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		outp->ior->func->hdmi.ctrl(outp->ior, hidx, args->v0.state,
v0                203 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 					   args->v0.max_ac_packet,
v0                204 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 					   args->v0.rekey, avi, avi_size,
v0                209 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 					outp->ior, hidx, args->v0.scdc);
v0                216 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			struct nv50_disp_sor_lvds_script_v0 v0;
v0                220 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                223 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				   args->v0.version, args->v0.script);
v0                224 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			disp->sor.lvdsconf = args->v0.script;
v0                233 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			struct nv50_disp_sor_dp_mst_link_v0 v0;
v0                237 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                239 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				   args->v0.version, args->v0.state);
v0                240 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			dp->lt.mst = !!args->v0.state;
v0                248 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 			struct nv50_disp_sor_dp_mst_vcpi_v0 v0;
v0                252 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 		if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                255 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				   args->v0.version, args->v0.start_slot,
v0                256 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				   args->v0.num_slots, args->v0.pbn,
v0                257 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 				   args->v0.aligned_pbn);
v0                261 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 						 args->v0.start_slot,
v0                262 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 						 args->v0.num_slots,
v0                263 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 						 args->v0.pbn,
v0                264 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 						 args->v0.aligned_pbn);
v0                 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c 		struct nvc37b_window_imm_channel_dma_v0 v0;
v0                 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c 			   args->v0.version, args->v0.pushbuf, args->v0.index);
v0                 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c 		if (!(disp->wndw.mask & BIT(args->v0.index)))
v0                 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c 		push = args->v0.pushbuf;
v0                 68 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c 		wndw = args->v0.index;
v0                156 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c 		struct nvc37e_window_channel_dma_v0 v0;
v0                163 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                166 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c 			   args->v0.version, args->v0.pushbuf, args->v0.index);
v0                167 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c 		if (!(disp->wndw.mask & BIT(args->v0.index)))
v0                169 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c 		push = args->v0.pushbuf;
v0                170 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c 		wndw = args->v0.index;
v0                 73 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		struct nv_dma_v0 v0;
v0                 89 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
v0                 92 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 			   args->v0.version, args->v0.target, args->v0.access,
v0                 93 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 			   args->v0.start, args->v0.limit);
v0                 94 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->target = args->v0.target;
v0                 95 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->access = args->v0.access;
v0                 96 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->start  = args->v0.start;
v0                 97 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->limit  = args->v0.limit;
v0                 74 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		struct gf100_dma_v0 v0;
v0                 94 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 97 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 			   args->v0.version, args->v0.priv, args->v0.kind);
v0                 98 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		kind = args->v0.kind;
v0                 99 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		user = args->v0.priv;
v0                 72 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		struct gf119_dma_v0 v0;
v0                 92 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 95 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 			   args->v0.version, args->v0.page, args->v0.kind);
v0                 96 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		kind = args->v0.kind;
v0                 97 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		page = args->v0.page;
v0                 71 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		struct gf119_dma_v0 v0;
v0                 91 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 94 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 			   args->v0.version, args->v0.page, args->v0.kind);
v0                 95 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		kind = args->v0.kind != 0;
v0                 96 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		page = args->v0.page != 0;
v0                 74 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		struct nv50_dma_v0 v0;
v0                 94 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 96 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 				   "comp %d kind %02x\n", args->v0.version,
v0                 97 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 			   args->v0.priv, args->v0.part, args->v0.comp,
v0                 98 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 			   args->v0.kind);
v0                 99 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		user = args->v0.priv;
v0                100 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		part = args->v0.part;
v0                101 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		comp = args->v0.comp;
v0                102 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		kind = args->v0.kind;
v0                 39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 		struct g82_channel_dma_v0 v0;
v0                 46 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 49 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 			   args->v0.version, args->v0.vmm, args->v0.pushbuf,
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 			   args->v0.offset);
v0                 51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 		if (!args->v0.pushbuf)
v0                 60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 	ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
v0                 65 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 	args->v0.chid = chan->base.chid;
v0                 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 	nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
v0                 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 	nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
v0                 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 	nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
v0                 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 	nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
v0                170 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 		struct nv03_channel_dma_v0 v0;
v0                179 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                181 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 				   "offset %08x\n", args->v0.version,
v0                182 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 			   args->v0.pushbuf, args->v0.offset);
v0                183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 		if (!args->v0.pushbuf)
v0                193 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 				  0x1000, 0x1000, false, 0, args->v0.pushbuf,
v0                202 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	args->v0.chid = chan->base.chid;
v0                206 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
v0                207 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
v0                 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 		struct nv03_channel_dma_v0 v0;
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 				   "offset %08x\n", args->v0.version,
v0                 53 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 			   args->v0.pushbuf, args->v0.offset);
v0                 54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 		if (!args->v0.pushbuf)
v0                 64 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 				  0x1000, 0x1000, false, 0, args->v0.pushbuf,
v0                 73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 	args->v0.chid = chan->base.chid;
v0                 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
v0                 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
v0                 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 		struct nv03_channel_dma_v0 v0;
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 				   "offset %08x\n", args->v0.version,
v0                 53 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 			   args->v0.pushbuf, args->v0.offset);
v0                 54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 		if (!args->v0.pushbuf)
v0                 64 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 				  0x1000, 0x1000, false, 0, args->v0.pushbuf,
v0                 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 	args->v0.chid = chan->base.chid;
v0                 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
v0                 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
v0                188 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 		struct nv03_channel_dma_v0 v0;
v0                197 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                199 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 				   "offset %08x\n", args->v0.version,
v0                200 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 			   args->v0.pushbuf, args->v0.offset);
v0                201 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 		if (!args->v0.pushbuf)
v0                211 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 				  0x1000, 0x1000, false, 0, args->v0.pushbuf,
v0                221 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	args->v0.chid = chan->base.chid;
v0                225 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
v0                226 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
v0                 39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 		struct nv50_channel_dma_v0 v0;
v0                 46 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 49 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 			   args->v0.version, args->v0.vmm, args->v0.pushbuf,
v0                 50 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 			   args->v0.offset);
v0                 51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 		if (!args->v0.pushbuf)
v0                 60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 	ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
v0                 65 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 	args->v0.chid = chan->base.chid;
v0                 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 	nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
v0                 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 	nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
v0                 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 	nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
v0                 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 	nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
v0                 39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 		struct g82_channel_gpfifo_v0 v0;
v0                 47 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 			   args->v0.version, args->v0.vmm, args->v0.pushbuf,
v0                 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 			   args->v0.ioffset, args->v0.ilength);
v0                 53 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 		if (!args->v0.pushbuf)
v0                 62 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 	ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
v0                 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 	args->v0.chid = chan->base.chid;
v0                 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 	ioffset = args->v0.ioffset;
v0                 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 	ilength = order_base_2(args->v0.ilength / 8);
v0                218 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 		struct fermi_channel_gpfifo_v0 v0;
v0                227 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                230 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 			   args->v0.version, args->v0.vmm, args->v0.ioffset,
v0                231 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 			   args->v0.ilength);
v0                232 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 		if (!args->v0.vmm)
v0                245 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 				  0x1000, 0x1000, true, args->v0.vmm, 0,
v0                258 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	args->v0.chid = chan->base.chid;
v0                263 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	ioffset = args->v0.ioffset;
v0                264 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	ilength = order_base_2(args->v0.ilength / 8);
v0                335 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 		struct kepler_channel_gpfifo_a_v0 v0;
v0                340 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                344 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 			   args->v0.version, args->v0.vmm, args->v0.ioffset,
v0                345 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 			   args->v0.ilength, args->v0.runlist, args->v0.priv);
v0                346 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 		if (args->v0.priv && !oclass->client->super)
v0                349 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 					      &args->v0.runlist,
v0                350 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 					      &args->v0.chid,
v0                351 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 					       args->v0.vmm,
v0                352 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 					       args->v0.ioffset,
v0                353 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 					       args->v0.ilength,
v0                354 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 					      &args->v0.inst,
v0                355 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 					       args->v0.priv,
v0                229 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 		struct volta_channel_gpfifo_a_v0 v0;
v0                234 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                238 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 			   args->v0.version, args->v0.vmm, args->v0.ioffset,
v0                239 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 			   args->v0.ilength, args->v0.runlist, args->v0.priv);
v0                240 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 		if (args->v0.priv && !oclass->client->super)
v0                243 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 					      &args->v0.runlist,
v0                244 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 					      &args->v0.chid,
v0                245 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 					       args->v0.vmm,
v0                246 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 					       args->v0.ioffset,
v0                247 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 					       args->v0.ilength,
v0                248 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 					      &args->v0.inst,
v0                249 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 					       args->v0.priv,
v0                250 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 					      &args->v0.token,
v0                 39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 		struct nv50_channel_gpfifo_v0 v0;
v0                 47 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 			   args->v0.version, args->v0.vmm, args->v0.pushbuf,
v0                 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 			   args->v0.ioffset, args->v0.ilength);
v0                 53 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 		if (!args->v0.pushbuf)
v0                 62 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 	ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
v0                 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 	args->v0.chid = chan->base.chid;
v0                 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 	ioffset = args->v0.ioffset;
v0                 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 	ilength = order_base_2(args->v0.ilength / 8);
v0                 57 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 		struct volta_channel_gpfifo_a_v0 v0;
v0                 62 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 66 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 			   args->v0.version, args->v0.vmm, args->v0.ioffset,
v0                 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 			   args->v0.ilength, args->v0.runlist, args->v0.priv);
v0                 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 		if (args->v0.priv && !oclass->client->super)
v0                 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 					      &args->v0.runlist,
v0                 72 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 					      &args->v0.chid,
v0                 73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 					       args->v0.vmm,
v0                 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 					       args->v0.ioffset,
v0                 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 					       args->v0.ilength,
v0                 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 					      &args->v0.inst,
v0                 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 					       args->v0.priv,
v0                 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c 					      &args->v0.token,
v0                165 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		struct fermi_a_zbc_color_v0 v0;
v0                169 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                170 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		switch (args->v0.format) {
v0                190 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 			ret = gf100_gr_zbc_color_get(gr, args->v0.format,
v0                191 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 							   args->v0.ds,
v0                192 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 							   args->v0.l2);
v0                194 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 				args->v0.index = ret;
v0                211 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		struct fermi_a_zbc_depth_v0 v0;
v0                215 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                216 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		switch (args->v0.format) {
v0                218 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 			ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
v0                219 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 							   args->v0.ds,
v0                220 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 							   args->v0.l2);
v0                265 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		struct nvif_perfdom_read_v0 v0;
v0                272 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                273 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		nvif_ioctl(object, "perfdom read vers %d\n", args->v0.version);
v0                287 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			args->v0.ctr[i] = dom->ctr[i]->ctr;
v0                288 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	args->v0.clk = dom->clk;
v0                371 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		struct nvif_perfdom_v0 v0;
v0                382 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                384 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			   args->v0.version, args->v0.domain, args->v0.mode);
v0                388 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	for (c = 0; c < ARRAY_SIZE(args->v0.ctr); c++) {
v0                392 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		for (s = 0; s < ARRAY_SIZE(args->v0.ctr[c].signal); s++) {
v0                393 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			sig[s] = nvkm_perfsig_find(pm, args->v0.domain,
v0                394 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 						   args->v0.ctr[c].signal[s],
v0                396 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			if (args->v0.ctr[c].signal[s] && !sig[s])
v0                400 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 				src[s][m] = args->v0.ctr[c].source[s][m];
v0                407 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		ret = nvkm_perfctr_new(sdom, c, args->v0.domain, sig, src,
v0                408 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 				       args->v0.ctr[c].logic_op, &ctr[c]);
v0                424 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	dom->mode = args->v0.mode;
v0                438 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		struct nvif_perfmon_query_domain_v0 v0;
v0                447 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                449 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			   args->v0.version, args->v0.iter);
v0                450 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		di = (args->v0.iter & 0xff) - 1;
v0                463 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		args->v0.id         = di;
v0                464 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		args->v0.signal_nr  = nvkm_perfdom_count_perfsig(dom);
v0                465 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		strncpy(args->v0.name, dom->name, sizeof(args->v0.name) - 1);
v0                469 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		args->v0.counter_nr = 4;
v0                473 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		args->v0.iter = ++di;
v0                477 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	args->v0.iter = 0xff;
v0                486 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		struct nvif_perfmon_query_signal_v0 v0;
v0                498 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                501 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			   args->v0.version, args->v0.domain, args->v0.iter);
v0                502 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		si = (args->v0.iter & 0xffff) - 1;
v0                506 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	dom = nvkm_perfdom_find(pm, args->v0.domain);
v0                513 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			snprintf(args->v0.name, sizeof(args->v0.name),
v0                516 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			strncpy(args->v0.name, sig->name,
v0                517 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 				sizeof(args->v0.name) - 1);
v0                520 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		args->v0.signal = si;
v0                521 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		args->v0.source_nr = nvkm_perfsig_count_perfsrc(sig);
v0                526 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			args->v0.iter = ++si;
v0                531 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	args->v0.iter = 0xffff;
v0                540 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		struct nvif_perfmon_query_source_v0 v0;
v0                551 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                554 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			   args->v0.version, args->v0.domain, args->v0.signal,
v0                555 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 			   args->v0.iter);
v0                556 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		si = (args->v0.iter & 0xff) - 1;
v0                560 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	sig = nvkm_perfsig_find(pm, args->v0.domain, args->v0.signal, &dom);
v0                573 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		args->v0.source = sig->source[si];
v0                574 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		args->v0.mask   = src->mask;
v0                575 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		strncpy(args->v0.name, src->name, sizeof(args->v0.name) - 1);
v0                579 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		args->v0.iter = ++si;
v0                583 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	args->v0.iter = 0xff;
v0                 48 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c 		struct nv04_nvsw_get_ref_v0 v0;
v0                 52 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
v0                 53 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c 		args->v0.ref = atomic_read(&chan->ref);
v0                 90 drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c 		struct nvif_clb069_v0 v0;
v0                 96 drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 97 drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c 		args->v0.entries = buffer->entries;
v0                 98 drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c 		args->v0.get = buffer->get;
v0                 99 drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c 		args->v0.put = buffer->put;
v0                211 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	u8 v0 = next->bios.ramcfg_11_03_c0;
v0                225 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
v0                150 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c 		struct nvif_mem_ram_v0 v0;
v0                172 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                173 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c 		if (args->v0.dma) {
v0                175 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c 			mem->dma = args->v0.dma;
v0                178 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.c 			mem->sgl = args->v0.sgl;
v0                 40 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c 		struct gf100_mem_map_v0 v0;
v0                 46 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 47 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c 		uvmm.ro   = args->v0.ro;
v0                 48 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c 		uvmm.kind = args->v0.kind;
v0                 74 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c 		struct gf100_mem_v0 v0;
v0                 79 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 80 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.c 		contig = args->v0.contig;
v0                 40 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c 		struct nv50_mem_map_v0 v0;
v0                 47 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 48 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c 		uvmm.ro   = args->v0.ro;
v0                 49 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c 		uvmm.kind = args->v0.kind;
v0                 50 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c 		uvmm.comp = args->v0.comp;
v0                 71 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c 		struct nv50_mem_v0 v0;
v0                 76 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 77 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c 		type   = args->v0.bankswz ? 0x02 : 0x01;
v0                 78 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.c 		contig = args->v0.contig;
v0                148 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c 		struct nvif_mem_v0 v0;
v0                155 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true))) {
v0                156 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c 		type = args->v0.type;
v0                157 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c 		page = args->v0.page;
v0                158 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c 		size = args->v0.size;
v0                188 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c 	args->v0.page = nvkm_memory_page(umem->memory);
v0                189 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c 	args->v0.addr = nvkm_memory_addr(umem->memory);
v0                190 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c 	args->v0.size = nvkm_memory_size(umem->memory);
v0                 61 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		struct nvif_mmu_heap_v0 v0;
v0                 66 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 67 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		if ((index = args->v0.index) >= mmu->heap_nr)
v0                 69 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.size = mmu->heap[index].size;
v0                 81 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		struct nvif_mmu_type_v0 v0;
v0                 86 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 87 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		if ((index = args->v0.index) >= mmu->type_nr)
v0                 90 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.heap = mmu->type[index].heap;
v0                 91 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.vram = !!(type & NVKM_MEM_VRAM);
v0                 92 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.host = !!(type & NVKM_MEM_HOST);
v0                 93 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.comp = !!(type & NVKM_MEM_COMP);
v0                 94 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.disp = !!(type & NVKM_MEM_DISP);
v0                 95 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.kind = !!(type & NVKM_MEM_KIND);
v0                 96 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.mappable = !!(type & NVKM_MEM_MAPPABLE);
v0                 97 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.coherent = !!(type & NVKM_MEM_COHERENT);
v0                 98 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.uncached = !!(type & NVKM_MEM_UNCACHED);
v0                110 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		struct nvif_mmu_kind_v0 v0;
v0                118 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true))) {
v0                119 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		if (argc != args->v0.count * sizeof(*args->v0.data))
v0                121 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		if (args->v0.count > count)
v0                123 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		memcpy(args->v0.data, kind, args->v0.count);
v0                155 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		struct nvif_mmu_v0 v0;
v0                164 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                165 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.dmabits = mmu->dma_bits;
v0                166 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.heap_nr = mmu->heap_nr;
v0                167 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.type_nr = mmu->type_nr;
v0                168 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c 		args->v0.kind_nr = kinds;
v0                 50 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		struct nvif_vmm_pfnclr_v0 v0;
v0                 56 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                 57 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		addr = args->v0.addr;
v0                 58 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		size = args->v0.size;
v0                 79 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		struct nvif_vmm_pfnmap_v0 v0;
v0                 86 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true))) {
v0                 87 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		page = args->v0.page;
v0                 88 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		addr = args->v0.addr;
v0                 89 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		size = args->v0.size;
v0                 90 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		phys = args->v0.phys;
v0                 91 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		if (argc != (size >> page) * sizeof(args->v0.phys[0]))
v0                113 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		struct nvif_vmm_unmap_v0 v0;
v0                120 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                121 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		addr = args->v0.addr;
v0                156 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		struct nvif_vmm_map_v0 v0;
v0                164 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, true))) {
v0                165 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		addr = args->v0.addr;
v0                166 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		size = args->v0.size;
v0                167 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		handle = args->v0.memory;
v0                168 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		offset = args->v0.offset;
v0                235 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		struct nvif_vmm_put_v0 v0;
v0                242 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                243 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		addr = args->v0.addr;
v0                248 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	vma = nvkm_vmm_node_search(vmm, args->v0.addr);
v0                273 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		struct nvif_vmm_get_v0 v0;
v0                282 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                283 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		getref = args->v0.type == NVIF_VMM_GET_V0_PTES;
v0                284 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		mapref = args->v0.type == NVIF_VMM_GET_V0_ADDR;
v0                285 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		sparse = args->v0.sparse;
v0                286 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		page = args->v0.page;
v0                287 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		align = args->v0.align;
v0                288 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		size = args->v0.size;
v0                299 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	args->v0.addr = vma->addr;
v0                308 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		struct nvif_vmm_page_v0 v0;
v0                317 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                318 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		if ((index = args->v0.index) >= nr)
v0                321 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		args->v0.shift = page[index].shift;
v0                322 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		args->v0.sparse = !!(type & NVKM_VMM_PAGE_SPARSE);
v0                323 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		args->v0.vram = !!(type & NVKM_VMM_PAGE_VRAM);
v0                324 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		args->v0.host = !!(type & NVKM_VMM_PAGE_HOST);
v0                325 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		args->v0.comp = !!(type & NVKM_VMM_PAGE_COMP);
v0                378 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		struct nvif_vmm_v0 v0;
v0                386 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, more))) {
v0                387 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		managed = args->v0.managed != 0;
v0                388 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		addr = args->v0.addr;
v0                389 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		size = args->v0.size;
v0                413 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	args->v0.page_nr = 0;
v0                415 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 		args->v0.page_nr++;
v0                416 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	args->v0.addr = uvmm->vmm->start;
v0                417 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	args->v0.size = uvmm->vmm->limit;
v0                246 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		struct gf100_vmm_map_v0 v0;
v0                257 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                258 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		vol  = !!args->v0.vol;
v0                259 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		ro   = !!args->v0.ro;
v0                260 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		priv = !!args->v0.priv;
v0                261 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		kind =   args->v0.kind;
v0                151 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c 		struct gm200_vmm_v0 v0;
v0                155 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                156 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c 		switch (args->v0.bigpage) {
v0                319 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		struct gp100_vmm_map_v0 v0;
v0                330 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                331 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		vol  = !!args->v0.vol;
v0                332 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		ro   = !!args->v0.ro;
v0                333 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		priv = !!args->v0.priv;
v0                334 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		kind =   args->v0.kind;
v0                395 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		struct gp100_vmm_fault_cancel_v0 v0;
v0                400 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	if ((ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false)))
v0                406 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	aper = (args->v0.inst >> 8) & 3;
v0                407 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	args->v0.inst >>= 12;
v0                408 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	args->v0.inst |= aper << 28;
v0                409 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	args->v0.inst |= 0x80000000;
v0                412 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		if ((inst = nvkm_gr_ctxsw_inst(device)) == args->v0.inst) {
v0                415 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 					     (args->v0.hub    << 20) |
v0                416 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 					     (args->v0.gpc    << 15) |
v0                417 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 					     (args->v0.client << 9));
v0                515 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		struct gp100_vmm_v0 v0;
v0                520 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                521 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		replay = args->v0.fault_replay != 0;
v0                233 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		struct nv50_vmm_map_v0 v0;
v0                245 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
v0                246 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		ro   = !!args->v0.ro;
v0                247 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		priv = !!args->v0.priv;
v0                248 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		kind = args->v0.kind & 0x7f;
v0                249 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		comp = args->v0.comp & 0x03;
v0               1020 drivers/infiniband/hw/hfi1/tid_rdma.c 	void *v0, *v1, *vm1;
v0               1026 drivers/infiniband/hw/hfi1/tid_rdma.c 		v0 = page_address(pages[i]);
v0               1027 drivers/infiniband/hw/hfi1/tid_rdma.c 		trace_hfi1_tid_flow_page(flow->req->qp, flow, i, 1, 0, v0);
v0               1032 drivers/infiniband/hw/hfi1/tid_rdma.c 		if (v1 != (v0 + PAGE_SIZE)) {
v0               1049 drivers/infiniband/hw/hfi1/tid_rdma.c 		if (vm1 && v0 != (vm1 + PAGE_SIZE)) {
v0                295 drivers/input/mouse/sentelic.c 	int v0, v1, v2;
v0                301 drivers/input/mouse/sentelic.c 	if (fsp_reg_read(psmouse, FSP_REG_SN0, &v0))
v0                307 drivers/input/mouse/sentelic.c 	*sn = (v0 << 16) | (v1 << 8) | v2;
v0                359 drivers/media/usb/gspca/w996Xcf.c 		      v0 = u0 + hw_bufsize / 4,
v0                360 drivers/media/usb/gspca/w996Xcf.c 		      y1 = v0 + hw_bufsize / 4,
v0                374 drivers/media/usb/gspca/w996Xcf.c 	reg_w(sd, 0x28, v0 & 0xffff); /* V buf.0, low */
v0                375 drivers/media/usb/gspca/w996Xcf.c 	reg_w(sd, 0x29, v0 >> 16);    /* V buf.0, high */
v0                110 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2)				\
v0                116 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h 		return mlxsw_pci_cqe##v0##_##name##_get(cqe);			\
v0                129 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h 		mlxsw_pci_cqe##v0##_##name##_set(cqe, val);			\
v0               3729 drivers/net/ethernet/sun/niu.c 	u64 v0 = lp->v0;
v0               3730 drivers/net/ethernet/sun/niu.c 	u32 tx_vec = (v0 >> 32);
v0               3731 drivers/net/ethernet/sun/niu.c 	u32 rx_vec = (v0 & 0xffffffff);
v0               3735 drivers/net/ethernet/sun/niu.c 		     "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
v0               4061 drivers/net/ethernet/sun/niu.c 			      u64 v0, u64 v1, u64 v2)
v0               4066 drivers/net/ethernet/sun/niu.c 	lp->v0 = v0;
v0               4081 drivers/net/ethernet/sun/niu.c 					if (!v0)
v0               4101 drivers/net/ethernet/sun/niu.c 	if ((v0 | v1) & 0x8000000000000000ULL) {
v0               4148 drivers/net/ethernet/sun/niu.c static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
v0               4154 drivers/net/ethernet/sun/niu.c 	tx_vec = (v0 >> 32);
v0               4155 drivers/net/ethernet/sun/niu.c 	rx_vec = (v0 & 0xffffffff);
v0               4183 drivers/net/ethernet/sun/niu.c 			      u64 v0, u64 v1, u64 v2)
v0               4186 drivers/net/ethernet/sun/niu.c 		lp->v0 = v0;
v0               4189 drivers/net/ethernet/sun/niu.c 		__niu_fastpath_interrupt(np, lp->ldg_num, v0);
v0               4200 drivers/net/ethernet/sun/niu.c 	u64 v0, v1, v2;
v0               4208 drivers/net/ethernet/sun/niu.c 	v0 = nr64(LDSV0(ldg));
v0               4214 drivers/net/ethernet/sun/niu.c 		       (unsigned long long) v0,
v0               4218 drivers/net/ethernet/sun/niu.c 	if (unlikely(!v0 && !v1 && !v2)) {
v0               4223 drivers/net/ethernet/sun/niu.c 	if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
v0               4224 drivers/net/ethernet/sun/niu.c 		int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
v0               4228 drivers/net/ethernet/sun/niu.c 	if (likely(v0 & ~((u64)1 << LDN_MIF)))
v0               4229 drivers/net/ethernet/sun/niu.c 		niu_schedule_napi(np, lp, v0, v1, v2);
v0               3174 drivers/net/ethernet/sun/niu.h 	u64		v0, v1, v2;
v0                 44 drivers/net/gtp.c 		} v0;
v0                114 drivers/net/gtp.c 		    pdp->u.v0.tid == tid)
v0                415 drivers/net/gtp.c 	gtp0->flow	= htons(pctx->u.v0.flow);
v0                418 drivers/net/gtp.c 	gtp0->tid	= cpu_to_be64(pctx->u.v0.tid);
v0                922 drivers/net/gtp.c 		pctx->u.v0.tid = nla_get_u64(info->attrs[GTPA_TID]);
v0                923 drivers/net/gtp.c 		pctx->u.v0.flow = nla_get_u16(info->attrs[GTPA_FLOW]);
v0                975 drivers/net/gtp.c 				   pctx->u.v0.tid, pctx);
v0               1001 drivers/net/gtp.c 		hash_tid = gtp0_hashfn(pctx->u.v0.tid) % gtp->hash_size;
v0               1014 drivers/net/gtp.c 			   pctx->u.v0.tid, &pctx->peer_addr_ip4,
v0               1160 drivers/net/gtp.c 			   pctx->u.v0.tid, pctx);
v0               1191 drivers/net/gtp.c 		if (nla_put_u64_64bit(skb, GTPA_TID, pctx->u.v0.tid, GTPA_PAD) ||
v0               1192 drivers/net/gtp.c 		    nla_put_u16(skb, GTPA_FLOW, pctx->u.v0.flow))
v0                419 drivers/net/ieee802154/mac802154_hwsim.c 	u32 v0, v1;
v0                431 drivers/net/ieee802154/mac802154_hwsim.c 	v0 = nla_get_u32(info->attrs[MAC802154_HWSIM_ATTR_RADIO_ID]);
v0                434 drivers/net/ieee802154/mac802154_hwsim.c 	if (v0 == v1)
v0                438 drivers/net/ieee802154/mac802154_hwsim.c 	phy_v0 = hwsim_get_radio_by_id(v0);
v0                481 drivers/net/ieee802154/mac802154_hwsim.c 	u32 v0, v1;
v0                493 drivers/net/ieee802154/mac802154_hwsim.c 	v0 = nla_get_u32(info->attrs[MAC802154_HWSIM_ATTR_RADIO_ID]);
v0                497 drivers/net/ieee802154/mac802154_hwsim.c 	phy_v0 = hwsim_get_radio_by_id(v0);
v0                528 drivers/net/ieee802154/mac802154_hwsim.c 	u32 v0, v1;
v0                542 drivers/net/ieee802154/mac802154_hwsim.c 	v0 = nla_get_u32(info->attrs[MAC802154_HWSIM_ATTR_RADIO_ID]);
v0                547 drivers/net/ieee802154/mac802154_hwsim.c 	phy_v0 = hwsim_get_radio_by_id(v0);
v0               1334 drivers/net/wireless/broadcom/b43/main.c 	u32 v0, v1;
v0               1339 drivers/net/wireless/broadcom/b43/main.c 		v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
v0               1340 drivers/net/wireless/broadcom/b43/main.c 		if (!(v0 & 0x00000001))
v0               1344 drivers/net/wireless/broadcom/b43/main.c 		stat.cookie = (v0 >> 16);
v0               1347 drivers/net/wireless/broadcom/b43/main.c 		tmp = (v0 & 0x0000FFFF);
v0                415 drivers/net/wireless/broadcom/b43legacy/main.c 		u16 v0;
v0                427 drivers/net/wireless/broadcom/b43legacy/main.c 			v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
v0                442 drivers/net/wireless/broadcom/b43legacy/main.c 		*tsf |= v0;
v0                480 drivers/net/wireless/broadcom/b43legacy/main.c 		u16 v0 = (tsf & 0x000000000000FFFFULL);
v0                489 drivers/net/wireless/broadcom/b43legacy/main.c 		b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
v0                706 drivers/net/wireless/broadcom/b43legacy/main.c 	u32 v0;
v0                712 drivers/net/wireless/broadcom/b43legacy/main.c 		v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
v0                713 drivers/net/wireless/broadcom/b43legacy/main.c 		if (!(v0 & 0x00000001))
v0                717 drivers/net/wireless/broadcom/b43legacy/main.c 		stat.cookie = (v0 >> 16);
v0                720 drivers/net/wireless/broadcom/b43legacy/main.c 		tmp = (v0 & 0x0000FFFF);
v0               1756 drivers/net/wireless/broadcom/b43legacy/phy.c 	s8 v0;
v0               1783 drivers/net/wireless/broadcom/b43legacy/phy.c 	v0 = (s8)(tmp & 0x00FF);
v0               1790 drivers/net/wireless/broadcom/b43legacy/phy.c 	if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) {
v0               1793 drivers/net/wireless/broadcom/b43legacy/phy.c 		v0 = (s8)(tmp & 0x00FF);
v0               1799 drivers/net/wireless/broadcom/b43legacy/phy.c 		if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F)
v0               1801 drivers/net/wireless/broadcom/b43legacy/phy.c 		v0 = (v0 + 0x20) & 0x3F;
v0               1809 drivers/net/wireless/broadcom/b43legacy/phy.c 	average = (v0 + v1 + v2 + v3 + 2) / 4;
v0               21255 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c 		u16 v0 = 0x211, v1 = 0x222, v2 = 0x144, v3 = 0x188;
v0               21262 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c 						 1, 0x02, 16, &v0);
v0               21273 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c 						 1, 0x12, 16, &v0);
v0               2587 drivers/staging/media/ipu3/include/intel-ipu3.h 	__u32 v0;
v0               2604 drivers/staging/media/ipu3/include/intel-ipu3.h 	__u32 v0;
v0               2850 drivers/staging/media/ipu3/ipu3-css-params.c 		xnr_dmem->alpha.v0 = 2047;
v0                 93 fs/adfs/super.c 	unsigned int v0, v1, v2, v3;
v0                 96 fs/adfs/super.c 	v0 = v1 = v2 = v3 = 0;
v0                 98 fs/adfs/super.c 		v0 += map[i]     + (v3 >> 8);
v0                100 fs/adfs/super.c 		v1 += map[i + 1] + (v0 >> 8);
v0                101 fs/adfs/super.c 		v0 &= 0xff;
v0                107 fs/adfs/super.c 	v0 +=           v3 >> 8;
v0                108 fs/adfs/super.c 	v1 += map[1] + (v0 >> 8);
v0                112 fs/adfs/super.c 	return v0 ^ v1 ^ v2 ^ v3;
v0                344 fs/fuse/file.c 	u32 v0 = v;
v0                350 fs/fuse/file.c 		v0 += ((v1 << 4 ^ v1 >> 5) + v1) ^ (sum + k[sum & 3]);
v0                352 fs/fuse/file.c 		v1 += ((v0 << 4 ^ v0 >> 5) + v0) ^ (sum + k[sum>>11 & 3]);
v0                355 fs/fuse/file.c 	return (u64) v0 + ((u64) v1 << 32);
v0                 24 include/uapi/linux/netfilter/xt_string.h 		} v0;
v0                231 include/uapi/linux/pkt_sched.h 	struct tc_sfq_qopt v0;
v0                 22 lib/atomic64_test.c 	atomic##bit##_set(&v, v0);				\
v0                 23 lib/atomic64_test.c 	r = v0;							\
v0                 46 lib/atomic64_test.c 	atomic##bit##_set(&v, v0);				\
v0                 47 lib/atomic64_test.c 	r = v0;							\
v0                 55 lib/atomic64_test.c 	atomic##bit##_set(&v, v0);				\
v0                 56 lib/atomic64_test.c 	r = v0;							\
v0                 58 lib/atomic64_test.c 	BUG_ON(atomic##bit##_##op(val, &v) != v0);		\
v0                106 lib/atomic64_test.c 	int v0 = 0xaaa31337;
v0                138 lib/atomic64_test.c 	INC_RETURN_FAMILY_TEST(, v0);
v0                139 lib/atomic64_test.c 	DEC_RETURN_FAMILY_TEST(, v0);
v0                141 lib/atomic64_test.c 	XCHG_FAMILY_TEST(, v0, v1);
v0                142 lib/atomic64_test.c 	CMPXCHG_FAMILY_TEST(, v0, v1, onestwos);
v0                149 lib/atomic64_test.c 	long long v0 = 0xaaa31337c001d00dLL;
v0                157 lib/atomic64_test.c 	atomic64_t v = ATOMIC64_INIT(v0);
v0                158 lib/atomic64_test.c 	long long r = v0;
v0                190 lib/atomic64_test.c 	INIT(v0);
v0                195 lib/atomic64_test.c 	INIT(v0);
v0                200 lib/atomic64_test.c 	INC_RETURN_FAMILY_TEST(64, v0);
v0                201 lib/atomic64_test.c 	DEC_RETURN_FAMILY_TEST(64, v0);
v0                203 lib/atomic64_test.c 	XCHG_FAMILY_TEST(64, v0, v1);
v0                204 lib/atomic64_test.c 	CMPXCHG_FAMILY_TEST(64, v0, v1, v2);
v0                206 lib/atomic64_test.c 	INIT(v0);
v0                207 lib/atomic64_test.c 	BUG_ON(atomic64_add_unless(&v, one, v0));
v0                210 lib/atomic64_test.c 	INIT(v0);
v0                 23 lib/siphash.c  	v0 += v1; v1 = rol64(v1, 13); v1 ^= v0; v0 = rol64(v0, 32); \
v0                 25 lib/siphash.c  	v0 += v3; v3 = rol64(v3, 21); v3 ^= v0; \
v0                 30 lib/siphash.c  	u64 v0 = 0x736f6d6570736575ULL; \
v0                 38 lib/siphash.c  	v0 ^= key->key[0];
v0                 44 lib/siphash.c  	v0 ^= b; \
v0                 50 lib/siphash.c  	return (v0 ^ v1) ^ (v2 ^ v3);
v0                 63 lib/siphash.c  		v0 ^= m;
v0                 96 lib/siphash.c  		v0 ^= m;
v0                129 lib/siphash.c  	v0 ^= first;
v0                146 lib/siphash.c  	v0 ^= first;
v0                150 lib/siphash.c  	v0 ^= second;
v0                169 lib/siphash.c  	v0 ^= first;
v0                173 lib/siphash.c  	v0 ^= second;
v0                177 lib/siphash.c  	v0 ^= third;
v0                197 lib/siphash.c  	v0 ^= first;
v0                201 lib/siphash.c  	v0 ^= second;
v0                205 lib/siphash.c  	v0 ^= third;
v0                209 lib/siphash.c  	v0 ^= forth;
v0                230 lib/siphash.c  	v0 ^= combined;
v0                246 lib/siphash.c  	v0 ^= b; \
v0                251 lib/siphash.c  	return (v0 ^ v1) ^ (v2 ^ v3);
v0                263 lib/siphash.c  		v0 ^= m;
v0                296 lib/siphash.c  		v0 ^= m;
v0                343 lib/siphash.c  	v0 ^= combined;
v0                362 lib/siphash.c  	v0 ^= combined;
v0                383 lib/siphash.c  	v0 ^= combined;
v0                387 lib/siphash.c  	v0 ^= combined;
v0                394 lib/siphash.c  	v0 += v1; v1 = rol32(v1, 5); v1 ^= v0; v0 = rol32(v0, 16); \
v0                396 lib/siphash.c  	v0 += v3; v3 = rol32(v3, 7); v3 ^= v0; \
v0                401 lib/siphash.c  	u32 v0 = 0; \
v0                409 lib/siphash.c  	v0 ^= key->key[0];
v0                414 lib/siphash.c  	v0 ^= b; \
v0                431 lib/siphash.c  		v0 ^= m;
v0                454 lib/siphash.c  		v0 ^= m;
v0                476 lib/siphash.c  	v0 ^= first;
v0                492 lib/siphash.c  	v0 ^= first;
v0                495 lib/siphash.c  	v0 ^= second;
v0                513 lib/siphash.c  	v0 ^= first;
v0                516 lib/siphash.c  	v0 ^= second;
v0                519 lib/siphash.c  	v0 ^= third;
v0                538 lib/siphash.c  	v0 ^= first;
v0                541 lib/siphash.c  	v0 ^= second;
v0                544 lib/siphash.c  	v0 ^= third;
v0                547 lib/siphash.c  	v0 ^= forth;
v0                796 net/sched/sch_sfq.c 	opt.v0.quantum	= q->quantum;
v0                797 net/sched/sch_sfq.c 	opt.v0.perturb_period = q->perturb_period / HZ;
v0                798 net/sched/sch_sfq.c 	opt.v0.limit	= q->limit;
v0                799 net/sched/sch_sfq.c 	opt.v0.divisor	= q->divisor;
v0                800 net/sched/sch_sfq.c 	opt.v0.flows	= q->maxflows;
v0                230 tools/include/uapi/linux/pkt_sched.h 	struct tc_sfq_qopt v0;