uint32_t 19 Documentation/usb/usbdevfs-drop-permissions.c void drop_privileges(int fd, uint32_t mask) uint32_t 58 Documentation/usb/usbdevfs-drop-permissions.c uint32_t mask, caps; uint32_t 14 arch/arc/include/asm/syscalls.h int sys_cacheflush(uint32_t, uint32_t uint32_t); uint32_t 1132 arch/arc/mm/cache.c SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags) uint32_t 22 arch/arm/boot/compressed/atags_to_fdt.c uint32_t *val_array, int size) uint32_t 40 arch/arm/boot/compressed/atags_to_fdt.c const char *property, uint32_t val) uint32_t 59 arch/arm/boot/compressed/atags_to_fdt.c static uint32_t get_cell_size(const void *fdt) uint32_t 62 arch/arm/boot/compressed/atags_to_fdt.c uint32_t cell_size = 1; uint32_t 63 arch/arm/boot/compressed/atags_to_fdt.c const uint32_t *size_len = getprop(fdt, "/", "#size-cells", &len); uint32_t 101 arch/arm/boot/compressed/atags_to_fdt.c static void hex_str(char *out, uint32_t value) uint32_t 103 arch/arm/boot/compressed/atags_to_fdt.c uint32_t digit; uint32_t 132 arch/arm/boot/compressed/atags_to_fdt.c uint32_t mem_reg_property[2 * 2 * NR_BANKS]; uint32_t 194 arch/arm/boot/compressed/atags_to_fdt.c uint32_t initrd_start, initrd_size; uint32_t 33 arch/arm/include/asm/div64.h static inline uint32_t __div64_32(uint64_t *n, uint32_t base) uint32_t 29 arch/arm/include/asm/string.h extern void *__memset32(uint32_t *, uint32_t v, __kernel_size_t); uint32_t 30 arch/arm/include/asm/string.h static inline void *memset32(uint32_t *p, uint32_t v, __kernel_size_t n) uint32_t 36 arch/arm/include/asm/string.h extern void *__memset64(uint64_t *, uint32_t low, __kernel_size_t, uint32_t hi); uint32_t 24 arch/arm/mach-alpine/alpine_cpu_pm.c int alpine_cpu_wakeup(unsigned int phys_cpu, uint32_t phys_resume_addr) uint32_t 47 arch/arm/mach-alpine/alpine_cpu_pm.c uint32_t watermark; uint32_t 15 arch/arm/mach-alpine/alpine_cpu_pm.h int alpine_cpu_wakeup(unsigned int phys_cpu, uint32_t phys_resume_addr); uint32_t 13 arch/arm/mach-alpine/alpine_cpu_resume.h uint32_t flags; uint32_t 14 arch/arm/mach-alpine/alpine_cpu_resume.h uint32_t resume_addr; uint32_t 20 arch/arm/mach-alpine/alpine_cpu_resume.h uint32_t watermark; uint32_t 21 arch/arm/mach-alpine/alpine_cpu_resume.h uint32_t flags; uint32_t 23 arch/arm/mach-alpine/platsmp.c if (addr > (phys_addr_t)(uint32_t)(-1)) { uint32_t 28 arch/arm/mach-alpine/platsmp.c return alpine_cpu_wakeup(cpu_logical_map(cpu), (uint32_t)addr); uint32_t 31 arch/arm/mach-bcm/board_bcm281xx.c uint32_t val; uint32_t 150 arch/arm/mach-imx/mach-mx27_3ds.c static const uint32_t mx27_3ds_keymap[] = { uint32_t 242 arch/arm/mach-imx/mach-mx31_3ds.c static const uint32_t mx31_3ds_keymap[] = { uint32_t 51 arch/arm/mach-mmp/clock-mmp2.c uint32_t clk_rst; uint32_t 60 arch/arm/mach-mmp/clock-mmp2.c uint32_t clk_rst; uint32_t 18 arch/arm/mach-mmp/clock.c uint32_t clk_rst; uint32_t 17 arch/arm/mach-mmp/clock.h uint32_t enable_val; /* value for clock enable (APMU) */ uint32_t 114 arch/arm/mach-mmp/pm-mmp2.c uint32_t idle_cfg, apcr; uint32_t 219 arch/arm/mach-mmp/pm-mmp2.c uint32_t apcr; uint32_t 29 arch/arm/mach-mmp/pm-pxa910.c uint32_t awucrm = 0, apcr = 0; uint32_t 134 arch/arm/mach-mmp/pm-pxa910.c uint32_t idle_cfg, apcr; uint32_t 254 arch/arm/mach-mmp/pm-pxa910.c uint32_t awucrm = 0; uint32_t 84 arch/arm/mach-mmp/pxa168.c uint32_t val; uint32_t 85 arch/arm/mach-mmp/pxa168.c uint32_t mask = APMU_PXA168_KP_WAKE_CLR; uint32_t 49 arch/arm/mach-mmp/time.c static inline uint32_t timer_read(void) uint32_t 154 arch/arm/mach-mmp/time.c uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR); uint32_t 190 arch/arm/mach-omap1/dma.c uint32_t val; uint32_t 313 arch/arm/mach-pxa/corgi.c static const uint32_t corgikbd_keymap[] = { uint32_t 68 arch/arm/mach-pxa/irq.c uint32_t icmr = __raw_readl(base + ICMR); uint32_t 78 arch/arm/mach-pxa/irq.c uint32_t icmr = __raw_readl(base + ICMR); uint32_t 93 arch/arm/mach-pxa/irq.c uint32_t icip, icmr, mask; uint32_t 109 arch/arm/mach-pxa/irq.c uint32_t ichp; uint32_t 112 arch/arm/mach-pxa/lubbock.c void lubbock_set_hexled(uint32_t value) uint32_t 227 arch/arm/mach-pxa/palmtc.c static const uint32_t palmtc_matrix_keys[] = { uint32_t 36 arch/arm/mach-pxa/pm.h extern void lubbock_set_hexled(uint32_t value); uint32_t 122 arch/arm/mach-pxa/pxa25x.c uint32_t mask = 0; uint32_t 205 arch/arm/mach-pxa/pxa27x.c uint32_t mask; uint32_t 300 arch/arm/mach-pxa/spitz.c static const uint32_t spitz_keymap[] = { uint32_t 372 arch/arm/mach-pxa/spitz.c static const uint32_t spitz_row_gpios[] = uint32_t 374 arch/arm/mach-pxa/spitz.c static const uint32_t spitz_col_gpios[] = uint32_t 969 arch/arm/mach-pxa/spitz.c uint32_t msc0 = __raw_readl(MSC0); uint32_t 408 arch/arm/mach-pxa/tosa.c static const uint32_t tosakbd_keymap[] = { uint32_t 889 arch/arm/mach-pxa/tosa.c uint32_t msc0 = __raw_readl(MSC0); uint32_t 184 arch/arm/mach-s3c64xx/mach-crag6410.c static uint32_t crag6410_keymap[] = { uint32_t 240 arch/arm/mach-s3c64xx/mach-smdk6410.c static uint32_t smdk6410_keymap[] __initdata = { uint32_t 109 arch/arm/mach-vexpress/spc.c uint32_t cur_rsp_mask; uint32_t 110 arch/arm/mach-vexpress/spc.c uint32_t cur_rsp_stat; uint32_t 355 arch/arm/mach-vexpress/spc.c static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data) uint32_t 381 arch/arm/mach-vexpress/spc.c uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS); uint32_t 401 arch/arm/mach-vexpress/spc.c static int ve_spc_populate_opps(uint32_t cluster) uint32_t 403 arch/arm/mach-vexpress/spc.c uint32_t data = 0, off, ret, idx; uint32_t 53 arch/arm/xen/enlighten.c DEFINE_PER_CPU(uint32_t, xen_vcpu_id); uint32_t 62 arch/arm/xen/enlighten.c uint32_t xen_start_flags; uint32_t 187 arch/arm64/kvm/vgic-sys-reg-v3.c uint32_t *ap_reg; uint32_t 17 arch/c6x/include/asm/delay.h uint32_t tmp; uint32_t 30 arch/c6x/include/asm/delay.h uint32_t cnt, endcnt; uint32_t 13 arch/csky/abiv1/alignment.c static inline uint32_t get_ptreg(struct pt_regs *regs, uint32_t rx) uint32_t 15 arch/csky/abiv1/alignment.c return rx == 15 ? regs->lr : *((uint32_t *)&(regs->a0) - 2 + rx); uint32_t 18 arch/csky/abiv1/alignment.c static inline void put_ptreg(struct pt_regs *regs, uint32_t rx, uint32_t val) uint32_t 23 arch/csky/abiv1/alignment.c *((uint32_t *)&(regs->a0) - 2 + rx) = val; uint32_t 32 arch/csky/abiv1/alignment.c static int ldb_asm(uint32_t addr, uint32_t *valp) uint32_t 34 arch/csky/abiv1/alignment.c uint32_t val; uint32_t 65 arch/csky/abiv1/alignment.c static int stb_asm(uint32_t addr, uint32_t val) uint32_t 95 arch/csky/abiv1/alignment.c static int ldh_c(struct pt_regs *regs, uint32_t rz, uint32_t addr) uint32_t 97 arch/csky/abiv1/alignment.c uint32_t byte0, byte1; uint32_t 117 arch/csky/abiv1/alignment.c static int sth_c(struct pt_regs *regs, uint32_t rz, uint32_t addr) uint32_t 119 arch/csky/abiv1/alignment.c uint32_t byte0, byte1; uint32_t 142 arch/csky/abiv1/alignment.c static int ldw_c(struct pt_regs *regs, uint32_t rz, uint32_t addr) uint32_t 144 arch/csky/abiv1/alignment.c uint32_t byte0, byte1, byte2, byte3; uint32_t 176 arch/csky/abiv1/alignment.c static int stw_c(struct pt_regs *regs, uint32_t rz, uint32_t addr) uint32_t 178 arch/csky/abiv1/alignment.c uint32_t byte0, byte1, byte2, byte3; uint32_t 216 arch/csky/abiv1/alignment.c uint32_t opcode = 0; uint32_t 217 arch/csky/abiv1/alignment.c uint32_t rx = 0; uint32_t 218 arch/csky/abiv1/alignment.c uint32_t rz = 0; uint32_t 219 arch/csky/abiv1/alignment.c uint32_t imm = 0; uint32_t 220 arch/csky/abiv1/alignment.c uint32_t addr = 0; uint32_t 251 arch/csky/abiv1/alignment.c opcode = (uint32_t)tmp; uint32_t 29 arch/csky/kernel/module.c static void jsri_2_lrw_jsr(uint32_t *location) uint32_t 44 arch/csky/kernel/module.c static void inline jsri_2_lrw_jsr(uint32_t *location) uint32_t 56 arch/csky/kernel/module.c uint32_t *location; uint32_t 74 arch/csky/kernel/module.c - (uint32_t)location; uint32_t 43 arch/csky/kernel/perf_event.c uint32_t count_width; uint32_t 44 arch/csky/kernel/perf_event.c uint32_t hpcr; uint32_t 92 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 109 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2>", (uint32_t) val); uint32_t 110 arch/csky/kernel/perf_event.c cpwgr("<0, 0x3>", (uint32_t) (val >> 32)); uint32_t 116 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 133 arch/csky/kernel/perf_event.c cpwgr("<0, 0x4>", (uint32_t) val); uint32_t 134 arch/csky/kernel/perf_event.c cpwgr("<0, 0x5>", (uint32_t) (val >> 32)); uint32_t 140 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 157 arch/csky/kernel/perf_event.c cpwgr("<0, 0x6>", (uint32_t) val); uint32_t 158 arch/csky/kernel/perf_event.c cpwgr("<0, 0x7>", (uint32_t) (val >> 32)); uint32_t 164 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 181 arch/csky/kernel/perf_event.c cpwgr("<0, 0x8>", (uint32_t) val); uint32_t 182 arch/csky/kernel/perf_event.c cpwgr("<0, 0x9>", (uint32_t) (val >> 32)); uint32_t 188 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 205 arch/csky/kernel/perf_event.c cpwgr("<0, 0xa>", (uint32_t) val); uint32_t 206 arch/csky/kernel/perf_event.c cpwgr("<0, 0xb>", (uint32_t) (val >> 32)); uint32_t 212 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 229 arch/csky/kernel/perf_event.c cpwgr("<0, 0xc>", (uint32_t) val); uint32_t 230 arch/csky/kernel/perf_event.c cpwgr("<0, 0xd>", (uint32_t) (val >> 32)); uint32_t 236 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 253 arch/csky/kernel/perf_event.c cpwgr("<0, 0xe>", (uint32_t) val); uint32_t 254 arch/csky/kernel/perf_event.c cpwgr("<0, 0xf>", (uint32_t) (val >> 32)); uint32_t 260 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 277 arch/csky/kernel/perf_event.c cpwgr("<0, 0x10>", (uint32_t) val); uint32_t 278 arch/csky/kernel/perf_event.c cpwgr("<0, 0x11>", (uint32_t) (val >> 32)); uint32_t 284 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 301 arch/csky/kernel/perf_event.c cpwgr("<0, 0x14>", (uint32_t) val); uint32_t 302 arch/csky/kernel/perf_event.c cpwgr("<0, 0x15>", (uint32_t) (val >> 32)); uint32_t 308 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 325 arch/csky/kernel/perf_event.c cpwgr("<0, 0x16>", (uint32_t) val); uint32_t 326 arch/csky/kernel/perf_event.c cpwgr("<0, 0x17>", (uint32_t) (val >> 32)); uint32_t 332 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 349 arch/csky/kernel/perf_event.c cpwgr("<0, 0x18>", (uint32_t) val); uint32_t 350 arch/csky/kernel/perf_event.c cpwgr("<0, 0x19>", (uint32_t) (val >> 32)); uint32_t 356 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 373 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1a>", (uint32_t) val); uint32_t 374 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1b>", (uint32_t) (val >> 32)); uint32_t 380 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 397 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1c>", (uint32_t) val); uint32_t 398 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1d>", (uint32_t) (val >> 32)); uint32_t 404 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 421 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1e>", (uint32_t) val); uint32_t 422 arch/csky/kernel/perf_event.c cpwgr("<0, 0x1f>", (uint32_t) (val >> 32)); uint32_t 428 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 445 arch/csky/kernel/perf_event.c cpwgr("<0, 0x20>", (uint32_t) val); uint32_t 446 arch/csky/kernel/perf_event.c cpwgr("<0, 0x21>", (uint32_t) (val >> 32)); uint32_t 452 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 469 arch/csky/kernel/perf_event.c cpwgr("<0, 0x22>", (uint32_t) val); uint32_t 470 arch/csky/kernel/perf_event.c cpwgr("<0, 0x23>", (uint32_t) (val >> 32)); uint32_t 476 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 493 arch/csky/kernel/perf_event.c cpwgr("<0, 0x24>", (uint32_t) val); uint32_t 494 arch/csky/kernel/perf_event.c cpwgr("<0, 0x25>", (uint32_t) (val >> 32)); uint32_t 500 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 517 arch/csky/kernel/perf_event.c cpwgr("<0, 0x26>", (uint32_t) val); uint32_t 518 arch/csky/kernel/perf_event.c cpwgr("<0, 0x27>", (uint32_t) (val >> 32)); uint32_t 524 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 541 arch/csky/kernel/perf_event.c cpwgr("<0, 0x28>", (uint32_t) val); uint32_t 542 arch/csky/kernel/perf_event.c cpwgr("<0, 0x29>", (uint32_t) (val >> 32)); uint32_t 548 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 565 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2a>", (uint32_t) val); uint32_t 566 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2b>", (uint32_t) (val >> 32)); uint32_t 572 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 589 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2c>", (uint32_t) val); uint32_t 590 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2d>", (uint32_t) (val >> 32)); uint32_t 596 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 613 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2e>", (uint32_t) val); uint32_t 614 arch/csky/kernel/perf_event.c cpwgr("<0, 0x2f>", (uint32_t) (val >> 32)); uint32_t 620 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 637 arch/csky/kernel/perf_event.c cpwgr("<0, 0x30>", (uint32_t) val); uint32_t 638 arch/csky/kernel/perf_event.c cpwgr("<0, 0x31>", (uint32_t) (val >> 32)); uint32_t 644 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 661 arch/csky/kernel/perf_event.c cpwgr("<0, 0x32>", (uint32_t) val); uint32_t 662 arch/csky/kernel/perf_event.c cpwgr("<0, 0x33>", (uint32_t) (val >> 32)); uint32_t 668 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 685 arch/csky/kernel/perf_event.c cpwgr("<0, 0x34>", (uint32_t) val); uint32_t 686 arch/csky/kernel/perf_event.c cpwgr("<0, 0x35>", (uint32_t) (val >> 32)); uint32_t 692 arch/csky/kernel/perf_event.c uint32_t lo, hi, tmp; uint32_t 709 arch/csky/kernel/perf_event.c cpwgr("<0, 0x36>", (uint32_t) val); uint32_t 710 arch/csky/kernel/perf_event.c cpwgr("<0, 0x37>", (uint32_t) (val >> 32)); uint32_t 22 arch/h8300/kernel/module.c uint32_t *loc = uint32_t 23 arch/h8300/kernel/module.c (uint32_t *)(sechdrs[sechdrs[relsec].sh_info].sh_addr uint32_t 29 arch/h8300/kernel/module.c uint32_t v = sym->st_value + rela[i].r_addend; uint32_t 33 arch/h8300/kernel/module.c loc = (uint32_t *)((uint32_t)loc - 1); uint32_t 73 arch/hexagon/kernel/module.c uint32_t *location; uint32_t 74 arch/hexagon/kernel/module.c uint32_t value; uint32_t 102 arch/hexagon/kernel/module.c int dist = (int)(value - (uint32_t)location); uint32_t 109 arch/hexagon/kernel/module.c dist, value, (uint32_t)location, uint32_t 133 arch/hexagon/kernel/module.c *location = value - (uint32_t)location; uint32_t 769 arch/ia64/kernel/module.c case RF_32LSB: put_unaligned(val, (uint32_t *) location); break; uint32_t 31 arch/m68k/kernel/module.c uint32_t *location; uint32_t 51 arch/m68k/kernel/module.c *location += sym->st_value - (uint32_t)location; uint32_t 71 arch/m68k/kernel/module.c uint32_t *location; uint32_t 91 arch/m68k/kernel/module.c *location = rel[i].r_addend + sym->st_value - (uint32_t)location; uint32_t 59 arch/microblaze/lib/memcpy.c const uint32_t *i_src; uint32_t 60 arch/microblaze/lib/memcpy.c uint32_t *i_dst; uint32_t 62 arch/microblaze/lib/memmove.c const uint32_t *i_src; uint32_t 63 arch/microblaze/lib/memmove.c uint32_t *i_dst; uint32_t 52 arch/microblaze/lib/memset.c uint32_t *i_src; uint32_t 53 arch/microblaze/lib/memset.c uint32_t w32 = 0; uint32_t 60 arch/mips/boot/elf2ecoff.c uint32_t vaddr; uint32_t 61 arch/mips/boot/elf2ecoff.c uint32_t len; uint32_t 164 arch/mips/boot/elf2ecoff.c (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ uint32_t 165 arch/mips/boot/elf2ecoff.c (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ uint32_t 166 arch/mips/boot/elf2ecoff.c (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ uint32_t 167 arch/mips/boot/elf2ecoff.c (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24) )) uint32_t 279 arch/mips/boot/elf2ecoff.c uint32_t cur_vma = UINT32_MAX; uint32_t 569 arch/mips/boot/elf2ecoff.c uint32_t gap = ph[i].p_vaddr - cur_vma; uint32_t 17 arch/mips/boot/tools/relocs.c uint32_t *offset; uint32_t 169 arch/mips/boot/tools/relocs.c static uint32_t elf32_to_cpu(uint32_t val) uint32_t 177 arch/mips/boot/tools/relocs.c static uint32_t cpu_to_elf32(uint32_t val) uint32_t 442 arch/mips/boot/tools/relocs.c static void add_reloc(struct relocs *r, uint32_t offset, unsigned type) uint32_t 551 arch/mips/boot/tools/relocs.c static int write_reloc_as_bin(uint32_t v, FILE *f) uint32_t 557 arch/mips/boot/tools/relocs.c memcpy(buf, &v, sizeof(uint32_t)); uint32_t 561 arch/mips/boot/tools/relocs.c static int write_reloc_as_text(uint32_t v, FILE *f) uint32_t 569 arch/mips/boot/tools/relocs.c return sizeof(uint32_t); uint32_t 575 arch/mips/boot/tools/relocs.c int (*write_reloc)(uint32_t, FILE *) = write_reloc_as_bin; uint32_t 226 arch/mips/cavium-octeon/executive/cvmx-bootmem.c uint32_t flags) uint32_t 437 arch/mips/cavium-octeon/executive/cvmx-bootmem.c int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags) uint32_t 574 arch/mips/cavium-octeon/executive/cvmx-bootmem.c cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags) uint32_t 636 arch/mips/cavium-octeon/executive/cvmx-bootmem.c (uint32_t)CVMX_BOOTMEM_FLAG_NO_LOCKING); uint32_t 646 arch/mips/cavium-octeon/executive/cvmx-bootmem.c (uint32_t)CVMX_BOOTMEM_FLAG_NO_LOCKING); uint32_t 676 arch/mips/cavium-octeon/executive/cvmx-bootmem.c static int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags) uint32_t 729 arch/mips/cavium-octeon/executive/cvmx-bootmem.c uint32_t flags) uint32_t 49 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c uint32_t clock_div = 0; uint32_t 50 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); uint32_t 87 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data) uint32_t 49 arch/mips/cavium-octeon/executive/cvmx-l2c.c int cvmx_l2c_get_core_way_partition(uint32_t core) uint32_t 51 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t field; uint32_t 84 arch/mips/cavium-octeon/executive/cvmx-l2c.c int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask) uint32_t 86 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t field; uint32_t 87 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t valid_mask; uint32_t 142 arch/mips/cavium-octeon/executive/cvmx-l2c.c int cvmx_l2c_set_hw_way_partition(uint32_t mask) uint32_t 144 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t valid_mask; uint32_t 169 arch/mips/cavium-octeon/executive/cvmx-l2c.c void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t 170 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t clear_on_read) uint32_t 233 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint64_t cvmx_l2c_read_perf(uint32_t counter) uint32_t 466 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t tag_addr; uint32_t 467 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t index = cvmx_l2c_address_to_index(address); uint32_t 488 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t tag_addr; uint32_t 490 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t index = cvmx_l2c_address_to_index(address); uint32_t 650 arch/mips/cavium-octeon/executive/cvmx-l2c.c union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index) uint32_t 730 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t cvmx_l2c_address_to_index(uint64_t addr) uint32_t 749 arch/mips/cavium-octeon/executive/cvmx-l2c.c uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7; uint32_t 868 arch/mips/cavium-octeon/executive/cvmx-l2c.c void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index) uint32_t 871 arch/mips/cavium-octeon/executive/cvmx-l2c.c if (index > (uint32_t)cvmx_l2c_get_num_sets()) { uint32_t 877 arch/mips/cavium-octeon/executive/cvmx-l2c.c if (assoc > (uint32_t)cvmx_l2c_get_num_assoc()) { uint32_t 58 arch/mips/cavium-octeon/executive/octeon-model.c static const char *__init octeon_model_get_string_buffer(uint32_t chip_id, uint32_t 70 arch/mips/cavium-octeon/executive/octeon-model.c uint32_t fuse_data = 0; uint32_t 507 arch/mips/cavium-octeon/executive/octeon-model.c const char *__init octeon_model_get_string(uint32_t chip_id) uint32_t 233 arch/mips/cavium-octeon/octeon-usb.c uint32_t gpio_pwr[3]; uint32_t 15 arch/mips/cavium-octeon/octeon_boot.h uint32_t app_start_func_addr; uint32_t 17 arch/mips/cavium-octeon/octeon_boot.h uint32_t k0_val; uint32_t 20 arch/mips/cavium-octeon/octeon_boot.h uint32_t flags; /* flags */ uint32_t 21 arch/mips/cavium-octeon/octeon_boot.h uint32_t pad; uint32_t 27 arch/mips/cavium-octeon/octeon_boot.h uint32_t labi_signature; uint32_t 28 arch/mips/cavium-octeon/octeon_boot.h uint32_t start_core0_addr; uint32_t 29 arch/mips/cavium-octeon/octeon_boot.h uint32_t avail_coremask; uint32_t 30 arch/mips/cavium-octeon/octeon_boot.h uint32_t pci_console_active; uint32_t 31 arch/mips/cavium-octeon/octeon_boot.h uint32_t icache_prefetch_disable; uint32_t 32 arch/mips/cavium-octeon/octeon_boot.h uint32_t padding; uint32_t 34 arch/mips/cavium-octeon/octeon_boot.h uint32_t start_app_addr; uint32_t 35 arch/mips/cavium-octeon/octeon_boot.h uint32_t cur_exception_base; uint32_t 36 arch/mips/cavium-octeon/octeon_boot.h uint32_t no_mark_private_data; uint32_t 37 arch/mips/cavium-octeon/octeon_boot.h uint32_t compact_flash_common_base_addr; uint32_t 38 arch/mips/cavium-octeon/octeon_boot.h uint32_t compact_flash_attribute_base_addr; uint32_t 39 arch/mips/cavium-octeon/octeon_boot.h uint32_t led_display_base_addr; uint32_t 41 arch/mips/cavium-octeon/octeon_boot.h uint32_t start_core0_addr; uint32_t 42 arch/mips/cavium-octeon/octeon_boot.h uint32_t labi_signature; uint32_t 44 arch/mips/cavium-octeon/octeon_boot.h uint32_t pci_console_active; uint32_t 45 arch/mips/cavium-octeon/octeon_boot.h uint32_t avail_coremask; uint32_t 47 arch/mips/cavium-octeon/octeon_boot.h uint32_t padding; uint32_t 48 arch/mips/cavium-octeon/octeon_boot.h uint32_t icache_prefetch_disable; uint32_t 52 arch/mips/cavium-octeon/octeon_boot.h uint32_t cur_exception_base; uint32_t 53 arch/mips/cavium-octeon/octeon_boot.h uint32_t start_app_addr; uint32_t 55 arch/mips/cavium-octeon/octeon_boot.h uint32_t compact_flash_common_base_addr; uint32_t 56 arch/mips/cavium-octeon/octeon_boot.h uint32_t no_mark_private_data; uint32_t 58 arch/mips/cavium-octeon/octeon_boot.h uint32_t led_display_base_addr; uint32_t 59 arch/mips/cavium-octeon/octeon_boot.h uint32_t compact_flash_attribute_base_addr; uint32_t 115 arch/mips/cavium-octeon/setup.c static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) uint32_t 808 arch/mips/cavium-octeon/setup.c uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; uint32_t 312 arch/mips/cavium-octeon/smp.c uint32_t mask, new_mask; uint32_t 335 arch/mips/cavium-octeon/smp.c uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr + uint32_t 370 arch/mips/cavium-octeon/smp.c uint32_t avail_coremask; uint32_t 385 arch/mips/cavium-octeon/smp.c avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED( uint32_t 396 arch/mips/cavium-octeon/smp.c (uint32_t) (unsigned long) start_after_reset; uint32_t 37 arch/mips/generic/board-sead3.c uint32_t rev; uint32_t 54 arch/mips/generic/board-sead3.c uint32_t cfg, cpu_phandle; uint32_t 57 arch/mips/generic/board-sead3.c cfg = __raw_readl((uint32_t *)SEAD_CONFIG); uint32_t 198 arch/mips/include/asm/elf.h uint32_t isa_ext; /* Mask of processor-specific extensions */ uint32_t 199 arch/mips/include/asm/elf.h uint32_t ases; /* Mask of ASEs used */ uint32_t 200 arch/mips/include/asm/elf.h uint32_t flags1; /* Mask of general flags */ uint32_t 201 arch/mips/include/asm/elf.h uint32_t flags2; uint32_t 293 arch/mips/include/asm/mach-pmcs-msp71xx/msp_gpio_macros.h uint32_t data; uint32_t 365 arch/mips/include/asm/mips-cm.h uint32_t cfg; uint32_t 101 arch/mips/include/asm/mips-gic.h addr += (intr / 32) * sizeof(uint32_t); \ uint32_t 120 arch/mips/include/asm/mips-gic.h addr += (intr / 32) * sizeof(uint32_t); \ uint32_t 139 arch/mips/include/asm/mips-gic.h uint32_t _val; \ uint32_t 141 arch/mips/include/asm/mips-gic.h addr += (intr / 32) * sizeof(uint32_t); \ uint32_t 45 arch/mips/include/asm/netlogic/haldefs.h static inline uint32_t uint32_t 46 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg(uint64_t base, uint32_t reg) uint32_t 48 arch/mips/include/asm/netlogic/haldefs.h volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; uint32_t 54 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) uint32_t 56 arch/mips/include/asm/netlogic/haldefs.h volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; uint32_t 71 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg64(uint64_t base, uint32_t reg) uint32_t 98 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) uint32_t 128 arch/mips/include/asm/netlogic/haldefs.h static inline uint32_t uint32_t 129 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg_xkphys(uint64_t base, uint32_t reg) uint32_t 135 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) uint32_t 141 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) uint32_t 147 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) uint32_t 157 arch/mips/include/asm/netlogic/haldefs.h nlm_pcicfg_base(uint32_t devoffset) uint32_t 165 arch/mips/include/asm/netlogic/haldefs.h nlm_mmio_base(uint32_t devoffset) uint32_t 149 arch/mips/include/asm/netlogic/mips-extns.h uint32_t prid = read_c0_prid() & PRID_IMP_MASK; uint32_t 160 arch/mips/include/asm/netlogic/mips-extns.h uint32_t prid = read_c0_prid() & PRID_IMP_MASK; uint32_t 232 arch/mips/include/asm/netlogic/mips-extns.h ({ uint32_t __res; \ uint32_t 102 arch/mips/include/asm/netlogic/psb-bootinfo.h uint32_t type; /* type of memory segment */ uint32_t 274 arch/mips/include/asm/netlogic/xlp-hal/pic.h static inline uint32_t uint32_t 277 arch/mips/include/asm/netlogic/xlp-hal/pic.h return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); uint32_t 105 arch/mips/include/asm/netlogic/xlp-hal/uart.h uint32_t lcr; uint32_t 123 arch/mips/include/asm/netlogic/xlp-hal/uart.h uint32_t lsr; uint32_t 158 arch/mips/include/asm/netlogic/xlp-hal/uart.h uint32_t lcr; uint32_t 244 arch/mips/include/asm/netlogic/xlr/fmn.h static inline uint32_t nlm_cop2_enable_irqsave(void) uint32_t 246 arch/mips/include/asm/netlogic/xlr/fmn.h uint32_t sr = read_c0_status(); uint32_t 252 arch/mips/include/asm/netlogic/xlr/fmn.h static inline void nlm_cop2_disable_irqrestore(uint32_t sr) uint32_t 259 arch/mips/include/asm/netlogic/xlr/fmn.h uint32_t config; uint32_t 279 arch/mips/include/asm/netlogic/xlr/fmn.h uint32_t status; uint32_t 315 arch/mips/include/asm/netlogic/xlr/fmn.h uint32_t status, tmp; uint32_t 225 arch/mips/include/asm/netlogic/xlr/pic.h uint32_t reg; uint32_t 234 arch/mips/include/asm/netlogic/xlr/pic.h uint32_t reg; uint32_t 269 arch/mips/include/asm/netlogic/xlr/pic.h uint32_t up1, up2, low; uint32_t 281 arch/mips/include/asm/netlogic/xlr/pic.h static inline uint32_t uint32_t 290 arch/mips/include/asm/netlogic/xlr/pic.h uint32_t up, low; uint32_t 44 arch/mips/include/asm/netlogic/xlr/xlr.h uint32_t prid = read_c0_prid(); uint32_t 53 arch/mips/include/asm/netlogic/xlr/xlr.h uint32_t prid = read_c0_prid(); uint32_t 59 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t major_version; uint32_t 60 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t minor_version; uint32_t 67 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t exception_base_addr; uint32_t 68 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t stack_size; uint32_t 69 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t flags; uint32_t 70 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t core_mask; uint32_t 72 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t dram_size; uint32_t 74 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t phy_mem_desc_addr; uint32_t 76 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t debugger_flags_base_addr; uint32_t 79 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t eclock_hz; uint32_t 82 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t dclock_hz; uint32_t 84 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t reserved0; uint32_t 113 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t dfa_ref_clock_hz; uint32_t 120 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t config_flags; uint32_t 142 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t minor_version; uint32_t 143 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t major_version; uint32_t 150 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t stack_size; uint32_t 151 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t exception_base_addr; uint32_t 153 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t core_mask; uint32_t 154 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t flags; uint32_t 156 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t phy_mem_desc_addr; uint32_t 157 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t dram_size; uint32_t 159 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t eclock_hz; uint32_t 160 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t debugger_flags_base_addr; uint32_t 162 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t reserved0; uint32_t 163 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t dclock_hz; uint32_t 183 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t config_flags; uint32_t 184 arch/mips/include/asm/octeon/cvmx-bootinfo.h uint32_t dfa_ref_clock_hz; uint32_t 100 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t lock; uint32_t 102 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t flags; uint32_t 106 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t major_version; uint32_t 112 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t minor_version; uint32_t 118 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t named_block_num_blocks; uint32_t 121 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t named_block_name_len; uint32_t 125 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t flags; uint32_t 126 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t lock; uint32_t 129 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t minor_version; uint32_t 130 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t major_version; uint32_t 134 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t named_block_name_len; uint32_t 135 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t named_block_num_blocks; uint32_t 275 arch/mips/include/asm/octeon/cvmx-bootmem.h uint32_t flags); uint32_t 302 arch/mips/include/asm/octeon/cvmx-bootmem.h char *name, uint32_t flags); uint32_t 321 arch/mips/include/asm/octeon/cvmx-bootmem.h int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags); uint32_t 133 arch/mips/include/asm/octeon/cvmx-cmd-queue.h uint32_t max_depth; uint32_t 39 arch/mips/include/asm/octeon/cvmx-helper-jtag.h extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data); uint32_t 169 arch/mips/include/asm/octeon/cvmx-l2c.h void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t 170 arch/mips/include/asm/octeon/cvmx-l2c.h uint32_t clear_on_read); uint32_t 180 arch/mips/include/asm/octeon/cvmx-l2c.h uint64_t cvmx_l2c_read_perf(uint32_t counter); uint32_t 191 arch/mips/include/asm/octeon/cvmx-l2c.h int cvmx_l2c_get_core_way_partition(uint32_t core); uint32_t 209 arch/mips/include/asm/octeon/cvmx-l2c.h int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); uint32_t 235 arch/mips/include/asm/octeon/cvmx-l2c.h int cvmx_l2c_set_hw_way_partition(uint32_t mask); uint32_t 299 arch/mips/include/asm/octeon/cvmx-l2c.h union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index); uint32_t 302 arch/mips/include/asm/octeon/cvmx-l2c.h static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t 303 arch/mips/include/asm/octeon/cvmx-l2c.h uint32_t index) uint32_t 305 arch/mips/include/asm/octeon/cvmx-l2c.h static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t 306 arch/mips/include/asm/octeon/cvmx-l2c.h uint32_t index) uint32_t 319 arch/mips/include/asm/octeon/cvmx-l2c.h uint32_t cvmx_l2c_address_to_index(uint64_t addr); uint32_t 362 arch/mips/include/asm/octeon/cvmx-l2c.h void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index); uint32_t 141 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t u32; uint32_t 144 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t reserved_18_31:14; uint32_t 145 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t addr_idx:14; uint32_t 146 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t ca:1; uint32_t 147 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t end_swp:2; uint32_t 148 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t addr_v:1; uint32_t 150 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t addr_v:1; uint32_t 151 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t end_swp:2; uint32_t 152 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t ca:1; uint32_t 153 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t addr_idx:14; uint32_t 154 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t reserved_18_31:14; uint32_t 949 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t u32; uint32_t 952 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t reserved_16_31:16; uint32_t 953 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t dbell:16; uint32_t 955 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t dbell:16; uint32_t 956 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint32_t reserved_16_31:16; uint32_t 118 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 121 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_18_31:14; uint32_t 122 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t addr_idx:14; uint32_t 123 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ca:1; uint32_t 124 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t end_swp:2; uint32_t 125 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t addr_v:1; uint32_t 127 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t addr_v:1; uint32_t 128 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t end_swp:2; uint32_t 129 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ca:1; uint32_t 130 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t addr_idx:14; uint32_t 131 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_18_31:14; uint32_t 168 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 171 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t devid:16; uint32_t 172 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t vendid:16; uint32_t 174 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t vendid:16; uint32_t 175 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t devid:16; uint32_t 181 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 184 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dpe:1; uint32_t 185 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t sse:1; uint32_t 186 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t rma:1; uint32_t 187 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t rta:1; uint32_t 188 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t sta:1; uint32_t 189 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t devt:2; uint32_t 190 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdpe:1; uint32_t 191 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t fbb:1; uint32_t 192 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_22_22:1; uint32_t 193 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t m66:1; uint32_t 194 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cle:1; uint32_t 195 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t i_stat:1; uint32_t 196 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_11_18:8; uint32_t 197 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t i_dis:1; uint32_t 198 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t fbbe:1; uint32_t 199 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t see:1; uint32_t 200 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ads:1; uint32_t 201 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pee:1; uint32_t 202 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t vps:1; uint32_t 203 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mwice:1; uint32_t 204 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scse:1; uint32_t 205 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t me:1; uint32_t 206 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msae:1; uint32_t 207 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t isae:1; uint32_t 209 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t isae:1; uint32_t 210 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msae:1; uint32_t 211 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t me:1; uint32_t 212 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scse:1; uint32_t 213 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mwice:1; uint32_t 214 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t vps:1; uint32_t 215 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pee:1; uint32_t 216 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ads:1; uint32_t 217 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t see:1; uint32_t 218 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t fbbe:1; uint32_t 219 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t i_dis:1; uint32_t 220 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_11_18:8; uint32_t 221 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t i_stat:1; uint32_t 222 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cle:1; uint32_t 223 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t m66:1; uint32_t 224 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_22_22:1; uint32_t 225 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t fbb:1; uint32_t 226 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdpe:1; uint32_t 227 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t devt:2; uint32_t 228 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t sta:1; uint32_t 229 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t rta:1; uint32_t 230 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t rma:1; uint32_t 231 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t sse:1; uint32_t 232 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dpe:1; uint32_t 238 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 241 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cc:24; uint32_t 242 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t rid:8; uint32_t 244 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t rid:8; uint32_t 245 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cc:24; uint32_t 251 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 254 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bcap:1; uint32_t 255 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t brb:1; uint32_t 256 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_28_29:2; uint32_t 257 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bcod:4; uint32_t 258 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ht:8; uint32_t 259 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lt:8; uint32_t 260 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cls:8; uint32_t 262 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cls:8; uint32_t 263 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lt:8; uint32_t 264 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ht:8; uint32_t 265 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bcod:4; uint32_t 266 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_28_29:2; uint32_t 267 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t brb:1; uint32_t 268 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bcap:1; uint32_t 274 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 277 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbase:20; uint32_t 278 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbasez:8; uint32_t 279 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pf:1; uint32_t 280 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t typ:2; uint32_t 281 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mspc:1; uint32_t 283 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mspc:1; uint32_t 284 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t typ:2; uint32_t 285 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pf:1; uint32_t 286 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbasez:8; uint32_t 287 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbase:20; uint32_t 293 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 296 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t hbase:32; uint32_t 298 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t hbase:32; uint32_t 304 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 307 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbase:5; uint32_t 308 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbasez:23; uint32_t 309 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pf:1; uint32_t 310 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t typ:2; uint32_t 311 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mspc:1; uint32_t 313 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mspc:1; uint32_t 314 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t typ:2; uint32_t 315 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pf:1; uint32_t 316 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbasez:23; uint32_t 317 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbase:5; uint32_t 323 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 326 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t hbase:32; uint32_t 328 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t hbase:32; uint32_t 334 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 337 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbasez:28; uint32_t 338 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pf:1; uint32_t 339 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t typ:2; uint32_t 340 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mspc:1; uint32_t 342 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mspc:1; uint32_t 343 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t typ:2; uint32_t 344 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pf:1; uint32_t 345 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lbasez:28; uint32_t 351 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 354 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t hbase:25; uint32_t 355 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t hbasez:7; uint32_t 357 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t hbasez:7; uint32_t 358 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t hbase:25; uint32_t 364 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 367 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cisp:32; uint32_t 369 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cisp:32; uint32_t 375 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 378 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ssid:16; uint32_t 379 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ssvid:16; uint32_t 381 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ssvid:16; uint32_t 382 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ssid:16; uint32_t 388 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 391 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erbar:16; uint32_t 392 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erbarz:5; uint32_t 393 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_1_10:10; uint32_t 394 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erbar_en:1; uint32_t 396 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erbar_en:1; uint32_t 397 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_1_10:10; uint32_t 398 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erbarz:5; uint32_t 399 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erbar:16; uint32_t 405 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 408 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_8_31:24; uint32_t 409 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cp:8; uint32_t 411 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t cp:8; uint32_t 412 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_8_31:24; uint32_t 418 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 421 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ml:8; uint32_t 422 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mg:8; uint32_t 423 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t inta:8; uint32_t 424 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t il:8; uint32_t 426 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t il:8; uint32_t 427 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t inta:8; uint32_t 428 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mg:8; uint32_t 429 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ml:8; uint32_t 435 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 438 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t trdnpr:1; uint32_t 439 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t trdard:1; uint32_t 440 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t rdsati:1; uint32_t 441 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t trdrs:1; uint32_t 442 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t trtae:1; uint32_t 443 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t twsei:1; uint32_t 444 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t twsen:1; uint32_t 445 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t twtae:1; uint32_t 446 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmae:1; uint32_t 447 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tslte:3; uint32_t 448 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tilt:4; uint32_t 449 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pbe:12; uint32_t 450 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dppmr:1; uint32_t 451 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_2_2:1; uint32_t 452 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tswc:1; uint32_t 453 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mltd:1; uint32_t 455 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mltd:1; uint32_t 456 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tswc:1; uint32_t 457 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_2_2:1; uint32_t 458 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dppmr:1; uint32_t 459 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pbe:12; uint32_t 460 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tilt:4; uint32_t 461 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tslte:3; uint32_t 462 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmae:1; uint32_t 463 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t twtae:1; uint32_t 464 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t twsen:1; uint32_t 465 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t twsei:1; uint32_t 466 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t trtae:1; uint32_t 467 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t trdrs:1; uint32_t 468 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t rdsati:1; uint32_t 469 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t trdard:1; uint32_t 470 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t trdnpr:1; uint32_t 476 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 479 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tscme:32; uint32_t 481 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tscme:32; uint32_t 487 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 490 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tdsrps:32; uint32_t 492 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tdsrps:32; uint32_t 498 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 501 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mrbcm:1; uint32_t 502 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mrbci:1; uint32_t 503 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdwe:1; uint32_t 504 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdre:1; uint32_t 505 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdrimc:1; uint32_t 506 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdrrmc:3; uint32_t 507 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmes:8; uint32_t 508 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t teci:1; uint32_t 509 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmei:1; uint32_t 510 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmse:1; uint32_t 511 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmdpes:1; uint32_t 512 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmapes:1; uint32_t 513 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_9_10:2; uint32_t 514 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tibcd:1; uint32_t 515 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tibde:1; uint32_t 516 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_6_6:1; uint32_t 517 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tidomc:1; uint32_t 518 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tdomc:5; uint32_t 520 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tdomc:5; uint32_t 521 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tidomc:1; uint32_t 522 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_6_6:1; uint32_t 523 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tibde:1; uint32_t 524 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tibcd:1; uint32_t 525 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_9_10:2; uint32_t 526 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmapes:1; uint32_t 527 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmdpes:1; uint32_t 528 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmse:1; uint32_t 529 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmei:1; uint32_t 530 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t teci:1; uint32_t 531 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tmes:8; uint32_t 532 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdrrmc:3; uint32_t 533 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdrimc:1; uint32_t 534 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdre:1; uint32_t 535 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdwe:1; uint32_t 536 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mrbci:1; uint32_t 537 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mrbcm:1; uint32_t 543 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 546 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdsp:32; uint32_t 548 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mdsp:32; uint32_t 554 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 557 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scmre:32; uint32_t 559 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scmre:32; uint32_t 565 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 568 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mac:7; uint32_t 569 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_19_24:6; uint32_t 570 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t flush:1; uint32_t 571 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mra:1; uint32_t 572 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mtta:1; uint32_t 573 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mrv:8; uint32_t 574 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mttv:8; uint32_t 576 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mttv:8; uint32_t 577 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mrv:8; uint32_t 578 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mtta:1; uint32_t 579 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mra:1; uint32_t 580 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t flush:1; uint32_t 581 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_19_24:6; uint32_t 582 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mac:7; uint32_t 588 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 591 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_23_31:9; uint32_t 592 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t most:3; uint32_t 593 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mmbc:2; uint32_t 594 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t roe:1; uint32_t 595 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dpere:1; uint32_t 596 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ncp:8; uint32_t 597 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pxcid:8; uint32_t 599 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pxcid:8; uint32_t 600 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ncp:8; uint32_t 601 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dpere:1; uint32_t 602 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t roe:1; uint32_t 603 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mmbc:2; uint32_t 604 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t most:3; uint32_t 605 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_23_31:9; uint32_t 611 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 614 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_30_31:2; uint32_t 615 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scemr:1; uint32_t 616 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mcrsd:3; uint32_t 617 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mostd:3; uint32_t 618 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mmrbcd:2; uint32_t 619 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dc:1; uint32_t 620 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t usc:1; uint32_t 621 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scd:1; uint32_t 622 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t m133:1; uint32_t 623 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t w64:1; uint32_t 624 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bn:8; uint32_t 625 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dn:5; uint32_t 626 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t fn:3; uint32_t 628 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t fn:3; uint32_t 629 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dn:5; uint32_t 630 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bn:8; uint32_t 631 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t w64:1; uint32_t 632 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t m133:1; uint32_t 633 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scd:1; uint32_t 634 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t usc:1; uint32_t 635 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dc:1; uint32_t 636 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mmrbcd:2; uint32_t 637 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mostd:3; uint32_t 638 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mcrsd:3; uint32_t 639 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scemr:1; uint32_t 640 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_30_31:2; uint32_t 646 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 649 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmes:5; uint32_t 650 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t d2s:1; uint32_t 651 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t d1s:1; uint32_t 652 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t auxc:3; uint32_t 653 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dsi:1; uint32_t 654 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_20_20:1; uint32_t 655 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmec:1; uint32_t 656 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pcimiv:3; uint32_t 657 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ncp:8; uint32_t 658 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmcid:8; uint32_t 660 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmcid:8; uint32_t 661 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ncp:8; uint32_t 662 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pcimiv:3; uint32_t 663 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmec:1; uint32_t 664 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_20_20:1; uint32_t 665 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dsi:1; uint32_t 666 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t auxc:3; uint32_t 667 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t d1s:1; uint32_t 668 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t d2s:1; uint32_t 669 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmes:5; uint32_t 675 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 678 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmdia:8; uint32_t 679 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bpccen:1; uint32_t 680 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bd3h:1; uint32_t 681 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_16_21:6; uint32_t 682 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmess:1; uint32_t 683 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmedsia:2; uint32_t 684 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmds:4; uint32_t 685 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmeens:1; uint32_t 686 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_2_7:6; uint32_t 687 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ps:2; uint32_t 689 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ps:2; uint32_t 690 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_2_7:6; uint32_t 691 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmeens:1; uint32_t 692 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmds:4; uint32_t 693 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmedsia:2; uint32_t 694 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmess:1; uint32_t 695 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_16_21:6; uint32_t 696 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bd3h:1; uint32_t 697 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bpccen:1; uint32_t 698 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmdia:8; uint32_t 704 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 707 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_24_31:8; uint32_t 708 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t m64:1; uint32_t 709 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mme:3; uint32_t 710 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mmc:3; uint32_t 711 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msien:1; uint32_t 712 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ncp:8; uint32_t 713 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msicid:8; uint32_t 715 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msicid:8; uint32_t 716 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ncp:8; uint32_t 717 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msien:1; uint32_t 718 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mmc:3; uint32_t 719 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t mme:3; uint32_t 720 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t m64:1; uint32_t 721 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_24_31:8; uint32_t 727 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 730 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msi31t2:30; uint32_t 731 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_0_1:2; uint32_t 733 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_0_1:2; uint32_t 734 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msi31t2:30; uint32_t 740 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 743 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msi:32; uint32_t 745 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msi:32; uint32_t 751 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 754 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_16_31:16; uint32_t 755 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msimd:16; uint32_t 757 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t msimd:16; uint32_t 758 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_16_31:16; uint32_t 785 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 788 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_29_31:3; uint32_t 789 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb1_hole:3; uint32_t 790 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb1_siz:1; uint32_t 791 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb_ca:1; uint32_t 792 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb_es:2; uint32_t 793 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb1:1; uint32_t 794 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb0:1; uint32_t 795 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erst_n:1; uint32_t 796 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2pres:1; uint32_t 797 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scmtyp:1; uint32_t 798 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scm:1; uint32_t 799 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t en_wfilt:1; uint32_t 800 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_14_14:1; uint32_t 801 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ap_pcix:1; uint32_t 802 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ap_64ad:1; uint32_t 803 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t b12_bist:1; uint32_t 804 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmo_amod:1; uint32_t 805 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmo_fpc:3; uint32_t 806 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tsr_hwm:3; uint32_t 807 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_enb:1; uint32_t 808 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_esx:2; uint32_t 809 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_cax:1; uint32_t 811 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_cax:1; uint32_t 812 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_esx:2; uint32_t 813 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_enb:1; uint32_t 814 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tsr_hwm:3; uint32_t 815 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmo_fpc:3; uint32_t 816 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmo_amod:1; uint32_t 817 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t b12_bist:1; uint32_t 818 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ap_64ad:1; uint32_t 819 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ap_pcix:1; uint32_t 820 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_14_14:1; uint32_t 821 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t en_wfilt:1; uint32_t 822 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scm:1; uint32_t 823 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scmtyp:1; uint32_t 824 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2pres:1; uint32_t 825 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erst_n:1; uint32_t 826 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb0:1; uint32_t 827 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb1:1; uint32_t 828 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb_es:2; uint32_t 829 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb_ca:1; uint32_t 830 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb1_siz:1; uint32_t 831 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bb1_hole:3; uint32_t 832 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_29_31:3; uint32_t 837 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_20_31:12; uint32_t 838 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erst_n:1; uint32_t 839 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2pres:1; uint32_t 840 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scmtyp:1; uint32_t 841 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scm:1; uint32_t 842 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t en_wfilt:1; uint32_t 843 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_14_14:1; uint32_t 844 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ap_pcix:1; uint32_t 845 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ap_64ad:1; uint32_t 846 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t b12_bist:1; uint32_t 847 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmo_amod:1; uint32_t 848 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmo_fpc:3; uint32_t 849 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tsr_hwm:3; uint32_t 850 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_enb:1; uint32_t 851 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_esx:2; uint32_t 852 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_cax:1; uint32_t 854 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_cax:1; uint32_t 855 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_esx:2; uint32_t 856 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2_enb:1; uint32_t 857 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t tsr_hwm:3; uint32_t 858 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmo_fpc:3; uint32_t 859 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pmo_amod:1; uint32_t 860 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t b12_bist:1; uint32_t 861 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ap_64ad:1; uint32_t 862 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ap_pcix:1; uint32_t 863 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_14_14:1; uint32_t 864 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t en_wfilt:1; uint32_t 865 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scm:1; uint32_t 866 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t scmtyp:1; uint32_t 867 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t bar2pres:1; uint32_t 868 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t erst_n:1; uint32_t 869 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_20_31:12; uint32_t 875 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 878 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_16_31:16; uint32_t 879 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t inc_val:16; uint32_t 881 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t inc_val:16; uint32_t 882 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_16_31:16; uint32_t 888 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 891 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dma_cnt:32; uint32_t 893 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dma_cnt:32; uint32_t 899 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 902 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_cnt:32; uint32_t 904 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_cnt:32; uint32_t 910 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 913 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dma_time:32; uint32_t 915 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t dma_time:32; uint32_t 921 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 924 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t icnt:32; uint32_t 926 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t icnt:32; uint32_t 1800 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 1803 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_6_31:26; uint32_t 1804 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t intr:6; uint32_t 1806 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t intr:6; uint32_t 1807 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_6_31:26; uint32_t 1813 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 1816 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_cnt:16; uint32_t 1817 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ptr_cnt:16; uint32_t 1819 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t ptr_cnt:16; uint32_t 1820 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_cnt:16; uint32_t 1826 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 1829 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_cnt:32; uint32_t 1831 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_cnt:32; uint32_t 1837 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 1840 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_cnt:32; uint32_t 1842 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_cnt:32; uint32_t 1848 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 1851 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_time:32; uint32_t 1853 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t pkt_time:32; uint32_t 1859 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 1862 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_9_31:23; uint32_t 1863 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t min_data:6; uint32_t 1864 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t prefetch:3; uint32_t 1866 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t prefetch:3; uint32_t 1867 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t min_data:6; uint32_t 1868 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_9_31:23; uint32_t 1874 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 1877 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_9_31:23; uint32_t 1878 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t min_data:6; uint32_t 1879 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t prefetch:3; uint32_t 1881 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t prefetch:3; uint32_t 1882 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t min_data:6; uint32_t 1883 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_9_31:23; uint32_t 1889 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t u32; uint32_t 1892 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_9_31:23; uint32_t 1893 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t min_data:6; uint32_t 1894 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t prefetch:3; uint32_t 1896 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t prefetch:3; uint32_t 1897 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t min_data:6; uint32_t 1898 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t reserved_9_31:23; uint32_t 55 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 57 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t dpe:1, uint32_t 58 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t sse:1, uint32_t 59 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t rma:1, uint32_t 60 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t rta:1, uint32_t 61 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t sta:1, uint32_t 62 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t devt:2, uint32_t 63 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mdpe:1, uint32_t 64 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t fbb:1, uint32_t 65 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_22_22:1, uint32_t 66 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m66:1, uint32_t 67 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t cl:1, uint32_t 68 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t i_stat:1, uint32_t 69 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_11_18:8, uint32_t 70 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t i_dis:1, uint32_t 71 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t fbbe:1, uint32_t 72 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t see:1, uint32_t 73 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ids_wcc:1, uint32_t 74 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t per:1, uint32_t 75 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t vps:1, uint32_t 76 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mwice:1, uint32_t 77 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t scse:1, uint32_t 78 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t me:1, uint32_t 79 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t msae:1, uint32_t 80 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t isae:1, uint32_t 86 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 88 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t slt:8, uint32_t 89 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t subbnum:8, uint32_t 90 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t sbnum:8, uint32_t 91 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pbnum:8, uint32_t 97 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 99 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ml_addr:12, uint32_t 100 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_16_19:4, uint32_t 101 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mb_addr:12, uint32_t 102 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_0_3:4, uint32_t 108 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 110 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lmem_limit:12, uint32_t 111 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_17_19:3, uint32_t 112 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mem64b:1, uint32_t 113 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lmem_base:12, uint32_t 114 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_1_3:3, uint32_t 115 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mem64a:1, uint32_t 121 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 123 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t umem_base; uint32_t 128 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 130 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t umem_limit; uint32_t 135 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 137 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_22_31:10, uint32_t 138 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t tp:1, uint32_t 139 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ap_d:1, uint32_t 140 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ur_d:1, uint32_t 141 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t fe_d:1, uint32_t 142 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t nfe_d:1, uint32_t 143 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ce_d:1, uint32_t 144 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_15_15:1, uint32_t 145 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mrrs:3, uint32_t 146 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ns_en:1, uint32_t 147 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ap_en:1, uint32_t 148 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pf_en:1, uint32_t 149 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t etf_en:1, uint32_t 150 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mps:3, uint32_t 151 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ro_en:1, uint32_t 152 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ur_en:1, uint32_t 153 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t fe_en:1, uint32_t 154 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t nfe_en:1, uint32_t 155 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ce_en:1, uint32_t 161 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 163 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pnum:8, uint32_t 164 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_23_23:1, uint32_t 165 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t aspm:1, uint32_t 166 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lbnc:1, uint32_t 167 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t dllarc:1, uint32_t 168 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t sderc:1, uint32_t 169 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t cpm:1, uint32_t 170 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t l1el:3, uint32_t 171 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t l0el:3, uint32_t 172 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t aslpms:2, uint32_t 173 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mlw:6, uint32_t 174 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mls:4, uint32_t 180 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 182 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lab:1, uint32_t 183 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lbm:1, uint32_t 184 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t dlla:1, uint32_t 185 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t scc:1, uint32_t 186 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lt:1, uint32_t 187 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_26_26:1, uint32_t 188 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t nlw:6, uint32_t 189 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ls:4, uint32_t 190 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_12_15:4, uint32_t 191 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lab_int_enb:1, uint32_t 192 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lbm_int_enb:1, uint32_t 193 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t hawd:1, uint32_t 194 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ecpm:1, uint32_t 195 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t es:1, uint32_t 196 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ccc:1, uint32_t 197 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t rl:1, uint32_t 198 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ld:1, uint32_t 199 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t rcb:1, uint32_t 200 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_2_2:1, uint32_t 201 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t aslpc:2, uint32_t 207 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 209 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_25_31:7, uint32_t 210 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t dlls_c:1, uint32_t 211 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t emis:1, uint32_t 212 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pds:1, uint32_t 213 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mrlss:1, uint32_t 214 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ccint_d:1, uint32_t 215 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pd_c:1, uint32_t 216 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mrls_c:1, uint32_t 217 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pf_d:1, uint32_t 218 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t abp_d:1, uint32_t 219 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_13_15:3, uint32_t 220 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t dlls_en:1, uint32_t 221 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t emic:1, uint32_t 222 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pcc:1, uint32_t 223 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pic:1, uint32_t 224 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t aic:1, uint32_t 225 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t hpint_en:1, uint32_t 226 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ccint_en:1, uint32_t 227 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pd_en:1, uint32_t 228 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t mrls_en:1, uint32_t 229 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pf_en:1, uint32_t 230 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t abp_en:1, uint32_t 236 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 238 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_17_31:15, uint32_t 239 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t crssv:1, uint32_t 240 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_5_15:11, uint32_t 241 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t crssve:1, uint32_t 242 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t pmeie:1, uint32_t 243 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t sefee:1, uint32_t 244 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t senfee:1, uint32_t 245 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t secee:1, uint32_t 251 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 253 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_22_31:10, uint32_t 254 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ler:1, uint32_t 255 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ep3s:1, uint32_t 256 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ep2s:1, uint32_t 257 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ep1s:1, uint32_t 258 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t eqc:1, uint32_t 259 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t cdl:1, uint32_t 260 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t cde:4, uint32_t 261 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t csos:1, uint32_t 262 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t emc:1, uint32_t 263 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t tm:3, uint32_t 264 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t sde:1, uint32_t 265 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t hasd:1, uint32_t 266 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ec:1, uint32_t 267 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t tls:4, uint32_t 273 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 275 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_12_31:20, uint32_t 276 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t tplp:1, uint32_t 277 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_9_10:2, uint32_t 278 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ce:1, uint32_t 279 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t cc:1, uint32_t 280 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ge:1, uint32_t 281 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t gc:1, uint32_t 282 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t fep:5, uint32_t 288 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 290 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_3_31:29, uint32_t 291 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t fere:1, uint32_t 292 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t nfere:1, uint32_t 293 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t cere:1, uint32_t 299 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 301 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t rtl:16, uint32_t 302 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t rtltl:16, uint32_t 308 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 310 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_26_31:6, uint32_t 311 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t eccrc:1, uint32_t 312 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_22_24:3, uint32_t 313 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lme:6, uint32_t 314 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_12_15:4, uint32_t 315 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t link_rate:4, uint32_t 316 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t flm:1, uint32_t 317 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_6_6:1, uint32_t 318 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t dllle:1, uint32_t 319 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_4_4:1, uint32_t 320 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ra:1, uint32_t 321 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t le:1, uint32_t 322 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t sd:1, uint32_t 323 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t omr:1, uint32_t 329 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 331 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_cfg0_filt:1, uint32_t 332 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_io_filt:1, uint32_t 333 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t msg_ctrl:1, uint32_t 334 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_cpl_ecrc_filt:1, uint32_t 335 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_ecrc_filt:1, uint32_t 336 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_cpl_len_err:1, uint32_t 337 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_cpl_attr_err:1, uint32_t 338 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_cpl_tc_err:1, uint32_t 339 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_cpl_fun_err:1, uint32_t 340 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_cpl_rid_err:1, uint32_t 341 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_cpl_tag_err:1, uint32_t 342 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_lk_filt:1, uint32_t 343 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_cfg1_filt:1, uint32_t 344 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_bar_match:1, uint32_t 345 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_pois_filt:1, uint32_t 346 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t m_fun:1, uint32_t 347 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t dfcwt:1, uint32_t 348 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_11_14:4, uint32_t 349 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t skpiv:11, uint32_t 355 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h uint32_t u32; uint32_t 357 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t reserved_21_31:11, uint32_t 358 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t s_d_e:1, uint32_t 359 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t ctcrb:1, uint32_t 360 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t cpyts:1, uint32_t 361 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t dsc:1, uint32_t 362 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t le:9, uint32_t 363 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t n_fts:8, uint32_t 185 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t dropped_octets; uint32_t 187 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t dropped_packets; uint32_t 189 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t pci_raw_packets; uint32_t 191 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t octets; uint32_t 193 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t packets; uint32_t 199 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t multicast_packets; uint32_t 205 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t broadcast_packets; uint32_t 207 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t len_64_packets; uint32_t 209 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t len_65_127_packets; uint32_t 211 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t len_128_255_packets; uint32_t 213 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t len_256_511_packets; uint32_t 215 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t len_512_1023_packets; uint32_t 217 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t len_1024_1518_packets; uint32_t 219 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t len_1519_max_packets; uint32_t 221 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t fcs_align_err_packets; uint32_t 223 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t runt_packets; uint32_t 225 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t runt_crc_packets; uint32_t 227 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t oversize_packets; uint32_t 229 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t oversize_crc_packets; uint32_t 231 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t inb_packets; uint32_t 461 arch/mips/include/asm/octeon/cvmx-pip.h uint32_t initialization_vector) uint32_t 119 arch/mips/include/asm/octeon/cvmx-pko.h uint32_t packets; uint32_t 393 arch/mips/include/asm/octeon/cvmx-pko.h uint32_t tag = uint32_t 1534 arch/mips/include/asm/octeon/cvmx-pow.h static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag, uint32_t 1598 arch/mips/include/asm/octeon/cvmx-pow.h static inline void cvmx_pow_tag_sw(uint32_t tag, uint32_t 1641 arch/mips/include/asm/octeon/cvmx-pow.h static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, uint32_t 1715 arch/mips/include/asm/octeon/cvmx-pow.h static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag, uint32_t 1806 arch/mips/include/asm/octeon/cvmx-pow.h static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, uint32_t 1893 arch/mips/include/asm/octeon/cvmx-pow.h uint32_t prio_mask = 0; uint32_t 1953 arch/mips/include/asm/octeon/cvmx-pow.h uint32_t tag, uint32_t 2035 arch/mips/include/asm/octeon/cvmx-pow.h static inline void cvmx_pow_tag_sw_desched(uint32_t tag, uint32_t 2150 arch/mips/include/asm/octeon/cvmx-pow.h static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits) uint32_t 2165 arch/mips/include/asm/octeon/cvmx-pow.h static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag) uint32_t 2180 arch/mips/include/asm/octeon/cvmx-pow.h static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag) uint32_t 75 arch/mips/include/asm/octeon/cvmx-scratch.h static inline uint32_t cvmx_scratch_read32(uint64_t address) uint32_t 77 arch/mips/include/asm/octeon/cvmx-scratch.h return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address); uint32_t 124 arch/mips/include/asm/octeon/cvmx-scratch.h *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) = uint32_t 125 arch/mips/include/asm/octeon/cvmx-scratch.h (uint32_t) value; uint32_t 49 arch/mips/include/asm/octeon/cvmx-spinlock.h volatile uint32_t value; uint32_t 161 arch/mips/include/asm/octeon/cvmx-spinlock.h static inline void cvmx_spinlock_bit_lock(uint32_t *word) uint32_t 193 arch/mips/include/asm/octeon/cvmx-spinlock.h static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word) uint32_t 225 arch/mips/include/asm/octeon/cvmx-spinlock.h static inline void cvmx_spinlock_bit_unlock(uint32_t *word) uint32_t 63 arch/mips/include/asm/octeon/cvmx-sysinfo.h uint32_t stack_size; uint32_t 65 arch/mips/include/asm/octeon/cvmx-sysinfo.h uint32_t heap_size; uint32_t 69 arch/mips/include/asm/octeon/cvmx-sysinfo.h uint32_t init_core; uint32_t 75 arch/mips/include/asm/octeon/cvmx-sysinfo.h uint32_t cpu_clock_hz; uint32_t 78 arch/mips/include/asm/octeon/cvmx-sysinfo.h uint32_t dram_data_rate_hz; uint32_t 106 arch/mips/include/asm/octeon/cvmx-sysinfo.h uint32_t dfa_ref_clock_hz; uint32_t 108 arch/mips/include/asm/octeon/cvmx-sysinfo.h uint32_t bootloader_config_flags; uint32_t 97 arch/mips/include/asm/octeon/cvmx.h static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); uint32_t 98 arch/mips/include/asm/octeon/cvmx.h static inline uint32_t cvmx_get_proc_id(void) uint32_t 100 arch/mips/include/asm/octeon/cvmx.h uint32_t id; uint32_t 397 arch/mips/include/asm/octeon/cvmx.h static inline uint32_t cvmx_pop(uint32_t val) uint32_t 399 arch/mips/include/asm/octeon/cvmx.h uint32_t pop; uint32_t 482 arch/mips/include/asm/octeon/cvmx.h static inline uint32_t cvmx_octeon_num_cores(void) uint32_t 313 arch/mips/include/asm/octeon/octeon-model.h static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); uint32_t 364 arch/mips/include/asm/octeon/octeon-model.h static inline int __octeon_is_model_runtime__(uint32_t model) uint32_t 366 arch/mips/include/asm/octeon/octeon-model.h uint32_t cpuid = cvmx_get_proc_id(); uint32_t 395 arch/mips/include/asm/octeon/octeon-model.h const char *__init octeon_model_get_string(uint32_t chip_id); uint32_t 402 arch/mips/include/asm/octeon/octeon-model.h static inline uint32_t cvmx_get_octeon_family(void) uint32_t 59 arch/mips/include/asm/octeon/octeon.h uint32_t desc_version; uint32_t 60 arch/mips/include/asm/octeon/octeon.h uint32_t desc_size; uint32_t 68 arch/mips/include/asm/octeon/octeon.h uint32_t exception_base_addr; uint32_t 69 arch/mips/include/asm/octeon/octeon.h uint32_t stack_size; uint32_t 70 arch/mips/include/asm/octeon/octeon.h uint32_t heap_size; uint32_t 72 arch/mips/include/asm/octeon/octeon.h uint32_t argc; uint32_t 73 arch/mips/include/asm/octeon/octeon.h uint32_t argv[OCTEON_ARGV_MAX_ARGS]; uint32_t 85 arch/mips/include/asm/octeon/octeon.h uint32_t flags; uint32_t 86 arch/mips/include/asm/octeon/octeon.h uint32_t core_mask; uint32_t 88 arch/mips/include/asm/octeon/octeon.h uint32_t dram_size; uint32_t 90 arch/mips/include/asm/octeon/octeon.h uint32_t phy_mem_desc_addr; uint32_t 92 arch/mips/include/asm/octeon/octeon.h uint32_t debugger_flags_base_addr; uint32_t 94 arch/mips/include/asm/octeon/octeon.h uint32_t eclock_hz; uint32_t 96 arch/mips/include/asm/octeon/octeon.h uint32_t dclock_hz; uint32_t 98 arch/mips/include/asm/octeon/octeon.h uint32_t spi_clock_hz; uint32_t 110 arch/mips/include/asm/octeon/octeon.h uint32_t desc_size; uint32_t 111 arch/mips/include/asm/octeon/octeon.h uint32_t desc_version; uint32_t 119 arch/mips/include/asm/octeon/octeon.h uint32_t stack_size; uint32_t 120 arch/mips/include/asm/octeon/octeon.h uint32_t exception_base_addr; uint32_t 121 arch/mips/include/asm/octeon/octeon.h uint32_t argc; uint32_t 122 arch/mips/include/asm/octeon/octeon.h uint32_t heap_size; uint32_t 127 arch/mips/include/asm/octeon/octeon.h uint32_t argv[OCTEON_ARGV_MAX_ARGS]; uint32_t 139 arch/mips/include/asm/octeon/octeon.h uint32_t core_mask; uint32_t 140 arch/mips/include/asm/octeon/octeon.h uint32_t flags; uint32_t 142 arch/mips/include/asm/octeon/octeon.h uint32_t phy_mem_desc_addr; uint32_t 144 arch/mips/include/asm/octeon/octeon.h uint32_t dram_size; uint32_t 146 arch/mips/include/asm/octeon/octeon.h uint32_t eclock_hz; uint32_t 148 arch/mips/include/asm/octeon/octeon.h uint32_t debugger_flags_base_addr; uint32_t 150 arch/mips/include/asm/octeon/octeon.h uint32_t spi_clock_hz; uint32_t 152 arch/mips/include/asm/octeon/octeon.h uint32_t dclock_hz; uint32_t 295 arch/mips/include/asm/octeon/octeon.h static inline void octeon_npi_write32(uint64_t address, uint32_t val) uint32_t 346 arch/mips/include/asm/octeon/octeon.h static inline uint32_t octeon_npi_read32(uint64_t address) uint32_t 204 arch/mips/include/asm/sibyte/sb1250_defs.h #define _SB_MAKE32(x) ((uint32_t)(x)) uint32_t 13 arch/mips/include/asm/vr41xx/pci.h uint32_t bus_base_address; uint32_t 14 arch/mips/include/asm/vr41xx/pci.h uint32_t address_mask; uint32_t 15 arch/mips/include/asm/vr41xx/pci.h uint32_t pci_base_address; uint32_t 19 arch/mips/include/asm/vr41xx/pci.h uint32_t address_mask; uint32_t 20 arch/mips/include/asm/vr41xx/pci.h uint32_t bus_base_address; uint32_t 29 arch/mips/include/asm/vr41xx/pci.h uint32_t base_address; uint32_t 33 arch/mips/include/asm/vr41xx/pci.h uint32_t base_address; uint32_t 58 arch/mips/include/asm/vr41xx/pci.h uint32_t pci_clock_max; uint32_t 75 arch/mips/kernel/signal.c uint32_t __user *csr = sc + abi->off_sc_fpc_csr; uint32_t 94 arch/mips/kernel/signal.c uint32_t __user *csr = sc + abi->off_sc_fpc_csr; uint32_t 130 arch/mips/kernel/signal.c uint32_t __user *csr = sc + abi->off_sc_fpc_csr; uint32_t 139 arch/mips/kernel/signal.c uint32_t __user *csr = sc + abi->off_sc_fpc_csr; uint32_t 329 arch/mips/kernel/signal.c uint32_t __user *csr = sc + abi->off_sc_fpc_csr; uint32_t 330 arch/mips/kernel/signal.c uint32_t __user *used_math = sc + abi->off_sc_used_math; uint32_t 382 arch/mips/kernel/signal.c uint32_t __user *csr = sc + abi->off_sc_fpc_csr; uint32_t 383 arch/mips/kernel/signal.c uint32_t __user *used_math = sc + abi->off_sc_used_math; uint32_t 294 arch/mips/kernel/traps.c printk("Status: %08x ", (uint32_t) regs->cp0_status); uint32_t 228 arch/mips/kernel/vpe.c static int apply_r_mips_none(struct module *me, uint32_t *location, uint32_t 234 arch/mips/kernel/vpe.c static int apply_r_mips_gprel16(struct module *me, uint32_t *location, uint32_t 259 arch/mips/kernel/vpe.c static int apply_r_mips_pc16(struct module *me, uint32_t *location, uint32_t 278 arch/mips/kernel/vpe.c static int apply_r_mips_32(struct module *me, uint32_t *location, uint32_t 286 arch/mips/kernel/vpe.c static int apply_r_mips_26(struct module *me, uint32_t *location, uint32_t 311 arch/mips/kernel/vpe.c static int apply_r_mips_hi16(struct module *me, uint32_t *location, uint32_t 333 arch/mips/kernel/vpe.c static int apply_r_mips_lo16(struct module *me, uint32_t *location, uint32_t 404 arch/mips/kernel/vpe.c static int (*reloc_handlers[]) (struct module *me, uint32_t *location, uint32_t 433 arch/mips/kernel/vpe.c uint32_t *location; uint32_t 36 arch/mips/loongson32/common/time.c static uint32_t ls1x_jiffies_per_tick; uint32_t 38 arch/mips/loongson32/common/time.c static inline void ls1x_pwmtimer_set_period(uint32_t period) uint32_t 32 arch/mips/loongson64/loongson-3/smp.c static uint32_t core0_c0count[NR_CPUS]; uint32_t 301 arch/mips/loongson64/loongson-3/smp.c uint32_t initcount; uint32_t 61 arch/mips/mm/cerr-sb1.c static uint32_t extract_ic(unsigned short addr, int data); uint32_t 62 arch/mips/mm/cerr-sb1.c static uint32_t extract_dc(unsigned short addr, int data); uint32_t 133 arch/mips/mm/cerr-sb1.c uint32_t status, l2_err, memio_err; uint32_t 167 arch/mips/mm/cerr-sb1.c uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res; uint32_t 302 arch/mips/mm/cerr-sb1.c static unsigned char inst_parity(uint32_t word) uint32_t 319 arch/mips/mm/cerr-sb1.c static uint32_t extract_ic(unsigned short addr, int data) uint32_t 323 arch/mips/mm/cerr-sb1.c uint32_t taghi, taglolo, taglohi; uint32_t 380 arch/mips/mm/cerr-sb1.c uint32_t datahi, insta, instb; uint32_t 401 arch/mips/mm/cerr-sb1.c if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) { uint32_t 426 arch/mips/mm/cerr-sb1.c uint32_t w; uint32_t 435 arch/mips/mm/cerr-sb1.c w = (uint32_t)(t >> 32); uint32_t 438 arch/mips/mm/cerr-sb1.c w = (uint32_t)(t & 0xFFFFFFFF); uint32_t 475 arch/mips/mm/cerr-sb1.c static uint32_t extract_dc(unsigned short addr, int data) uint32_t 479 arch/mips/mm/cerr-sb1.c uint32_t taghi, taglolo, taglohi; uint32_t 530 arch/mips/mm/cerr-sb1.c uint32_t datalohi, datalolo, datahi; uint32_t 231 arch/mips/mti-malta/malta-dtshim.c uint32_t cpu_phandle, sc_cfg; uint32_t 217 arch/mips/netlogic/common/smp.c uint32_t core0_thr_mask, core_thr_mask; uint32_t 95 arch/mips/netlogic/xlp/ahci-init.c static void sata_clear_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit) uint32_t 97 arch/mips/netlogic/xlp/ahci-init.c uint32_t reg_val; uint32_t 103 arch/mips/netlogic/xlp/ahci-init.c static void sata_set_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit) uint32_t 105 arch/mips/netlogic/xlp/ahci-init.c uint32_t reg_val; uint32_t 113 arch/mips/netlogic/xlp/ahci-init.c uint32_t reg_val; uint32_t 163 arch/mips/netlogic/xlp/ahci-init.c uint32_t val = 0; uint32_t 183 arch/mips/netlogic/xlp/ahci-init.c uint32_t val; uint32_t 185 arch/mips/netlogic/xlp/nlm_hal.c uint32_t val; uint32_t 469 arch/mips/netlogic/xlp/nlm_hal.c uint32_t val; uint32_t 72 arch/mips/netlogic/xlp/usb-init.c uint32_t val; uint32_t 85 arch/mips/netlogic/xlp/usb-init.c uint32_t val; uint32_t 55 arch/mips/netlogic/xlp/wakeup.c uint32_t coremask, value; uint32_t 95 arch/mips/netlogic/xlp/wakeup.c volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); uint32_t 113 arch/mips/netlogic/xlp/wakeup.c uint32_t syscoremask, mask, fusemask; uint32_t 75 arch/mips/netlogic/xlr/fmn.c uint32_t mflags, bkt_status; uint32_t 123 arch/mips/netlogic/xlr/fmn.c uint32_t flags; uint32_t 196 arch/mips/netlogic/xlr/fmn.c uint32_t flags; uint32_t 151 arch/mips/netlogic/xlr/platform.c uint32_t val; uint32_t 137 arch/mips/oprofile/op_model_loongson3.c uint32_t cause, handled = IRQ_NONE; uint32_t 115 arch/mips/pci/msi-xlp.c uint32_t msi_enabled_mask; uint32_t 116 arch/mips/pci/msi-xlp.c uint32_t msi_alloc_mask; uint32_t 117 arch/mips/pci/msi-xlp.c uint32_t msix_alloc_mask; uint32_t 209 arch/mips/pci/msi-xlp.c uint32_t status_reg, bit; uint32_t 70 arch/mips/pci/ops-emma2rh.c int size, uint32_t * val) uint32_t 41 arch/mips/pci/ops-vr41xx.c writel(((uint32_t)number << 16) | ((devfn & 0xff) << 8) | uint32_t 49 arch/mips/pci/ops-vr41xx.c int size, uint32_t *val) uint32_t 51 arch/mips/pci/ops-vr41xx.c uint32_t data; uint32_t 77 arch/mips/pci/ops-vr41xx.c int size, uint32_t val) uint32_t 79 arch/mips/pci/ops-vr41xx.c uint32_t data; uint32_t 114 arch/mips/pci/pci-ar724x.c int size, uint32_t *value) uint32_t 161 arch/mips/pci/pci-ar724x.c int size, uint32_t value) uint32_t 191 arch/mips/pci/pci-bcm1480.c uint32_t cmdreg; uint32_t 89 arch/mips/pci/pci-octeon.c uint32_t dconfig; uint32_t 199 arch/mips/pci/pci-sb1250.c uint32_t cmdreg; uint32_t 105 arch/mips/pci/pci-vr41xx.c uint32_t val; uint32_t 73 arch/mips/pci/pci-vr41xx.h #define TRDYV(val) ((uint32_t)(val) & 0xffU) uint32_t 84 arch/mips/pci/pci-vr41xx.h #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U) uint32_t 108 arch/mips/pci/pci-vr41xx.h #define RTYVAL(val) (((uint32_t)(val) << 7) & 0xff00U) uint32_t 172 arch/mips/pci/pcie-octeon.c static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset) uint32_t 199 arch/mips/pci/pcie-octeon.c static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t 200 arch/mips/pci/pcie-octeon.c uint32_t val) uint32_t 309 arch/mips/pci/pcie-octeon.c static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, uint32_t 369 arch/mips/pci/pcie-octeon.c int reg, uint32_t val) uint32_t 1846 arch/mips/pci/pcie-octeon.c static int device_needs_bus_num_war(uint32_t deviceid) uint32_t 1929 arch/mips/pci/pcie-octeon.c uint32_t device0; uint32_t 2002 arch/mips/pci/pcie-octeon.c uint32_t device0; uint32_t 183 arch/mips/sibyte/bcm1480/irq.c *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0; uint32_t 34 arch/mips/sibyte/common/bus_watcher.c uint32_t l2_err; uint32_t 35 arch/mips/sibyte/common/bus_watcher.c uint32_t memio_err; uint32_t 47 arch/mips/sibyte/common/bus_watcher.c static void print_summary(uint32_t status, uint32_t l2_err, uint32_t 48 arch/mips/sibyte/common/bus_watcher.c uint32_t memio_err) uint32_t 245 arch/mips/sibyte/common/cfe.c cfe_eptseal = (uint32_t)(unsigned long)prom_vec; uint32_t 264 arch/mips/sibyte/common/cfe.c cfe_eptseal = (unsigned int)((uint32_t *)prom_vec)[3]; uint32_t 166 arch/mips/sibyte/sb1250/irq.c *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0; uint32_t 67 arch/mips/vdso/genvdso.h uint32_t flags; uint32_t 56 arch/nios2/kernel/module.c uint32_t word; uint32_t 57 arch/nios2/kernel/module.c uint32_t *loc uint32_t 65 arch/nios2/kernel/module.c uint32_t v = sym->st_value + rela[i].r_addend; uint32_t 78 arch/nios2/kernel/module.c v -= (uint32_t)loc + 4; uint32_t 95 arch/nios2/kernel/module.c if ((v >> 28) != ((uint32_t)loc >> 28)) { uint32_t 25 arch/openrisc/kernel/module.c uint32_t *location; uint32_t 26 arch/openrisc/kernel/module.c uint32_t value; uint32_t 52 arch/openrisc/kernel/module.c value -= (uint32_t)location; uint32_t 30 arch/openrisc/lib/memcpy.c uint32_t *dest_w = (uint32_t *)dest, *src_w = (uint32_t *)src; uint32_t 105 arch/openrisc/lib/memcpy.c uint32_t *dest_w = (uint32_t *)dest, *src_w = (uint32_t *)src; uint32_t 43 arch/parisc/include/asm/hardware.h volatile uint32_t nothing; /* reg 0 */ uint32_t 44 arch/parisc/include/asm/hardware.h volatile uint32_t io_eim; uint32_t 45 arch/parisc/include/asm/hardware.h volatile uint32_t io_dc_adata; uint32_t 46 arch/parisc/include/asm/hardware.h volatile uint32_t io_ii_cdata; uint32_t 47 arch/parisc/include/asm/hardware.h volatile uint32_t io_dma_link; /* reg 4 */ uint32_t 48 arch/parisc/include/asm/hardware.h volatile uint32_t io_dma_command; uint32_t 49 arch/parisc/include/asm/hardware.h volatile uint32_t io_dma_address; uint32_t 50 arch/parisc/include/asm/hardware.h volatile uint32_t io_dma_count; uint32_t 51 arch/parisc/include/asm/hardware.h volatile uint32_t io_flex; /* reg 8 */ uint32_t 52 arch/parisc/include/asm/hardware.h volatile uint32_t io_spa_address; uint32_t 53 arch/parisc/include/asm/hardware.h volatile uint32_t reserved1[2]; uint32_t 54 arch/parisc/include/asm/hardware.h volatile uint32_t io_command; /* reg 12 */ uint32_t 55 arch/parisc/include/asm/hardware.h volatile uint32_t io_status; uint32_t 56 arch/parisc/include/asm/hardware.h volatile uint32_t io_control; uint32_t 57 arch/parisc/include/asm/hardware.h volatile uint32_t io_data; uint32_t 58 arch/parisc/include/asm/hardware.h volatile uint32_t reserved2; /* reg 16 */ uint32_t 59 arch/parisc/include/asm/hardware.h volatile uint32_t chain_addr; uint32_t 60 arch/parisc/include/asm/hardware.h volatile uint32_t sub_mask_clr; uint32_t 61 arch/parisc/include/asm/hardware.h volatile uint32_t reserved3[13]; uint32_t 62 arch/parisc/include/asm/hardware.h volatile uint32_t undefined[480]; uint32_t 63 arch/parisc/include/asm/hardware.h volatile uint32_t unpriv[512]; uint32_t 67 arch/parisc/include/asm/hardware.h volatile uint32_t unused1[12]; uint32_t 68 arch/parisc/include/asm/hardware.h volatile uint32_t io_command; uint32_t 69 arch/parisc/include/asm/hardware.h volatile uint32_t io_status; uint32_t 70 arch/parisc/include/asm/hardware.h volatile uint32_t io_control; uint32_t 71 arch/parisc/include/asm/hardware.h volatile uint32_t unused2[1]; uint32_t 72 arch/parisc/include/asm/hardware.h volatile uint32_t io_err_resp; uint32_t 73 arch/parisc/include/asm/hardware.h volatile uint32_t io_err_info; uint32_t 74 arch/parisc/include/asm/hardware.h volatile uint32_t io_err_req; uint32_t 75 arch/parisc/include/asm/hardware.h volatile uint32_t unused3[11]; uint32_t 76 arch/parisc/include/asm/hardware.h volatile uint32_t io_io_low; uint32_t 77 arch/parisc/include/asm/hardware.h volatile uint32_t io_io_high; uint32_t 562 arch/parisc/kernel/module.c (uint32_t)loc, val, addend, uint32_t 181 arch/parisc/kernel/perf.c static int perf_config(uint32_t *image_ptr); uint32_t 189 arch/parisc/kernel/perf.c static int perf_stop_counters(uint32_t *raddr); uint32_t 190 arch/parisc/kernel/perf.c static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num); uint32_t 191 arch/parisc/kernel/perf.c static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer); uint32_t 192 arch/parisc/kernel/perf.c static int perf_rdr_clear(uint32_t rdr_num); uint32_t 194 arch/parisc/kernel/perf.c static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer); uint32_t 197 arch/parisc/kernel/perf.c extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width); uint32_t 198 arch/parisc/kernel/perf.c extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width); uint32_t 199 arch/parisc/kernel/perf.c extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer); uint32_t 200 arch/parisc/kernel/perf.c extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer); uint32_t 215 arch/parisc/kernel/perf.c static int perf_config(uint32_t *image_ptr) uint32_t 218 arch/parisc/kernel/perf.c uint32_t raddr[4]; uint32_t 240 arch/parisc/kernel/perf.c return sizeof(uint32_t); uint32_t 292 arch/parisc/kernel/perf.c uint32_t image_type; uint32_t 293 arch/parisc/kernel/perf.c uint32_t interface_type; uint32_t 294 arch/parisc/kernel/perf.c uint32_t test; uint32_t 306 arch/parisc/kernel/perf.c if (count != sizeof(uint32_t)) uint32_t 309 arch/parisc/kernel/perf.c if (copy_from_user(&image_type, buf, sizeof(uint32_t))) uint32_t 361 arch/parisc/kernel/perf.c uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0); uint32_t 362 arch/parisc/kernel/perf.c uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0); uint32_t 363 arch/parisc/kernel/perf.c uint32_t IVAaddress = (uint32_t)&PA2_0_iva; uint32_t 430 arch/parisc/kernel/perf.c uint32_t raddr[4]; uint32_t 549 arch/parisc/kernel/perf.c static int perf_stop_counters(uint32_t *raddr) uint32_t 569 arch/parisc/kernel/perf.c raddr[0] = (uint32_t)tmp64; uint32_t 575 arch/parisc/kernel/perf.c raddr[1] = (uint32_t)tmp64; uint32_t 582 arch/parisc/kernel/perf.c raddr[2] = (uint32_t)tmp64; uint32_t 588 arch/parisc/kernel/perf.c raddr[3] = (uint32_t)tmp64; uint32_t 627 arch/parisc/kernel/perf.c raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL); uint32_t 628 arch/parisc/kernel/perf.c raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL); uint32_t 629 arch/parisc/kernel/perf.c raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL); uint32_t 630 arch/parisc/kernel/perf.c raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL); uint32_t 642 arch/parisc/kernel/perf.c static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num) uint32_t 656 arch/parisc/kernel/perf.c static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer) uint32_t 659 arch/parisc/kernel/perf.c uint32_t width, xbits, i; uint32_t 706 arch/parisc/kernel/perf.c static int perf_rdr_clear(uint32_t rdr_num) uint32_t 739 arch/parisc/kernel/perf.c uint32_t dwords; uint32_t 740 arch/parisc/kernel/perf.c const uint32_t *intrigue_rdr; uint32_t 820 arch/parisc/kernel/perf.c static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer) uint32_t 15 arch/parisc/kernel/perf_images.h static uint32_t onyx_images[][PCXU_IMAGE_SIZE/sizeof(uint32_t)] __ro_after_init = { uint32_t 2083 arch/parisc/kernel/perf_images.h static uint32_t cuda_images[][PCXW_IMAGE_SIZE/sizeof(uint32_t)] __ro_after_init = { uint32_t 30 arch/powerpc/boot/mktree.c uint32_t bb_magic; /* 0x0052504F */ uint32_t 31 arch/powerpc/boot/mktree.c uint32_t bb_dest; /* Target address of the image */ uint32_t 32 arch/powerpc/boot/mktree.c uint32_t bb_num_512blocks; /* Size, rounded-up, in 512 byte blks */ uint32_t 33 arch/powerpc/boot/mktree.c uint32_t bb_debug_flag; /* Run debugger or image after load */ uint32_t 34 arch/powerpc/boot/mktree.c uint32_t bb_entry_point; /* The image address to start */ uint32_t 35 arch/powerpc/boot/mktree.c uint32_t bb_checksum; /* 32 bit checksum including header */ uint32_t 36 arch/powerpc/boot/mktree.c uint32_t reserved[2]; uint32_t 14 arch/powerpc/boot/xz_config.h static inline uint32_t swab32p(void *p) uint32_t 16 arch/powerpc/boot/xz_config.h uint32_t *q = p; uint32_t 22 arch/powerpc/boot/xz_config.h #define get_le32(p) (*((uint32_t *) (p))) uint32_t 37 arch/powerpc/boot/xz_config.h static inline uint32_t get_unaligned_be32(const void *p) uint32_t 137 arch/powerpc/include/asm/epapr_hcalls.h uint32_t config, unsigned int priority, uint32_t destination) uint32_t 169 arch/powerpc/include/asm/epapr_hcalls.h uint32_t *config, unsigned int *priority, uint32_t *destination) uint32_t 292 arch/powerpc/include/asm/epapr_hcalls.h const uint32_t *p = (const uint32_t *) buffer; uint32_t 335 arch/powerpc/include/asm/epapr_hcalls.h uint32_t *p = (uint32_t *) buffer; uint32_t 125 arch/powerpc/include/asm/fsl_hcalls.h uint32_t *propvalue_len) uint32_t 149 arch/powerpc/include/asm/fsl_hcalls.h r5 = (uint32_t)dtpath_addr; uint32_t 150 arch/powerpc/include/asm/fsl_hcalls.h r7 = (uint32_t)propname_addr; uint32_t 151 arch/powerpc/include/asm/fsl_hcalls.h r9 = (uint32_t)propvalue_addr; uint32_t 179 arch/powerpc/include/asm/fsl_hcalls.h uint32_t propvalue_len) uint32_t 203 arch/powerpc/include/asm/fsl_hcalls.h r5 = (uint32_t)dtpath_addr; uint32_t 204 arch/powerpc/include/asm/fsl_hcalls.h r7 = (uint32_t)propname_addr; uint32_t 205 arch/powerpc/include/asm/fsl_hcalls.h r9 = (uint32_t)propvalue_addr; uint32_t 286 arch/powerpc/include/asm/fsl_hcalls.h uint32_t entry_point, int load) uint32_t 370 arch/powerpc/include/asm/fsl_hcalls.h r5 = (uint32_t) sg_list; uint32_t 492 arch/powerpc/include/asm/fsl_hcalls.h static inline unsigned int fh_err_get_info(int queue, uint32_t *bufsize, uint32_t 493 arch/powerpc/include/asm/fsl_hcalls.h uint32_t addr_hi, uint32_t addr_lo, int peek) uint32_t 24 arch/powerpc/include/asm/hvconsole.h extern int hvc_get_chars(uint32_t vtermno, char *buf, int count); uint32_t 25 arch/powerpc/include/asm/hvconsole.h extern int hvc_put_chars(uint32_t vtermno, const char *buf, int count); uint32_t 33 arch/powerpc/include/asm/hvcserver.h uint32_t unit_address; uint32_t 34 arch/powerpc/include/asm/hvcserver.h uint32_t partition_ID; uint32_t 39 arch/powerpc/include/asm/hvcserver.h extern int hvcs_get_partner_info(uint32_t unit_address, uint32_t 41 arch/powerpc/include/asm/hvcserver.h extern int hvcs_register_connection(uint32_t unit_address, uint32_t 42 arch/powerpc/include/asm/hvcserver.h uint32_t p_partition_ID, uint32_t p_unit_address); uint32_t 43 arch/powerpc/include/asm/hvcserver.h extern int hvcs_free_connection(uint32_t unit_address); uint32_t 75 arch/powerpc/include/asm/hvsi.h int (*get_chars)(uint32_t termno, char *buf, int count); uint32_t 76 arch/powerpc/include/asm/hvsi.h int (*put_chars)(uint32_t termno, const char *buf, int count); uint32_t 77 arch/powerpc/include/asm/hvsi.h uint32_t termno; uint32_t 83 arch/powerpc/include/asm/hvsi.h int (*get_chars)(uint32_t termno, char *buf, int count), uint32_t 84 arch/powerpc/include/asm/hvsi.h int (*put_chars)(uint32_t termno, const char *buf, uint32_t 42 arch/powerpc/include/asm/io_event_irq.h uint32_t drc_index; /* 0x04 DRC Index */ uint32_t 1042 arch/powerpc/include/asm/kvm_ppc.h ea = (uint32_t)ea; uint32_t 36 arch/powerpc/include/asm/opal.h int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn, uint32_t 38 arch/powerpc/include/asm/opal.h int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn, uint32_t 40 arch/powerpc/include/asm/opal.h int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap, uint32_t 41 arch/powerpc/include/asm/opal.h uint64_t rate_phys, uint32_t size); uint32_t 52 arch/powerpc/include/asm/opal.h int64_t opal_rtc_write(uint32_t year_month_day, uint32_t 55 arch/powerpc/include/asm/opal.h int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day, uint32_t 56 arch/powerpc/include/asm/opal.h uint32_t hour_min); uint32_t 59 arch/powerpc/include/asm/opal.h int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag); uint32_t 79 arch/powerpc/include/asm/opal.h uint64_t offset, uint32_t data); uint32_t 80 arch/powerpc/include/asm/opal.h int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); uint32_t 81 arch/powerpc/include/asm/opal.h int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority); uint32_t 93 arch/powerpc/include/asm/opal.h int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type, uint32_t 94 arch/powerpc/include/asm/opal.h uint32_t func, uint64_t addr, uint64_t mask); uint32_t 116 arch/powerpc/include/asm/opal.h int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe, uint32_t 118 arch/powerpc/include/asm/opal.h int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number); uint32_t 119 arch/powerpc/include/asm/opal.h int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, uint32_t 120 arch/powerpc/include/asm/opal.h uint32_t state); uint32_t 121 arch/powerpc/include/asm/opal.h int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number, uint32_t 123 arch/powerpc/include/asm/opal.h int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, uint32_t 125 arch/powerpc/include/asm/opal.h int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq); uint32_t 126 arch/powerpc/include/asm/opal.h int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, uint32_t 127 arch/powerpc/include/asm/opal.h uint32_t xive_num); uint32_t 128 arch/powerpc/include/asm/opal.h int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, uint32_t 130 arch/powerpc/include/asm/opal.h int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, uint32_t 133 arch/powerpc/include/asm/opal.h int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, uint32_t 134 arch/powerpc/include/asm/opal.h uint32_t xive_num, uint8_t msi_range, uint32_t 167 arch/powerpc/include/asm/opal.h int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val); uint32_t 168 arch/powerpc/include/asm/opal.h int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val); uint32_t 170 arch/powerpc/include/asm/opal.h int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, uint32_t 171 arch/powerpc/include/asm/opal.h uint32_t addr, uint32_t data, uint32_t sz); uint32_t 172 arch/powerpc/include/asm/opal.h int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type, uint32_t 173 arch/powerpc/include/asm/opal.h uint32_t addr, __be32 *data, uint32_t sz); uint32_t 181 arch/powerpc/include/asm/opal.h int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result); uint32_t 187 arch/powerpc/include/asm/opal.h int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer); uint32_t 188 arch/powerpc/include/asm/opal.h int64_t opal_dump_ack(uint32_t dump_id); uint32_t 196 arch/powerpc/include/asm/opal.h int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer, uint32_t 198 arch/powerpc/include/asm/opal.h int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer, uint32_t 200 arch/powerpc/include/asm/opal.h int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data); uint32_t 204 arch/powerpc/include/asm/opal.h int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end); uint32_t 205 arch/powerpc/include/asm/opal.h int64_t opal_unregister_dump_region(uint32_t id); uint32_t 215 arch/powerpc/include/asm/opal.h int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id, uint32_t 229 arch/powerpc/include/asm/opal.h int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len); uint32_t 236 arch/powerpc/include/asm/opal.h int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll); uint32_t 238 arch/powerpc/include/asm/opal.h int64_t opal_int_eoi(uint32_t xirr); uint32_t 239 arch/powerpc/include/asm/opal.h int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr); uint32_t 240 arch/powerpc/include/asm/opal.h int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type, uint32_t 241 arch/powerpc/include/asm/opal.h uint32_t pe_num, uint32_t tce_size, uint32_t 242 arch/powerpc/include/asm/opal.h uint64_t dma_addr, uint32_t npages); uint32_t 245 arch/powerpc/include/asm/opal.h int64_t opal_xive_get_irq_info(uint32_t girq, uint32_t 251 arch/powerpc/include/asm/opal.h int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp, uint32_t 253 arch/powerpc/include/asm/opal.h int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio, uint32_t 254 arch/powerpc/include/asm/opal.h uint32_t lirq); uint32_t 255 arch/powerpc/include/asm/opal.h int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, uint32_t 261 arch/powerpc/include/asm/opal.h int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, uint32_t 265 arch/powerpc/include/asm/opal.h int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr); uint32_t 266 arch/powerpc/include/asm/opal.h int64_t opal_xive_alloc_vp_block(uint32_t alloc_order); uint32_t 276 arch/powerpc/include/asm/opal.h int64_t opal_xive_allocate_irq_raw(uint32_t chip_id); uint32_t 277 arch/powerpc/include/asm/opal.h int64_t opal_xive_free_irq(uint32_t girq); uint32_t 278 arch/powerpc/include/asm/opal.h int64_t opal_xive_sync(uint32_t type, uint32_t id); uint32_t 279 arch/powerpc/include/asm/opal.h int64_t opal_xive_dump(uint32_t type, uint32_t id); uint32_t 280 arch/powerpc/include/asm/opal.h int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio, uint32_t 283 arch/powerpc/include/asm/opal.h int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio, uint32_t 284 arch/powerpc/include/asm/opal.h uint32_t qtoggle, uint32_t 285 arch/powerpc/include/asm/opal.h uint32_t qindex); uint32_t 288 arch/powerpc/include/asm/opal.h int64_t opal_imc_counters_init(uint32_t type, uint64_t address, uint32_t 290 arch/powerpc/include/asm/opal.h int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir); uint32_t 291 arch/powerpc/include/asm/opal.h int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir); uint32_t 299 arch/powerpc/include/asm/opal.h int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct); uint32_t 315 arch/powerpc/include/asm/opal.h extern int opal_get_chars(uint32_t vtermno, char *buf, int count); uint32_t 316 arch/powerpc/include/asm/opal.h extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); uint32_t 317 arch/powerpc/include/asm/opal.h extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len); uint32_t 318 arch/powerpc/include/asm/opal.h extern int opal_flush_chars(uint32_t vtermno, bool wait); uint32_t 319 arch/powerpc/include/asm/opal.h extern int opal_flush_console(uint32_t vtermno); uint32_t 20 arch/powerpc/include/asm/pnv-pci.h extern int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len); uint32_t 111 arch/powerpc/include/asm/processor.h uint32_t dbcr0; uint32_t 112 arch/powerpc/include/asm/processor.h uint32_t dbcr1; uint32_t 114 arch/powerpc/include/asm/processor.h uint32_t dbcr2; uint32_t 122 arch/powerpc/include/asm/processor.h uint32_t dbsr; uint32_t 206 arch/powerpc/include/asm/rtas.h uint32_t rtas_error_extended_log_length(const struct rtas_error_log *elog) uint32_t 263 arch/powerpc/include/asm/rtas.h inline uint32_t rtas_ext_event_company_id(struct rtas_ext_event_log_v6 *ext_log) uint32_t 60 arch/powerpc/include/asm/string.h extern void *__memset32(uint32_t *, uint32_t v, __kernel_size_t); uint32_t 68 arch/powerpc/include/asm/string.h static inline void *memset32(uint32_t *p, uint32_t v, __kernel_size_t n) uint32_t 99 arch/powerpc/include/asm/vio.h uint32_t unit_address; uint32_t 100 arch/powerpc/include/asm/vio.h uint32_t resource_id; uint32_t 127 arch/powerpc/include/asm/xive.h extern int xive_native_get_queue_info(u32 vp_id, uint32_t prio, uint32_t 134 arch/powerpc/include/asm/xive.h extern int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle, uint32_t 136 arch/powerpc/include/asm/xive.h extern int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle, uint32_t 43 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t isa; uint32_t 44 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t usable_privilege; uint32_t 45 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t hv_support; uint32_t 46 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t os_support; uint32_t 47 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t hfscr_bit_nr; uint32_t 48 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t fscr_bit_nr; uint32_t 49 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t hwcap_bit_nr; uint32_t 178 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t word = f->hwcap_bit_nr / 32; uint32_t 179 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t bit = f->hwcap_bit_nr % 32; uint32_t 211 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t word = f->hwcap_bit_nr / 32; uint32_t 212 arch/powerpc/kernel/dt_cpu_ftrs.c uint32_t bit = f->hwcap_bit_nr % 32; uint32_t 1824 arch/powerpc/kernel/eeh.c uint32_t phbid, pe_no; uint32_t 1889 arch/powerpc/kernel/eeh.c uint32_t domain, bus, dev, fn; uint32_t 2030 arch/powerpc/kernel/eeh.c uint32_t domain, bus, dev, fn; uint32_t 703 arch/powerpc/kernel/eeh_pe.c uint32_t val; uint32_t 72 arch/powerpc/kernel/module_32.c uint32_t *x, *y, tmp; uint32_t 75 arch/powerpc/kernel/module_32.c y = (uint32_t *)_x; uint32_t 76 arch/powerpc/kernel/module_32.c x = (uint32_t *)_y; uint32_t 78 arch/powerpc/kernel/module_32.c for (i = 0; i < sizeof(Elf32_Rela) / sizeof(uint32_t); i++) { uint32_t 172 arch/powerpc/kernel/module_32.c static uint32_t do_plt_call(void *location, uint32_t 189 arch/powerpc/kernel/module_32.c if (entry_matches(entry, val)) return (uint32_t)entry; uint32_t 205 arch/powerpc/kernel/module_32.c return (uint32_t)entry; uint32_t 217 arch/powerpc/kernel/module_32.c uint32_t *location; uint32_t 218 arch/powerpc/kernel/module_32.c uint32_t value; uint32_t 236 arch/powerpc/kernel/module_32.c *(uint32_t *)location = value; uint32_t 258 arch/powerpc/kernel/module_32.c if ((int)(value - (uint32_t)location) < -0x02000000 uint32_t 259 arch/powerpc/kernel/module_32.c || (int)(value - (uint32_t)location) >= 0x02000000) uint32_t 265 arch/powerpc/kernel/module_32.c value, (uint32_t)location); uint32_t 267 arch/powerpc/kernel/module_32.c *(uint32_t *)location); uint32_t 268 arch/powerpc/kernel/module_32.c *(uint32_t *)location uint32_t 269 arch/powerpc/kernel/module_32.c = (*(uint32_t *)location & ~0x03fffffc) uint32_t 270 arch/powerpc/kernel/module_32.c | ((value - (uint32_t)location) uint32_t 273 arch/powerpc/kernel/module_32.c *(uint32_t *)location); uint32_t 275 arch/powerpc/kernel/module_32.c *(uint32_t *)location & 0x03fffffc, uint32_t 276 arch/powerpc/kernel/module_32.c (uint32_t)location, uint32_t 277 arch/powerpc/kernel/module_32.c (*(uint32_t *)location & 0x03fffffc) uint32_t 278 arch/powerpc/kernel/module_32.c + (uint32_t)location); uint32_t 283 arch/powerpc/kernel/module_32.c *(uint32_t *)location = value - (uint32_t)location; uint32_t 659 arch/powerpc/kernel/module_64.c *(uint32_t *)location uint32_t 660 arch/powerpc/kernel/module_64.c = (*(uint32_t *)location & ~0x03fffffc) uint32_t 702 arch/powerpc/kernel/module_64.c if ((((uint32_t *)location)[0] & ~0xfffc) != uint32_t 705 arch/powerpc/kernel/module_64.c if (((uint32_t *)location)[1] != uint32_t 713 arch/powerpc/kernel/module_64.c ((uint32_t *)location)[0] = PPC_INST_ADDIS | __PPC_RT(R2) | uint32_t 715 arch/powerpc/kernel/module_64.c ((uint32_t *)location)[1] = PPC_INST_ADDI | __PPC_RT(R2) | uint32_t 1038 arch/powerpc/kernel/rtas.c uint32_t ext_log_length = rtas_error_extended_log_length(log); uint32_t 1040 arch/powerpc/kernel/rtas.c uint32_t company_id = rtas_ext_event_company_id(ext_log); uint32_t 163 arch/powerpc/kernel/rtasd.c uint32_t extended_log_length; uint32_t 433 arch/powerpc/kvm/book3s.c mp_pa = (uint32_t)mp_pa; uint32_t 522 arch/powerpc/kvm/book3s_pr.c kvmppc_mmu_pte_flush(vcpu, (uint32_t)vcpu->arch.magic_page_pa, uint32_t 657 arch/powerpc/kvm/book3s_pr.c mp_pa = (uint32_t)mp_pa; uint32_t 2064 arch/powerpc/kvm/booke.c uint32_t type = dbg->arch.bp[n].type; uint32_t 70 arch/powerpc/kvm/e500_mmu_host.c uint32_t mas0, uint32_t 71 arch/powerpc/kvm/e500_mmu_host.c uint32_t lpid) uint32_t 130 arch/powerpc/kvm/mpic.c uint32_t val); uint32_t 148 arch/powerpc/kvm/mpic.c uint32_t ivpr; /* IRQ vector/priority register */ uint32_t 149 arch/powerpc/kvm/mpic.c uint32_t idr; /* IRQ destination register */ uint32_t 150 arch/powerpc/kvm/mpic.c uint32_t destmask; /* bitmap of CPU destinations */ uint32_t 186 arch/powerpc/kvm/mpic.c uint32_t outputs_active[NUM_OUTPUTS]; uint32_t 203 arch/powerpc/kvm/mpic.c uint32_t model; uint32_t 204 arch/powerpc/kvm/mpic.c uint32_t flags; uint32_t 205 arch/powerpc/kvm/mpic.c uint32_t nb_irqs; uint32_t 206 arch/powerpc/kvm/mpic.c uint32_t vid; uint32_t 207 arch/powerpc/kvm/mpic.c uint32_t vir; /* Vendor identification register */ uint32_t 208 arch/powerpc/kvm/mpic.c uint32_t vector_mask; uint32_t 209 arch/powerpc/kvm/mpic.c uint32_t tfrr_reset; uint32_t 210 arch/powerpc/kvm/mpic.c uint32_t ivpr_reset; uint32_t 211 arch/powerpc/kvm/mpic.c uint32_t idr_reset; uint32_t 212 arch/powerpc/kvm/mpic.c uint32_t brr1; uint32_t 213 arch/powerpc/kvm/mpic.c uint32_t mpic_mode_mask; uint32_t 216 arch/powerpc/kvm/mpic.c uint32_t frr; /* Feature reporting register */ uint32_t 217 arch/powerpc/kvm/mpic.c uint32_t gcr; /* Global configuration register */ uint32_t 218 arch/powerpc/kvm/mpic.c uint32_t pir; /* Processor initialization register */ uint32_t 219 arch/powerpc/kvm/mpic.c uint32_t spve; /* Spurious vector register */ uint32_t 220 arch/powerpc/kvm/mpic.c uint32_t tfrr; /* Timer frequency reporting register */ uint32_t 225 arch/powerpc/kvm/mpic.c uint32_t nb_cpus; uint32_t 228 arch/powerpc/kvm/mpic.c uint32_t tccr; /* Global timer current count register */ uint32_t 229 arch/powerpc/kvm/mpic.c uint32_t tbcr; /* Global timer base count register */ uint32_t 233 arch/powerpc/kvm/mpic.c uint32_t msir; /* Shared Message Signaled Interrupt Register */ uint32_t 235 arch/powerpc/kvm/mpic.c uint32_t max_irq; uint32_t 236 arch/powerpc/kvm/mpic.c uint32_t irq_ipi0; uint32_t 237 arch/powerpc/kvm/mpic.c uint32_t irq_tim0; uint32_t 238 arch/powerpc/kvm/mpic.c uint32_t irq_msi; uint32_t 562 arch/powerpc/kvm/mpic.c static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ) uint32_t 567 arch/powerpc/kvm/mpic.c static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ) uint32_t 575 arch/powerpc/kvm/mpic.c static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ) uint32_t 581 arch/powerpc/kvm/mpic.c uint32_t val) uint32_t 584 arch/powerpc/kvm/mpic.c uint32_t normal_mask = (1UL << opp->nb_cpus) - 1; uint32_t 585 arch/powerpc/kvm/mpic.c uint32_t crit_mask = 0; uint32_t 586 arch/powerpc/kvm/mpic.c uint32_t mask = normal_mask; uint32_t 626 arch/powerpc/kvm/mpic.c uint32_t val) uint32_t 640 arch/powerpc/kvm/mpic.c uint32_t val) uint32_t 642 arch/powerpc/kvm/mpic.c uint32_t mask; uint32_t 852 arch/powerpc/kvm/mpic.c uint32_t retval = -1; uint32_t 915 arch/powerpc/kvm/mpic.c uint32_t retval; uint32_t 970 arch/powerpc/kvm/mpic.c uint32_t r = 0; uint32_t 1006 arch/powerpc/kvm/mpic.c uint32_t r = 0; uint32_t 1127 arch/powerpc/kvm/mpic.c static uint32_t openpic_iack(struct openpic *opp, struct irq_dest *dst, uint32_t 1196 arch/powerpc/kvm/mpic.c uint32_t retval; uint32_t 286 arch/powerpc/platforms/512x/clock-commonclk.c static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len) uint32_t 288 arch/powerpc/platforms/512x/clock-commonclk.c uint32_t val; uint32_t 55 arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c uint32_t mask; uint32_t 46 arch/powerpc/platforms/85xx/ppa8548.c uint32_t svid, phid1; uint32_t 54 arch/powerpc/platforms/85xx/socrates_fpga_pic.c static inline uint32_t socrates_fpga_pic_read(int reg) uint32_t 59 arch/powerpc/platforms/85xx/socrates_fpga_pic.c static inline void socrates_fpga_pic_write(int reg, uint32_t val) uint32_t 66 arch/powerpc/platforms/85xx/socrates_fpga_pic.c uint32_t cause; uint32_t 110 arch/powerpc/platforms/85xx/socrates_fpga_pic.c uint32_t mask; uint32_t 50 arch/powerpc/platforms/85xx/xes_mpc85xx.c volatile uint32_t ctl, tmp; uint32_t 162 arch/powerpc/platforms/cell/spufs/spufs.h uint32_t lsa; /* local storage address */ uint32_t 370 arch/powerpc/platforms/powernv/eeh-powernv.c uint32_t pcie_flags; uint32_t 23 arch/powerpc/platforms/powernv/opal-dump.c uint32_t id; /* becomes object name */ uint32_t 24 arch/powerpc/platforms/powernv/opal-dump.c uint32_t type; uint32_t 25 arch/powerpc/platforms/powernv/opal-dump.c uint32_t size; uint32_t 46 arch/powerpc/platforms/powernv/opal-dump.c static const char* dump_type_to_string(uint32_t type) uint32_t 75 arch/powerpc/platforms/powernv/opal-dump.c static int64_t dump_send_ack(uint32_t dump_id) uint32_t 213 arch/powerpc/platforms/powernv/opal-dump.c static int64_t dump_read_info(uint32_t *dump_id, uint32_t *dump_size, uint32_t *dump_type) uint32_t 321 arch/powerpc/platforms/powernv/opal-dump.c static struct dump_obj *create_dump_obj(uint32_t id, size_t size, uint32_t 322 arch/powerpc/platforms/powernv/opal-dump.c uint32_t type) uint32_t 369 arch/powerpc/platforms/powernv/opal-dump.c uint32_t dump_id, dump_size, dump_type; uint32_t 90 arch/powerpc/platforms/powernv/opal-flash.c uint32_t size; uint32_t 97 arch/powerpc/platforms/powernv/opal-flash.c uint32_t size; uint32_t 103 arch/powerpc/platforms/powernv/opal-flash.c uint32_t buf_size; /* Image size */ uint32_t 104 arch/powerpc/platforms/powernv/opal-flash.c uint32_t result; /* Update results token */ uint32_t 30 arch/powerpc/platforms/powernv/opal-hmi.c uint32_t xstop_reason; uint32_t 37 arch/powerpc/platforms/powernv/opal-msglog.c uint32_t out_pos, avail; uint32_t 55 arch/powerpc/platforms/powernv/opal-xscom.c static int opal_scom_read(uint32_t chip, uint64_t addr, u64 reg, u64 *value) uint32_t 70 arch/powerpc/platforms/powernv/opal-xscom.c static int opal_scom_write(uint32_t chip, uint64_t addr, u64 reg, u64 value) uint32_t 59 arch/powerpc/platforms/powernv/opal.c static uint32_t opal_heartbeat; uint32_t 266 arch/powerpc/platforms/powernv/opal.c static void opal_message_do_notify(uint32_t msg_type, void *msg) uint32_t 345 arch/powerpc/platforms/powernv/opal.c int opal_get_chars(uint32_t vtermno, char *buf, int count) uint32_t 362 arch/powerpc/platforms/powernv/opal.c static int __opal_put_chars(uint32_t vtermno, const char *data, int total_len, bool atomic) uint32_t 418 arch/powerpc/platforms/powernv/opal.c int opal_put_chars(uint32_t vtermno, const char *data, int total_len) uint32_t 429 arch/powerpc/platforms/powernv/opal.c int opal_put_chars_atomic(uint32_t vtermno, const char *data, int total_len) uint32_t 434 arch/powerpc/platforms/powernv/opal.c static s64 __opal_flush_console(uint32_t vtermno) uint32_t 467 arch/powerpc/platforms/powernv/opal.c int opal_flush_console(uint32_t vtermno) uint32_t 486 arch/powerpc/platforms/powernv/opal.c int opal_flush_chars(uint32_t vtermno, bool wait) uint32_t 77 arch/powerpc/platforms/powernv/pci.c int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len) uint32_t 401 arch/powerpc/platforms/ps3/os-area.c uint32_t *value_32; uint32_t 28 arch/powerpc/platforms/pseries/hvconsole.c int hvc_get_chars(uint32_t vtermno, char *buf, int count) uint32_t 55 arch/powerpc/platforms/pseries/hvconsole.c int hvc_put_chars(uint32_t vtermno, const char *buf, int count) uint32_t 82 arch/powerpc/platforms/pseries/hvcserver.c static int hvcs_next_partner(uint32_t unit_address, uint32_t 119 arch/powerpc/platforms/pseries/hvcserver.c int hvcs_get_partner_info(uint32_t unit_address, struct list_head *head, uint32_t 213 arch/powerpc/platforms/pseries/hvcserver.c int hvcs_register_connection( uint32_t unit_address, uint32_t 214 arch/powerpc/platforms/pseries/hvcserver.c uint32_t p_partition_ID, uint32_t p_unit_address) uint32_t 233 arch/powerpc/platforms/pseries/hvcserver.c int hvcs_free_connection(uint32_t unit_address) uint32_t 28 arch/powerpc/platforms/pseries/papr_scm.c uint32_t drc_index; uint32_t 185 arch/powerpc/platforms/pseries/papr_scm.c *(uint32_t *)(hdr->out_buf + data_offset) = be32_to_cpu(data[0] & 0xffffffff); uint32_t 222 arch/powerpc/platforms/pseries/papr_scm.c data = *(uint32_t *)(hdr->in_buf + data_offset); uint32_t 72 arch/powerpc/platforms/pseries/pmem.c uint32_t index; uint32_t 1670 arch/powerpc/platforms/pseries/vio.c (uint32_t)of_read_number(prop, 1)); uint32_t 391 arch/s390/include/asm/qdio.h struct { uint32_t _s_addr; } addr; uint32_t 87 arch/s390/include/asm/string.h void *__memset32(uint32_t *s, uint32_t v, size_t count); uint32_t 95 arch/s390/include/asm/string.h static inline void *memset32(uint32_t *s, uint32_t v, size_t count) uint32_t 287 arch/s390/kvm/vsie.c const uint32_t crycbd_o = READ_ONCE(scb_o->crycbd); uint32_t 363 arch/s390/kvm/vsie.c const uint32_t __new_ibc = scb_o->ibc; uint32_t 364 arch/s390/kvm/vsie.c const uint32_t new_ibc = READ_ONCE(__new_ibc) & 0x0fffU; uint32_t 442 arch/s390/kvm/vsie.c const uint32_t __new_prefix = scb_o->prefix; uint32_t 443 arch/s390/kvm/vsie.c const uint32_t new_prefix = READ_ONCE(__new_prefix); uint32_t 34 arch/sh/kernel/module.c uint32_t *location; uint32_t 35 arch/sh/kernel/module.c uint32_t value; uint32_t 11 arch/sh/lib/div64-generic.c uint32_t __div64_32(u64 *xp, u32 y) uint32_t 13 arch/sh/lib/div64-generic.c uint32_t rem; uint32_t 26 arch/um/drivers/daemon_user.c uint32_t magic; uint32_t 27 arch/um/drivers/daemon_user.c uint32_t version; uint32_t 12 arch/um/drivers/mconsole.h #define u32 uint32_t uint32_t 30 arch/um/drivers/vector_transports.c uint32_t rx_key; uint32_t 31 arch/um/drivers/vector_transports.c uint32_t tx_key; uint32_t 32 arch/um/drivers/vector_transports.c uint32_t sequence; uint32_t 41 arch/um/drivers/vector_transports.c uint32_t checksum_offset; uint32_t 42 arch/um/drivers/vector_transports.c uint32_t key_offset; uint32_t 43 arch/um/drivers/vector_transports.c uint32_t sequence_offset; uint32_t 52 arch/um/drivers/vector_transports.c uint32_t counter; uint32_t 61 arch/um/drivers/vector_transports.c uint32_t cookie_offset; uint32_t 62 arch/um/drivers/vector_transports.c uint32_t session_offset; uint32_t 63 arch/um/drivers/vector_transports.c uint32_t counter_offset; uint32_t 70 arch/um/drivers/vector_transports.c uint32_t *counter; uint32_t 73 arch/um/drivers/vector_transports.c *(uint32_t *) header = cpu_to_be32(L2TPV3_DATA_PACKET); uint32_t 74 arch/um/drivers/vector_transports.c (*(uint32_t *) (header + td->session_offset)) = td->tx_session; uint32_t 81 arch/um/drivers/vector_transports.c (*(uint32_t *)(header + td->cookie_offset)) = uint32_t 85 arch/um/drivers/vector_transports.c counter = (uint32_t *)(header + td->counter_offset); uint32_t 100 arch/um/drivers/vector_transports.c uint32_t *sequence; uint32_t 101 arch/um/drivers/vector_transports.c *((uint32_t *) header) = *((uint32_t *) &td->expected_header); uint32_t 103 arch/um/drivers/vector_transports.c (*(uint32_t *) (header + td->key_offset)) = td->tx_key; uint32_t 105 arch/um/drivers/vector_transports.c sequence = (uint32_t *)(header + td->sequence_offset); uint32_t 134 arch/um/drivers/vector_transports.c uint32_t *session; uint32_t 149 arch/um/drivers/vector_transports.c cookie = *(uint32_t *)(header + td->cookie_offset); uint32_t 156 arch/um/drivers/vector_transports.c session = (uint32_t *) (header + td->session_offset); uint32_t 169 arch/um/drivers/vector_transports.c uint32_t key; uint32_t 175 arch/um/drivers/vector_transports.c if (*((uint32_t *) header) != *((uint32_t *) &td->expected_header)) { uint32_t 178 arch/um/drivers/vector_transports.c *((uint32_t *) &td->expected_header), uint32_t 179 arch/um/drivers/vector_transports.c *((uint32_t *) header) uint32_t 185 arch/um/drivers/vector_transports.c key = (*(uint32_t *)(header + td->key_offset)); uint32_t 677 arch/um/drivers/vector_user.c uint32_t *mac1 = (uint32_t *)(mac + 2); uint32_t 239 arch/x86/boot/compressed/misc.c *(uint32_t *)ptr += delta; uint32_t 21 arch/x86/boot/compressed/mkpiggy.c uint32_t olen; uint32_t 46 arch/x86/include/asm/hypervisor.h uint32_t (*detect)(void); uint32_t 1184 arch/x86/include/asm/kvm_host.h uint32_t guest_irq, bool set); uint32_t 11 arch/x86/include/asm/olpc.h uint32_t boardrev; uint32_t 28 arch/x86/include/asm/olpc.h static inline uint32_t olpc_board(uint8_t id) uint32_t 33 arch/x86/include/asm/olpc.h static inline uint32_t olpc_board_pre(uint8_t id) uint32_t 60 arch/x86/include/asm/olpc.h static inline int olpc_board_at_least(uint32_t rev) uint32_t 944 arch/x86/include/asm/processor.h static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) uint32_t 946 arch/x86/include/asm/processor.h uint32_t base, eax, signature[3]; uint32_t 244 arch/x86/include/asm/string_32.h static inline void *memset32(uint32_t *s, uint32_t v, size_t n) uint32_t 34 arch/x86/include/asm/string_64.h static inline void *memset32(uint32_t *s, uint32_t v, size_t n) uint32_t 338 arch/x86/include/asm/xen/hypercall.h HYPERVISOR_multicall(void *call_list, uint32_t nr_calls) uint32_t 41 arch/x86/include/asm/xen/hypervisor.h static inline uint32_t xen_cpuid_base(void) uint32_t 93 arch/x86/include/asm/xen/interface.h DEFINE_GUEST_HANDLE(uint32_t); uint32_t 260 arch/x86/include/asm/xen/interface.h uint32_t counters; uint32_t 261 arch/x86/include/asm/xen/interface.h uint32_t ctrls; uint32_t 283 arch/x86/include/asm/xen/interface.h uint32_t fixed_counters; uint32_t 284 arch/x86/include/asm/xen/interface.h uint32_t arch_counters; uint32_t 353 arch/x86/include/asm/xen/interface.h uint32_t lapic_lvtpc; uint32_t 50 arch/x86/include/asm/xen/interface_32.h uint32_t ebx; uint32_t 51 arch/x86/include/asm/xen/interface_32.h uint32_t ecx; uint32_t 52 arch/x86/include/asm/xen/interface_32.h uint32_t edx; uint32_t 53 arch/x86/include/asm/xen/interface_32.h uint32_t esi; uint32_t 54 arch/x86/include/asm/xen/interface_32.h uint32_t edi; uint32_t 55 arch/x86/include/asm/xen/interface_32.h uint32_t ebp; uint32_t 56 arch/x86/include/asm/xen/interface_32.h uint32_t eax; uint32_t 59 arch/x86/include/asm/xen/interface_32.h uint32_t eip; uint32_t 63 arch/x86/include/asm/xen/interface_32.h uint32_t eflags; /* eflags.IF == !saved_upcall_mask */ uint32_t 64 arch/x86/include/asm/xen/interface_32.h uint32_t esp; uint32_t 92 arch/x86/include/asm/xen/interface_64.h uint32_t _e ## name; \ uint32_t 115 arch/x86/include/asm/xen/interface_64.h uint32_t error_code; /* private */ uint32_t 116 arch/x86/include/asm/xen/interface_64.h uint32_t entry_vector; /* private */ uint32_t 19 arch/x86/kernel/cpu/acrn.c static uint32_t __init acrn_detect(void) uint32_t 65 arch/x86/kernel/cpu/hypervisor.c uint32_t pri, max_pri = 0; uint32_t 149 arch/x86/kernel/cpu/mshyperv.c static uint32_t __init ms_hyperv_platform(void) uint32_t 94 arch/x86/kernel/cpu/vmware.c uint32_t eax, ebx, ecx, edx; uint32_t 96 arch/x86/kernel/cpu/vmware.c return eax != (uint32_t)-1 && ebx == VMWARE_HYPERVISOR_MAGIC; uint32_t 175 arch/x86/kernel/cpu/vmware.c uint32_t eax, ebx, ecx, edx; uint32_t 232 arch/x86/kernel/cpu/vmware.c static uint32_t __init vmware_platform(void) uint32_t 260 arch/x86/kernel/cpu/vmware.c uint32_t eax, ebx, ecx, edx; uint32_t 27 arch/x86/kernel/jailhouse.c static uint32_t jailhouse_cpuid_base(void) uint32_t 36 arch/x86/kernel/jailhouse.c static uint32_t __init jailhouse_detect(void) uint32_t 74 arch/x86/kernel/kexec-bzimage64.c uint32_t cmdline_low_32, cmdline_ext_32; uint32_t 660 arch/x86/kernel/kvm.c static noinline uint32_t __kvm_cpuid_base(void) uint32_t 671 arch/x86/kernel/kvm.c static inline uint32_t kvm_cpuid_base(void) uint32_t 698 arch/x86/kernel/kvm.c static uint32_t __init kvm_detect(void) uint32_t 98 arch/x86/kernel/module.c uint32_t *location; uint32_t 118 arch/x86/kernel/module.c *location += sym->st_value - (uint32_t)location; uint32_t 1602 arch/x86/kvm/lapic.c static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) uint32_t 1961 arch/x86/kvm/lapic.c uint32_t old_divisor = apic->divide_count; uint32_t 1482 arch/x86/kvm/svm.c static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) uint32_t 3901 arch/x86/kvm/svm.c uint32_t type = uint32_t 3903 arch/x86/kvm/svm.c uint32_t idt_v = uint32_t 5321 arch/x86/kvm/svm.c uint32_t guest_irq, bool set) uint32_t 4436 arch/x86/kvm/vmx/nested.c uint32_t revision; uint32_t 4372 arch/x86/kvm/vmx/vmx.c uint32_t intr; uint32_t 5665 arch/x86/kvm/vmx/vmx.c static void vmx_dump_sel(char *name, uint32_t sel) uint32_t 5674 arch/x86/kvm/vmx/vmx.c static void vmx_dump_dtsel(char *name, uint32_t limit) uint32_t 7459 arch/x86/kvm/vmx/vmx.c uint32_t guest_irq, bool set) uint32_t 1712 arch/x86/kvm/x86.c static uint32_t div_frac(uint32_t dividend, uint32_t divisor) uint32_t 1724 arch/x86/kvm/x86.c uint32_t tps32; uint32_t 1733 arch/x86/kvm/x86.c tps32 = (uint32_t)tps64; uint32_t 10340 arch/x86/kvm/x86.c uint32_t guest_irq, bool set) uint32_t 168 arch/x86/pci/ce4100.c uint32_t mask; uint32_t 41 arch/x86/pci/olpc.c static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ uint32_t 54 arch/x86/pci/olpc.c static const uint32_t gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ uint32_t 67 arch/x86/pci/olpc.c static const uint32_t lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ uint32_t 80 arch/x86/pci/olpc.c static const uint32_t gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ uint32_t 93 arch/x86/pci/olpc.c static const uint32_t aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */ uint32_t 107 arch/x86/pci/olpc.c static const uint32_t isa_hdr[] = { /* dev f function 0 - devfn = 78 */ uint32_t 120 arch/x86/pci/olpc.c static const uint32_t ac97_hdr[] = { /* dev f function 3 - devfn = 7b */ uint32_t 133 arch/x86/pci/olpc.c static const uint32_t ohci_hdr[] = { /* dev f function 4 - devfn = 7c */ uint32_t 147 arch/x86/pci/olpc.c static const uint32_t ehci_hdr[] = { /* dev f function 4 - devfn = 7d */ uint32_t 165 arch/x86/pci/olpc.c static uint32_t ff_loc = ~0; uint32_t 166 arch/x86/pci/olpc.c static uint32_t zero_loc; uint32_t 179 arch/x86/pci/olpc.c static uint32_t *hdr_addr(const uint32_t *hdr, int reg) uint32_t 181 arch/x86/pci/olpc.c uint32_t addr; uint32_t 194 arch/x86/pci/olpc.c addr = (uint32_t)hdr + reg + (bar_probing ? -0x10 : 0x20); uint32_t 197 arch/x86/pci/olpc.c return (uint32_t *)addr; uint32_t 201 arch/x86/pci/olpc.c unsigned int devfn, int reg, int len, uint32_t *value) uint32_t 203 arch/x86/pci/olpc.c uint32_t *addr; uint32_t 263 arch/x86/pci/olpc.c unsigned int devfn, int reg, int len, uint32_t value) uint32_t 435 arch/x86/pci/xen.c uint32_t eax = cpuid_eax(xen_cpuid_base() + 4); uint32_t 19 arch/x86/tools/relocs.c uint32_t *offset; uint32_t 316 arch/x86/tools/relocs.c static uint32_t elf32_to_cpu(uint32_t val) uint32_t 649 arch/x86/tools/relocs.c static void add_reloc(struct relocs *r, uint32_t offset) uint32_t 977 arch/x86/tools/relocs.c const uint32_t *a, *b; uint32_t 987 arch/x86/tools/relocs.c static int write32(uint32_t v, FILE *f) uint32_t 995 arch/x86/tools/relocs.c static int write32_as_text(uint32_t v, FILE *f) uint32_t 1003 arch/x86/tools/relocs.c int (*write_reloc)(uint32_t, FILE *) = write32; uint32_t 51 arch/x86/xen/enlighten.c DEFINE_PER_CPU(uint32_t, xen_vcpu_id); uint32_t 74 arch/x86/xen/enlighten.c uint32_t xen_start_flags __attribute__((section(".data"))) = 0; uint32_t 88 arch/x86/xen/enlighten_hvm.c uint32_t eax, ebx, ecx, edx, base; uint32_t 104 arch/x86/xen/enlighten_hvm.c uint32_t msr; uint32_t 257 arch/x86/xen/enlighten_hvm.c static uint32_t __init xen_platform_hvm(void) uint32_t 259 arch/x86/xen/enlighten_hvm.c uint32_t xen_domain = xen_cpuid_base(); uint32_t 214 arch/x86/xen/enlighten_pv.c uint32_t buf[3]; uint32_t 1449 arch/x86/xen/enlighten_pv.c static uint32_t __init xen_platform_pv(void) uint32_t 37 arch/x86/xen/pmu.c static __read_mostly uint32_t amd_counters_base; uint32_t 38 arch/x86/xen/pmu.c static __read_mostly uint32_t amd_ctrls_base; uint32_t 101 arch/x86/xen/pmu.c uint32_t eax, ebx, ecx, edx; uint32_t 112 arch/x86/xen/pmu.c static inline uint32_t get_fam15h_addr(u32 addr) uint32_t 314 arch/x86/xen/pmu.c bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err) uint32_t 345 arch/x86/xen/pmu.c uint32_t msr; uint32_t 366 arch/x86/xen/pmu.c uint32_t msr; uint32_t 395 arch/x86/xen/pmu.c int pmu_apic_update(uint32_t val) uint32_t 17 arch/x86/xen/pmu.h bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err); uint32_t 18 arch/x86/xen/pmu.h int pmu_apic_update(uint32_t reg); uint32_t 57 arch/xtensa/kernel/module.c uint32_t value; uint32_t 79 arch/xtensa/kernel/module.c *(uint32_t *)location += value; uint32_t 126 arch/xtensa/kernel/perf_event.c static inline uint32_t xtensa_pmu_read_counter(int idx) uint32_t 131 arch/xtensa/kernel/perf_event.c static inline void xtensa_pmu_write_counter(int idx, uint32_t v) uint32_t 368 arch/xtensa/kernel/perf_event.c uint32_t v = get_er(XTENSA_PMU_PMSTAT(i)); uint32_t 121 arch/xtensa/platforms/iss/include/platform/simcall.h static inline int simc_lseek(int fd, uint32_t off, int whence) uint32_t 176 block/partitions/efi.c uint32_t sz = 0; uint32_t 218 block/partitions/efi.c if (sz != (uint32_t) total_sectors - 1 && sz != 0xFFFFFFFF) uint32_t 220 block/partitions/efi.c sz, min_t(uint32_t, uint32_t 35 crypto/asymmetric_keys/asym_tpm.c uint32_t keyhandle, unsigned char *keyauth, uint32_t 37 crypto/asymmetric_keys/asym_tpm.c uint32_t *newhandle) uint32_t 42 crypto/asymmetric_keys/asym_tpm.c uint32_t authhandle = 0; uint32_t 44 crypto/asymmetric_keys/asym_tpm.c uint32_t ordinal; uint32_t 65 crypto/asymmetric_keys/asym_tpm.c nonceodd, cont, sizeof(uint32_t), &ordinal, uint32_t 102 crypto/asymmetric_keys/asym_tpm.c static int tpm_flushspecific(struct tpm_buf *tb, uint32_t handle) uint32_t 119 crypto/asymmetric_keys/asym_tpm.c uint32_t keyhandle, unsigned char *keyauth, uint32_t 120 crypto/asymmetric_keys/asym_tpm.c const unsigned char *blob, uint32_t bloblen, uint32_t 121 crypto/asymmetric_keys/asym_tpm.c void *out, uint32_t outlen) uint32_t 126 crypto/asymmetric_keys/asym_tpm.c uint32_t authhandle = 0; uint32_t 128 crypto/asymmetric_keys/asym_tpm.c uint32_t ordinal; uint32_t 129 crypto/asymmetric_keys/asym_tpm.c uint32_t datalen; uint32_t 151 crypto/asymmetric_keys/asym_tpm.c nonceodd, cont, sizeof(uint32_t), &ordinal, uint32_t 152 crypto/asymmetric_keys/asym_tpm.c sizeof(uint32_t), &datalen, uint32_t 180 crypto/asymmetric_keys/asym_tpm.c sizeof(uint32_t), TPM_DATA_OFFSET, uint32_t 181 crypto/asymmetric_keys/asym_tpm.c datalen, TPM_DATA_OFFSET + sizeof(uint32_t), uint32_t 188 crypto/asymmetric_keys/asym_tpm.c memcpy(out, tb->data + TPM_DATA_OFFSET + sizeof(uint32_t), uint32_t 205 crypto/asymmetric_keys/asym_tpm.c uint32_t keyhandle, unsigned char *keyauth, uint32_t 206 crypto/asymmetric_keys/asym_tpm.c const unsigned char *blob, uint32_t bloblen, uint32_t 207 crypto/asymmetric_keys/asym_tpm.c void *out, uint32_t outlen) uint32_t 212 crypto/asymmetric_keys/asym_tpm.c uint32_t authhandle = 0; uint32_t 214 crypto/asymmetric_keys/asym_tpm.c uint32_t ordinal; uint32_t 215 crypto/asymmetric_keys/asym_tpm.c uint32_t datalen; uint32_t 237 crypto/asymmetric_keys/asym_tpm.c nonceodd, cont, sizeof(uint32_t), &ordinal, uint32_t 238 crypto/asymmetric_keys/asym_tpm.c sizeof(uint32_t), &datalen, uint32_t 266 crypto/asymmetric_keys/asym_tpm.c sizeof(uint32_t), TPM_DATA_OFFSET, uint32_t 267 crypto/asymmetric_keys/asym_tpm.c datalen, TPM_DATA_OFFSET + sizeof(uint32_t), uint32_t 274 crypto/asymmetric_keys/asym_tpm.c memcpy(out, tb->data + TPM_DATA_OFFSET + sizeof(uint32_t), uint32_t 325 crypto/asymmetric_keys/asym_tpm.c static inline uint32_t definite_length(uint32_t len) uint32_t 335 crypto/asymmetric_keys/asym_tpm.c uint32_t len) uint32_t 355 crypto/asymmetric_keys/asym_tpm.c static uint32_t derive_pub_key(const void *pub_key, uint32_t len, uint8_t *buf) uint32_t 358 crypto/asymmetric_keys/asym_tpm.c uint32_t n_len = definite_length(len) + 1 + len + 1; uint32_t 359 crypto/asymmetric_keys/asym_tpm.c uint32_t e_len = definite_length(3) + 1 + 3; uint32_t 416 crypto/asymmetric_keys/asym_tpm.c uint32_t der_pub_key_len; uint32_t 469 crypto/asymmetric_keys/asym_tpm.c uint32_t der_pub_key_len; uint32_t 524 crypto/asymmetric_keys/asym_tpm.c uint32_t keyhandle; uint32_t 648 crypto/asymmetric_keys/asym_tpm.c uint32_t keyhandle; uint32_t 652 crypto/asymmetric_keys/asym_tpm.c uint32_t in_len = params->in_len; uint32_t 758 crypto/asymmetric_keys/asym_tpm.c uint32_t der_pub_key_len; uint32_t 833 crypto/asymmetric_keys/asym_tpm.c uint32_t len = tk->blob_len; uint32_t 835 crypto/asymmetric_keys/asym_tpm.c uint32_t sz; uint32_t 836 crypto/asymmetric_keys/asym_tpm.c uint32_t key_len; uint32_t 915 crypto/asymmetric_keys/asym_tpm.c struct tpm_key *tpm_key_create(const void *blob, uint32_t blob_len) uint32_t 255 crypto/asymmetric_keys/verify_pefile.c tmp = ctx->image_checksum_offset + sizeof(uint32_t); uint32_t 260 drivers/acpi/acpi_pad.c static uint32_t acpi_pad_idle_cpus_num(void) uint32_t 393 drivers/acpi/acpi_pad.c uint32_t idle_cpus; uint32_t 119 drivers/android/binder.c static uint32_t binder_debug_mask = BINDER_DEBUG_USER_ERROR | uint32_t 243 drivers/android/binder.c uint32_t cmd; uint32_t 368 drivers/android/binder.c uint32_t desc; uint32_t 1684 drivers/android/binder.c uint32_t desc, bool increment, bool strong, uint32_t 1727 drivers/android/binder.c uint32_t desc, bool strong, struct binder_ref_data *rdata) uint32_t 1940 drivers/android/binder.c uint32_t error_code) uint32_t 2006 drivers/android/binder.c uint32_t error_code) uint32_t 2823 drivers/android/binder.c uint32_t *error) uint32_t 2859 drivers/android/binder.c uint32_t return_error = 0; uint32_t 2860 drivers/android/binder.c uint32_t return_error_param = 0; uint32_t 2861 drivers/android/binder.c uint32_t return_error_line = 0; uint32_t 3602 drivers/android/binder.c uint32_t cmd; uint32_t 3611 drivers/android/binder.c if (get_user(cmd, (uint32_t __user *)ptr)) uint32_t 3613 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 3625 drivers/android/binder.c uint32_t target; uint32_t 3631 drivers/android/binder.c if (get_user(target, (uint32_t __user *)ptr)) uint32_t 3634 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 3854 drivers/android/binder.c uint32_t target; uint32_t 3859 drivers/android/binder.c if (get_user(target, (uint32_t __user *)ptr)) uint32_t 3861 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 4037 drivers/android/binder.c struct binder_thread *thread, uint32_t cmd) uint32_t 4053 drivers/android/binder.c uint32_t cmd, const char *cmd_name) uint32_t 4057 drivers/android/binder.c if (put_user(cmd, (uint32_t __user *)ptr)) uint32_t 4059 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 4188 drivers/android/binder.c if (put_user(BR_NOOP, (uint32_t __user *)ptr)) uint32_t 4190 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 4227 drivers/android/binder.c uint32_t cmd; uint32_t 4270 drivers/android/binder.c if (put_user(e->cmd, (uint32_t __user *)ptr)) uint32_t 4274 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 4283 drivers/android/binder.c if (put_user(cmd, (uint32_t __user *)ptr)) uint32_t 4285 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 4383 drivers/android/binder.c uint32_t cmd; uint32_t 4409 drivers/android/binder.c if (put_user(cmd, (uint32_t __user *)ptr)) uint32_t 4411 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 4484 drivers/android/binder.c if (put_user(cmd, (uint32_t __user *)ptr)) uint32_t 4486 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 4504 drivers/android/binder.c if (put_user(cmd, (uint32_t __user *)ptr)) { uint32_t 4513 drivers/android/binder.c ptr += sizeof(uint32_t); uint32_t 4569 drivers/android/binder.c if (put_user(BR_SPAWN_LOOPER, (uint32_t __user *)buffer)) uint32_t 39 drivers/android/binder_alloc.c static uint32_t binder_alloc_debug_mask = BINDER_DEBUG_USER_ERROR; uint32_t 103 drivers/android/binder_alloc.h uint32_t buffer_free; uint32_t 133 drivers/android/binder_internal.h uint32_t return_error; uint32_t 134 drivers/android/binder_internal.h uint32_t return_error_param; uint32_t 149 drivers/android/binder_trace.h __field(uint32_t, ref_desc) uint32_t 172 drivers/android/binder_trace.h __field(uint32_t, ref_desc) uint32_t 199 drivers/android/binder_trace.h __field(uint32_t, src_ref_desc) uint32_t 201 drivers/android/binder_trace.h __field(uint32_t, dest_ref_desc) uint32_t 362 drivers/android/binder_trace.h TP_PROTO(uint32_t cmd), uint32_t 365 drivers/android/binder_trace.h __field(uint32_t, cmd) uint32_t 378 drivers/android/binder_trace.h TP_PROTO(uint32_t cmd), uint32_t 381 drivers/android/binder_trace.h __field(uint32_t, cmd) uint32_t 93 drivers/atm/solos-pci.c uint32_t dma_addr; uint32_t 164 drivers/atm/solos-pci.c static uint32_t fpga_tx(struct solos_card *); uint32_t 521 drivers/atm/solos-pci.c uint32_t data32; uint32_t 546 drivers/atm/solos-pci.c uint32_t data32; uint32_t 559 drivers/atm/solos-pci.c uint32_t data32; uint32_t 716 drivers/atm/solos-pci.c uint32_t word; uint32_t 718 drivers/atm/solos-pci.c word = swahb32p((uint32_t *)(fw->data + offset + i)); uint32_t 720 drivers/atm/solos-pci.c word = *(uint32_t *)(fw->data + offset + i); uint32_t 760 drivers/atm/solos-pci.c uint32_t card_flags; uint32_t 761 drivers/atm/solos-pci.c uint32_t rx_done = 0; uint32_t 1049 drivers/atm/solos-pci.c static uint32_t fpga_tx(struct solos_card *card) uint32_t 1051 drivers/atm/solos-pci.c uint32_t tx_pending, card_flags; uint32_t 1052 drivers/atm/solos-pci.c uint32_t tx_started = 0; uint32_t 1198 drivers/atm/solos-pci.c uint32_t data32; uint32_t 53 drivers/auxdisplay/ht16k33.c uint32_t cols; uint32_t 54 drivers/auxdisplay/ht16k33.c uint32_t rows; uint32_t 55 drivers/auxdisplay/ht16k33.c uint32_t row_shift; uint32_t 56 drivers/auxdisplay/ht16k33.c uint32_t debounce_ms; uint32_t 65 drivers/auxdisplay/ht16k33.c uint32_t refresh_rate; uint32_t 393 drivers/auxdisplay/ht16k33.c uint32_t dft_brightness; uint32_t 194 drivers/block/skd_s1120.h uint32_t control; uint32_t 195 drivers/block/skd_s1120.h uint32_t byte_count; uint32_t 828 drivers/block/xen-blkback/blkback.c uint32_t flags; uint32_t 136 drivers/block/xen-blkback/common.h uint32_t _pad1; /* offsetof(blkif_reqest..,u.rw.id)==8 */ uint32_t 145 drivers/block/xen-blkback/common.h uint32_t _pad2; /* offsetof(blkif_..,u.discard.id)==8 */ uint32_t 154 drivers/block/xen-blkback/common.h uint32_t _pad3; /* offsetof(blkif_..,u.discard.id)==8 */ uint32_t 161 drivers/block/xen-blkback/common.h uint32_t _pad1; /* offsetof(blkif_..,u.indirect.id)==8 */ uint32_t 174 drivers/block/xen-blkback/common.h uint32_t _pad3; /* make it 64 byte aligned */ uint32_t 59 drivers/char/hw_random/iproc-rng200.c uint32_t val; uint32_t 98 drivers/char/hw_random/iproc-rng200.c uint32_t num_remaining = max; uint32_t 99 drivers/char/hw_random/iproc-rng200.c uint32_t status; uint32_t 102 drivers/char/hw_random/iproc-rng200.c uint32_t num_resets = 0; uint32_t 125 drivers/char/hw_random/iproc-rng200.c if (num_remaining >= sizeof(uint32_t)) { uint32_t 127 drivers/char/hw_random/iproc-rng200.c *(uint32_t *)buf = ioread32(priv->base + uint32_t 129 drivers/char/hw_random/iproc-rng200.c buf += sizeof(uint32_t); uint32_t 130 drivers/char/hw_random/iproc-rng200.c num_remaining -= sizeof(uint32_t); uint32_t 133 drivers/char/hw_random/iproc-rng200.c uint32_t rnd_number = ioread32(priv->base + uint32_t 158 drivers/char/hw_random/iproc-rng200.c uint32_t val; uint32_t 172 drivers/char/hw_random/iproc-rng200.c uint32_t val; uint32_t 80 drivers/char/ipmi/bt-bmc.c uint32_t val = 0; uint32_t 50 drivers/clk/clk-axi-clkgen.c static uint32_t axi_clkgen_lookup_filter(unsigned int m) uint32_t 80 drivers/clk/clk-axi-clkgen.c static const uint32_t axi_clkgen_lock_table[] = { uint32_t 92 drivers/clk/clk-axi-clkgen.c static uint32_t axi_clkgen_lookup_lock(unsigned int m) uint32_t 258 drivers/clk/clk-axi-clkgen.c uint32_t filter; uint32_t 259 drivers/clk/clk-axi-clkgen.c uint32_t lock; uint32_t 58 drivers/clk/clk-hi655x.c uint32_t val; uint32_t 56 drivers/clk/clk-rk808.c uint32_t val; uint32_t 4827 drivers/clk/clk.c uint32_t idx; uint32_t 65 drivers/clk/mediatek/clk-mtk.h uint32_t mux_reg; uint32_t 66 drivers/clk/mediatek/clk-mtk.h uint32_t divider_reg; uint32_t 67 drivers/clk/mediatek/clk-mtk.h uint32_t gate_reg; uint32_t 216 drivers/clk/mediatek/clk-mtk.h uint32_t reg; uint32_t 217 drivers/clk/mediatek/clk-mtk.h uint32_t pwr_reg; uint32_t 218 drivers/clk/mediatek/clk-mtk.h uint32_t en_mask; uint32_t 219 drivers/clk/mediatek/clk-mtk.h uint32_t pd_reg; uint32_t 220 drivers/clk/mediatek/clk-mtk.h uint32_t tuner_reg; uint32_t 221 drivers/clk/mediatek/clk-mtk.h uint32_t tuner_en_reg; uint32_t 231 drivers/clk/mediatek/clk-mtk.h uint32_t pcw_reg; uint32_t 233 drivers/clk/mediatek/clk-mtk.h uint32_t pcw_chg_reg; uint32_t 34 drivers/clk/renesas/r9a06g032-clocks.c uint32_t managed: 1; uint32_t 35 drivers/clk/renesas/r9a06g032-clocks.c uint32_t type: 3; uint32_t 36 drivers/clk/renesas/r9a06g032-clocks.c uint32_t index: 8; uint32_t 37 drivers/clk/renesas/r9a06g032-clocks.c uint32_t source : 8; /* source index + 1 (0 == none) */ uint32_t 52 drivers/clocksource/bcm_kona_timer.c uint32_t reg; uint32_t 70 drivers/clocksource/bcm_kona_timer.c kona_timer_get_counter(void __iomem *timer_base, uint32_t *msw, uint32_t *lsw) uint32_t 114 drivers/clocksource/bcm_kona_timer.c uint32_t lsw, msw; uint32_t 115 drivers/clocksource/bcm_kona_timer.c uint32_t reg; uint32_t 94 drivers/clocksource/clksrc_st_lpc.c uint32_t mode; uint32_t 262 drivers/clocksource/timer-imx-gpt.c uint32_t tstat; uint32_t 75 drivers/clocksource/timer-oxnas-rps.c uint32_t cfg = rps->timer_prescaler; uint32_t 20 drivers/counter/ftm-quaddec.c uint32_t flags; \ uint32_t 35 drivers/counter/ftm-quaddec.c static void ftm_read(struct ftm_quaddec *ftm, uint32_t offset, uint32_t *data) uint32_t 43 drivers/counter/ftm-quaddec.c static void ftm_write(struct ftm_quaddec *ftm, uint32_t offset, uint32_t data) uint32_t 54 drivers/counter/ftm-quaddec.c uint32_t flag; uint32_t 122 drivers/counter/ftm-quaddec.c uint32_t scflags; uint32_t 184 drivers/counter/ftm-quaddec.c uint32_t cntval; uint32_t 257 drivers/cpufreq/arm_big_little.c uint32_t min_freq = ~0; uint32_t 268 drivers/cpufreq/arm_big_little.c uint32_t max_freq = 0; uint32_t 90 drivers/cpufreq/bmips-cpufreq.c uint32_t mode; uint32_t 975 drivers/cpufreq/intel_pstate.c uint32_t turbo_fp; uint32_t 114 drivers/cpufreq/pxa3xx-cpufreq.c uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK; uint32_t 115 drivers/cpufreq/pxa3xx-cpufreq.c uint32_t accr = ACCR; uint32_t 116 drivers/cpufreq/pxa3xx-cpufreq.c uint32_t xclkcfg; uint32_t 135 drivers/cpufreq/pxa3xx-cpufreq.c uint32_t mask; uint32_t 136 drivers/cpufreq/pxa3xx-cpufreq.c uint32_t accr = ACCR; uint32_t 47 drivers/crypto/mxs-dcp.c uint32_t next_cmd_addr; uint32_t 48 drivers/crypto/mxs-dcp.c uint32_t control0; uint32_t 49 drivers/crypto/mxs-dcp.c uint32_t control1; uint32_t 50 drivers/crypto/mxs-dcp.c uint32_t source; uint32_t 51 drivers/crypto/mxs-dcp.c uint32_t destination; uint32_t 52 drivers/crypto/mxs-dcp.c uint32_t size; uint32_t 53 drivers/crypto/mxs-dcp.c uint32_t payload; uint32_t 54 drivers/crypto/mxs-dcp.c uint32_t status; uint32_t 73 drivers/crypto/mxs-dcp.c uint32_t caps; uint32_t 92 drivers/crypto/mxs-dcp.c uint32_t fill; uint32_t 96 drivers/crypto/mxs-dcp.c uint32_t alg; uint32_t 173 drivers/crypto/mxs-dcp.c uint32_t stat; uint32_t 291 drivers/crypto/mxs-dcp.c uint32_t dst_off = 0; uint32_t 292 drivers/crypto/mxs-dcp.c uint32_t last_out_len = 0; uint32_t 963 drivers/crypto/mxs-dcp.c uint32_t stat; uint32_t 64 drivers/crypto/padlock-sha.c static inline void padlock_output_block(uint32_t *src, uint32_t 65 drivers/crypto/padlock-sha.c uint32_t *dst, size_t count) uint32_t 119 drivers/crypto/padlock-sha.c padlock_output_block((uint32_t *)result, (uint32_t *)out, 5); uint32_t 180 drivers/crypto/padlock-sha.c padlock_output_block((uint32_t *)result, (uint32_t *)out, 8); uint32_t 352 drivers/crypto/padlock-sha.c padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 5); uint32_t 437 drivers/crypto/padlock-sha.c padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 8); uint32_t 147 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t instances; uint32_t 157 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_accel_mask)(uint32_t fuse); uint32_t 158 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_ae_mask)(uint32_t fuse); uint32_t 159 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_sram_bar_id)(struct adf_hw_device_data *self); uint32_t 160 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_misc_bar_id)(struct adf_hw_device_data *self); uint32_t 161 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_etr_bar_id)(struct adf_hw_device_data *self); uint32_t 162 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_num_aes)(struct adf_hw_device_data *self); uint32_t 163 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_num_accels)(struct adf_hw_device_data *self); uint32_t 164 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_pf2vf_offset)(uint32_t i); uint32_t 165 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_vintmsk_offset)(uint32_t i); uint32_t 176 drivers/crypto/qat/qat_common/adf_accel_devices.h const uint32_t **cfg); uint32_t 183 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t fuses; uint32_t 184 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t accel_capabilities_mask; uint32_t 185 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t instance_id; uint32_t 121 drivers/crypto/qat/qat_common/adf_accel_engine.c uint32_t ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev); uint32_t 142 drivers/crypto/qat/qat_common/adf_accel_engine.c uint32_t ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev); uint32_t 104 drivers/crypto/qat/qat_common/adf_cfg_common.h #define IOCTL_STATUS_ACCEL_DEV _IOW(ADF_CTL_IOC_MAGIC, 3, uint32_t) uint32_t 126 drivers/crypto/qat/qat_common/adf_common_drv.h struct adf_accel_dev *adf_devmgr_get_dev_by_id(uint32_t id); uint32_t 129 drivers/crypto/qat/qat_common/adf_common_drv.h int adf_devmgr_verify_id(uint32_t id); uint32_t 130 drivers/crypto/qat/qat_common/adf_common_drv.h void adf_devmgr_get_num_dev(uint32_t *num); uint32_t 236 drivers/crypto/qat/qat_common/adf_common_drv.h uint32_t vf_mask); uint32_t 238 drivers/crypto/qat/qat_common/adf_common_drv.h uint32_t vf_mask); uint32_t 273 drivers/crypto/qat/qat_common/adf_ctl_drv.c static void adf_ctl_stop_devices(uint32_t id) uint32_t 377 drivers/crypto/qat/qat_common/adf_ctl_drv.c uint32_t num_devices = 0; uint32_t 55 drivers/crypto/qat/qat_common/adf_dev_mgr.c static uint32_t num_devices; uint32_t 358 drivers/crypto/qat/qat_common/adf_dev_mgr.c struct adf_accel_dev *adf_devmgr_get_dev_by_id(uint32_t id) uint32_t 383 drivers/crypto/qat/qat_common/adf_dev_mgr.c int adf_devmgr_verify_id(uint32_t id) uint32_t 410 drivers/crypto/qat/qat_common/adf_dev_mgr.c void adf_devmgr_get_num_dev(uint32_t *num) uint32_t 54 drivers/crypto/qat/qat_common/adf_transport.c static inline uint32_t adf_modulo(uint32_t data, uint32_t shift) uint32_t 56 drivers/crypto/qat/qat_common/adf_transport.c uint32_t div = data >> shift; uint32_t 57 drivers/crypto/qat/qat_common/adf_transport.c uint32_t mult = div << shift; uint32_t 69 drivers/crypto/qat/qat_common/adf_transport.c static int adf_verify_ring_size(uint32_t msg_size, uint32_t msg_num) uint32_t 80 drivers/crypto/qat/qat_common/adf_transport.c static int adf_reserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) uint32_t 92 drivers/crypto/qat/qat_common/adf_transport.c static void adf_unreserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) uint32_t 99 drivers/crypto/qat/qat_common/adf_transport.c static void adf_enable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring) uint32_t 109 drivers/crypto/qat/qat_common/adf_transport.c static void adf_disable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring) uint32_t 117 drivers/crypto/qat/qat_common/adf_transport.c int adf_send_message(struct adf_etr_ring_data *ring, uint32_t *msg) uint32_t 139 drivers/crypto/qat/qat_common/adf_transport.c uint32_t msg_counter = 0; uint32_t 140 drivers/crypto/qat/qat_common/adf_transport.c uint32_t *msg = (uint32_t *)((uintptr_t)ring->base_addr + ring->head); uint32_t 143 drivers/crypto/qat/qat_common/adf_transport.c ring->callback((uint32_t *)msg); uint32_t 150 drivers/crypto/qat/qat_common/adf_transport.c msg = (uint32_t *)((uintptr_t)ring->base_addr + ring->head); uint32_t 161 drivers/crypto/qat/qat_common/adf_transport.c uint32_t ring_config = BUILD_RING_CONFIG(ring->ring_size); uint32_t 169 drivers/crypto/qat/qat_common/adf_transport.c uint32_t ring_config = uint32_t 184 drivers/crypto/qat/qat_common/adf_transport.c uint32_t ring_size_bytes = uint32_t 218 drivers/crypto/qat/qat_common/adf_transport.c uint32_t ring_size_bytes = uint32_t 231 drivers/crypto/qat/qat_common/adf_transport.c uint32_t bank_num, uint32_t num_msgs, uint32_t 232 drivers/crypto/qat/qat_common/adf_transport.c uint32_t msg_size, const char *ring_name, uint32_t 240 drivers/crypto/qat/qat_common/adf_transport.c uint32_t ring_num; uint32_t 333 drivers/crypto/qat/qat_common/adf_transport.c uint32_t empty_rings, i; uint32_t 356 drivers/crypto/qat/qat_common/adf_transport.c uint32_t key, uint32_t *value) uint32_t 373 drivers/crypto/qat/qat_common/adf_transport.c uint32_t bank_num_in_accel) uint32_t 387 drivers/crypto/qat/qat_common/adf_transport.c uint32_t bank_num, void __iomem *csr_addr) uint32_t 392 drivers/crypto/qat/qat_common/adf_transport.c uint32_t i, coalesc_enabled = 0; uint32_t 464 drivers/crypto/qat/qat_common/adf_transport.c uint32_t size; uint32_t 465 drivers/crypto/qat/qat_common/adf_transport.c uint32_t num_banks = 0; uint32_t 511 drivers/crypto/qat/qat_common/adf_transport.c uint32_t i; uint32_t 531 drivers/crypto/qat/qat_common/adf_transport.c uint32_t i, num_banks = GET_MAX_BANKS(accel_dev); uint32_t 57 drivers/crypto/qat/qat_common/adf_transport.h uint32_t bank_num, uint32_t num_mgs, uint32_t msg_size, uint32_t 61 drivers/crypto/qat/qat_common/adf_transport.h int adf_send_message(struct adf_etr_ring_data *ring, uint32_t *msg); uint32_t 135 drivers/crypto/qat/qat_common/adf_transport_access_macros.h uint32_t l_base = 0, u_base = 0; \ uint32_t 136 drivers/crypto/qat/qat_common/adf_transport_access_macros.h l_base = (uint32_t)(value & 0xFFFFFFFF); \ uint32_t 137 drivers/crypto/qat/qat_common/adf_transport_access_macros.h u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \ uint32_t 80 drivers/crypto/qat/qat_common/adf_transport_internal.h uint32_t irq_coalesc_timer; uint32_t 86 drivers/crypto/qat/qat_common/adf_transport_internal.h uint32_t bank_number; uint32_t 96 drivers/crypto/qat/qat_common/icp_qat_fw.h uint32_t content_desc_resrvd3; uint32_t 99 drivers/crypto/qat/qat_common/icp_qat_fw.h uint32_t serv_specif_fields[4]; uint32_t 108 drivers/crypto/qat/qat_common/icp_qat_fw.h uint32_t src_length; uint32_t 109 drivers/crypto/qat/qat_common/icp_qat_fw.h uint32_t dst_length; uint32_t 113 drivers/crypto/qat/qat_common/icp_qat_fw.h uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5]; uint32_t 126 drivers/crypto/qat/qat_common/icp_qat_fw.h uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13]; uint32_t 155 drivers/crypto/qat/qat_common/icp_qat_fw.h uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; uint32_t 73 drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h uint32_t resrvd2; uint32_t 88 drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_4]; uint32_t 90 drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h uint32_t version_patch_num; uint32_t 106 drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h uint32_t resrvd2; uint32_t 233 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t content_desc_resrvd3; uint32_t 236 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4]; uint32_t 248 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t content_desc_resrvd3; uint32_t 251 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4]; uint32_t 264 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3]; uint32_t 268 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t resrvd1; uint32_t 318 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t cipher_offset; uint32_t 319 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t cipher_length; uint32_t 321 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4]; uint32_t 330 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t auth_off; uint32_t 331 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t auth_len; uint32_t 347 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6]; uint32_t 359 drivers/crypto/qat/qat_common/icp_qat_fw_la.h uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; uint32_t 108 drivers/crypto/qat/qat_common/icp_qat_hw.h uint32_t config; uint32_t 109 drivers/crypto/qat/qat_common/icp_qat_hw.h uint32_t reserved; uint32_t 134 drivers/crypto/qat/qat_common/icp_qat_hw.h uint32_t reserved; uint32_t 230 drivers/crypto/qat/qat_common/icp_qat_hw.h uint32_t val; uint32_t 231 drivers/crypto/qat/qat_common/icp_qat_hw.h uint32_t reserved; uint32_t 80 drivers/crypto/qat/qat_common/qat_algs.c uint32_t len; uint32_t 81 drivers/crypto/qat/qat_common/qat_algs.c uint32_t resrvd; uint32_t 87 drivers/crypto/qat/qat_common/qat_algs.c uint32_t num_bufs; uint32_t 88 drivers/crypto/qat/qat_common/qat_algs.c uint32_t num_mapped_bufs; uint32_t 897 drivers/crypto/qat/qat_common/qat_algs.c ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg); uint32_t 942 drivers/crypto/qat/qat_common/qat_algs.c ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg); uint32_t 1088 drivers/crypto/qat/qat_common/qat_algs.c ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg); uint32_t 1148 drivers/crypto/qat/qat_common/qat_algs.c ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg); uint32_t 392 drivers/crypto/qat/qat_common/qat_asym_algs.c ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg); uint32_t 786 drivers/crypto/qat/qat_common/qat_asym_algs.c ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg); uint32_t 938 drivers/crypto/qat/qat_common/qat_asym_algs.c ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg); uint32_t 53 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static const uint32_t thrd_to_arb_map_sku4[] = { uint32_t 59 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static const uint32_t thrd_to_arb_map_sku6[] = { uint32_t 71 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_accel_mask(uint32_t fuse) uint32_t 77 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_ae_mask(uint32_t fuse) uint32_t 82 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_num_accels(struct adf_hw_device_data *self) uint32_t 84 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c uint32_t i, ctr = 0; uint32_t 96 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_num_aes(struct adf_hw_device_data *self) uint32_t 98 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c uint32_t i, ctr = 0; uint32_t 110 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_misc_bar_id(struct adf_hw_device_data *self) uint32_t 115 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_etr_bar_id(struct adf_hw_device_data *self) uint32_t 120 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_sram_bar_id(struct adf_hw_device_data *self) uint32_t 164 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_pf2vf_offset(uint32_t i) uint32_t 169 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_vintmsk_offset(uint32_t i) uint32_t 73 drivers/crypto/rockchip/rk3288_crypto.c in = IS_ALIGNED((uint32_t)sg_src->offset, 4) && uint32_t 74 drivers/crypto/rockchip/rk3288_crypto.c IS_ALIGNED((uint32_t)sg_src->length, align_mask); uint32_t 77 drivers/crypto/rockchip/rk3288_crypto.c out = IS_ALIGNED((uint32_t)sg_dst->offset, 4) && uint32_t 78 drivers/crypto/rockchip/rk3288_crypto.c IS_ALIGNED((uint32_t)sg_dst->length, align_mask); uint32_t 32 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t type; uint32_t 41 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t algonum; uint32_t 42 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t service; uint32_t 99 drivers/crypto/virtio/virtio_crypto_algs.c virtio_crypto_alg_validate_key(int key_len, uint32_t *alg) uint32_t 115 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t alg, const uint8_t *key, uint32_t 268 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t alg; uint32_t 305 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t alg; uint32_t 425 drivers/crypto/virtio/virtio_crypto_algs.c cpu_to_le32((uint32_t)dst_len); uint32_t 633 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t service = virtio_crypto_algs[i].service; uint32_t 634 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t algonum = virtio_crypto_algs[i].algonum; uint32_t 663 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t service = virtio_crypto_algs[i].service; uint32_t 664 drivers/crypto/virtio/virtio_crypto_algs.c uint32_t algonum = virtio_crypto_algs[i].algonum; uint32_t 108 drivers/crypto/virtio/virtio_crypto_common.h uint32_t service, uint32_t 109 drivers/crypto/virtio/virtio_crypto_common.h uint32_t algo); uint32_t 111 drivers/crypto/virtio/virtio_crypto_common.h uint32_t service, uint32_t 112 drivers/crypto/virtio/virtio_crypto_common.h uint32_t algo); uint32_t 15 drivers/crypto/virtio/virtio_crypto_mgr.c static uint32_t num_devices; uint32_t 184 drivers/crypto/virtio/virtio_crypto_mgr.c struct virtio_crypto *virtcrypto_get_dev_node(int node, uint32_t service, uint32_t 185 drivers/crypto/virtio/virtio_crypto_mgr.c uint32_t algo) uint32_t 278 drivers/crypto/virtio/virtio_crypto_mgr.c uint32_t service, uint32_t 279 drivers/crypto/virtio/virtio_crypto_mgr.c uint32_t algo) uint32_t 281 drivers/crypto/virtio/virtio_crypto_mgr.c uint32_t service_mask = 1u << service; uint32_t 282 drivers/crypto/virtio/virtio_crypto_mgr.c uint32_t algo_mask = 0; uint32_t 313 drivers/devfreq/rk3399_dmc.c uint32_t *timing; uint32_t 525 drivers/dma-buf/dma-fence.c dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, uint32_t 526 drivers/dma-buf/dma-fence.c uint32_t *idx) uint32_t 562 drivers/dma-buf/dma-fence.c dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, uint32_t 563 drivers/dma-buf/dma-fence.c bool intr, signed long timeout, uint32_t *idx) uint32_t 56 drivers/dma/bcm2835-dma.c uint32_t info; uint32_t 57 drivers/dma/bcm2835-dma.c uint32_t src; uint32_t 58 drivers/dma/bcm2835-dma.c uint32_t dst; uint32_t 59 drivers/dma/bcm2835-dma.c uint32_t length; uint32_t 60 drivers/dma/bcm2835-dma.c uint32_t stride; uint32_t 61 drivers/dma/bcm2835-dma.c uint32_t next; uint32_t 62 drivers/dma/bcm2835-dma.c uint32_t pad[2]; uint32_t 892 drivers/dma/bcm2835-dma.c uint32_t chans_available; uint32_t 107 drivers/dma/dma-jz4780.c uint32_t dcm; uint32_t 108 drivers/dma/dma-jz4780.c uint32_t dsa; uint32_t 109 drivers/dma/dma-jz4780.c uint32_t dta; uint32_t 110 drivers/dma/dma-jz4780.c uint32_t dtc; uint32_t 125 drivers/dma/dma-jz4780.c uint32_t status; uint32_t 133 drivers/dma/dma-jz4780.c uint32_t transfer_type; uint32_t 134 drivers/dma/dma-jz4780.c uint32_t transfer_shift; uint32_t 155 drivers/dma/dma-jz4780.c uint32_t chan_reserved; uint32_t 160 drivers/dma/dma-jz4780.c uint32_t transfer_type; uint32_t 182 drivers/dma/dma-jz4780.c static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma, uint32_t 189 drivers/dma/dma-jz4780.c unsigned int chn, unsigned int reg, uint32_t val) uint32_t 194 drivers/dma/dma-jz4780.c static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma, uint32_t 201 drivers/dma/dma-jz4780.c unsigned int reg, uint32_t val) uint32_t 263 drivers/dma/dma-jz4780.c static uint32_t jz4780_dma_transfer_size(struct jz4780_dma_chan *jzchan, uint32_t 264 drivers/dma/dma-jz4780.c unsigned long val, uint32_t *shift) uint32_t 306 drivers/dma/dma-jz4780.c uint32_t width, maxburst, tsz; uint32_t 456 drivers/dma/dma-jz4780.c uint32_t tsz; uint32_t 672 drivers/dma/dma-jz4780.c uint32_t dcs; uint32_t 729 drivers/dma/dma-jz4780.c uint32_t dmac; uint32_t 72 drivers/dma/ioat/hw.h uint32_t size; uint32_t 74 drivers/dma/ioat/hw.h uint32_t ctl; uint32_t 106 drivers/dma/ioat/hw.h uint32_t size; uint32_t 108 drivers/dma/ioat/hw.h uint32_t ctl; uint32_t 144 drivers/dma/ioat/hw.h uint32_t size; uint32_t 145 drivers/dma/ioat/hw.h uint32_t dwbes; uint32_t 155 drivers/dma/ioat/hw.h uint32_t ctl; uint32_t 202 drivers/dma/ioat/hw.h uint32_t size; uint32_t 204 drivers/dma/ioat/hw.h uint32_t ctl; uint32_t 88 drivers/dma/ipu/ipu_idmac.c static uint32_t bytes_per_pixel(enum pixel_fmt fmt) uint32_t 115 drivers/dma/ipu/ipu_idmac.c uint32_t ic_conf, mask; uint32_t 134 drivers/dma/ipu/ipu_idmac.c uint32_t ic_conf, mask; uint32_t 150 drivers/dma/ipu/ipu_idmac.c static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel) uint32_t 152 drivers/dma/ipu/ipu_idmac.c uint32_t stat = TASK_STAT_IDLE; uint32_t 153 drivers/dma/ipu/ipu_idmac.c uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT); uint32_t 283 drivers/dma/ipu/ipu_idmac.c uint32_t pixel_fmt, uint16_t width, uint32_t 435 drivers/dma/ipu/ipu_idmac.c static void ipu_write_param_mem(uint32_t addr, uint32_t *data, uint32_t 436 drivers/dma/ipu/ipu_idmac.c uint32_t num_words) uint32_t 452 drivers/dma/ipu/ipu_idmac.c static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size, uint32_t 453 drivers/dma/ipu/ipu_idmac.c uint32_t *resize_coeff, uint32_t 454 drivers/dma/ipu/ipu_idmac.c uint32_t *downsize_coeff) uint32_t 456 drivers/dma/ipu/ipu_idmac.c uint32_t temp_size; uint32_t 457 drivers/dma/ipu/ipu_idmac.c uint32_t temp_downsize; uint32_t 511 drivers/dma/ipu/ipu_idmac.c uint32_t reg, ic_conf; uint32_t 512 drivers/dma/ipu/ipu_idmac.c uint32_t downsize_coeff, resize_coeff; uint32_t 554 drivers/dma/ipu/ipu_idmac.c static uint32_t dma_param_addr(uint32_t dma_ch) uint32_t 575 drivers/dma/ipu/ipu_idmac.c static uint32_t ipu_channel_conf_mask(enum ipu_channel channel) uint32_t 577 drivers/dma/ipu/ipu_idmac.c uint32_t mask; uint32_t 606 drivers/dma/ipu/ipu_idmac.c uint32_t reg; uint32_t 653 drivers/dma/ipu/ipu_idmac.c uint32_t stride, uint32_t 662 drivers/dma/ipu/ipu_idmac.c uint32_t reg; uint32_t 663 drivers/dma/ipu/ipu_idmac.c uint32_t stride_bytes; uint32_t 687 drivers/dma/ipu/ipu_idmac.c ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10); uint32_t 733 drivers/dma/ipu/ipu_idmac.c uint32_t reg; uint32_t 951 drivers/dma/ipu/ipu_idmac.c uint32_t ipu_conf; uint32_t 954 drivers/dma/ipu/ipu_idmac.c uint32_t reg; uint32_t 1011 drivers/dma/ipu/ipu_idmac.c uint32_t reg; uint32_t 1013 drivers/dma/ipu/ipu_idmac.c uint32_t ipu_conf; uint32_t 1074 drivers/dma/ipu/ipu_idmac.c uint32_t reg; uint32_t 169 drivers/dma/ipu/ipu_intern.h extern bool ipu_irq_status(uint32_t irq); uint32_t 97 drivers/dma/ipu/ipu_irq.c uint32_t reg; uint32_t 120 drivers/dma/ipu/ipu_irq.c uint32_t reg; uint32_t 120 drivers/dma/moxart-dma.c uint32_t len; uint32_t 37 drivers/dma/ti/omap-dma.c uint32_t irq_enable_mask; uint32_t 45 drivers/dma/ti/omap-dma.c uint32_t ccr; uint32_t 66 drivers/dma/ti/omap-dma.c uint32_t next_desc; uint32_t 67 drivers/dma/ti/omap-dma.c uint32_t en; uint32_t 68 drivers/dma/ti/omap-dma.c uint32_t addr; /* src or dst */ uint32_t 79 drivers/dma/ti/omap-dma.c uint32_t en; /* number of elements (24-bit) */ uint32_t 80 drivers/dma/ti/omap-dma.c uint32_t fn; /* number of frames (16-bit) */ uint32_t 99 drivers/dma/ti/omap-dma.c uint32_t ccr; /* CCR value */ uint32_t 102 drivers/dma/ti/omap-dma.c uint32_t csdp; /* CSDP value */ uint32_t 288 drivers/dma/ti/omap-dma.c static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr) uint32_t 400 drivers/dma/ti/omap-dma.c uint32_t cdp = CDP_TMODE_LLIST | CDP_NTYPE_TYPE2 | CDP_FAST; uint32_t 453 drivers/dma/ti/omap-dma.c uint32_t val; uint32_t 462 drivers/dma/ti/omap-dma.c uint32_t sysconfig; uint32_t 749 drivers/dma/ti/omap-dma.c static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg) uint32_t 752 drivers/dma/ti/omap-dma.c uint32_t val; uint32_t 857 drivers/dma/ti/omap-dma.c uint32_t ccr = omap_dma_chan_read(c, CCR); uint32_t 82 drivers/edac/armada_xp_edac.c static uint32_t axp_mc_calc_address(struct axp_mc_drvdata *drvdata, uint32_t 128 drivers/edac/armada_xp_edac.c uint32_t data_h, data_l, recv_ecc, calc_ecc, addr; uint32_t 129 drivers/edac/armada_xp_edac.c uint32_t cnt_sbe, cnt_dbe, cause_err, cause_msg; uint32_t 130 drivers/edac/armada_xp_edac.c uint32_t row_val, col_val, bank_val, addr_val; uint32_t 222 drivers/edac/armada_xp_edac.c uint32_t config, addr_ctrl, rank_ctrl; uint32_t 291 drivers/edac/armada_xp_edac.c uint32_t config; uint32_t 389 drivers/edac/armada_xp_edac.c uint32_t inject_addr; uint32_t 390 drivers/edac/armada_xp_edac.c uint32_t inject_mask; uint32_t 410 drivers/edac/armada_xp_edac.c uint32_t cnt, src, txn, err, attr_cap, addr_cap, way_cap; uint32_t 517 drivers/edac/armada_xp_edac.c uint32_t l2x0_aux_ctrl; uint32_t 48 drivers/firmware/tegra/bpmp-debugfs.c static int seqbuf_read_u32(struct seqbuf *seqbuf, uint32_t *v) uint32_t 107 drivers/firmware/tegra/bpmp-debugfs.c .fnameaddr = cpu_to_le32((uint32_t)name), uint32_t 108 drivers/firmware/tegra/bpmp-debugfs.c .fnamelen = cpu_to_le32((uint32_t)sz_name), uint32_t 109 drivers/firmware/tegra/bpmp-debugfs.c .dataaddr = cpu_to_le32((uint32_t)data), uint32_t 110 drivers/firmware/tegra/bpmp-debugfs.c .datalen = cpu_to_le32((uint32_t)sz_data), uint32_t 143 drivers/firmware/tegra/bpmp-debugfs.c .fnameaddr = cpu_to_le32((uint32_t)name), uint32_t 144 drivers/firmware/tegra/bpmp-debugfs.c .fnamelen = cpu_to_le32((uint32_t)sz_name), uint32_t 145 drivers/firmware/tegra/bpmp-debugfs.c .dataaddr = cpu_to_le32((uint32_t)data), uint32_t 146 drivers/firmware/tegra/bpmp-debugfs.c .datalen = cpu_to_le32((uint32_t)sz_data), uint32_t 166 drivers/firmware/tegra/bpmp-debugfs.c .dataaddr = cpu_to_le32((uint32_t)addr), uint32_t 167 drivers/firmware/tegra/bpmp-debugfs.c .datalen = cpu_to_le32((uint32_t)size), uint32_t 302 drivers/firmware/tegra/bpmp-debugfs.c struct dentry *parent, uint32_t depth) uint32_t 305 drivers/firmware/tegra/bpmp-debugfs.c uint32_t d, t; uint32_t 87 drivers/fsi/fsi-core.c uint32_t size; /* size of slave address space */ uint32_t 106 drivers/fsi/fsi-core.c uint8_t slave_id, uint32_t addr, void *val, size_t size); uint32_t 108 drivers/fsi/fsi-core.c uint8_t slave_id, uint32_t addr, const void *val, size_t size); uint32_t 128 drivers/fsi/fsi-core.c int fsi_device_read(struct fsi_device *dev, uint32_t addr, void *val, uint32_t 138 drivers/fsi/fsi-core.c int fsi_device_write(struct fsi_device *dev, uint32_t addr, const void *val, uint32_t 150 drivers/fsi/fsi-core.c uint32_t addr = FSI_PEEK_BASE + ((dev->unit - 2) * sizeof(uint32_t)); uint32_t 152 drivers/fsi/fsi-core.c return fsi_slave_read(dev->slave, addr, val, sizeof(uint32_t)); uint32_t 179 drivers/fsi/fsi-core.c static int fsi_slave_calc_addr(struct fsi_slave *slave, uint32_t *addrp, uint32_t 182 drivers/fsi/fsi-core.c uint32_t addr = *addrp; uint32_t 232 drivers/fsi/fsi-core.c static inline uint32_t fsi_smode_echodly(int x) uint32_t 238 drivers/fsi/fsi-core.c static inline uint32_t fsi_smode_senddly(int x) uint32_t 244 drivers/fsi/fsi-core.c static inline uint32_t fsi_smode_lbcrr(int x) uint32_t 250 drivers/fsi/fsi-core.c static inline uint32_t fsi_smode_sid(int x) uint32_t 255 drivers/fsi/fsi-core.c static uint32_t fsi_slave_smode(int id, u8 t_senddly, u8 t_echodly) uint32_t 265 drivers/fsi/fsi-core.c uint32_t smode; uint32_t 280 drivers/fsi/fsi-core.c uint32_t addr, size_t size) uint32_t 284 drivers/fsi/fsi-core.c uint32_t reg; uint32_t 339 drivers/fsi/fsi-core.c int fsi_slave_read(struct fsi_slave *slave, uint32_t addr, uint32_t 364 drivers/fsi/fsi-core.c int fsi_slave_write(struct fsi_slave *slave, uint32_t addr, uint32_t 390 drivers/fsi/fsi-core.c uint32_t addr, uint32_t size) uint32_t 404 drivers/fsi/fsi-core.c uint32_t addr, uint32_t size) uint32_t 410 drivers/fsi/fsi-core.c uint32_t addr, uint32_t size) uint32_t 414 drivers/fsi/fsi-core.c uint32_t psize; uint32_t 462 drivers/fsi/fsi-core.c uint32_t engine_addr; uint32_t 473 drivers/fsi/fsi-core.c for (i = 2; i < engine_page_size / sizeof(uint32_t); i++) { uint32_t 476 drivers/fsi/fsi-core.c uint32_t conf; uint32_t 981 drivers/fsi/fsi-core.c uint32_t cfam_id; uint32_t 1049 drivers/fsi/fsi-core.c uint32_t prop; uint32_t 1109 drivers/fsi/fsi-core.c static int fsi_check_access(uint32_t addr, size_t size) uint32_t 1124 drivers/fsi/fsi-core.c uint8_t slave_id, uint32_t addr, void *val, size_t size) uint32_t 1141 drivers/fsi/fsi-core.c uint8_t slave_id, uint32_t addr, const void *val, size_t size) uint32_t 106 drivers/fsi/fsi-master-ast-cf.c uint32_t cf_mem_addr; uint32_t 115 drivers/fsi/fsi-master-ast-cf.c uint32_t last_addr; uint32_t 118 drivers/fsi/fsi-master-ast-cf.c uint32_t cvic_sw_irq; uint32_t 160 drivers/fsi/fsi-master-ast-cf.c uint32_t addr) uint32_t 167 drivers/fsi/fsi-master-ast-cf.c uint32_t addr, uint32_t *rel_addrp) uint32_t 169 drivers/fsi/fsi-master-ast-cf.c uint32_t last_addr = master->last_addr; uint32_t 191 drivers/fsi/fsi-master-ast-cf.c *rel_addrp = (uint32_t)rel_addr; uint32_t 197 drivers/fsi/fsi-master-ast-cf.c int id, bool valid, uint32_t addr) uint32_t 210 drivers/fsi/fsi-master-ast-cf.c uint32_t addr, size_t size, uint32_t 216 drivers/fsi/fsi-master-ast-cf.c uint32_t rel_addr; uint32_t 307 drivers/fsi/fsi-master-ast-cf.c static int do_copro_command(struct fsi_master_acf *master, uint32_t op) uint32_t 309 drivers/fsi/fsi-master-ast-cf.c uint32_t timeout = 10000000; uint32_t 361 drivers/fsi/fsi-master-ast-cf.c uint32_t op; uint32_t 378 drivers/fsi/fsi-master-ast-cf.c uint32_t *response, u8 *tag) uint32_t 382 drivers/fsi/fsi-master-ast-cf.c uint32_t rdata = 0; uint32_t 383 drivers/fsi/fsi-master-ast-cf.c uint32_t crc; uint32_t 473 drivers/fsi/fsi-master-ast-cf.c uint32_t response; uint32_t 598 drivers/fsi/fsi-master-ast-cf.c uint8_t id, uint32_t addr, void *val, uint32_t 622 drivers/fsi/fsi-master-ast-cf.c uint8_t id, uint32_t addr, const void *val, uint32_t 635 drivers/fsi/fsi-master-ast-cf.c id, addr, size, *(uint32_t *)val); uint32_t 882 drivers/fsi/fsi-master-ast-cf.c uint32_t fw_vers, fw_api, fw_options; uint32_t 905 drivers/fsi/fsi-master-ast-cf.c uint32_t val; uint32_t 928 drivers/fsi/fsi-master-ast-cf.c uint32_t val; uint32_t 1219 drivers/fsi/fsi-master-ast-cf.c uint32_t cf_mem_align; uint32_t 1301 drivers/fsi/fsi-master-ast-cf.c master->cf_mem_addr = (uint32_t)res.start; uint32_t 34 drivers/fsi/fsi-master-gpio.c uint32_t last_addr; uint32_t 186 drivers/fsi/fsi-master-gpio.c uint32_t addr) uint32_t 193 drivers/fsi/fsi-master-gpio.c uint32_t addr, uint32_t *rel_addrp) uint32_t 195 drivers/fsi/fsi-master-gpio.c uint32_t last_addr = master->last_addr; uint32_t 217 drivers/fsi/fsi-master-gpio.c *rel_addrp = (uint32_t)rel_addr; uint32_t 223 drivers/fsi/fsi-master-gpio.c int id, bool valid, uint32_t addr) uint32_t 236 drivers/fsi/fsi-master-gpio.c uint32_t addr, size_t size, const void *data) uint32_t 241 drivers/fsi/fsi-master-gpio.c uint32_t rel_addr; uint32_t 339 drivers/fsi/fsi-master-gpio.c uint32_t crc; uint32_t 562 drivers/fsi/fsi-master-gpio.c uint8_t id, uint32_t addr, void *val, size_t size) uint32_t 581 drivers/fsi/fsi-master-gpio.c uint8_t id, uint32_t addr, const void *val, size_t size) uint32_t 85 drivers/fsi/fsi-master-hub.c uint32_t addr, size; /* slave-relative addr of */ uint32_t 92 drivers/fsi/fsi-master-hub.c uint8_t id, uint32_t addr, void *val, size_t size) uint32_t 104 drivers/fsi/fsi-master-hub.c uint8_t id, uint32_t addr, const void *val, size_t size) uint32_t 117 drivers/fsi/fsi-master-hub.c uint32_t addr; uint32_t 240 drivers/fsi/fsi-master-hub.c uint32_t reg, links; uint32_t 57 drivers/fsi/fsi-master.h uint32_t addr, void *val, size_t size); uint32_t 59 drivers/fsi/fsi-master.h uint32_t addr, const void *val, size_t size); uint32_t 118 drivers/fsi/fsi-sbefifo.c uint32_t magic; uint32_t 76 drivers/fsi/fsi-scom.c uint32_t addr, uint32_t *status) uint32_t 83 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 89 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 95 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 99 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 108 drivers/fsi/fsi-scom.c uint32_t addr, uint32_t *status) uint32_t 117 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 121 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 130 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 135 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 145 drivers/fsi/fsi-scom.c uint64_t addr, uint32_t *status) uint32_t 175 drivers/fsi/fsi-scom.c uint64_t addr, uint32_t *status) uint32_t 188 drivers/fsi/fsi-scom.c uint64_t addr, uint32_t *status) uint32_t 217 drivers/fsi/fsi-scom.c uint64_t addr, uint32_t *status) uint32_t 229 drivers/fsi/fsi-scom.c uint64_t addr, uint32_t *status) uint32_t 239 drivers/fsi/fsi-scom.c static int handle_fsi2pib_status(struct scom_device *scom, uint32_t status) uint32_t 241 drivers/fsi/fsi-scom.c uint32_t dummy = -1; uint32_t 247 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 258 drivers/fsi/fsi-scom.c uint32_t dummy = -1; uint32_t 267 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 287 drivers/fsi/fsi-scom.c uint32_t status, dummy = -1; uint32_t 296 drivers/fsi/fsi-scom.c &dummy, sizeof(uint32_t)); uint32_t 321 drivers/fsi/fsi-scom.c uint32_t status, dummy = -1; uint32_t 330 drivers/fsi/fsi-scom.c &dummy, sizeof(uint32_t)); uint32_t 427 drivers/fsi/fsi-scom.c static void raw_convert_status(struct scom_access *acc, uint32_t status) uint32_t 446 drivers/fsi/fsi-scom.c uint32_t status; uint32_t 465 drivers/fsi/fsi-scom.c uint32_t status; uint32_t 494 drivers/fsi/fsi-scom.c uint32_t flags, dummy = -1; uint32_t 501 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 504 drivers/fsi/fsi-scom.c sizeof(uint32_t)); uint32_t 150 drivers/gpio/gpio-cs5535.c uint32_t lo, hi; uint32_t 168 drivers/gpio/gpio-cs5535.c uint32_t shift = (offset % 8) * 4; uint32_t 170 drivers/gpio/gpio-cs5535.c uint32_t val; uint32_t 558 drivers/gpio/gpio-max732x.c uint32_t id_data = (uint32_t)max732x_features[id->driver_data]; uint32_t 263 drivers/gpio/gpio-pxa.c uint32_t value, mask = GPIO_bit(offset); uint32_t 290 drivers/gpio/gpio-pxa.c uint32_t tmp, mask = GPIO_bit(offset); uint32_t 389 drivers/gpio/gpio-pxa.c uint32_t grer, gfer; uint32_t 502 drivers/gpio/gpio-pxa.c uint32_t grer, gfer; uint32_t 33 drivers/gpio/sgpio-aspeed.c uint32_t dir_in[3]; uint32_t 104 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t num_gpu; uint32_t 105 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t num_dgpu; uint32_t 106 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t num_apu; uint32_t 319 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t default_mclk; uint32_t 320 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t default_sclk; uint32_t 321 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t default_dispclk; uint32_t 322 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t current_dispclk; uint32_t 323 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t dp_extclk; uint32_t 324 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t max_pixel_clock; uint32_t 362 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t domain; uint32_t 363 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t align; uint32_t 406 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t length_dw; uint32_t 408 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t *ptr; uint32_t 409 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t flags; uint32_t 445 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t chunk_id; uint32_t 446 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t length_dw; uint32_t 490 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t ib_idx, int idx) uint32_t 496 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t ib_idx, int idx, uint32_t 497 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t value) uint32_t 509 drivers/gpu/drm/amd/amdgpu/amdgpu.h volatile uint32_t *wb; uint32_t 533 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t reg_offset; uint32_t 601 drivers/gpu/drm/amd/amdgpu/amdgpu.h volatile uint32_t *ptr; uint32_t 638 drivers/gpu/drm/amd/amdgpu/amdgpu.h typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); uint32_t 639 drivers/gpu/drm/amd/amdgpu/amdgpu.h typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); uint32_t 641 drivers/gpu/drm/amd/amdgpu/amdgpu.h typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); uint32_t 642 drivers/gpu/drm/amd/amdgpu/amdgpu.h typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); uint32_t 644 drivers/gpu/drm/amd/amdgpu/amdgpu.h typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); uint32_t 645 drivers/gpu/drm/amd/amdgpu/amdgpu.h typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); uint32_t 728 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val); uint32_t 729 drivers/gpu/drm/amd/amdgpu/amdgpu.h void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val, uint32_t 730 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t ficadl_val, uint32_t ficadh_val); uint32_t 785 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t family; uint32_t 786 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t rev_id; uint32_t 787 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t external_rev_id; uint32_t 814 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t bios_size; uint32_t 817 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t bios_scratch_reg_offset; uint32_t 818 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; uint32_t 976 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; uint32_t 1032 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t flags); uint32_t 1036 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t 1037 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t acc_flags); uint32_t 1038 drivers/gpu/drm/amd/amdgpu/amdgpu.h void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t 1039 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t acc_flags); uint32_t 1040 drivers/gpu/drm/amd/amdgpu/amdgpu.h void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); uint32_t 1041 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); uint32_t 1091 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t tmp_ = RREG32(reg); \ uint32_t 1100 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t tmp_ = RREG32_PLL(reg); \ uint32_t 1236 drivers/gpu/drm/amd/amdgpu/amdgpu.h struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); uint32_t 51 drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) uint32_t 88 drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) uint32_t 385 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, uint32_t 466 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd) uint32_t 505 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c size_t buffer_size, uint32_t *metadata_size, uint32_t 506 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c uint32_t *flags) uint32_t 593 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd) uint32_t 601 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c uint32_t vmid, uint64_t gpu_addr, uint32_t 602 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c uint32_t *ib_cmd, uint32_t ib_len) uint32_t 56 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h uint32_t domain; uint32_t 60 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h uint32_t mapping_flags; uint32_t 135 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h uint32_t vmid, uint64_t gpu_addr, uint32_t 136 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h uint32_t *ib_cmd, uint32_t ib_len); uint32_t 163 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, uint32_t 169 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd); uint32_t 174 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h size_t buffer_size, uint32_t *metadata_size, uint32_t 175 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h uint32_t *flags); uint32_t 179 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd); uint32_t 213 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h uint64_t *offset, uint32_t flags); uint32_t 72 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, uint32_t 76 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t base[8] = { uint32_t 94 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t retval; uint32_t 131 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t __user *wptr, struct mm_struct *mm) uint32_t 135 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t sdma_base_addr, sdmax_gfx_context_cntl; uint32_t 137 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t data; uint32_t 204 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t engine_id, uint32_t queue_id, uint32_t 205 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t (**dump)[2], uint32_t *n_regs) uint32_t 208 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); uint32_t 209 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t i = 0, reg; uint32_t 213 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); uint32_t 238 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t sdma_base_addr; uint32_t 239 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t sdma_rlc_rb_cntl; uint32_t 258 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t sdma_base_addr; uint32_t 259 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t temp; uint32_t 57 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, uint32_t 58 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sh_mem_config, uint32_t 59 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, uint32_t 60 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sh_mem_bases); uint32_t 63 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); uint32_t 64 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t 65 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t queue_id, uint32_t __user *wptr, uint32_t 66 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t wptr_shift, uint32_t wptr_mask, uint32_t 69 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t pipe_id, uint32_t queue_id, uint32_t 70 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t (**dump)[2], uint32_t *n_regs); uint32_t 72 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t __user *wptr, struct mm_struct *mm); uint32_t 74 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t engine_id, uint32_t queue_id, uint32_t 75 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t (**dump)[2], uint32_t *n_regs); uint32_t 77 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t pipe_id, uint32_t queue_id); uint32_t 81 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c unsigned int utimeout, uint32_t pipe_id, uint32_t 82 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t queue_id); uint32_t 86 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static uint32_t get_watch_base_addr(struct amdgpu_device *adev); uint32_t 91 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t cntl_val, uint32_t 92 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t addr_hi, uint32_t 93 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t addr_lo); uint32_t 95 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t gfx_index_val, uint32_t 96 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sq_cmd); uint32_t 97 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, uint32_t 105 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, uint32_t 178 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, uint32_t 179 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t queue, uint32_t vmid) uint32_t 195 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t 196 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t queue_id) uint32_t 200 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; uint32_t 201 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); uint32_t 206 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static uint32_t get_queue_mask(struct amdgpu_device *adev, uint32_t 207 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t pipe_id, uint32_t queue_id) uint32_t 212 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c return ((uint32_t)1) << bit; uint32_t 220 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, uint32_t 221 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sh_mem_config, uint32_t 222 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sh_mem_ape1_base, uint32_t 223 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sh_mem_ape1_limit, uint32_t 224 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sh_mem_bases) uint32_t 249 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | uint32_t 289 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) uint32_t 292 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t mec; uint32_t 293 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t pipe; uint32_t 309 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, uint32_t 313 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t base[2] = { uint32_t 325 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t retval; uint32_t 336 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static uint32_t get_watch_base_addr(struct amdgpu_device *adev) uint32_t 338 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) - uint32_t 357 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t 358 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t queue_id, uint32_t __user *wptr, uint32_t 359 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t wptr_shift, uint32_t wptr_mask, uint32_t 364 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t *mqd_hqd; uint32_t 365 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t reg, hqd_base, data; uint32_t 374 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t value, mec, pipe; uint32_t 418 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t queue_size = uint32_t 455 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t pipe_id, uint32_t queue_id, uint32_t 456 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t (**dump)[2], uint32_t *n_regs) uint32_t 459 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t i = 0, reg; uint32_t 468 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); uint32_t 487 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t __user *wptr, struct mm_struct *mm) uint32_t 491 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sdma_base_addr, sdmax_gfx_context_cntl; uint32_t 493 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t data; uint32_t 562 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t engine_id, uint32_t queue_id, uint32_t 563 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t (**dump)[2], uint32_t *n_regs) uint32_t 566 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); uint32_t 567 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t i = 0, reg; uint32_t 574 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); uint32_t 596 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t pipe_id, uint32_t queue_id) uint32_t 599 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t act; uint32_t 601 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t low, high; uint32_t 621 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sdma_base_addr; uint32_t 622 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sdma_rlc_rb_cntl; uint32_t 638 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c unsigned int utimeout, uint32_t pipe_id, uint32_t 639 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t queue_id) uint32_t 644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t temp; uint32_t 749 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sdma_base_addr; uint32_t 750 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t temp; uint32_t 785 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t reg; uint32_t 796 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t reg; uint32_t 807 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t seq; uint32_t 874 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t cntl_val, uint32_t 875 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t addr_hi, uint32_t 876 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t addr_lo) uint32_t 882 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t gfx_index_val, uint32_t 883 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t sq_cmd) uint32_t 886 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t data = 0; uint32_t 906 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, uint32_t 913 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, uint32_t 69 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = { uint32_t 78 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t mask:24; uint32_t 79 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t vmid:4; uint32_t 80 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t atc:1; uint32_t 81 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t mode:2; uint32_t 82 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t valid:1; uint32_t 84 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t u32All; uint32_t 93 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, uint32_t 94 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, uint32_t 95 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases); uint32_t 100 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); uint32_t 101 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t 102 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t queue_id, uint32_t __user *wptr, uint32_t 103 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t wptr_shift, uint32_t wptr_mask, uint32_t 106 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t pipe_id, uint32_t queue_id, uint32_t 107 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t (**dump)[2], uint32_t *n_regs); uint32_t 109 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t __user *wptr, struct mm_struct *mm); uint32_t 111 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t engine_id, uint32_t queue_id, uint32_t 112 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t (**dump)[2], uint32_t *n_regs); uint32_t 114 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t pipe_id, uint32_t queue_id); uint32_t 118 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c unsigned int utimeout, uint32_t pipe_id, uint32_t 119 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t queue_id); uint32_t 126 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t cntl_val, uint32_t 127 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t addr_hi, uint32_t 128 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t addr_lo); uint32_t 130 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t gfx_index_val, uint32_t 131 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sq_cmd); uint32_t 132 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, uint32_t 141 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint64_t va, uint32_t vmid); uint32_t 142 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, uint32_t 146 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd); uint32_t 209 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, uint32_t 210 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t queue, uint32_t vmid) uint32_t 213 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); uint32_t 227 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t 228 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t queue_id) uint32_t 232 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; uint32_t 233 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); uint32_t 243 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, uint32_t 244 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sh_mem_config, uint32_t 245 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sh_mem_ape1_base, uint32_t 246 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sh_mem_ape1_limit, uint32_t 247 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sh_mem_bases) uint32_t 272 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | uint32_t 287 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) uint32_t 290 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t mec; uint32_t 291 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t pipe; uint32_t 306 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m) uint32_t 308 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t retval; uint32_t 328 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t 329 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t queue_id, uint32_t __user *wptr, uint32_t 330 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t wptr_shift, uint32_t wptr_mask, uint32_t 335 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t *mqd_hqd; uint32_t 336 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t reg, wptr_val, data; uint32_t 375 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t pipe_id, uint32_t queue_id, uint32_t 376 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t (**dump)[2], uint32_t *n_regs) uint32_t 379 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t i = 0, reg; uint32_t 388 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); uint32_t 411 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t __user *wptr, struct mm_struct *mm) uint32_t 416 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sdma_base_addr; uint32_t 417 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t data; uint32_t 475 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t engine_id, uint32_t queue_id, uint32_t 476 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t (**dump)[2], uint32_t *n_regs) uint32_t 479 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + uint32_t 481 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t i = 0, reg; uint32_t 485 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); uint32_t 502 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t pipe_id, uint32_t queue_id) uint32_t 505 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t act; uint32_t 507 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t low, high; uint32_t 527 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sdma_base_addr; uint32_t 528 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sdma_rlc_rb_cntl; uint32_t 543 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c unsigned int utimeout, uint32_t pipe_id, uint32_t 544 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t queue_id) uint32_t 547 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t temp; uint32_t 648 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sdma_base_addr; uint32_t 649 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t temp; uint32_t 700 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t cntl_val, uint32_t 701 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t addr_hi, uint32_t 702 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t addr_lo) uint32_t 730 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t gfx_index_val, uint32_t 731 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sq_cmd) uint32_t 734 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t data; uint32_t 754 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, uint32_t 764 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t reg; uint32_t 774 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t reg; uint32_t 782 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint64_t va, uint32_t vmid) uint32_t 791 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, uint32_t 850 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd) uint32_t 854 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); uint32_t 51 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, uint32_t 52 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sh_mem_config, uint32_t 53 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, uint32_t 54 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sh_mem_bases); uint32_t 57 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); uint32_t 58 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t 59 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t queue_id, uint32_t __user *wptr, uint32_t 60 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t wptr_shift, uint32_t wptr_mask, uint32_t 63 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t pipe_id, uint32_t queue_id, uint32_t 64 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t (**dump)[2], uint32_t *n_regs); uint32_t 66 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t __user *wptr, struct mm_struct *mm); uint32_t 68 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t engine_id, uint32_t queue_id, uint32_t 69 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t (**dump)[2], uint32_t *n_regs); uint32_t 71 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t pipe_id, uint32_t queue_id); uint32_t 75 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c unsigned int utimeout, uint32_t pipe_id, uint32_t 76 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t queue_id); uint32_t 82 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t cntl_val, uint32_t 83 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t addr_hi, uint32_t 84 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t addr_lo); uint32_t 86 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t gfx_index_val, uint32_t 87 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sq_cmd); uint32_t 88 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, uint32_t 97 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint64_t va, uint32_t vmid); uint32_t 98 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, uint32_t 165 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, uint32_t 166 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t queue, uint32_t vmid) uint32_t 169 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); uint32_t 183 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t 184 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t queue_id) uint32_t 188 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; uint32_t 189 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); uint32_t 199 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, uint32_t 200 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sh_mem_config, uint32_t 201 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sh_mem_ape1_base, uint32_t 202 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sh_mem_ape1_limit, uint32_t 203 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sh_mem_bases) uint32_t 229 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | uint32_t 244 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) uint32_t 247 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t mec; uint32_t 248 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t pipe; uint32_t 263 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m) uint32_t 265 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t retval; uint32_t 284 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t 285 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t queue_id, uint32_t __user *wptr, uint32_t 286 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t wptr_shift, uint32_t wptr_mask, uint32_t 291 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t *mqd_hqd; uint32_t 292 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t reg, wptr_val, data; uint32_t 301 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t value, mec, pipe; uint32_t 360 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t pipe_id, uint32_t queue_id, uint32_t 361 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t (**dump)[2], uint32_t *n_regs) uint32_t 364 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t i = 0, reg; uint32_t 373 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); uint32_t 396 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t __user *wptr, struct mm_struct *mm) uint32_t 401 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sdma_base_addr; uint32_t 402 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t data; uint32_t 459 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t engine_id, uint32_t queue_id, uint32_t 460 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t (**dump)[2], uint32_t *n_regs) uint32_t 463 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + uint32_t 465 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t i = 0, reg; uint32_t 469 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); uint32_t 495 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t pipe_id, uint32_t queue_id) uint32_t 498 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t act; uint32_t 500 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t low, high; uint32_t 520 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sdma_base_addr; uint32_t 521 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sdma_rlc_rb_cntl; uint32_t 536 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c unsigned int utimeout, uint32_t pipe_id, uint32_t 537 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t queue_id) uint32_t 540 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t temp; uint32_t 644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sdma_base_addr; uint32_t 645 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t temp; uint32_t 677 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t reg; uint32_t 687 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t reg; uint32_t 701 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t cntl_val, uint32_t 702 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t addr_hi, uint32_t 703 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t addr_lo) uint32_t 709 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t gfx_index_val, uint32_t 710 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sq_cmd) uint32_t 713 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t data = 0; uint32_t 733 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, uint32_t 741 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint64_t va, uint32_t vmid) uint32_t 750 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, uint32_t 89 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, uint32_t 90 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t queue, uint32_t vmid) uint32_t 106 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t 107 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t queue_id) uint32_t 111 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; uint32_t 112 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); uint32_t 117 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c static uint32_t get_queue_mask(struct amdgpu_device *adev, uint32_t 118 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t pipe_id, uint32_t queue_id) uint32_t 123 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c return ((uint32_t)1) << bit; uint32_t 131 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, uint32_t 132 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sh_mem_config, uint32_t 133 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sh_mem_ape1_base, uint32_t 134 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sh_mem_ape1_limit, uint32_t 135 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sh_mem_bases) uint32_t 160 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | uint32_t 209 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) uint32_t 212 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t mec; uint32_t 213 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t pipe; uint32_t 229 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, uint32_t 233 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t base[2] = { uint32_t 239 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t retval; uint32_t 259 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t 260 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t queue_id, uint32_t __user *wptr, uint32_t 261 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t wptr_shift, uint32_t wptr_mask, uint32_t 266 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t *mqd_hqd; uint32_t 267 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t reg, hqd_base, data; uint32_t 275 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t value, mec, pipe; uint32_t 319 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t queue_size = uint32_t 355 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t pipe_id, uint32_t queue_id, uint32_t 356 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t (**dump)[2], uint32_t *n_regs) uint32_t 359 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t i = 0, reg; uint32_t 368 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); uint32_t 387 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t __user *wptr, struct mm_struct *mm) uint32_t 391 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sdma_base_addr, sdmax_gfx_context_cntl; uint32_t 393 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t data; uint32_t 461 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t engine_id, uint32_t queue_id, uint32_t 462 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t (**dump)[2], uint32_t *n_regs) uint32_t 465 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); uint32_t 466 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t i = 0, reg; uint32_t 470 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); uint32_t 492 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t pipe_id, uint32_t queue_id) uint32_t 495 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t act; uint32_t 497 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t low, high; uint32_t 517 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sdma_base_addr; uint32_t 518 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sdma_rlc_rb_cntl; uint32_t 534 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c unsigned int utimeout, uint32_t pipe_id, uint32_t 535 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t queue_id) uint32_t 540 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t temp; uint32_t 587 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sdma_base_addr; uint32_t 588 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t temp; uint32_t 623 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t reg; uint32_t 634 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t reg; uint32_t 643 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t flush_type) uint32_t 646 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t seq; uint32_t 675 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t flush_type = 0; uint32_t 741 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t cntl_val, uint32_t 742 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t addr_hi, uint32_t 743 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t addr_lo) uint32_t 749 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t gfx_index_val, uint32_t 750 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t sq_cmd) uint32_t 753 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t data = 0; uint32_t 773 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd, uint32_t 781 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint64_t va, uint32_t vmid) uint32_t 789 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, uint32_t 25 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, uint32_t 26 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t sh_mem_config, uint32_t 27 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, uint32_t 28 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t sh_mem_bases); uint32_t 31 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); uint32_t 32 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t 33 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t queue_id, uint32_t __user *wptr, uint32_t 34 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t wptr_shift, uint32_t wptr_mask, uint32_t 37 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t pipe_id, uint32_t queue_id, uint32_t 38 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t (**dump)[2], uint32_t *n_regs); uint32_t 40 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t pipe_id, uint32_t queue_id); uint32_t 43 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h unsigned int utimeout, uint32_t pipe_id, uint32_t 44 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t queue_id); uint32_t 48 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t cntl_val, uint32_t 49 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t addr_hi, uint32_t 50 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t addr_lo); uint32_t 52 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t gfx_index_val, uint32_t 53 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t sq_cmd); uint32_t 54 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd, uint32_t 62 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, uint32_t 65 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint64_t va, uint32_t vmid); uint32_t 60 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c uint32_t domain; uint32_t 274 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain, uint32_t 771 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size) uint32_t 1073 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c uint64_t *offset, uint32_t flags) uint32_t 1085 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c uint32_t mapping_flags; uint32_t 1305 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c uint32_t domain; uint32_t 2024 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c uint32_t domain = mem->domain; uint32_t 1021 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1041 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1059 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1070 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1111 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1153 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1207 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1216 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1252 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1379 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1673 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c uint32_t bios_6_scratch; uint32_t 1690 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c uint32_t bios_2_scratch, bios_6_scratch; uint32_t 1785 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == uint32_t 1786 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << uint32_t 1827 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) uint32_t 1841 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) uint32_t 1855 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) uint32_t 1869 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) uint32_t 1883 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) uint32_t 1899 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) uint32_t 1902 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c uint32_t r; uint32_t 1917 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) uint32_t 1933 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) uint32_t 1936 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c uint32_t r; uint32_t 73 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c uint32_t start_addr, size; uint32_t 87 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == uint32_t 88 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << uint32_t 227 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry); uint32_t 271 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c uint32_t handle = args->in.list_handle; uint32_t 37 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h uint32_t priority; uint32_t 44 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset) uint32_t 51 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c uint32_t value) uint32_t 57 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device, uint32_t 87 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c unsigned index, uint32_t value) uint32_t 112 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) uint32_t 210 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c uint32_t data_size; uint32_t 243 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c uint32_t ucode_size; uint32_t 244 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c uint32_t ucode_start_address; uint32_t 1494 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c uint32_t connector_id, uint32_t 1495 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c uint32_t supported_device, uint32_t 1509 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c uint32_t subpixel_order = SubPixelNone; uint32_t 34 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h uint32_t connector_id, uint32_t 35 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h uint32_t supported_device, uint32_t 41 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t *offset) uint32_t 112 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t uf_offset = 0; uint32_t 156 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t __user *cdata; uint32_t 171 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); uint32_t 177 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c size *= sizeof(uint32_t); uint32_t 190 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { uint32_t 204 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { uint32_t 408 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t domain; uint32_t 456 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t domain = validated->allowed_domains; uint32_t 470 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t other; uint32_t 845 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ib->ptr = (uint32_t *)kptr; uint32_t 1069 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t handle, u64 point, uint32_t 1562 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t fence_count = wait->in.fence_count; uint32_t 1608 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t fence_count = wait->in.fence_count; uint32_t 1609 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t first = ~0; uint32_t 1671 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c uint32_t fence_count = wait->in.fence_count; uint32_t 38 drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c u32 domain, uint32_t size) uint32_t 67 drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c uint64_t csa_addr, uint32_t size) uint32_t 30 drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev); uint32_t 33 drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h u32 domain, uint32_t size); uint32_t 36 drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h uint64_t csa_addr, uint32_t size); uint32_t 255 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c uint32_t *id) uint32_t 273 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c *id = (uint32_t)r; uint32_t 299 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) uint32_t 313 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c struct amdgpu_fpriv *fpriv, uint32_t id, uint32_t 349 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c struct amdgpu_fpriv *fpriv, uint32_t id, uint32_t 402 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c uint32_t id; uint32_t 439 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) uint32_t 575 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c uint32_t id, i; uint32_t 597 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c uint32_t id, i; uint32_t 619 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c uint32_t id; uint32_t 43 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h uint32_t vram_lost_counter; uint32_t 65 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); uint32_t 163 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 167 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = put_user(value, (uint32_t *)buf); uint32_t 169 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = get_user(value, (uint32_t *)buf); uint32_t 241 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 244 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = put_user(value, (uint32_t *)buf); uint32_t 280 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 282 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = get_user(value, (uint32_t *)buf); uint32_t 320 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 323 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = put_user(value, (uint32_t *)buf); uint32_t 359 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 361 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = get_user(value, (uint32_t *)buf); uint32_t 399 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 402 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = put_user(value, (uint32_t *)buf); uint32_t 438 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 440 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = get_user(value, (uint32_t *)buf); uint32_t 475 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t *config, no_regs = 0; uint32_t 526 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 529 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = put_user(value, (uint32_t *)buf); uint32_t 563 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t values[16]; uint32_t 623 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t offset, se, sh, cu, wave, simd, data[32]; uint32_t 651 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 654 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = put_user(value, (uint32_t *)buf); uint32_t 695 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; uint32_t 730 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t value; uint32_t 733 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c r = put_user(value, (uint32_t *)buf); uint32_t 936 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t sync_seq, last_seq; uint32_t 994 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t preempt_seq; uint32_t 166 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t 167 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t acc_flags) uint32_t 169 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t ret; uint32_t 202 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { uint32_t 223 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { uint32_t 240 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t 241 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t acc_flags) uint32_t 399 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) uint32_t 416 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) uint32_t 433 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) uint32_t 450 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) uint32_t 468 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, uint32_t 469 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t block, uint32_t reg) uint32_t 489 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t block, uint32_t 490 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t reg, uint32_t v) uint32_t 687 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, uint32_t 700 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); uint32_t 827 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t reg; uint32_t 840 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t fw_ver; uint32_t 846 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c fw_ver = *((uint32_t *)adev->pm.fw->data + 69); uint32_t 1720 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t smu_version; uint32_t 2575 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t flags) uint32_t 2683 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); uint32_t 137 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c uint32_t *p = (uint32_t *)binary; uint32_t 144 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); uint32_t 154 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) uint32_t 165 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, uint32_t 151 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c uint32_t page_flip_flags, uint32_t target, uint32_t 221 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + uint32_t 373 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c uint32_t devices; uint32_t 499 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, uint32_t 502 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; uint32_t 41 drivers/gpu/drm/amd/amdgpu/amdgpu_display.h uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, uint32_t 42 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t kiq; uint32_t 43 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t mec_ring0; uint32_t 44 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t mec_ring1; uint32_t 45 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t mec_ring2; uint32_t 46 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t mec_ring3; uint32_t 47 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t mec_ring4; uint32_t 48 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t mec_ring5; uint32_t 49 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t mec_ring6; uint32_t 50 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t mec_ring7; uint32_t 51 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t userqueue_start; uint32_t 52 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t userqueue_end; uint32_t 53 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t gfx_ring0; uint32_t 54 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t gfx_ring1; uint32_t 55 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t sdma_engine[8]; uint32_t 56 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t ih; uint32_t 59 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t vcn_ring0_1; uint32_t 60 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t vcn_ring2_3; uint32_t 61 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t vcn_ring4_5; uint32_t 62 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t vcn_ring6_7; uint32_t 65 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t uvd_ring0_1; uint32_t 66 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t uvd_ring2_3; uint32_t 67 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t uvd_ring4_5; uint32_t 68 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t uvd_ring6_7; uint32_t 69 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t vce_ring0_1; uint32_t 70 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t vce_ring2_3; uint32_t 71 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t vce_ring4_5; uint32_t 72 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t vce_ring6_7; uint32_t 75 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t first_non_cp; uint32_t 76 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t last_non_cp; uint32_t 77 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t max_assignment; uint32_t 79 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h uint32_t sdma_doorbell_range; uint32_t 909 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c uint32_t clk_freq; uint32_t 926 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c uint32_t clk_freq; uint32_t 941 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) uint32_t 451 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h uint32_t fw_version; uint32_t 452 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h uint32_t pcie_gen_mask; uint32_t 453 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h uint32_t pcie_mlw_mask; uint32_t 455 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h uint32_t smu_prv_buffer_size; uint32_t 459 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h uint32_t pp_feature; uint32_t 500 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h void *data, uint32_t *size); uint32_t 520 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h uint32_t block_type, bool gate); uint32_t 142 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c uint32_t seq; uint32_t 194 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s) uint32_t 196 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c uint32_t seq; uint32_t 237 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c uint32_t seq, last_seq; uint32_t 341 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c uint32_t wait_seq, uint32_t 344 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c uint32_t seq; uint32_t 31 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h uint32_t gds_size; uint32_t 32 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h uint32_t gws_size; uint32_t 33 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h uint32_t oa_size; uint32_t 34 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h uint32_t gds_compute_max_wave_id; uint32_t 38 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h uint32_t mem_base; uint32_t 39 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h uint32_t mem_size; uint32_t 40 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h uint32_t gws; uint32_t 41 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h uint32_t oa; uint32_t 220 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c uint32_t handle; uint32_t 291 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c uint32_t handle; uint32_t 365 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c uint32_t handle, uint64_t *offset_p) uint32_t 389 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c uint32_t handle = args->in.handle; uint32_t 428 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c uint32_t handle = args->in.handle; uint32_t 512 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c uint32_t operation) uint32_t 540 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | uint32_t 543 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | uint32_t 751 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c uint32_t handle; uint32_t 58 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h uint32_t handle, uint64_t *offset_p); uint32_t 107 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg) uint32_t 129 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg) uint32_t 100 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t reg_base; uint32_t 101 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t free_mask; uint32_t 111 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t rb_backend_disable; uint32_t 112 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t user_rb_backend_disable; uint32_t 113 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t raster_config; uint32_t 114 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t raster_config_1; uint32_t 154 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t tile_mode_array[32]; uint32_t 155 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t macrotile_mode_array[16]; uint32_t 161 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t double_offchip_lds_buf; uint32_t 163 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t db_debug2; uint32_t 165 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t num_sc_per_sh; uint32_t 166 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t num_packer_per_sc; uint32_t 167 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t pa_sc_tile_steering_override; uint32_t 172 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t simd_per_cu; uint32_t 173 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t max_waves_per_simd; uint32_t 174 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t wave_front_size; uint32_t 175 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t max_scratch_slots_per_cu; uint32_t 176 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t lds_size; uint32_t 179 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t number; uint32_t 180 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t ao_cu_mask; uint32_t 181 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t ao_cu_bitmap[4][4]; uint32_t 182 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t bitmap[4][4]; uint32_t 190 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t 191 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t wave, uint32_t *dst, int *no_fields); uint32_t 192 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t 193 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t wave, uint32_t thread, uint32_t start, uint32_t 194 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t size, uint32_t *dst); uint32_t 195 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t 196 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t wave, uint32_t start, uint32_t size, uint32_t 197 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t *dst); uint32_t 207 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t size; uint32_t 208 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t bo_size; uint32_t 221 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t gds_reserve_addr; uint32_t 222 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t gds_reserve_size; uint32_t 234 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t *pfp_fw_ptr; uint32_t 240 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t *ce_fw_ptr; uint32_t 246 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t *me_fw_ptr; uint32_t 247 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t num_me; uint32_t 248 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t num_pipe_per_me; uint32_t 249 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t num_queue_per_pipe; uint32_t 267 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t me_fw_version; uint32_t 269 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t pfp_fw_version; uint32_t 271 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t ce_fw_version; uint32_t 273 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t rlc_fw_version; uint32_t 275 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t mec_fw_version; uint32_t 277 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t mec2_fw_version; uint32_t 278 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t me_feature_version; uint32_t 279 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t ce_feature_version; uint32_t 280 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t pfp_feature_version; uint32_t 281 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t rlc_feature_version; uint32_t 282 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t rlc_srlc_fw_version; uint32_t 283 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t rlc_srlc_feature_version; uint32_t 284 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t rlc_srlg_fw_version; uint32_t 285 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t rlc_srlg_feature_version; uint32_t 286 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t rlc_srls_fw_version; uint32_t 287 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t rlc_srls_feature_version; uint32_t 288 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t mec_feature_version; uint32_t 289 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t mec2_feature_version; uint32_t 305 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t gfx_current_status; uint32_t 312 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t grbm_soft_reset; uint32_t 313 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t srbm_soft_reset; uint32_t 321 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ uint32_t 349 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); uint32_t 350 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); uint32_t 96 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c uint32_t gpu_page_idx, uint64_t addr, uint32_t 273 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c uint32_t hash; uint32_t 78 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t ctx0_ptb_addr_lo32; uint32_t 79 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t ctx0_ptb_addr_hi32; uint32_t 80 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t vm_inv_eng0_sem; uint32_t 81 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t vm_inv_eng0_req; uint32_t 82 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t vm_inv_eng0_ack; uint32_t 83 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t vm_context0_cntl; uint32_t 84 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t vm_l2_pro_fault_status; uint32_t 85 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t vm_l2_pro_fault_cntl; uint32_t 93 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, uint32_t 94 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t vmhub, uint32_t flush_type); uint32_t 105 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t flags); uint32_t 154 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t fw_version; uint32_t 156 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t vram_type; uint32_t 157 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t srbm_soft_reset; uint32_t 160 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t sdpif_register; uint32_t 223 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h uint32_t gpu_page_idx, uint64_t addr, uint32_t 45 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t temp; uint32_t 87 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t temp; uint32_t 106 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t val; uint32_t 121 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t val; uint32_t 135 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t val; uint32_t 148 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c uint32_t val; uint32_t 133 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c uint32_t status = 0, alloc_size; uint32_t 52 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h uint32_t current_gpu_reset_count; uint32_t 54 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h uint32_t gds_base; uint32_t 55 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h uint32_t gds_size; uint32_t 56 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h uint32_t gws_base; uint32_t 57 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h uint32_t gws_size; uint32_t 58 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h uint32_t oa_base; uint32_t 59 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h uint32_t oa_size; uint32_t 38 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h uint32_t ptr_mask; uint32_t 44 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h volatile uint32_t *ring; uint32_t 48 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h volatile uint32_t *wptr_cpu; uint32_t 51 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h volatile uint32_t *rptr_cpu; uint32_t 386 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; uint32_t 57 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h const uint32_t *iv_entry; uint32_t 99 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h uint32_t srbm_soft_reset; uint32_t 49 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h uint32_t preamble_status; uint32_t 50 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h uint32_t preemption_status; uint32_t 51 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h uint32_t num_ibs; uint32_t 57 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h uint32_t gds_base, gds_size; uint32_t 58 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h uint32_t gws_base, gws_size; uint32_t 59 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h uint32_t oa_base, oa_size; uint32_t 60 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h uint32_t vram_lost_counter; uint32_t 306 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c uint32_t ib_start_alignment = 0; uint32_t 307 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c uint32_t ib_size_alignment = 0; uint32_t 455 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c uint32_t size = info->return_size; uint32_t 457 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c uint32_t ui32 = 0; uint32_t 497 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c uint32_t count = 0; uint32_t 629 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c uint32_t *regs; uint32_t 782 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c uint32_t bios_size = adev->bios_size; uint32_t 791 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c uint32_t bios_offset = info->vbios_info.offset; uint32_t 37 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t *ucode_fw_ptr; uint32_t 38 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t ucode_fw_version; uint32_t 44 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t *data_fw_ptr; uint32_t 45 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t data_fw_version; uint32_t 53 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t process_id; uint32_t 61 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t inprocess_gang_priority; uint32_t 62 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t gang_global_priority_level; uint32_t 63 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t doorbell_offset; uint32_t 66 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t queue_type; uint32_t 67 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t paging; uint32_t 71 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t doorbell_offset; uint32_t 79 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h uint32_t suspend_fence_value; uint32_t 153 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t mask_clk_reg; uint32_t 154 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t mask_data_reg; uint32_t 155 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t a_clk_reg; uint32_t 156 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t a_data_reg; uint32_t 157 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t en_clk_reg; uint32_t 158 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t en_data_reg; uint32_t 159 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t y_clk_reg; uint32_t 160 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t y_data_reg; uint32_t 161 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t mask_clk_mask; uint32_t 162 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t mask_data_mask; uint32_t 163 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t a_clk_mask; uint32_t 164 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t a_data_mask; uint32_t 165 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t en_clk_mask; uint32_t 166 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t en_data_mask; uint32_t 167 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t y_clk_mask; uint32_t 168 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t y_data_mask; uint32_t 192 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t reference_freq; uint32_t 195 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t reference_div; uint32_t 196 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t post_div; uint32_t 199 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t pll_in_min; uint32_t 200 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t pll_in_max; uint32_t 201 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t pll_out_min; uint32_t 202 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t pll_out_max; uint32_t 203 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t lcd_pll_out_min; uint32_t 204 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t lcd_pll_out_max; uint32_t 205 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t best_vco; uint32_t 208 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t min_ref_div; uint32_t 209 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t max_ref_div; uint32_t 210 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t min_post_div; uint32_t 211 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t max_post_div; uint32_t 212 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t min_feedback_div; uint32_t 213 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t max_feedback_div; uint32_t 214 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t min_frac_feedback_div; uint32_t 215 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t max_frac_feedback_div; uint32_t 218 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t flags; uint32_t 221 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t id; uint32_t 286 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t encoder_enum, uint32_t 287 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t supported_device, uint32_t 290 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t connector_id, uint32_t 291 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t supported_device, uint32_t 385 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t crtc_offset; uint32_t 438 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t lcd_misc; uint32_t 440 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t lcd_ss_id; uint32_t 452 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t encoder_enum; uint32_t 453 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t encoder_id; uint32_t 454 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t devices; uint32_t 455 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t active_device; uint32_t 456 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t flags; uint32_t 457 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t pixel_clock; uint32_t 460 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t underscan_hborder; uint32_t 461 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t underscan_vborder; uint32_t 534 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t connector_id; uint32_t 535 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t devices; uint32_t 632 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t page_flip_flags, uint32_t target, uint32_t 361 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c uint64_t offset, uint64_t size, uint32_t domain, uint32_t 708 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c uint32_t domain; uint32_t 909 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c uint32_t mem_type = bo->tbo.mem.mem_type; uint32_t 1179 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c uint32_t metadata_size, uint64_t flags) uint32_t 1223 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c size_t buffer_size, uint32_t *metadata_size, uint32_t 1453 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, uint32_t 1454 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c uint32_t domain) uint32_t 241 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h uint64_t offset, uint64_t size, uint32_t domain, uint32_t 263 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h uint32_t metadata_size, uint64_t flags); uint32_t 265 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h size_t buffer_size, uint32_t *metadata_size, uint32_t 279 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, uint32_t 280 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h uint32_t domain); uint32_t 101 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c void *data, uint32_t *size) uint32_t 650 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t parameter_size = 0; uint32_t 656 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t type; uint32_t 728 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t size = 0; uint32_t 858 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) uint32_t 896 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; uint32_t 943 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; uint32_t 986 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; uint32_t 1026 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; uint32_t 1066 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; uint32_t 1106 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; uint32_t 1129 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t value = 0; uint32_t 1157 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value); uint32_t 1160 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); uint32_t 1180 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t value = 0; uint32_t 1208 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value); uint32_t 1211 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); uint32_t 1269 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t parameter_size = 0; uint32_t 1273 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t i = 0; uint32_t 2011 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t limit = 0; uint32_t 2029 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t limit = 0; uint32_t 2078 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t sclk; uint32_t 2108 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mclk; uint32_t 2755 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) uint32_t 3047 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t value; uint32_t 3049 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t query = 0; uint32_t 3067 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c size = sizeof(uint32_t); uint32_t 39 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version); uint32_t 109 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t 110 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t reg_val, uint32_t mask, bool check_changed) uint32_t 112 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t val; uint32_t 193 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint64_t tmr_mc, uint32_t size) uint32_t 205 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint64_t pri_buf_mc, uint32_t size) uint32_t 215 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t *tmr_size) uint32_t 304 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t size, uint32_t shared_size) uint32_t 364 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t id, uint32_t value) uint32_t 372 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t value) uint32_t 393 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t xgmi_ta_size, uint32_t shared_size) uint32_t 458 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t xgmi_session_id) uint32_t 490 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t ta_cmd_id, uint32_t 491 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t xgmi_session_id) uint32_t 499 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) uint32_t 578 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t ras_ta_size, uint32_t shared_size) uint32_t 643 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t ras_session_id) uint32_t 675 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t ta_cmd_id, uint32_t 676 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t ras_session_id) uint32_t 684 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) uint32_t 68 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t ring_size; uint32_t 122 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t num_nodes; uint32_t 128 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t session_id; uint32_t 138 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t session_id; uint32_t 160 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t sos_fw_version; uint32_t 161 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t sos_feature_version; uint32_t 162 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t sys_bin_size; uint32_t 163 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t sos_bin_size; uint32_t 164 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t toc_bin_size; uint32_t 165 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t kdb_bin_size; uint32_t 177 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t asd_fw_version; uint32_t 178 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t asd_feature_version; uint32_t 179 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t asd_ucode_size; uint32_t 202 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t ta_fw_version; uint32_t 203 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t ta_xgmi_ucode_version; uint32_t 204 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t ta_xgmi_ucode_size; uint32_t 206 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t ta_ras_ucode_version; uint32_t 207 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t ta_ras_ucode_size; uint32_t 267 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t 268 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t field_val, uint32_t mask, bool check_changed); uint32_t 277 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); uint32_t 279 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); uint32_t 287 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t value); uint32_t 128 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c uint32_t sub_block; uint32_t 1409 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c uint32_t *hw_supported, uint32_t *supported) uint32_t 305 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h uint32_t sub_block_index; uint32_t 313 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h uint32_t hw_supported; uint32_t 315 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h uint32_t supported; uint32_t 316 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h uint32_t features; uint32_t 336 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h uint32_t flags; uint32_t 60 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c uint32_t *pp = (uint32_t *) buff; uint32_t 72 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c uint32_t *pp = (uint32_t *)buff; uint32_t 103 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control); uint32_t 241 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c static uint32_t __correct_eeprom_dest_address(uint32_t curr_address) uint32_t 243 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE; uint32_t 270 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control) uint32_t 273 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c uint32_t tbl_sum = 0; uint32_t 282 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c static uint32_t __calc_recs_byte_sum(struct eeprom_table_record *records, uint32_t 286 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c uint32_t tbl_sum = 0; uint32_t 300 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c static inline uint32_t __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control, uint32_t 309 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c uint32_t old_hdr_byte_sum) uint32_t 426 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control); uint32_t 38 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h uint32_t header; uint32_t 39 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h uint32_t version; uint32_t 40 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h uint32_t first_rec_offset; uint32_t 41 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h uint32_t tbl_size; uint32_t 42 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h uint32_t checksum; uint32_t 48 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h uint32_t next_addr; uint32_t 52 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h uint32_t tbl_byte_sum; uint32_t 93 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 126 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c uint32_t count; uint32_t 392 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c uint32_t reg0, uint32_t reg1, uint32_t 393 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c uint32_t ref, uint32_t mask) uint32_t 441 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c uint32_t value, result, early[3]; uint32_t 453 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c r = put_user(early[i], (uint32_t *)buf); uint32_t 468 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c r = put_user(value, (uint32_t*)buf); uint32_t 73 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h volatile uint32_t *cpu_addr; uint32_t 75 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t sync_seq; uint32_t 99 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s); uint32_t 103 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t wait_seq, uint32_t 114 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t align_mask; uint32_t 126 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); uint32_t 127 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx); uint32_t 135 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t flags); uint32_t 142 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, uint32_t 143 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t gds_base, uint32_t gds_size, uint32_t 144 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t gws_base, uint32_t gws_size, uint32_t 145 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t oa_base, uint32_t oa_size); uint32_t 150 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); uint32_t 161 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); uint32_t 162 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); uint32_t 163 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); uint32_t 164 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, uint32_t 165 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t val, uint32_t mask); uint32_t 167 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t reg0, uint32_t reg1, uint32_t 168 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t ref, uint32_t mask); uint32_t 185 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h volatile uint32_t *ring; uint32_t 194 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t buf_mask; uint32_t 257 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); uint32_t 270 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t reg0, uint32_t val0, uint32_t 271 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t reg1, uint32_t val1); uint32_t 289 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) uint32_t 135 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h volatile uint32_t *sr_ptr; uint32_t 141 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h volatile uint32_t *cs_ptr; uint32_t 147 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h volatile uint32_t *cp_table_ptr; uint32_t 261 drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c uint32_t idx = best_bo->fence->context; uint32_t 358 drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c uint32_t idx; uint32_t 62 drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c uint32_t id; uint32_t 48 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index) uint32_t 69 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c uint32_t index = 0; uint32_t 45 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h uint32_t fw_version; uint32_t 46 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h uint32_t feature_version; uint32_t 59 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h uint32_t srbm_soft_reset; uint32_t 70 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h uint32_t copy_max_bytes; uint32_t 82 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h uint32_t byte_count); uint32_t 85 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h uint32_t fill_max_bytes; uint32_t 93 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h uint32_t src_data, uint32_t 97 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h uint32_t byte_count); uint32_t 105 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index); uint32_t 27 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t state; uint32_t 28 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dscclk_mhz; uint32_t 29 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dcfclk_mhz; uint32_t 30 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t socclk_mhz; uint32_t 31 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dram_speed_mts; uint32_t 32 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t fabricclk_mhz; uint32_t 33 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dispclk_mhz; uint32_t 34 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t phyclk_mhz; uint32_t 35 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dppclk_mhz; uint32_t 39 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t sr_exit_time_us; uint32_t 40 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t sr_enter_plus_exit_time_us; uint32_t 41 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t urgent_latency_us; uint32_t 42 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t urgent_latency_pixel_data_only_us; uint32_t 43 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t urgent_latency_pixel_mixed_with_vm_data_us; uint32_t 44 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t urgent_latency_vm_data_only_us; uint32_t 45 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t writeback_latency_us; uint32_t 46 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t ideal_dram_bw_after_urgent_percent; uint32_t 47 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly uint32_t 48 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; uint32_t 49 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only; uint32_t 50 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t max_avg_sdp_bw_use_normal_percent; uint32_t 51 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t max_avg_dram_bw_use_normal_percent; uint32_t 52 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t max_request_size_bytes; uint32_t 53 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t downspread_percent; uint32_t 54 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dram_page_open_time_ns; uint32_t 55 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dram_rw_turnaround_time_ns; uint32_t 56 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dram_return_buffer_per_channel_bytes; uint32_t 57 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dram_channel_width_bytes; uint32_t 58 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t fabric_datapath_to_dcn_data_return_bytes; uint32_t 59 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dcn_downspread_percent; uint32_t 60 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dispclk_dppclk_vco_speed_mhz; uint32_t 61 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dfs_vco_period_ps; uint32_t 62 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t urgent_out_of_order_return_per_channel_pixel_only_bytes; uint32_t 63 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; uint32_t 64 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t urgent_out_of_order_return_per_channel_vm_only_bytes; uint32_t 65 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t round_trip_ping_latency_dcfclk_cycles; uint32_t 66 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t urgent_out_of_order_return_per_channel_bytes; uint32_t 67 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t channel_interleave_bytes; uint32_t 68 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t num_banks; uint32_t 69 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t num_chans; uint32_t 70 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t vmm_page_size_bytes; uint32_t 71 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t dram_clock_change_latency_us; uint32_t 72 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t writeback_dram_clock_change_latency_us; uint32_t 73 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t return_bus_width_bytes; uint32_t 74 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t voltage_override; uint32_t 75 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t xfc_bus_transport_time_us; uint32_t 76 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t xfc_xbuf_latency_tolerance_us; uint32_t 77 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t use_urgent_burst_bw; uint32_t 78 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t num_states; uint32_t 39 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h TP_PROTO(unsigned did, uint32_t reg, uint32_t value), uint32_t 43 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __field(uint32_t, reg) uint32_t 44 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __field(uint32_t, value) uint32_t 58 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h TP_PROTO(unsigned did, uint32_t reg, uint32_t value), uint32_t 62 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __field(uint32_t, reg) uint32_t 63 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __field(uint32_t, value) uint32_t 326 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h uint32_t incr, uint64_t flags), uint32_t 447 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h TP_PROTO(struct amdgpu_bo* bo, uint32_t new_placement, uint32_t old_placement), uint32_t 69 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) uint32_t 85 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, uint32_t 770 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t userflags; uint32_t 1223 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t page_flags) uint32_t 1334 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t flags) uint32_t 1546 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t value = 0; uint32_t 1559 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t bytes = 4 - (pos & 3); uint32_t 1560 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t shift = (pos & 3) * 8; uint32_t 1561 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t mask = 0xffffffff << shift; uint32_t 1569 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); uint32_t 1575 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c value |= (*(uint32_t *)buf << shift) & mask; uint32_t 1964 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint64_t dst_offset, uint32_t byte_count, uint32_t 1972 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t max_bytes; uint32_t 2009 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t cur_size_in_bytes = min(byte_count, max_bytes); uint32_t 2038 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t src_data, uint32_t 2043 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; uint32_t 2101 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count, uint32_t 2176 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t value; uint32_t 2182 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); uint32_t 2187 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c r = put_user(value, (uint32_t *)buf); uint32_t 2220 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t value; uint32_t 2225 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c r = get_user(value, (uint32_t *)buf); uint32_t 2230 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); uint32_t 87 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h uint64_t dst_offset, uint32_t byte_count, uint32_t 98 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h uint32_t src_data, uint32_t 123 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h uint32_t flags); uint32_t 29 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ uint32_t 30 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t header_size_bytes; /* size of just the header in bytes */ uint32_t 35 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_version; uint32_t 36 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_size_bytes; /* size of ucode in bytes */ uint32_t 37 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ uint32_t 38 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t crc32; /* crc32 checksum of the payload */ uint32_t 44 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t io_debug_size_bytes; /* size of debug array in dwords */ uint32_t 45 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ uint32_t 51 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_start_addr; uint32_t 57 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ppt_offset_bytes; /* soft pptable offset */ uint32_t 58 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ppt_size_bytes; /* soft pptable size */ uint32_t 62 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t id; uint32_t 63 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ppt_offset_bytes; uint32_t 64 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ppt_size_bytes; uint32_t 70 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t pptable_count; uint32_t 71 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t pptable_entry_offset; uint32_t 77 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_feature_version; uint32_t 78 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t sos_offset_bytes; uint32_t 79 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t sos_size_bytes; uint32_t 85 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t toc_header_version; uint32_t 86 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t toc_offset_bytes; uint32_t 87 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t toc_size_bytes; uint32_t 88 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t kdb_header_version; uint32_t 89 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t kdb_offset_bytes; uint32_t 90 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t kdb_size_bytes; uint32_t 96 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reserve[3]; uint32_t 97 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t kdb_header_version; uint32_t 98 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t kdb_offset_bytes; uint32_t 99 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t kdb_size_bytes; uint32_t 105 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ta_xgmi_ucode_version; uint32_t 106 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ta_xgmi_offset_bytes; uint32_t 107 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ta_xgmi_size_bytes; uint32_t 108 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ta_ras_ucode_version; uint32_t 109 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ta_ras_offset_bytes; uint32_t 110 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ta_ras_size_bytes; uint32_t 116 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_feature_version; uint32_t 117 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t jt_offset; /* jt location */ uint32_t 118 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t jt_size; /* size of jt */ uint32_t 124 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_ucode_version; uint32_t 125 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_ucode_size_bytes; uint32_t 126 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_ucode_offset_bytes; uint32_t 127 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_ucode_data_version; uint32_t 128 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_ucode_data_size_bytes; uint32_t 129 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_ucode_data_offset_bytes; uint32_t 130 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_uc_start_addr_lo; uint32_t 131 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_uc_start_addr_hi; uint32_t 132 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_data_start_addr_lo; uint32_t 133 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t mes_data_start_addr_hi; uint32_t 139 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_feature_version; uint32_t 140 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_and_restore_offset; uint32_t 141 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t clear_state_descriptor_offset; uint32_t 142 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t avail_scratch_ram_locations; uint32_t 143 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t master_pkt_description_offset; uint32_t 149 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_feature_version; uint32_t 150 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t jt_offset; /* jt location */ uint32_t 151 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t jt_size; /* size of jt */ uint32_t 152 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_and_restore_offset; uint32_t 153 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t clear_state_descriptor_offset; uint32_t 154 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t avail_scratch_ram_locations; uint32_t 155 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_restore_list_size; uint32_t 156 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_format_start; uint32_t 157 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_format_separate_start; uint32_t 158 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t starting_offsets_start; uint32_t 159 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ uint32_t 160 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ uint32_t 161 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ uint32_t 162 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ uint32_t 163 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ uint32_t 164 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ uint32_t 165 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ uint32_t 166 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ uint32_t 172 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ uint32_t 173 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_cntl_ucode_ver; uint32_t 174 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_cntl_feature_ver; uint32_t 175 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_cntl_size_bytes; uint32_t 176 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_cntl_offset_bytes; uint32_t 177 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_gpm_ucode_ver; uint32_t 178 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_gpm_feature_ver; uint32_t 179 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_gpm_size_bytes; uint32_t 180 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_gpm_offset_bytes; uint32_t 181 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_srm_ucode_ver; uint32_t 182 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_srm_feature_ver; uint32_t 183 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_srm_size_bytes; uint32_t 184 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t save_restore_list_srm_offset_bytes; uint32_t 190 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_feature_version; uint32_t 191 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_change_version; uint32_t 192 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t jt_offset; /* jt location */ uint32_t 193 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t jt_size; /* size of jt */ uint32_t 199 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t digest_size; uint32_t 204 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_num_se; uint32_t 205 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_num_cu_per_sh; uint32_t 206 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_num_sh_per_se; uint32_t 207 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_num_rb_per_se; uint32_t 208 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_num_tccs; uint32_t 209 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_num_gprs; uint32_t 210 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_num_max_gs_thds; uint32_t 211 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_gs_table_depth; uint32_t 212 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_gsprim_buff_depth; uint32_t 213 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_parameter_cache_depth; uint32_t 214 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_double_offchip_lds_buffer; uint32_t 215 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_wave_size; uint32_t 216 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_max_waves_per_simd; uint32_t 217 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_max_scratch_slots_per_cu; uint32_t 218 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t gc_lds_size; uint32_t 223 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t num_sc_per_sh; uint32_t 224 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t num_packer_per_sc; uint32_t 244 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ uint32_t 245 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ uint32_t 342 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t ucode_size; uint32_t 344 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t tmr_mc_addr_lo; uint32_t 345 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h uint32_t tmr_mc_addr_hi; uint32_t 39 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index; \ uint32_t 63 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h uint32_t umc_instance); uint32_t 69 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h uint32_t max_ras_err_cnt_per_query; uint32_t 71 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h uint32_t channel_inst_num; uint32_t 73 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h uint32_t umc_inst_num; uint32_t 75 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h uint32_t channel_offs; uint32_t 77 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h const uint32_t *channel_idx_tbl; uint32_t 425 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t handle = atomic_read(&adev->uvd.handles[i]); uint32_t 457 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t lo, hi; uint32_t 480 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t cmd; uint32_t 495 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; uint32_t 514 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, uint32_t 809 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t cmd; uint32_t 944 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); uint32_t 972 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) uint32_t 1026 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t data[4]; uint32_t 1121 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 1126 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t *msg; uint32_t 1153 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 1158 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t *msg; uint32_t 1276 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) uint32_t 1279 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t used_handles = 0; uint32_t 48 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h uint32_t srbm_soft_reset; uint32_t 77 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 79 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 83 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx); uint32_t 87 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev); uint32_t 407 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t handle = atomic_read(&adev->vce.handles[i]); uint32_t 431 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 511 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 576 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx, uint32_t 624 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx, uint32_t 625 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c int lo, int hi, unsigned size, uint32_t index) uint32_t 674 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t handle, uint32_t *allocated) uint32_t 709 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) uint32_t 714 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t destroyed = 0; uint32_t 715 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t created = 0; uint32_t 716 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t allocated = 0; uint32_t 717 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t tmp, handle = 0; uint32_t 718 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t *size = &tmp; uint32_t 726 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); uint32_t 727 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); uint32_t 792 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); uint32_t 793 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); uint32_t 945 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx) uint32_t 949 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t destroyed = 0; uint32_t 950 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t created = 0; uint32_t 951 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t allocated = 0; uint32_t 952 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t tmp, handle = 0; uint32_t 956 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); uint32_t 957 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); uint32_t 1039 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t flags) uint32_t 1076 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c uint32_t rptr; uint32_t 44 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; uint32_t 52 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h uint32_t srbm_soft_reset; uint32_t 61 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 64 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 67 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx); uint32_t 68 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx); uint32_t 70 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h struct amdgpu_ib *ib, uint32_t flags); uint32_t 383 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c uint32_t tmp = 0; uint32_t 459 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 464 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c uint32_t *msg; uint32_t 493 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 498 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c uint32_t *msg; uint32_t 546 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c uint32_t rptr; uint32_t 571 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 624 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 713 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c uint32_t tmp = 0; uint32_t 739 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 781 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c uint32_t tmp = 0; uint32_t 82 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h uint32_t internal_reg_offset, addr; \ uint32_t 188 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h uint32_t *dpg_sram_curr_addr; uint32_t 48 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) uint32_t 52 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t seq; uint32_t 94 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) uint32_t 98 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t seq; uint32_t 141 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t reg0, uint32_t reg1, uint32_t 142 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t ref, uint32_t mask) uint32_t 148 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t seq; uint32_t 332 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t pf2vf_size = 0; uint32_t 333 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t checksum = 0; uint32_t 334 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t checkval; uint32_t 383 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c static uint32_t parse_clk(char *buf, bool min) uint32_t 386 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t clk = 0; uint32_t 400 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest) uint32_t 403 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t clk = 0; uint32_t 417 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest) uint32_t 420 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t clk = 0; uint32_t 35 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t *cpu_addr; uint32_t 94 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t size; uint32_t 96 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t version; uint32_t 98 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t reserved[2]; uint32_t 123 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t checksum; uint32_t 125 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t feature_flags; uint32_t 127 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t uvd_enc_max_pixels_count; uint32_t 129 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t uvd_enc_max_bandwidth; uint32_t 131 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t vce_enc_max_pixels_count; uint32_t 133 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t vce_enc_max_bandwidth; uint32_t 137 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t mecfw_ksize; uint32_t 141 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t uvdfw_ksize; uint32_t 145 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t vcefw_ksize; uint32_t 146 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 3)]; uint32_t 152 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t size; uint32_t 154 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t version; uint32_t 156 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t reserved[2]; uint32_t 192 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t checksum; uint32_t 196 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t driver_cert; uint32_t 198 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t os_info; uint32_t 200 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t fb_usage; uint32_t 202 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t gfx_usage; uint32_t 204 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t gfx_health; uint32_t 206 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t compute_usage; uint32_t 208 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t compute_health; uint32_t 210 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t vce_enc_usage; uint32_t 212 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t vce_enc_health; uint32_t 214 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t uvd_enc_usage; uint32_t 216 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t uvd_enc_health; uint32_t 217 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; uint32_t 247 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t caps; uint32_t 251 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t reg_val_offs; uint32_t 259 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t gim_feature; uint32_t 262 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t reg_access_mode; uint32_t 294 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); uint32_t 295 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); uint32_t 297 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t reg0, uint32_t rreg1, uint32_t 298 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t ref, uint32_t mask); uint32_t 309 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest); uint32_t 310 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest); uint32_t 167 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev, uint32_t 1285 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c unsigned count, uint32_t incr, uint32_t 1751 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c uint32_t mem_type = bo->tbo.mem.mem_type; uint32_t 2541 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) uint32_t 2564 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, uint32_t 2565 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c uint32_t fragment_size_default, unsigned max_level, uint32_t 167 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h uint32_t incr); uint32_t 172 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h uint32_t incr, uint64_t flags); uint32_t 225 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h unsigned count, uint32_t incr, uint64_t flags); uint32_t 303 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h uint32_t num_level; uint32_t 304 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h uint32_t block_size; uint32_t 305 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h uint32_t fragment_size; uint32_t 332 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h uint32_t xgmi_map_counter; uint32_t 397 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, uint32_t 398 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h uint32_t fragment_size_default, unsigned max_level, uint32_t 84 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c uint64_t addr, unsigned count, uint32_t incr, uint32_t 166 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c uint32_t incr, uint64_t flags) uint32_t 197 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c uint64_t addr, unsigned count, uint32_t incr, uint32_t 304 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c pages_per_node = max((uint32_t)pages_per_node, mem->page_alignment); uint32_t 308 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c nodes = kvmalloc_array((uint32_t)num_nodes, sizeof(*nodes), uint32_t 340 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c uint32_t alignment = mem->page_alignment; uint32_t 141 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; uint32_t 33 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c uint32_t i; uint32_t 35 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 36 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); uint32_t 37 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); uint32_t 38 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); uint32_t 39 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); uint32_t 40 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); uint32_t 41 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); uint32_t 42 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); uint32_t 43 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); uint32_t 44 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); uint32_t 45 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); uint32_t 46 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); uint32_t 47 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i])); uint32_t 48 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i])); uint32_t 49 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i])); uint32_t 50 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA5_HWIP][i] = (uint32_t *)(&(SDMA5_BASE.instance[i])); uint32_t 51 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i])); uint32_t 52 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i])); uint32_t 53 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); uint32_t 54 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); uint32_t 35 drivers/gpu/drm/amd/amdgpu/athub_v1_0.c uint32_t def, data; uint32_t 51 drivers/gpu/drm/amd/amdgpu/athub_v1_0.c uint32_t def, data; uint32_t 38 drivers/gpu/drm/amd/amdgpu/athub_v2_0.c uint32_t def, data; uint32_t 55 drivers/gpu/drm/amd/amdgpu/athub_v2_0.c uint32_t def, data; uint32_t 59 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t *ps, *ws; uint32_t 68 drivers/gpu/drm/amd/amdgpu/atom.c static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); uint32_t 69 drivers/gpu/drm/amd/amdgpu/atom.c int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); uint32_t 71 drivers/gpu/drm/amd/amdgpu/atom.c static uint32_t atom_arg_mask[8] = uint32_t 104 drivers/gpu/drm/amd/amdgpu/atom.c static uint32_t atom_iio_execute(struct atom_context *ctx, int base, uint32_t 105 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t index, uint32_t data) uint32_t 107 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t temp = 0xCDCDCDCD; uint32_t 176 drivers/gpu/drm/amd/amdgpu/atom.c static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, uint32_t 177 drivers/gpu/drm/amd/amdgpu/atom.c int *ptr, uint32_t *saved, int print) uint32_t 179 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t idx, val = 0xCDCDCDCD, align, arg; uint32_t 363 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t align = (attr >> 3) & 7, arg = attr & 7; uint32_t 397 drivers/gpu/drm/amd/amdgpu/atom.c static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) uint32_t 402 drivers/gpu/drm/amd/amdgpu/atom.c static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) uint32_t 404 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t val = 0xCDCDCDCD; uint32_t 428 drivers/gpu/drm/amd/amdgpu/atom.c static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, uint32_t 429 drivers/gpu/drm/amd/amdgpu/atom.c int *ptr, uint32_t *saved, int print) uint32_t 445 drivers/gpu/drm/amd/amdgpu/atom.c int *ptr, uint32_t val, uint32_t saved) uint32_t 447 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t align = uint32_t 583 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src, saved; uint32_t 597 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src, saved; uint32_t 632 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t saved; uint32_t 644 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src; uint32_t 670 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src; uint32_t 688 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src; uint32_t 766 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, mask, src, saved; uint32_t 783 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t src, saved; uint32_t 800 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src; uint32_t 812 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src; uint32_t 830 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src, saved; uint32_t 920 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t saved, dst; uint32_t 936 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t saved, dst; uint32_t 952 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t saved, dst; uint32_t 954 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; uint32_t 971 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t saved, dst; uint32_t 973 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; uint32_t 990 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src, saved; uint32_t 1004 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t src, val, target; uint32_t 1031 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src; uint32_t 1043 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, src, saved; uint32_t 1201 drivers/gpu/drm/amd/amdgpu/atom.c static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) uint32_t 1262 drivers/gpu/drm/amd/amdgpu/atom.c int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) uint32_t 1360 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t ps[16]; uint32_t 117 drivers/gpu/drm/amd/amdgpu/atom.h void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t 118 drivers/gpu/drm/amd/amdgpu/atom.h uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */ uint32_t 119 drivers/gpu/drm/amd/amdgpu/atom.h void (* ioreg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t 120 drivers/gpu/drm/amd/amdgpu/atom.h uint32_t (* ioreg_read)(struct card_info *, uint32_t); /* filled by driver */ uint32_t 121 drivers/gpu/drm/amd/amdgpu/atom.h void (* mc_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t 122 drivers/gpu/drm/amd/amdgpu/atom.h uint32_t (* mc_read)(struct card_info *, uint32_t); /* filled by driver */ uint32_t 123 drivers/gpu/drm/amd/amdgpu/atom.h void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t 124 drivers/gpu/drm/amd/amdgpu/atom.h uint32_t (* pll_read)(struct card_info *, uint32_t); /* filled by driver */ uint32_t 131 drivers/gpu/drm/amd/amdgpu/atom.h uint32_t cmd_table, data_table; uint32_t 135 drivers/gpu/drm/amd/amdgpu/atom.h uint32_t fb_base; uint32_t 136 drivers/gpu/drm/amd/amdgpu/atom.h uint32_t divmul[2]; uint32_t 142 drivers/gpu/drm/amd/amdgpu/atom.h uint32_t *scratch; uint32_t 150 drivers/gpu/drm/amd/amdgpu/atom.h int amdgpu_atom_execute_table(struct atom_context *, int, uint32_t *); uint32_t 81 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 110 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 127 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 143 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 159 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 175 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 187 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 232 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 297 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 399 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c index, (uint32_t *)&args); uint32_t 432 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c index, (uint32_t *)&args); uint32_t 518 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 548 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 744 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 85 drivers/gpu/drm/amd/amdgpu/atombios_dp.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 307 drivers/gpu/drm/amd/amdgpu/atombios_dp.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 344 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 441 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 747 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1172 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1200 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1324 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1669 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1742 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1757 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c uint32_t bios_0_scratch; uint32_t 1855 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; uint32_t 94 drivers/gpu/drm/amd/amdgpu/atombios_i2c.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 180 drivers/gpu/drm/amd/amdgpu/atombios_i2c.c amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 881 drivers/gpu/drm/amd/amdgpu/cik.c uint32_t tmp; uint32_t 1027 drivers/gpu/drm/amd/amdgpu/cik.c static uint32_t cik_get_register_value(struct amdgpu_device *adev, uint32_t 1032 drivers/gpu/drm/amd/amdgpu/cik.c uint32_t val; uint32_t 1126 drivers/gpu/drm/amd/amdgpu/cik.c uint32_t i; uint32_t 1310 drivers/gpu/drm/amd/amdgpu/cik.c uint32_t tmp; uint32_t 1712 drivers/gpu/drm/amd/amdgpu/cik.c static uint32_t cik_get_rev_id(struct amdgpu_device *adev) uint32_t 1754 drivers/gpu/drm/amd/amdgpu/cik.c uint32_t perfctr = 0; uint32_t 247 drivers/gpu/drm/amd/amdgpu/cik_ih.c uint32_t dw[4]; uint32_t 201 drivers/gpu/drm/amd/amdgpu/cik_sdma.c static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 225 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t flags) uint32_t 757 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t incr) uint32_t 787 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t incr, uint64_t flags) uint32_t 834 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 875 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t reg, uint32_t val) uint32_t 1316 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t byte_count) uint32_t 1338 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t src_data, uint32_t 1340 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t byte_count) uint32_t 226 drivers/gpu/drm/amd/amdgpu/cz_ih.c uint32_t dw[4]; uint32_t 74 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static const uint32_t dig_offsets[] = { uint32_t 85 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t reg; uint32_t 86 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t vblank; uint32_t 87 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t vline; uint32_t 88 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t hpd; uint32_t 1465 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) uint32_t 1840 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t fb_format, fb_pitch_pixels; uint32_t 2272 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t cur_lock; uint32_t 2356 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t handle, uint32_t 2357 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t width, uint32_t 2358 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t height, uint32_t 2456 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u16 *blue, uint32_t size, uint32_t 3214 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); uint32_t 3251 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t disp_int, mask; uint32_t 3461 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t encoder_enum, uint32_t 3462 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t supported_device, uint32_t 74 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static const uint32_t dig_offsets[] = { uint32_t 87 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t reg; uint32_t 88 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t vblank; uint32_t 89 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t vline; uint32_t 90 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t hpd; uint32_t 1507 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) uint32_t 1882 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t fb_format, fb_pitch_pixels; uint32_t 2351 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t cur_lock; uint32_t 2435 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t handle, uint32_t 2436 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t width, uint32_t 2437 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t height, uint32_t 2535 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u16 *blue, uint32_t size, uint32_t 3340 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); uint32_t 3378 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t disp_int, mask; uint32_t 3587 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t encoder_enum, uint32_t 3588 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t supported_device, uint32_t 77 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static const uint32_t dig_offsets[] = { uint32_t 88 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t reg; uint32_t 89 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t vblank; uint32_t 90 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t vline; uint32_t 91 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t hpd; uint32_t 1391 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t clock, int bpc) uint32_t 1798 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t fb_format, fb_pitch_pixels, pipe_config; uint32_t 2162 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t cur_lock; uint32_t 2249 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t handle, uint32_t 2250 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t width, uint32_t 2251 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t height, uint32_t 2348 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u16 *blue, uint32_t size, uint32_t 2933 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); uint32_t 3045 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t disp_int, mask, tmp; uint32_t 3271 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t encoder_enum, uint32_t 3272 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t supported_device, uint32_t 74 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static const uint32_t dig_offsets[] = { uint32_t 85 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t reg; uint32_t 86 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t vblank; uint32_t 87 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t vline; uint32_t 88 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t hpd; uint32_t 1428 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) uint32_t 1435 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t offset = dig->afmt->offset; uint32_t 1457 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t offset = dig->afmt->offset; uint32_t 1507 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t offset, val; uint32_t 1769 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t fb_format, fb_pitch_pixels; uint32_t 2175 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t cur_lock; uint32_t 2257 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t handle, uint32_t 2258 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t width, uint32_t 2259 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t height, uint32_t 2357 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u16 *blue, uint32_t size, uint32_t 3025 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); uint32_t 3137 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t disp_int, mask, tmp; uint32_t 3349 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t encoder_enum, uint32_t 3350 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t supported_device, uint32_t 105 drivers/gpu/drm/amd/amdgpu/dce_virtual.c u16 *green, u16 *blue, uint32_t size, uint32_t 97 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t ficaa_val) uint32_t 100 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t ficadl_val, ficadh_val; uint32_t 120 drivers/gpu/drm/amd/amdgpu/df_v3_6.c static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, uint32_t 121 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t ficadl_val, uint32_t ficadh_val) uint32_t 148 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t lo_addr, uint32_t *lo_val, uint32_t 149 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t hi_addr, uint32_t *hi_val) uint32_t 170 drivers/gpu/drm/amd/amdgpu/df_v3_6.c static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr, uint32_t 171 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val) uint32_t 319 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t *lo_base_addr, uint32_t 320 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t *hi_base_addr) uint32_t 353 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t *lo_base_addr, uint32_t 354 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t *hi_base_addr) uint32_t 362 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t *lo_base_addr, uint32_t 363 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t *hi_base_addr, uint32_t 364 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t *lo_val, uint32_t 365 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t *hi_val) uint32_t 368 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t eventsel, instance, unitmask; uint32_t 369 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t instance_10, instance_5432, instance_76; uint32_t 432 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t lo_base_addr, hi_base_addr; uint32_t 446 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; uint32_t 482 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; uint32_t 514 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; uint32_t 276 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; uint32_t 302 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; uint32_t 329 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; uint32_t 401 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c bool wc, uint32_t reg, uint32_t val) uint32_t 412 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c int mem_space, int opt, uint32_t addr0, uint32_t 413 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t addr1, uint32_t ref, uint32_t mask, uint32_t 414 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t inv) uint32_t 436 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t scratch; uint32_t 437 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp = 0; uint32_t 493 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t scratch; uint32_t 494 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp = 0; uint32_t 1110 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) uint32_t 1118 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, uint32_t 1119 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t thread, uint32_t regno, uint32_t 1120 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t num, uint32_t *out) uint32_t 1131 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) uint32_t 1157 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t 1158 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t wave, uint32_t start, uint32_t 1159 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t size, uint32_t *dst) uint32_t 1168 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t 1169 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t wave, uint32_t thread, uint32_t 1170 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t start, uint32_t size, uint32_t 1171 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t *dst) uint32_t 1564 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t num_sc; uint32_t 1565 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t enabled_rb_per_sh; uint32_t 1566 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t active_rb_bitmap; uint32_t 1567 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t num_rb_per_sc; uint32_t 1568 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t num_packer_per_sc; uint32_t 1569 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t pa_sc_tile_steering_override; uint32_t 1602 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t sh_mem_bases; uint32_t 1724 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | uint32_t 1855 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t rlc_pg_cntl; uint32_t 1887 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 2022 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) uint32_t 2024 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t total_size = 0; uint32_t 2048 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t total_size; uint32_t 2078 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t fw_size) uint32_t 2080 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t toc_offset; uint32_t 2081 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t toc_fw_size; uint32_t 2105 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t size; uint32_t 2118 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t fw_size; uint32_t 2179 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t fw_size; uint32_t 2195 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (uint32_t *)fw_data + uint32_t 2203 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (uint32_t *)fw_data + uint32_t 2212 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t rlc_g_offset, rlc_g_size, tmp; uint32_t 2245 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t usec_timeout = 50000; /* wait for 50ms */ uint32_t 2246 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 2282 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t usec_timeout = 50000; /* wait for 50ms */ uint32_t 2283 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 2319 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t usec_timeout = 50000; /* wait for 50ms */ uint32_t 2320 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 2356 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t usec_timeout = 50000; /* wait for 50ms */ uint32_t 2357 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 2393 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t cp_status; uint32_t 2394 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t bootload_status; uint32_t 2466 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 2467 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t usec_timeout = 50000; /* wait for 50ms */ uint32_t 2536 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 2537 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t usec_timeout = 50000; /* wait for 50ms */ uint32_t 2605 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 2606 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t usec_timeout = 50000; /* wait for 50ms */ uint32_t 3006 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 3023 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 3024 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t rb_bufsz; uint32_t 3265 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp; uint32_t 3688 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t data, pattern = 0xDEADBEEF; uint32_t 3709 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t data; uint32_t 3992 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t vmid, uint32_t 3993 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t gds_base, uint32_t gds_size, uint32_t 3994 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t gws_base, uint32_t gws_size, uint32_t 3995 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t oa_base, uint32_t oa_size) uint32_t 4054 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t rlc_cntl; uint32_t 4063 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t data; uint32_t 4080 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t data; uint32_t 4089 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t data, def; uint32_t 4151 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t data, def; uint32_t 4193 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t def, data; uint32_t 4455 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t flags) uint32_t 4492 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t flags) uint32_t 4565 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 4618 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) uint32_t 4620 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t dw2 = 0; uint32_t 4790 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) uint32_t 4806 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t 4807 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t val) uint32_t 4809 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t cmd = 0; uint32_t 4829 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 4830 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t val, uint32_t mask) uint32_t 4836 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t reg0, uint32_t reg1, uint32_t 4837 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t ref, uint32_t mask) uint32_t 4855 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t me, uint32_t pipe, uint32_t 4858 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t cp_int_cntl, cp_int_cntl_reg; uint32_t 5119 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tmp, target; uint32_t 1793 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t scratch; uint32_t 1794 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t tmp = 0; uint32_t 1866 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t flags) uint32_t 1908 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t scratch; uint32_t 1909 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t tmp = 0; uint32_t 2310 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 2363 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t reg, uint32_t val) uint32_t 2977 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) uint32_t 2987 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) uint32_t 2997 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t 2998 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t wave, uint32_t thread, uint32_t 2999 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t regno, uint32_t num, uint32_t *out) uint32_t 3012 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) uint32_t 3036 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t 3037 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t wave, uint32_t start, uint32_t 3038 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t size, uint32_t *dst) uint32_t 1030 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t *tile, *macrotile; uint32_t 1858 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t sh_mem_config; uint32_t 1859 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t sh_mem_bases; uint32_t 2090 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t scratch; uint32_t 2091 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t tmp = 0; uint32_t 2261 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t flags) uint32_t 2292 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t flags) uint32_t 2323 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) uint32_t 2325 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t dw2 = 0; uint32_t 2357 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t scratch; uint32_t 2358 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t tmp = 0; uint32_t 3050 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t tmp; uint32_t 3051 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t mqd_reg; uint32_t 3052 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t *mqd_data; uint32_t 3214 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 3283 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t reg, uint32_t val) uint32_t 4091 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t vmid, uint32_t 4092 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t gds_base, uint32_t gds_size, uint32_t 4093 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t gws_base, uint32_t gws_size, uint32_t 4094 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t oa_base, uint32_t oa_size) uint32_t 4132 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t value = 0; uint32_t 4141 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) uint32_t 4151 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t 4152 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t wave, uint32_t thread, uint32_t 4153 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t regno, uint32_t num, uint32_t *out) uint32_t 4166 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) uint32_t 4190 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t 4191 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t wave, uint32_t start, uint32_t 4192 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t size, uint32_t *dst) uint32_t 839 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t scratch; uint32_t 840 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t tmp = 0; uint32_t 881 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t tmp; uint32_t 2127 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t *modearray, *mod2array; uint32_t 3713 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t sh_mem_config; uint32_t 3714 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t sh_mem_bases; uint32_t 4049 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t data; uint32_t 4363 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t tmp; uint32_t 4462 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t tmp; uint32_t 4603 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t mqd_reg; uint32_t 4604 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t *mqd_data; uint32_t 5203 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t vmid, uint32_t 5204 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t gds_base, uint32_t gds_size, uint32_t 5205 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t gws_base, uint32_t gws_size, uint32_t 5206 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t oa_base, uint32_t oa_size) uint32_t 5241 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) uint32_t 5251 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t 5252 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t wave, uint32_t thread, uint32_t 5253 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t regno, uint32_t num, uint32_t *out) uint32_t 5266 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) uint32_t 5290 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t 5291 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t wave, uint32_t start, uint32_t 5292 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t size, uint32_t *dst) uint32_t 5526 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t reg_addr, uint32_t cmd) uint32_t 5528 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t data; uint32_t 5575 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t rlc_setting; uint32_t 5586 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t data; uint32_t 5613 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t data; uint32_t 5645 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t temp, data; uint32_t 5749 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t temp, temp1, data, data1; uint32_t 5860 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t msg_id, pp_state = 0; uint32_t 5861 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t pp_support_state = 0; uint32_t 5912 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t msg_id, pp_state = 0; uint32_t 5913 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t pp_support_state = 0; uint32_t 6118 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t flags) uint32_t 6150 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t flags) uint32_t 6221 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 6348 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t pipe_priority = acquire ? 0x2 : 0x0; uint32_t 6349 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t queue_priority = acquire ? 0xf : 0x0; uint32_t 6425 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) uint32_t 6427 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t dw2 = 0; uint32_t 6485 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) uint32_t 6501 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t 6502 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t val) uint32_t 6504 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t cmd; uint32_t 6528 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c uint32_t value = 0; uint32_t 806 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c bool wc, uint32_t reg, uint32_t val) uint32_t 818 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c int mem_space, int opt, uint32_t addr0, uint32_t 819 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t addr1, uint32_t ref, uint32_t mask, uint32_t 820 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t inv) uint32_t 842 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t scratch; uint32_t 843 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t tmp = 0; uint32_t 884 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t tmp; uint32_t 1157 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t smu_version; uint32_t 1491 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t pg_always_on_cu_num = 2; uint32_t 1492 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t always_on_cu_num; uint32_t 1493 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t i, j, k; uint32_t 1494 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t mask, cu_bitmap, counter; uint32_t 1534 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data; uint32_t 1583 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data; uint32_t 1776 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) uint32_t 1786 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t 1787 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t wave, uint32_t thread, uint32_t 1788 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t regno, uint32_t num, uint32_t *out) uint32_t 1801 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) uint32_t 1821 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t 1822 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t wave, uint32_t start, uint32_t 1823 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t size, uint32_t *dst) uint32_t 1830 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t 1831 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t wave, uint32_t thread, uint32_t 1832 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t start, uint32_t size, uint32_t 1833 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t *dst) uint32_t 2446 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t sh_mem_config; uint32_t 2447 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t sh_mem_bases; uint32_t 2756 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data = 0; uint32_t 2757 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t default_data = 0; uint32_t 2781 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data = 0; uint32_t 2824 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data = 0; uint32_t 2825 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t default_data = 0; uint32_t 2838 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data = 0; uint32_t 2839 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t default_data = 0; uint32_t 2852 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data = 0; uint32_t 2853 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t default_data = 0; uint32_t 2866 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data, default_data; uint32_t 2879 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data, default_data; uint32_t 2896 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data, default_data; uint32_t 2909 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data, default_data; uint32_t 3330 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t tmp; uint32_t 3415 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t tmp; uint32_t 4097 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t vmid, uint32_t 4098 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t gds_base, uint32_t gds_size, uint32_t 4099 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t gws_base, uint32_t gws_size, uint32_t 4100 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t oa_base, uint32_t oa_size) uint32_t 4542 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t rlc_setting; uint32_t 4554 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data; uint32_t 4571 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data; uint32_t 4619 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data, def; uint32_t 4694 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t data, def; uint32_t 4745 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t def, data; uint32_t 5014 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t flags) uint32_t 5047 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t flags) uint32_t 5116 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 5227 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t pipe_priority = acquire ? 0x2 : 0x0; uint32_t 5228 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t queue_priority = acquire ? 0xf : 0x0; uint32_t 5346 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) uint32_t 5348 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t dw2 = 0; uint32_t 5405 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) uint32_t 5421 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t 5422 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t val) uint32_t 5424 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t cmd = 0; uint32_t 5444 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 5445 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t val, uint32_t mask) uint32_t 5451 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t reg0, uint32_t reg1, uint32_t 5452 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t ref, uint32_t mask) uint32_t 5470 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t value = 0; uint32_t 5753 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t ip; uint32_t 5754 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t inst; uint32_t 5755 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t seg; uint32_t 5756 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t reg_offset; uint32_t 5757 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t per_se_instance; uint32_t 5759 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t sec_count_mask; uint32_t 5760 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t ded_count_mask; uint32_t 6098 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t sec_count, ded_count; uint32_t 6099 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t i; uint32_t 6100 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t reg_value; uint32_t 6101 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t se_id, instance_id; uint32_t 38 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint32_t 116 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c uint32_t tmp; uint32_t 137 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c uint32_t tmp; uint32_t 176 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c uint32_t tmp; uint32_t 204 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c uint32_t tmp; uint32_t 33 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint32_t 112 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c uint32_t tmp; uint32_t 132 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c uint32_t tmp; uint32_t 173 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c uint32_t tmp; uint32_t 201 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c uint32_t tmp; uint32_t 132 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c uint32_t status = 0; uint32_t 202 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid, uint32_t 203 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c uint32_t flush_type) uint32_t 229 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, uint32_t 230 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c unsigned int vmhub, uint32_t flush_type) uint32_t 306 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t 307 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c uint32_t vmhub, uint32_t flush_type) uint32_t 373 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0); uint32_t 416 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c uint32_t reg; uint32_t 458 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c uint32_t flags) uint32_t 365 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t 366 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c uint32_t vmhub, uint32_t flush_type) uint32_t 374 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c uint32_t reg; uint32_t 390 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c uint32_t flags) uint32_t 462 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; uint32_t 463 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c uint32_t high = adev->vm_manager.max_pfn - uint32_t 436 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t 437 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c uint32_t vmhub, uint32_t flush_type) uint32_t 446 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c uint32_t reg; uint32_t 467 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c uint32_t flags) uint32_t 522 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c uint32_t tmp; uint32_t 547 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; uint32_t 548 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c uint32_t high = adev->vm_manager.max_pfn - uint32_t 638 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t 639 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c uint32_t vmhub, uint32_t flush_type) uint32_t 648 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c uint32_t reg; uint32_t 690 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c uint32_t flags) uint32_t 774 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; uint32_t 775 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c uint32_t high = adev->vm_manager.max_pfn - uint32_t 1486 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c uint32_t data; uint32_t 1566 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c uint32_t data; uint32_t 96 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { uint32_t 131 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { uint32_t 166 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c static const uint32_t ecc_umc_mcumc_status_addrs[] = { uint32_t 335 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t status = 0; uint32_t 432 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, uint32_t 433 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t flush_type) uint32_t 459 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t vmhub) uint32_t 485 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t 486 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t vmhub, uint32_t flush_type) uint32_t 504 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t req = hub->vm_inv_eng0_req + eng; uint32_t 505 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t ack = hub->vm_inv_eng0_ack + eng; uint32_t 573 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); uint32_t 614 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t reg; uint32_t 661 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t flags) uint32_t 41 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint32_t 43 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint32_t 46 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h uint32_t vmid, uint64_t value); uint32_t 226 drivers/gpu/drm/amd/amdgpu/iceland_ih.c uint32_t dw[4]; uint32_t 3285 drivers/gpu/drm/amd/amdgpu/kv_dpm.c uint32_t sclk; uint32_t 3300 drivers/gpu/drm/amd/amdgpu/kv_dpm.c *((uint32_t *)value) = sclk; uint32_t 3306 drivers/gpu/drm/amd/amdgpu/kv_dpm.c *((uint32_t *)value) = kv_dpm_get_temp(adev); uint32_t 3315 drivers/gpu/drm/amd/amdgpu/kv_dpm.c uint32_t block_type, bool gate) uint32_t 189 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c uint32_t data = 0; uint32_t 198 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c (uint32_t)(adev->mes.uc_start_addr) >> 2); uint32_t 224 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c uint32_t data; uint32_t 249 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c (uint32_t)(adev->mes.uc_start_addr) >> 2); uint32_t 58 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint32_t 92 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint32_t tmp; uint32_t 142 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint32_t tmp; uint32_t 163 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint32_t tmp; uint32_t 204 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint32_t tmp; uint32_t 236 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint32_t tmp; uint32_t 439 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint32_t def, data, def1, data1, def2 = 0, data2 = 0; uint32_t 502 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint32_t def, data; uint32_t 569 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint32_t ea0_edc_cnt, ea0_edc_cnt2; uint32_t 570 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint32_t ea1_edc_cnt, ea1_edc_cnt2; uint32_t 39 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint32_t 63 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c uint32_t tmp; uint32_t 98 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c uint32_t tmp; uint32_t 118 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c uint32_t tmp; uint32_t 159 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c uint32_t tmp; uint32_t 190 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c uint32_t tmp; uint32_t 362 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c uint32_t def, data, def1, data1; uint32_t 399 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c uint32_t def, data; uint32_t 57 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c uint32_t vmid, uint64_t value) uint32_t 107 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c uint32_t tmp; uint32_t 163 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c uint32_t tmp; uint32_t 191 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c uint32_t tmp; uint32_t 246 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c uint32_t tmp; uint32_t 283 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c uint32_t tmp; uint32_t 535 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c uint32_t def, data, def1, data1; uint32_t 592 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c uint32_t def, data; uint32_t 40 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t version; uint32_t 41 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t header_size; uint32_t 42 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t vce_init_status; uint32_t 43 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t uvd_init_status; uint32_t 44 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t vce_table_offset; uint32_t 45 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t vce_table_size; uint32_t 46 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t uvd_table_offset; uint32_t 47 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t uvd_table_size; uint32_t 51 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset : 28; uint32_t 52 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t command_type : 4; uint32_t 56 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset : 20; uint32_t 57 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_idx_space : 8; uint32_t 58 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t command_type : 4; uint32_t 63 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_value; uint32_t 68 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t write_data; uint32_t 69 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t mask_value; uint32_t 74 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t mask_value; uint32_t 75 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t wait_value; uint32_t 84 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_value; uint32_t 88 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t *init_table, uint32_t 89 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset, uint32_t 90 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t value) uint32_t 98 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t *init_table, uint32_t 99 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset, uint32_t 100 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t mask, uint32_t data) uint32_t 110 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t *init_table, uint32_t 111 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset, uint32_t 112 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t mask, uint32_t wait) uint32_t 76 drivers/gpu/drm/amd/amdgpu/navi10_ih.c static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) uint32_t 258 drivers/gpu/drm/amd/amdgpu/navi10_ih.c uint32_t dw[8]; uint32_t 402 drivers/gpu/drm/amd/amdgpu/navi10_ih.c uint32_t data, def, field_val; uint32_t 35 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 36 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); uint32_t 37 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); uint32_t 38 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); uint32_t 39 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); uint32_t 40 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); uint32_t 41 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); uint32_t 42 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); uint32_t 43 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); uint32_t 44 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i])); uint32_t 45 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); uint32_t 46 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 47 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 48 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); uint32_t 49 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); uint32_t 50 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); uint32_t 33 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c uint32_t i; uint32_t 35 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 36 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); uint32_t 37 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); uint32_t 38 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); uint32_t 39 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); uint32_t 40 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); uint32_t 41 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); uint32_t 42 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); uint32_t 43 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); uint32_t 44 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); uint32_t 45 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); uint32_t 46 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 47 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 48 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); uint32_t 49 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); uint32_t 50 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); uint32_t 35 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 36 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); uint32_t 37 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); uint32_t 38 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); uint32_t 39 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); uint32_t 40 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); uint32_t 41 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); uint32_t 42 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); uint32_t 43 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); uint32_t 44 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); uint32_t 45 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); uint32_t 46 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 47 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 48 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); uint32_t 49 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); uint32_t 50 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); uint32_t 190 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c uint32_t def, data; uint32_t 216 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c uint32_t def, data; uint32_t 286 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c uint32_t reg; uint32_t 303 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c uint32_t def, data; uint32_t 148 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c uint32_t def, data; uint32_t 176 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c uint32_t def, data; uint32_t 246 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c uint32_t reg; uint32_t 263 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c uint32_t def, data; uint32_t 140 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset) uint32_t 142 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c uint32_t data; uint32_t 150 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset, uint32_t 151 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c uint32_t data) uint32_t 160 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c uint32_t def, data; uint32_t 199 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c uint32_t def, data; uint32_t 200 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c uint32_t def, data; uint32_t 292 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c uint32_t reg; uint32_t 309 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c uint32_t def, data; uint32_t 184 drivers/gpu/drm/amd/amdgpu/nv.c static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, uint32_t 187 drivers/gpu/drm/amd/amdgpu/nv.c uint32_t val; uint32_t 201 drivers/gpu/drm/amd/amdgpu/nv.c static uint32_t nv_get_register_value(struct amdgpu_device *adev, uint32_t 217 drivers/gpu/drm/amd/amdgpu/nv.c uint32_t i; uint32_t 483 drivers/gpu/drm/amd/amdgpu/nv.c static uint32_t nv_get_rev_id(struct amdgpu_device *adev) uint32_t 752 drivers/gpu/drm/amd/amdgpu/nv.c uint32_t hdp_clk_cntl, hdp_clk_cntl1; uint32_t 753 drivers/gpu/drm/amd/amdgpu/nv.c uint32_t hdp_mem_pwr_cntl; uint32_t 825 drivers/gpu/drm/amd/amdgpu/nv.c uint32_t hdp_clk_cntl; uint32_t 834 drivers/gpu/drm/amd/amdgpu/nv.c ~(uint32_t) uint32_t 890 drivers/gpu/drm/amd/amdgpu/nv.c uint32_t tmp; uint32_t 176 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) uint32_t 177 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) uint32_t 178 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) uint32_t 179 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) uint32_t 180 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a) uint32_t 181 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) uint32_t 182 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) uint32_t 183 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) uint32_t 184 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) uint32_t 185 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) uint32_t 186 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) uint32_t 187 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121) uint32_t 188 drivers/gpu/drm/amd/amdgpu/ppsmc.h #define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124) uint32_t 65 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */ uint32_t 66 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */ uint32_t 67 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */ uint32_t 68 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */ uint32_t 69 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */ uint32_t 70 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/ uint32_t 71 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */ uint32_t 72 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */ uint32_t 92 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t reg_value; /* Value to be set to the IH_RB_CNTL... register*/ uint32_t 118 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */ uint32_t 119 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */ uint32_t 120 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t app_len; /* length of the TA binary in bytes */ uint32_t 121 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */ uint32_t 122 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */ uint32_t 123 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */ uint32_t 135 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t session_id; /* Session ID of the loaded TA to be unloaded */ uint32_t 144 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */ uint32_t 145 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */ uint32_t 146 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */ uint32_t 158 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t num_desc; /* number of buffer descriptors in the list */ uint32_t 159 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */ uint32_t 168 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t session_id; /* Session ID of the TA to be executed */ uint32_t 169 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t ta_cmd_id; /* Command ID to be sent to TA */ uint32_t 178 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */ uint32_t 179 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */ uint32_t 180 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */ uint32_t 251 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ uint32_t 252 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ uint32_t 253 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t fw_size; /* FW buffer size in bytes */ uint32_t 261 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/ uint32_t 262 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */ uint32_t 263 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */ uint32_t 264 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t buf_size; /* Size of the save/restore buffer in bytes */ uint32_t 270 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t reg_value; uint32_t 271 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t reg_id; uint32_t 277 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ uint32_t 278 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ uint32_t 279 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t toc_size; /* FW buffer size in bytes */ uint32_t 302 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t status; /* +0 status of command execution */ uint32_t 303 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t session_id; /* +4 session ID in response to LoadTa command */ uint32_t 304 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */ uint32_t 305 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */ uint32_t 306 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */ uint32_t 308 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t reserved[3]; uint32_t 318 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t buf_size; /* +0 total size of the buffer in bytes */ uint32_t 319 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */ uint32_t 320 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t cmd_id; /* +8 command ID */ uint32_t 324 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */ uint32_t 325 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */ uint32_t 326 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t resp_offset; /* +20 offset within response buffer */ uint32_t 327 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */ uint32_t 349 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */ uint32_t 350 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */ uint32_t 351 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t cmd_buf_size; /* +8 command buffer size in bytes */ uint32_t 352 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */ uint32_t 353 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */ uint32_t 354 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t fence_value; /* +20 Fence value */ uint32_t 355 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */ uint32_t 356 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */ uint32_t 360 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h uint32_t reserved2[7]; /* +36 reserved, must be 0 */ uint32_t 203 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c uint32_t ring_size_dw = ring->ring_size / 4; uint32_t 204 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; uint32_t 335 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c uint32_t *ucode_mem = NULL; uint32_t 346 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c ucode_mem = (uint32_t *)ucode->kaddr; uint32_t 211 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t psp_gfxdrv_command_reg = 0; uint32_t 213 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t sol_reg; uint32_t 238 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c (uint32_t)(psp->fw_pri_mc_addr >> 20)); uint32_t 253 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t psp_gfxdrv_command_reg = 0; uint32_t 255 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t sol_reg; uint32_t 280 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c (uint32_t)(psp->fw_pri_mc_addr >> 20)); uint32_t 299 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t sol_reg; uint32_t 321 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c (uint32_t)(psp->fw_pri_mc_addr >> 20)); uint32_t 338 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t tmp; uint32_t 518 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t ring_size_dw = ring->ring_size / 4; uint32_t 519 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; uint32_t 669 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t *ucode_mem = NULL; uint32_t 680 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c ucode_mem = (uint32_t *)ucode->kaddr; uint32_t 698 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c uint32_t offset; uint32_t 90 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c uint32_t psp_gfxdrv_command_reg = 0; uint32_t 92 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c uint32_t sol_reg; uint32_t 117 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c (uint32_t)(psp->fw_pri_mc_addr >> 20)); uint32_t 136 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c uint32_t sol_reg; uint32_t 158 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c (uint32_t)(psp->fw_pri_mc_addr >> 20)); uint32_t 175 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c uint32_t tmp; uint32_t 348 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c uint32_t ring_size_dw = ring->ring_size / 4; uint32_t 349 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; uint32_t 489 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c uint32_t *ucode_mem = NULL; uint32_t 500 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c ucode_mem = (uint32_t *)ucode->kaddr; uint32_t 518 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c uint32_t offset; uint32_t 53 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554}; uint32_t 133 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t psp_gfxdrv_command_reg = 0; uint32_t 135 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t sol_reg; uint32_t 157 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c (uint32_t)(psp->fw_pri_mc_addr >> 20)); uint32_t 171 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver) uint32_t 182 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) { uint32_t 195 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t sol_reg, ver; uint32_t 220 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c (uint32_t)(psp->fw_pri_mc_addr >> 20)); uint32_t 267 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t tmp; uint32_t 424 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t ring_size_dw = ring->ring_size / 4; uint32_t 425 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; uint32_t 567 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t *ucode_mem = NULL; uint32_t 578 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c ucode_mem = (uint32_t *)ucode->kaddr; uint32_t 596 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t reg; uint32_t 605 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t offset; uint32_t 229 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 253 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t flags) uint32_t 696 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t incr) uint32_t 726 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t incr, uint64_t flags) uint32_t 773 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 816 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t reg, uint32_t val) uint32_t 1203 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t byte_count) uint32_t 1226 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t src_data, uint32_t 1228 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t byte_count) uint32_t 403 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 427 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t flags) uint32_t 967 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t incr) uint32_t 997 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t incr, uint64_t flags) uint32_t 1044 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 1087 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t reg, uint32_t val) uint32_t 1443 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t temp, data; uint32_t 1482 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t temp, data; uint32_t 1641 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t byte_count) uint32_t 1664 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t src_data, uint32_t 1666 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t byte_count) uint32_t 672 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 696 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t flags) uint32_t 716 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t addr0, uint32_t addr1, uint32_t 717 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t ref, uint32_t mask, uint32_t 718 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t inv) uint32_t 960 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) uint32_t 963 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); uint32_t 1158 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t def, data; uint32_t 1178 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t def, data; uint32_t 1309 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t temp; uint32_t 1524 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t incr) uint32_t 1555 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t incr, uint64_t flags) uint32_t 1603 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 1630 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t reg, uint32_t val) uint32_t 1638 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 1639 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t val, uint32_t mask) uint32_t 2004 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t instance; uint32_t 2031 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t err_source; uint32_t 2113 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t data, def; uint32_t 2152 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t data, def; uint32_t 2463 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t byte_count) uint32_t 2486 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t src_data, uint32_t 2488 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t byte_count) uint32_t 356 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 380 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t flags) uint32_t 1061 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t incr) uint32_t 1092 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t incr, uint64_t flags) uint32_t 1140 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 1173 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t reg, uint32_t val) uint32_t 1181 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 1182 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t val, uint32_t mask) uint32_t 1196 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t reg0, uint32_t reg1, uint32_t 1197 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t ref, uint32_t mask) uint32_t 1478 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t data, def; uint32_t 1515 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t data, def; uint32_t 1682 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t byte_count) uint32_t 1705 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t src_data, uint32_t 1707 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t byte_count) uint32_t 1017 drivers/gpu/drm/amd/amdgpu/si.c static uint32_t si_get_register_value(struct amdgpu_device *adev, uint32_t 1022 drivers/gpu/drm/amd/amdgpu/si.c uint32_t val; uint32_t 1095 drivers/gpu/drm/amd/amdgpu/si.c uint32_t i; uint32_t 1202 drivers/gpu/drm/amd/amdgpu/si.c uint32_t temp; uint32_t 1342 drivers/gpu/drm/amd/amdgpu/si.c uint32_t perfctr = 0; uint32_t 1419 drivers/gpu/drm/amd/amdgpu/si.c static uint32_t si_get_rev_id(struct amdgpu_device *adev) uint32_t 66 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t flags) uint32_t 341 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t incr) uint32_t 370 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t incr, uint64_t flags) uint32_t 422 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 459 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t reg, uint32_t val) uint32_t 778 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t byte_count) uint32_t 799 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t src_data, uint32_t 801 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t byte_count) uint32_t 7990 drivers/gpu/drm/amd/amdgpu/si_dpm.c uint32_t sclk, mclk; uint32_t 8003 drivers/gpu/drm/amd/amdgpu/si_dpm.c *((uint32_t *)value) = sclk; uint32_t 8011 drivers/gpu/drm/amd/amdgpu/si_dpm.c *((uint32_t *)value) = mclk; uint32_t 8017 drivers/gpu/drm/amd/amdgpu/si_dpm.c *((uint32_t *)value) = si_dpm_get_temp(adev); uint32_t 284 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; uint32_t 301 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; uint32_t 367 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_FUNC_CNTL; uint32_t 368 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_FUNC_CNTL_2; uint32_t 369 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_FUNC_CNTL_3; uint32_t 370 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_SPREAD_SPECTRUM; uint32_t 371 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 372 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t sclk_value; uint32_t 379 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_AD_FUNC_CNTL; uint32_t 380 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_AD_FUNC_CNTL_2; uint32_t 381 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_DQ_FUNC_CNTL; uint32_t 382 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_DQ_FUNC_CNTL_2; uint32_t 383 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMCLK_PWRMGT_CNTL; uint32_t 384 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vDLL_CNTL; uint32_t 385 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_SS; uint32_t 386 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_SS2; uint32_t 387 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t mclk_value; uint32_t 395 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMCLK_PWRMGT_CNTL; uint32_t 396 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vDLL_CNTL; uint32_t 397 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_FUNC_CNTL; uint32_t 398 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_FUNC_CNTL2; uint32_t 399 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_FUNC_CNTL3; uint32_t 400 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_SS; uint32_t 401 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_SS2; uint32_t 402 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t mclk_value; uint32_t 437 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t aT; uint32_t 438 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t bSP; uint32_t 466 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX]; uint32_t 478 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t lowSMIO[MAX_NO_VREG_STEPS]; uint32_t 700 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t TDPLimit; uint32_t 701 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t NearTDPLimit; uint32_t 702 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t SafePowerLimit; uint32_t 703 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t PowerBoostLimit; uint32_t 709 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_FUNC_CNTL; uint32_t 710 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_FUNC_CNTL_2; uint32_t 711 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_FUNC_CNTL_3; uint32_t 712 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_FUNC_CNTL_4; uint32_t 713 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_SPREAD_SPECTRUM; uint32_t 714 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 715 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t sclk_value; uint32_t 722 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_FUNC_CNTL; uint32_t 723 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_FUNC_CNTL_1; uint32_t 724 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_FUNC_CNTL_2; uint32_t 725 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_AD_FUNC_CNTL; uint32_t 726 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_AD_FUNC_CNTL_2; uint32_t 727 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_DQ_FUNC_CNTL; uint32_t 728 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_DQ_FUNC_CNTL_2; uint32_t 729 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMCLK_PWRMGT_CNTL; uint32_t 730 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vDLL_CNTL; uint32_t 731 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_SS; uint32_t 732 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t vMPLL_SS2; uint32_t 733 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t mclk_value; uint32_t 757 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t aT; uint32_t 758 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t bSP; uint32_t 765 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t powergate_en; uint32_t 770 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t SQPowerThrottle; uint32_t 771 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t SQPowerThrottle_2; uint32_t 772 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t reserved[2]; uint32_t 792 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; uint32_t 806 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; uint32_t 129 drivers/gpu/drm/amd/amdgpu/si_ih.c uint32_t dw[4]; uint32_t 52 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t dpm2Flags; uint32_t 65 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t SwitchDownCounter; uint32_t 66 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t SysScalingFactor; uint32_t 73 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t TDPLimit; uint32_t 74 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t NearTDPLimit; uint32_t 75 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t SafePowerLimit; uint32_t 76 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t PowerBoostLimit; uint32_t 77 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t MinLimitDelta; uint32_t 83 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t EstimatedDGPU_T; uint32_t 84 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t EstimatedDGPU_P; uint32_t 85 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t EstimatedAPU_T; uint32_t 86 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t EstimatedAPU_P; uint32_t 94 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t NearTDPLimitTherm; uint32_t 95 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t NearTDPLimitPAPM; uint32_t 96 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t PlatformPowerLimit; uint32_t 97 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t dGPU_T_Limit; uint32_t 98 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t dGPU_T_Warning; uint32_t 99 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t dGPU_T_Hysteresis; uint32_t 105 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL; uint32_t 106 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL_2; uint32_t 107 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL_3; uint32_t 108 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL_4; uint32_t 109 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vCG_SPLL_SPREAD_SPECTRUM; uint32_t 110 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 111 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t sclk_value; uint32_t 118 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vMPLL_FUNC_CNTL; uint32_t 119 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vMPLL_FUNC_CNTL_1; uint32_t 120 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vMPLL_FUNC_CNTL_2; uint32_t 121 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vMPLL_AD_FUNC_CNTL; uint32_t 122 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vMPLL_DQ_FUNC_CNTL; uint32_t 123 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vMCLK_PWRMGT_CNTL; uint32_t 124 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vDLL_CNTL; uint32_t 125 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vMPLL_SS; uint32_t 126 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t vMPLL_SS2; uint32_t 127 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t mclk_value; uint32_t 151 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t aT; uint32_t 152 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t bSP; uint32_t 163 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t SQPowerThrottle; uint32_t 164 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t SQPowerThrottle_2; uint32_t 165 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t MaxPoweredUpCU; uint32_t 168 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t reserved[2]; uint32_t 202 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX]; uint32_t 215 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS]; uint32_t 266 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t refresh_period; uint32_t 283 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t lkge_lut_V0; uint32_t 284 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t lkge_lut_Vstep; uint32_t 285 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t WinTime; uint32_t 286 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t R_LL; uint32_t 287 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t calculation_repeats; uint32_t 288 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t l2numWin_TDP; uint32_t 289 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t dc_cac; uint32_t 294 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t lkge_lut_T0; uint32_t 295 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t lkge_lut_Tstep; uint32_t 313 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; uint32_t 330 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t mc_arb_dram_timing; uint32_t 331 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t mc_arb_dram_timing2; uint32_t 350 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t freq[256]; uint32_t 351 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t ss[256]; uint32_t 371 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; uint32_t 372 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; uint32_t 373 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t K; uint32_t 374 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t T0; uint32_t 375 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t MaxT; uint32_t 381 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; uint32_t 382 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; uint32_t 383 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint32_t Tthreshold; uint32_t 55 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); uint32_t 82 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg = 0; uint32_t 127 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control) uint32_t 130 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t ret = I2C_OK; uint32_t 131 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg, reg_c_tx_abrt_source; uint32_t 178 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control) uint32_t 181 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t ret = I2C_OK; uint32_t 182 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg_ic_status, reg_c_tx_abrt_source; uint32_t 224 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control, uint32_t 226 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t numbytes, uint32_t i2c_flag) uint32_t 229 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t bytes_sent, reg, ret = 0; uint32_t 324 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control, uint32_t 326 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t numbytes, uint8_t i2c_flag) uint32_t 329 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t bytes_received, ret = I2C_OK; uint32_t 340 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg = 0; uint32_t 402 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg = 0; uint32_t 420 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c const uint32_t IDLE_TIMEOUT = 1024; uint32_t 421 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t timeout_count = 0; uint32_t 422 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity; uint32_t 477 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg_ic_enable_status, reg_ic_enable; uint32_t 543 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c static uint32_t smu_v11_0_i2c_eeprom_read_data(struct i2c_adapter *control, uint32_t 546 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t numbytes) uint32_t 548 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t ret = 0; uint32_t 566 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c static uint32_t smu_v11_0_i2c_eeprom_write_data(struct i2c_adapter *control, uint32_t 569 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t numbytes) uint32_t 571 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t ret; uint32_t 706 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t ret = I2C_OK; uint32_t 314 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t rom_index_offset; uint32_t 315 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t rom_data_offset; uint32_t 371 drivers/gpu/drm/amd/amdgpu/soc15.c static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, uint32_t 374 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t val; uint32_t 388 drivers/gpu/drm/amd/amdgpu/soc15.c static uint32_t soc15_get_register_value(struct amdgpu_device *adev, uint32_t 406 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t i; uint32_t 668 drivers/gpu/drm/amd/amdgpu/soc15.c static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) uint32_t 835 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t perfctr = 0; uint32_t 882 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t perfctr = 0; uint32_t 1347 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t def, data; uint32_t 1381 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t def, data; uint32_t 1410 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t def, data; uint32_t 1426 drivers/gpu/drm/amd/amdgpu/soc15.c uint32_t def, data; uint32_t 46 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t hwip; uint32_t 47 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t inst; uint32_t 48 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t seg; uint32_t 49 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t reg_offset; uint32_t 50 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t reg_value; uint32_t 51 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t se_num; uint32_t 52 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t instance; uint32_t 56 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t hwip; uint32_t 57 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t inst; uint32_t 58 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t seg; uint32_t 59 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t reg_offset; uint32_t 52 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t old_ = 0; \ uint32_t 53 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ uint32_t 54 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t loop = adev->usec_timeout; \ uint32_t 77 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t i = 0; \ uint32_t 78 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t retries = 50000; \ uint32_t 79 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \ uint32_t 80 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \ uint32_t 81 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \ uint32_t 100 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ uint32_t 102 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \ uint32_t 103 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \ uint32_t 104 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \ uint32_t 105 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \ uint32_t 118 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ uint32_t 29 drivers/gpu/drm/amd/amdgpu/ta_ras_if.h #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK) uint32_t 95 drivers/gpu/drm/amd/amdgpu/ta_ras_if.h uint32_t sub_block_index; // mem block. i.e. hbm, sram etc. uint32_t 111 drivers/gpu/drm/amd/amdgpu/ta_ras_if.h uint32_t cmd_id; uint32_t 112 drivers/gpu/drm/amd/amdgpu/ta_ras_if.h uint32_t resp_id; uint32_t 114 drivers/gpu/drm/amd/amdgpu/ta_ras_if.h uint32_t reserved; uint32_t 29 drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK) uint32_t 79 drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h uint32_t status; uint32_t 91 drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h uint32_t num_nodes; uint32_t 96 drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h uint32_t num_nodes; uint32_t 101 drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h uint32_t num_nodes; uint32_t 122 drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h uint32_t cmd_id; uint32_t 123 drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h uint32_t resp_id; uint32_t 125 drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h uint32_t reserved; uint32_t 228 drivers/gpu/drm/amd/amdgpu/tonga_ih.c uint32_t dw[4]; uint32_t 44 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c const uint32_t uint32_t 53 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t umc_instance) uint32_t 55 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t rsmu_umc_index; uint32_t 79 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t umc_reg_offset, uint32_t 82 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; uint32_t 83 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t ecc_err_cnt, ecc_err_cnt_addr; uint32_t 85 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t mc_umc_status_addr; uint32_t 127 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t umc_reg_offset, uint32_t 131 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t mc_umc_status_addr; uint32_t 148 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c struct ras_err_data *err_data, uint32_t umc_reg_offset, uint32_t 149 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t channel_index) uint32_t 165 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t umc_reg_offset, uint32_t channel_index) uint32_t 167 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t lsb, mc_umc_status_addr; uint32_t 214 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t umc_reg_offset, uint32_t channel_index) uint32_t 216 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; uint32_t 217 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c uint32_t ecc_err_cnt_addr; uint32_t 48 drivers/gpu/drm/amd/amdgpu/umc_v6_1.h extern const uint32_t uint32_t 159 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c uint32_t tmp; uint32_t 257 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c uint32_t rb_bufsz; uint32_t 317 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c uint32_t status; uint32_t 383 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c uint32_t i, j; uint32_t 384 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c uint32_t status; uint32_t 478 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c uint32_t tmp = 0; uint32_t 514 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c uint32_t flags) uint32_t 522 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 544 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c uint32_t size; uint32_t 155 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t tmp; uint32_t 256 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t size; uint32_t 295 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t rb_bufsz, tmp; uint32_t 296 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t lmi_swap_cntl; uint32_t 297 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t mp_swap_cntl; uint32_t 362 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t status; uint32_t 495 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t tmp = 0; uint32_t 530 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t flags) uint32_t 540 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 604 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t data1, data3, suvd_flags; uint32_t 650 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t data, data2; uint32_t 698 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c uint32_t data, data1, cgc_flags, suvd_flags; uint32_t 173 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t rptr; uint32_t 208 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 271 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t handle, uint32_t 470 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t tmp; uint32_t 582 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t size; uint32_t 702 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t rb_bufsz, tmp; uint32_t 703 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t lmi_swap_cntl; uint32_t 704 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t mp_swap_cntl; uint32_t 778 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t status; uint32_t 958 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t tmp = 0; uint32_t 994 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t flags) uint32_t 1020 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t flags) uint32_t 1032 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t reg, uint32_t val) uint32_t 1059 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 1074 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 1088 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 1250 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t data1, data3; uint32_t 1305 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t data, data2; uint32_t 1354 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t data, data1, cgc_flags, suvd_flags; uint32_t 178 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t rptr; uint32_t 216 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 278 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, uint32_t 524 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t tmp; uint32_t 652 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); uint32_t 653 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t offset; uint32_t 711 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t data = 0, loop; uint32_t 714 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t size; uint32_t 767 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t offset, size, tmp; uint32_t 768 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t table_size = 0; uint32_t 773 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t *init_table = adev->virt.mm_table.cpu_addr; uint32_t 858 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | uint32_t 869 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | uint32_t 933 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t rb_bufsz, tmp; uint32_t 934 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t lmi_swap_cntl; uint32_t 935 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t mp_swap_cntl; uint32_t 1024 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t status; uint32_t 1227 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t tmp = 0; uint32_t 1261 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t ib_idx) uint32_t 1272 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); uint32_t 1293 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t flags) uint32_t 1324 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t flags) uint32_t 1336 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg, uint32_t val) uint32_t 1351 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 1352 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t val, uint32_t mask) uint32_t 1374 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t data0, data1, mask; uint32_t 1385 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 1404 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg, uint32_t val, uint32_t 1405 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t mask) uint32_t 1426 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg, uint32_t val) uint32_t 1544 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t ip_instance; uint32_t 1583 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t data, data1, data2, suvd_flags; uint32_t 1639 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t data, data1, cgc_flags, suvd_flags; uint32_t 105 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c uint32_t status = RREG32(mmVCE_LMI_STATUS); uint32_t 122 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c uint32_t status = RREG32(mmVCE_STATUS); uint32_t 170 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c uint32_t size, offset; uint32_t 522 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c uint32_t val = 0; uint32_t 241 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c uint32_t status = RREG32(mmVCE_STATUS); uint32_t 526 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c uint32_t offset, size; uint32_t 706 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c uint32_t val = 0; uint32_t 758 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c uint32_t data = RREG32(mmVCE_CLOCK_GATING_A); uint32_t 837 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c uint32_t flags) uint32_t 862 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c uint32_t seq = ring->fence_drv.sync_seq; uint32_t 130 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t status = uint32_t 155 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t data = 0, loop; uint32_t 158 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t size; uint32_t 207 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t offset, size; uint32_t 208 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t table_size = 0; uint32_t 213 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t *init_table = adev->virt.mm_table.cpu_addr; uint32_t 249 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t low = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_lo; uint32_t 250 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t hi = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_hi; uint32_t 604 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t offset, size; uint32_t 911 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A); uint32_t 952 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c struct amdgpu_ib *ib, uint32_t flags) uint32_t 980 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c static void vce_v4_0_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 981 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t val, uint32_t mask) uint32_t 1002 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t reg, uint32_t val) uint32_t 1014 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t val = 0; uint32_t 50 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr); uint32_t 296 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); uint32_t 297 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t offset; uint32_t 363 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); uint32_t 364 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t offset; uint32_t 443 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t data; uint32_t 570 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t data = 0; uint32_t 635 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg_data = 0; uint32_t 689 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t data = 0; uint32_t 735 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t data = 0; uint32_t 785 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t rb_bufsz, tmp; uint32_t 786 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t lmi_swap_cntl; uint32_t 863 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t status; uint32_t 974 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t rb_bufsz, tmp; uint32_t 975 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t lmi_swap_cntl; uint32_t 1183 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t tmp; uint32_t 1230 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg_data = 0; uint32_t 1231 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg_data2 = 0; uint32_t 1519 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t flags) uint32_t 1540 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val, uint32_t 1541 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t mask) uint32_t 1563 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t data0, data1, mask; uint32_t 1575 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val) uint32_t 1679 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t flags) uint32_t 1691 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val, uint32_t 1692 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t mask) uint32_t 1713 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val) uint32_t 1884 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t flags) uint32_t 1935 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val, uint32_t 1936 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t mask) uint32_t 1939 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg_offset = (reg << 2); uint32_t 1968 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t data0, data1, mask; uint32_t 1980 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val) uint32_t 1983 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg_offset = (reg << 2); uint32_t 2000 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 2012 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) uint32_t 2027 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr) uint32_t 2031 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, reg_offset, val, mask, i; uint32_t 2139 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 365 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); uint32_t 366 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t offset; uint32_t 410 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); uint32_t 411 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t offset; uint32_t 511 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t data; uint32_t 614 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg_data = 0; uint32_t 669 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t tmp; uint32_t 737 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t tmp; uint32_t 792 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t data = 0; uint32_t 843 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t data = 0; uint32_t 890 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t data = 0; uint32_t 931 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t rb_bufsz, tmp; uint32_t 942 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->vcn.dpg_sram_curr_addr = (uint32_t*)adev->vcn.dpg_sram_cpu_addr; uint32_t 1017 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c (uint32_t)((uintptr_t)adev->vcn.dpg_sram_curr_addr - uint32_t 1057 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t rb_bufsz, tmp; uint32_t 1058 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t lmi_swap_cntl; uint32_t 1146 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t status; uint32_t 1230 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t tmp; uint32_t 1261 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t tmp; uint32_t 1335 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg_data = 0; uint32_t 1522 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 1583 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t flags) uint32_t 1599 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 1600 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t val, uint32_t mask) uint32_t 1622 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t data0, data1, mask; uint32_t 1634 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg, uint32_t val) uint32_t 1754 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t flags) uint32_t 1765 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 1766 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t val, uint32_t mask) uint32_t 1786 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) uint32_t 1939 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t flags) uint32_t 1987 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 1988 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t val, uint32_t mask) uint32_t 1990 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg_offset = (reg << 2); uint32_t 2018 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t data0, data1, mask; uint32_t 2029 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) uint32_t 2031 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg_offset = (reg << 2); uint32_t 2047 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) uint32_t 2098 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t tmp = 0; uint32_t 29 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); uint32_t 33 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h struct amdgpu_ib *ib, uint32_t flags); uint32_t 34 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 35 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t val, uint32_t mask); uint32_t 39 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t reg, uint32_t val); uint32_t 45 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h struct amdgpu_ib *ib, uint32_t flags); uint32_t 46 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 47 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t val, uint32_t mask); uint32_t 50 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); uint32_t 57 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h struct amdgpu_ib *ib, uint32_t flags); uint32_t 58 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t 59 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t val, uint32_t mask); uint32_t 62 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); uint32_t 63 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count); uint32_t 378 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); uint32_t 379 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t offset; uint32_t 431 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t data; uint32_t 549 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t data = 0; uint32_t 612 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t tmp; uint32_t 684 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t tmp; uint32_t 714 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t rb_bufsz, tmp; uint32_t 802 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t status; uint32_t 888 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t tmp; uint32_t 1330 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c uint32_t ip_instance; uint32_t 166 drivers/gpu/drm/amd/amdgpu/vega10_ih.c static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) uint32_t 189 drivers/gpu/drm/amd/amdgpu/vega10_ih.c static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) uint32_t 441 drivers/gpu/drm/amd/amdgpu/vega10_ih.c uint32_t dw[8]; uint32_t 479 drivers/gpu/drm/amd/amdgpu/vega10_ih.c uint32_t reg_rptr = 0; uint32_t 480 drivers/gpu/drm/amd/amdgpu/vega10_ih.c uint32_t v = 0; uint32_t 481 drivers/gpu/drm/amd/amdgpu/vega10_ih.c uint32_t i = 0; uint32_t 541 drivers/gpu/drm/amd/amdgpu/vega10_ih.c uint32_t wptr = cpu_to_le32(entry->src_data[0]); uint32_t 33 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c uint32_t i; uint32_t 35 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 36 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); uint32_t 37 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); uint32_t 38 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); uint32_t 39 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); uint32_t 40 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); uint32_t 41 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); uint32_t 42 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); uint32_t 43 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); uint32_t 44 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); uint32_t 45 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); uint32_t 46 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); uint32_t 47 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); uint32_t 48 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); uint32_t 49 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); uint32_t 50 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); uint32_t 51 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i])); uint32_t 52 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i])); uint32_t 53 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); uint32_t 54 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); uint32_t 33 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c uint32_t i; uint32_t 35 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); uint32_t 36 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); uint32_t 37 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); uint32_t 38 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); uint32_t 39 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); uint32_t 40 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); uint32_t 41 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); uint32_t 42 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); uint32_t 43 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); uint32_t 44 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); uint32_t 45 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); uint32_t 46 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); uint32_t 47 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); uint32_t 48 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); uint32_t 49 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); uint32_t 50 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); uint32_t 51 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); uint32_t 52 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); uint32_t 53 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i])); uint32_t 54 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i])); uint32_t 453 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t reg = 0; uint32_t 551 drivers/gpu/drm/amd/amdgpu/vi.c static uint32_t vi_get_register_value(struct amdgpu_device *adev, uint32_t 556 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t val; uint32_t 650 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t i; uint32_t 730 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t tmp; uint32_t 899 drivers/gpu/drm/amd/amdgpu/vi.c static uint32_t vi_get_rev_id(struct amdgpu_device *adev) uint32_t 954 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t perfctr = 0; uint32_t 1360 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t temp, data; uint32_t 1380 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t temp, data; uint32_t 1396 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t temp, data; uint32_t 1412 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t temp, data; uint32_t 1429 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t temp, data; uint32_t 1447 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t msg_id, pp_state = 0; uint32_t 1448 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t pp_support_state = 0; uint32_t 29 drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c const uint32_t *ih_ring_entry, uint32_t 30 drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c uint32_t *patched_ihre, uint32_t 85 drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c const uint32_t *ih_ring_entry) uint32_t 89 drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c uint32_t context_id = ihre->data & 0xfffffff; uint32_t 29 drivers/gpu/drm/amd/amdkfd/cik_int.h uint32_t source_id; uint32_t 30 drivers/gpu/drm/amd/amdkfd/cik_int.h uint32_t data; uint32_t 31 drivers/gpu/drm/amd/amdkfd/cik_int.h uint32_t ring_id; uint32_t 32 drivers/gpu/drm/amd/amdkfd/cik_int.h uint32_t reserved; uint32_t 23 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h static const uint32_t cwsr_trap_gfx8_hex[] = { uint32_t 276 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h static const uint32_t cwsr_trap_gfx9_hex[] = { uint32_t 682 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h static const uint32_t cwsr_trap_gfx10_hex[] = { uint32_t 1073 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h static const uint32_t cwsr_trap_arcturus_hex[] = { uint32_t 173 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c sizeof(uint32_t))) { uint32_t 179 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c sizeof(uint32_t))) { uint32_t 186 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c sizeof(uint32_t))) { uint32_t 193 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c sizeof(uint32_t))) { uint32_t 203 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c q_properties->read_ptr = (uint32_t *) args->read_pointer_address; uint32_t 204 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c q_properties->write_ptr = (uint32_t *) args->write_pointer_address; uint32_t 400 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr; uint32_t 401 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32); uint32_t 422 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c cu_mask_size = sizeof(uint32_t) * (max_num_cus/32); uint32_t 682 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx])); uint32_t 749 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c uint32_t computed_buff_size; uint32_t 801 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c wac_info.trapId = *((uint32_t *)(&args_buff[args_idx])); uint32_t 805 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c *((uint32_t *)(&args_buff[args_idx])); uint32_t 913 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c uint32_t nodes = 0; uint32_t 1164 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c args->num_tile_configs * sizeof(uint32_t)); uint32_t 1175 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c args->num_macro_tile_configs * sizeof(uint32_t)); uint32_t 1257 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c uint32_t flags = args->flags; uint32_t 1382 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c uint32_t *devices_arr = NULL; uint32_t 1491 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c uint32_t *devices_arr = NULL, i; uint32_t 1577 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c uint32_t flags; uint32_t 36 drivers/gpu/drm/amd/amdkfd/kfd_crat.c static uint32_t gpu_processor_id_low = 0x80001000; uint32_t 53 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t cache_size; uint32_t 54 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t cache_level; uint32_t 55 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t flags; uint32_t 59 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t num_cu_shared; uint32_t 198 drivers/gpu/drm/amd/amdkfd/kfd_crat.c find_subtype_mem(uint32_t heap_type, uint32_t flags, uint32_t width, uint32_t 220 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t heap_type; uint32_t 222 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t flags = 0; uint32_t 223 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t width; uint32_t 289 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t id; uint32_t 290 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t total_num_of_cu; uint32_t 355 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t id_from; uint32_t 356 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t id_to; uint32_t 483 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t proximity_domain) uint32_t 491 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t image_len; uint32_t 880 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t *num_entries, uint32_t 938 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t entries = 0; uint32_t 1036 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t proximity_domain, uint32_t 1074 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t proximity_domain) uint32_t 1109 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t proximity_domain_from, uint32_t 1110 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t proximity_domain_to) uint32_t 1139 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t proximity_domain) uint32_t 1148 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t total_num_of_cu; uint32_t 1151 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t nid = 0; uint32_t 1339 drivers/gpu/drm/amd/amdkfd/kfd_crat.c uint32_t proximity_domain) uint32_t 52 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t signature; uint32_t 53 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t length; uint32_t 58 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t oem_revision; uint32_t 59 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t creator_id; uint32_t 60 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t creator_revision; uint32_t 61 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t total_entries; uint32_t 100 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t flags; uint32_t 101 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t proximity_domain; uint32_t 102 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t processor_id_low; uint32_t 133 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t flags; uint32_t 134 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t proximity_domain; uint32_t 135 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t base_addr_low; uint32_t 136 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t base_addr_high; uint32_t 137 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t length_low; uint32_t 138 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t length_high; uint32_t 139 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t width; uint32_t 160 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t flags; uint32_t 161 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t processor_id_low; uint32_t 163 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t cache_size; uint32_t 189 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t flags; uint32_t 190 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t processor_id_low; uint32_t 192 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t tlb_level; uint32_t 220 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t flags; uint32_t 221 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t processor_id_low; uint32_t 223 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t apu_size; uint32_t 266 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t flags; uint32_t 267 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t proximity_domain_from; uint32_t 268 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t proximity_domain_to; uint32_t 272 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t minimum_latency; uint32_t 273 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t maximum_latency; uint32_t 274 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t minimum_bandwidth_mbs; uint32_t 275 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t maximum_bandwidth_mbs; uint32_t 276 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t recommended_transfer_size; uint32_t 291 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t flags; uint32_t 301 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t signature; uint32_t 302 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t length; uint32_t 307 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t oem_revision; uint32_t 308 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t creator_id; uint32_t 309 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t creator_revision; uint32_t 310 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t total_entries; uint32_t 322 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t proximity_domain); uint32_t 325 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint32_t proximity_domain); uint32_t 49 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c uint32_t *packet_buff, size_t size_in_bytes) uint32_t 76 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c pq_packets_size_in_bytes / sizeof(uint32_t), uint32_t 245 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c (uint32_t) (adw_info->watch_mask[index] & uint32_t 258 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c cntl->bitfields.vmid = (uint32_t) vmid; uint32_t 344 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c uint32_t *packet_buff_uint; uint32_t 591 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c uint32_t *packet_buff_uint; uint32_t 85 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t wave_id:4; uint32_t 86 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t simd_id:2; uint32_t 87 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t thread_id:6; uint32_t 88 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t:1; uint32_t 89 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t force_read:1; uint32_t 90 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t read_timeout:1; uint32_t 91 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t unindexed:1; uint32_t 92 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t index:16; uint32_t 95 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t u32All; uint32_t 102 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t data:32; uint32_t 104 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t u32All; uint32_t 111 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t cmd:3; uint32_t 112 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t:1; uint32_t 113 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t mode:3; uint32_t 114 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t check_vmid:1; uint32_t 115 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t trap_id:3; uint32_t 116 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t:5; uint32_t 117 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t wave_id:4; uint32_t 118 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t simd_id:2; uint32_t 119 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t:2; uint32_t 120 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t queue_id:3; uint32_t 121 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t:1; uint32_t 122 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t vm_id:4; uint32_t 124 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t u32All; uint32_t 131 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t data:32; uint32_t 133 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t u32All; uint32_t 140 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t instance_index:8; uint32_t 141 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t sh_index:8; uint32_t 142 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t se_index:8; uint32_t 143 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t:5; uint32_t 144 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t sh_broadcast_writes:1; uint32_t 145 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t instance_broadcast_writes:1; uint32_t 146 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t se_broadcast_writes:1; uint32_t 148 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t u32All; uint32_t 155 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t addr:16; uint32_t 156 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t:16; uint32_t 159 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t u32All; uint32_t 166 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t:6; uint32_t 167 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t addr:26; uint32_t 169 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t u32All; uint32_t 182 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t low_part; uint32_t 183 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t high_part; uint32_t 198 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t mask:24; uint32_t 199 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t vmid:4; uint32_t 200 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t atc:1; uint32_t 201 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t mode:2; uint32_t 202 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t valid:1; uint32_t 204 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t u32All; uint32_t 79 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t UserData:8; /* user data */ uint32_t 80 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t ShaderArray:1; /* Shader array */ uint32_t 81 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t Priv:1; /* Privileged */ uint32_t 82 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t Reserved0:4; /* Reserved, should be 0 */ uint32_t 83 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t WaveId:4; /* wave id */ uint32_t 84 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t SIMD:2; /* SIMD id */ uint32_t 85 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t HSACU:4; /* Compute unit */ uint32_t 86 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t ShaderEngine:2;/* Shader engine */ uint32_t 87 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t MessageType:2; /* see HSA_DBG_WAVEMSG_TYPE */ uint32_t 88 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t Reserved1:4; /* Reserved, should be 0 */ uint32_t 90 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t Value; uint32_t 92 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t Reserved2; uint32_t 180 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t NodeId; /* F-NUMA node that contains the device */ uint32_t 208 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t HWData3; uint32_t 215 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t NodeId; uint32_t 223 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t EventId; uint32_t 242 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t num_watch_points; uint32_t 247 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h uint32_t trapId; uint32_t 42 drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c uint32_t gpu_id; uint32_t 50 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 69 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 87 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 8 * sizeof(uint32_t), uint32_t 107 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 125 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 143 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 161 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 180 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 198 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 216 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 234 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 252 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 4 * sizeof(uint32_t), uint32_t 270 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 8 * sizeof(uint32_t), uint32_t 288 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 8 * sizeof(uint32_t), uint32_t 306 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 8 * sizeof(uint32_t), uint32_t 324 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 8 * sizeof(uint32_t), uint32_t 342 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 8 * sizeof(uint32_t), uint32_t 360 drivers/gpu/drm/amd/amdkfd/kfd_device.c .ih_ring_entry_size = 8 * sizeof(uint32_t), uint32_t 854 drivers/gpu/drm/amd/amdkfd/kfd_device.c uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; uint32_t 1009 drivers/gpu/drm/amd/amdkfd/kfd_device.c static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, uint32_t 1013 drivers/gpu/drm/amd/amdkfd/kfd_device.c return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); uint32_t 47 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint32_t filter_param); uint32_t 50 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint32_t filter_param); uint32_t 151 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint32_t *idx_offset = uint32_t 238 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); uint32_t 243 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c qpd->ib_base, (uint32_t *)qpd->ib_kaddr, uint32_t 244 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c pmf->release_mem_size / sizeof(uint32_t)); uint32_t 1284 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint32_t filter_param) uint32_t 1322 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint32_t filter_param) uint32_t 1680 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * uint32_t 1862 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint32_t (*dump)[2], uint32_t n_regs) uint32_t 1864 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint32_t i, count; uint32_t 1868 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { uint32_t 1885 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint32_t (*dump)[2], n_regs; uint32_t 63 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) uint32_t 97 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c uint32_t default_mtype; uint32_t 98 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c uint32_t ape1_mtype; uint32_t 183 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT); uint32_t 42 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd) uint32_t 44 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c uint32_t shared_base = pdd->lds_base >> 48; uint32_t 45 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c uint32_t private_base = pdd->scratch_base >> 48; uint32_t 43 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd) uint32_t 45 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c uint32_t shared_base = pdd->lds_base >> 48; uint32_t 46 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c uint32_t private_base = pdd->scratch_base >> 48; uint32_t 69 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) uint32_t 104 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c uint32_t default_mtype; uint32_t 105 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c uint32_t ape1_mtype; uint32_t 133 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c uint32_t default_mtype; uint32_t 134 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c uint32_t ape1_mtype; uint32_t 231 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT); uint32_t 128 drivers/gpu/drm/amd/amdkfd/kfd_events.c static struct kfd_event *lookup_event_by_id(struct kfd_process *p, uint32_t id) uint32_t 151 drivers/gpu/drm/amd/amdkfd/kfd_events.c struct kfd_process *p, uint32_t id, uint32_t bits) uint32_t 220 drivers/gpu/drm/amd/amdkfd/kfd_events.c (uint32_t)KFD_LAST_NONSIGNAL_EVENT_ID + 1, uint32_t 258 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t id; uint32_t 323 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t event_type, bool auto_reset, uint32_t node_id, uint32_t 324 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t *event_id, uint32_t *event_trigger_data, uint32_t 325 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint64_t *event_page_offset, uint32_t *event_slot_index) uint32_t 371 drivers/gpu/drm/amd/amdkfd/kfd_events.c int kfd_event_destroy(struct kfd_process *p, uint32_t event_id) uint32_t 407 drivers/gpu/drm/amd/amdkfd/kfd_events.c int kfd_set_event(struct kfd_process *p, uint32_t event_id) uint32_t 431 drivers/gpu/drm/amd/amdkfd/kfd_events.c int kfd_reset_event(struct kfd_process *p, uint32_t event_id) uint32_t 464 drivers/gpu/drm/amd/amdkfd/kfd_events.c void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, uint32_t 465 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t valid_id_bits) uint32_t 493 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t id; uint32_t 527 drivers/gpu/drm/amd/amdkfd/kfd_events.c static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events) uint32_t 530 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t i; uint32_t 546 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t event_id) uint32_t 581 drivers/gpu/drm/amd/amdkfd/kfd_events.c static uint32_t test_event_condition(bool all, uint32_t num_events, uint32_t 584 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t i; uint32_t 585 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t activated_count = 0; uint32_t 607 drivers/gpu/drm/amd/amdkfd/kfd_events.c static int copy_signaled_event_data(uint32_t num_events, uint32_t 615 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t i; uint32_t 635 drivers/gpu/drm/amd/amdkfd/kfd_events.c static long user_timeout_to_jiffies(uint32_t user_timeout_ms) uint32_t 648 drivers/gpu/drm/amd/amdkfd/kfd_events.c user_timeout_ms = min_t(uint32_t, user_timeout_ms, 0x7FFFFFFF); uint32_t 653 drivers/gpu/drm/amd/amdkfd/kfd_events.c static void free_waiters(uint32_t num_events, struct kfd_event_waiter *waiters) uint32_t 655 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t i; uint32_t 666 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t num_events, void __user *data, uint32_t 667 drivers/gpu/drm/amd/amdkfd/kfd_events.c bool all, uint32_t user_timeout_ms, uint32_t 668 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t *wait_result) uint32_t 672 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t i; uint32_t 836 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t id; uint32_t 978 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t id; uint32_t 1018 drivers/gpu/drm/amd/amdkfd/kfd_events.c uint32_t id, idx; uint32_t 82 drivers/gpu/drm/amd/amdkfd/kfd_events.h extern void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, uint32_t 83 drivers/gpu/drm/amd/amdkfd/kfd_events.h uint32_t valid_id_bits); uint32_t 29 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c const uint32_t *ih_ring_entry, uint32_t 30 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c uint32_t *patched_ihre, uint32_t 34 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c const uint32_t *data = ih_ring_entry; uint32_t 51 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c const uint32_t pasid_mask = 0xffff; uint32_t 88 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c const uint32_t *ih_ring_entry) uint32_t 91 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c uint32_t context_id; uint32_t 147 drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c uint32_t ih_ring_entry[KFD_MAX_RING_ENTRY_SIZE]; uint32_t 160 drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c const uint32_t *ih_ring_entry, uint32_t 161 drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c uint32_t *patched_ihre, bool *flag) uint32_t 123 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c prop.read_ptr = (uint32_t *) kq->rptr_gpu_addr; uint32_t 124 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c prop.write_ptr = (uint32_t *) kq->wptr_gpu_addr; uint32_t 154 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c retval = kfd_gtt_sa_allocate(dev, sizeof(uint32_t), uint32_t 215 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c uint32_t wptr, rptr; uint32_t 365 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c uint32_t *buffer, i; uint32_t 76 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h uint32_t pending_wptr; uint32_t 80 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h uint32_t *rptr_kernel; uint32_t 85 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h uint32_t *wptr_kernel; uint32_t 90 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h uint32_t *pq_kernel_addr; uint32_t 93 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h uint32_t *eop_kernel_addr; uint32_t 72 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c uint32_t *buffer, struct qcm_process_device *qpd) uint32_t 113 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c static int pm_runlist_v10(struct packet_manager *pm, uint32_t *buffer, uint32_t 151 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c static int pm_map_queues_v10(struct packet_manager *pm, uint32_t *buffer, uint32_t 209 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c static int pm_unmap_queues_v10(struct packet_manager *pm, uint32_t *buffer, uint32_t 212 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c uint32_t filter_param, bool reset, uint32_t 275 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c static int pm_query_status_v10(struct packet_manager *pm, uint32_t *buffer, uint32_t 276 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c uint64_t fence_address, uint32_t fence_value) uint32_t 302 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c static int pm_release_mem_v10(uint64_t gpu_addr, uint32_t *buffer) uint32_t 71 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c uint32_t *buffer, struct qcm_process_device *qpd) uint32_t 109 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer, uint32_t 147 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c static int pm_set_resources_v9(struct packet_manager *pm, uint32_t *buffer, uint32_t 175 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer, uint32_t 242 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer, uint32_t 245 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c uint32_t filter_param, bool reset, uint32_t 318 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer, uint32_t 319 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c uint64_t fence_address, uint32_t fence_value) uint32_t 345 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c static int pm_release_mem_v9(uint64_t gpu_addr, uint32_t *buffer) uint32_t 82 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c static int pm_map_process_vi(struct packet_manager *pm, uint32_t *buffer, uint32_t 115 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c static int pm_runlist_vi(struct packet_manager *pm, uint32_t *buffer, uint32_t 154 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer, uint32_t 182 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c static int pm_map_queues_vi(struct packet_manager *pm, uint32_t *buffer, uint32_t 240 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c static int pm_unmap_queues_vi(struct packet_manager *pm, uint32_t *buffer, uint32_t 243 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c uint32_t filter_param, bool reset, uint32_t 306 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c static int pm_query_status_vi(struct packet_manager *pm, uint32_t *buffer, uint32_t 307 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c uint64_t fence_address, uint32_t fence_value) uint32_t 331 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c static int pm_release_mem_vi(uint64_t gpu_addr, uint32_t *buffer) uint32_t 83 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t) uint32_t 97 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c const uint32_t *cu_mask, uint32_t cu_mask_count, uint32_t 98 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c uint32_t *se_mask) uint32_t 101 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c uint32_t cu_per_se[KFD_MAX_NUM_SE] = {0}; uint32_t 77 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h uint32_t pipe_id, uint32_t queue_id, uint32_t 86 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h unsigned int timeout, uint32_t pipe_id, uint32_t 87 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h uint32_t queue_id); uint32_t 93 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h uint64_t queue_address, uint32_t pipe_id, uint32_t 94 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h uint32_t queue_id); uint32_t 107 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h uint32_t mqd_size; uint32_t 119 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h const uint32_t *cu_mask, uint32_t cu_mask_count, uint32_t 120 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h uint32_t *se_mask); uint32_t 48 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ uint32_t 165 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t 166 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint32_t queue_id, struct queue_properties *p, uint32_t 170 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); uint32_t 171 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); uint32_t 174 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c (uint32_t __user *)p->write_ptr, uint32_t 179 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint32_t pipe_id, uint32_t queue_id, uint32_t 183 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c (uint32_t __user *)p->write_ptr, uint32_t 264 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c unsigned int timeout, uint32_t pipe_id, uint32_t 265 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint32_t queue_id) uint32_t 277 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c unsigned int timeout, uint32_t pipe_id, uint32_t 278 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint32_t queue_id) uint32_t 284 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint64_t queue_address, uint32_t pipe_id, uint32_t 285 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint32_t queue_id) uint32_t 294 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint64_t queue_address, uint32_t pipe_id, uint32_t 295 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c uint32_t queue_id) uint32_t 48 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ uint32_t 162 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint32_t pipe_id, uint32_t queue_id, uint32_t 167 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); uint32_t 170 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c (uint32_t __user *)p->write_ptr, uint32_t 242 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c unsigned int timeout, uint32_t pipe_id, uint32_t 243 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint32_t queue_id) uint32_t 264 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint64_t queue_address, uint32_t pipe_id, uint32_t 265 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint32_t queue_id) uint32_t 339 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint32_t pipe_id, uint32_t queue_id, uint32_t 343 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c (uint32_t __user *)p->write_ptr, uint32_t 385 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c unsigned int timeout, uint32_t pipe_id, uint32_t 386 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint32_t queue_id) uint32_t 392 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint64_t queue_address, uint32_t pipe_id, uint32_t 393 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c uint32_t queue_id) uint32_t 49 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; uint32_t 183 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint32_t pipe_id, uint32_t queue_id, uint32_t 187 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); uint32_t 190 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c (uint32_t __user *)p->write_ptr, uint32_t 261 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c unsigned int timeout, uint32_t pipe_id, uint32_t 262 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint32_t queue_id) uint32_t 283 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint64_t queue_address, uint32_t pipe_id, uint32_t 284 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint32_t queue_id) uint32_t 357 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint32_t pipe_id, uint32_t queue_id, uint32_t 361 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c (uint32_t __user *)p->write_ptr, uint32_t 399 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c unsigned int timeout, uint32_t pipe_id, uint32_t 400 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint32_t queue_id) uint32_t 406 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint64_t queue_address, uint32_t pipe_id, uint32_t 407 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c uint32_t queue_id) uint32_t 51 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ uint32_t 157 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint32_t pipe_id, uint32_t queue_id, uint32_t 161 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); uint32_t 162 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); uint32_t 165 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c (uint32_t __user *)p->write_ptr, uint32_t 254 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c unsigned int timeout, uint32_t pipe_id, uint32_t 255 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint32_t queue_id) uint32_t 269 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint64_t queue_address, uint32_t pipe_id, uint32_t 270 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint32_t queue_id) uint32_t 340 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint32_t pipe_id, uint32_t queue_id, uint32_t 344 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c (uint32_t __user *)p->write_ptr, uint32_t 381 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c unsigned int timeout, uint32_t pipe_id, uint32_t 382 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint32_t queue_id) uint32_t 388 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint64_t queue_address, uint32_t pipe_id, uint32_t 389 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c uint32_t queue_id) uint32_t 33 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c unsigned int temp = *wptr + increment_bytes / sizeof(uint32_t); uint32_t 35 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c WARN((temp * sizeof(uint32_t)) > buffer_size_bytes, uint32_t 211 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c alloc_size_bytes / sizeof(uint32_t), uint32_t 216 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c for (i = 0; i < alloc_size_bytes / sizeof(uint32_t); i++) uint32_t 275 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c uint32_t *buffer, size; uint32_t 281 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c size / sizeof(uint32_t), uint32_t 304 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c uint32_t *rl_buffer; uint32_t 315 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c packet_size_dwords = pm->pmf->runlist_size / sizeof(uint32_t); uint32_t 324 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c rl_ib_size / sizeof(uint32_t), false); uint32_t 344 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c uint32_t fence_value) uint32_t 346 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c uint32_t *buffer, size; uint32_t 355 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c size / sizeof(uint32_t), (unsigned int **)&buffer); uint32_t 375 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c uint32_t filter_param, bool reset, uint32_t 378 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c uint32_t *buffer, size; uint32_t 384 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c size / sizeof(uint32_t), (unsigned int **)&buffer); uint32_t 436 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c uint32_t *buffer, size; uint32_t 442 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c size / sizeof(uint32_t), (unsigned int **)&buffer); uint32_t 32 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved1:8; uint32_t 34 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t opcode:8; uint32_t 36 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t count:14; uint32_t 38 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t type:2; uint32_t 40 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t u32all; uint32_t 53 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t ordinal1; uint32_t 58 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t pasid:16; uint32_t 59 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved1:8; uint32_t 60 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t diq_enable:1; uint32_t 61 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t process_quantum:7; uint32_t 63 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t ordinal2; uint32_t 68 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t page_table_base:28; uint32_t 69 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved3:4; uint32_t 71 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t ordinal3; uint32_t 74 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t sh_mem_bases; uint32_t 75 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t sh_mem_ape1_base; uint32_t 76 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t sh_mem_ape1_limit; uint32_t 77 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t sh_mem_config; uint32_t 78 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t gds_addr_lo; uint32_t 79 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t gds_addr_hi; uint32_t 83 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t num_gws:6; uint32_t 84 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved4:2; uint32_t 85 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t num_oac:4; uint32_t 86 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved5:4; uint32_t 87 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t gds_size:6; uint32_t 88 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t num_queues:10; uint32_t 90 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t ordinal10; uint32_t 102 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t ordinal1; uint32_t 107 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t pasid:16; uint32_t 108 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved1:8; uint32_t 109 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t diq_enable:1; uint32_t 110 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t process_quantum:7; uint32_t 112 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t ordinal2; uint32_t 117 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t page_table_base:28; uint32_t 118 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved2:4; uint32_t 120 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t ordinal3; uint32_t 123 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved3; uint32_t 124 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t sh_mem_bases; uint32_t 125 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t sh_mem_config; uint32_t 126 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t sh_mem_ape1_base; uint32_t 127 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t sh_mem_ape1_limit; uint32_t 128 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t sh_hidden_private_base_vmid; uint32_t 129 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved4; uint32_t 130 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved5; uint32_t 131 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t gds_addr_lo; uint32_t 132 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t gds_addr_hi; uint32_t 136 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t num_gws:6; uint32_t 137 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved6:2; uint32_t 138 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t num_oac:4; uint32_t 139 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t reserved7:4; uint32_t 140 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t gds_size:6; uint32_t 141 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t num_queues:10; uint32_t 143 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t ordinal14; uint32_t 146 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t completion_signal_lo32; uint32_t 147 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h uint32_t completion_signal_hi32; uint32_t 31 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved1 : 8; /* < reserved */ uint32_t 32 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t opcode : 8; /* < IT opcode */ uint32_t 33 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t count : 14;/* < number of DWORDs - 1 in the uint32_t 36 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t type : 2; /* < packet identifier. uint32_t 40 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t u32All; uint32_t 58 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal1; uint32_t 63 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t vmid_mask:16; uint32_t 64 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t unmap_latency:8; uint32_t 65 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved1:5; uint32_t 68 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal2; uint32_t 71 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t queue_mask_lo; uint32_t 72 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t queue_mask_hi; uint32_t 73 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t gws_mask_lo; uint32_t 74 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t gws_mask_hi; uint32_t 78 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t oac_mask:16; uint32_t 79 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved2:16; uint32_t 81 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal7; uint32_t 86 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t gds_heap_base:10; uint32_t 87 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved3:1; uint32_t 88 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t gds_heap_size:10; uint32_t 89 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved4:11; uint32_t 91 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal8; uint32_t 105 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal1; uint32_t 110 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved1:2; uint32_t 111 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ib_base_lo:30; uint32_t 113 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal2; uint32_t 116 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ib_base_hi; uint32_t 120 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ib_size:20; uint32_t 121 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t chain:1; uint32_t 122 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t offload_polling:1; uint32_t 123 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t chained_runlist_idle_disable:1; uint32_t 124 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t valid:1; uint32_t 125 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t process_cnt:4; uint32_t 126 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved3:4; uint32_t 128 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal4; uint32_t 142 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal1; uint32_t 147 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t pasid:16; uint32_t 148 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved1:8; uint32_t 149 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t diq_enable:1; uint32_t 150 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t process_quantum:7; uint32_t 152 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal2; uint32_t 155 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t vm_context_page_table_base_addr_lo32; uint32_t 157 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t vm_context_page_table_base_addr_hi32; uint32_t 159 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t sh_mem_bases; uint32_t 161 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t sh_mem_config; uint32_t 163 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t sq_shader_tba_lo; uint32_t 165 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t sq_shader_tba_hi; uint32_t 167 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t sq_shader_tma_lo; uint32_t 169 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t sq_shader_tma_hi; uint32_t 171 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved6; uint32_t 173 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t gds_addr_lo; uint32_t 175 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t gds_addr_hi; uint32_t 179 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t num_gws:7; uint32_t 180 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t sdma_enable:1; uint32_t 181 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t num_oac:4; uint32_t 182 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t gds_size_hi:4; uint32_t 183 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t gds_size:6; uint32_t 184 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t num_queues:10; uint32_t 186 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal14; uint32_t 189 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t completion_signal_lo; uint32_t 191 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t completion_signal_hi; uint32_t 205 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal1; uint32_t 208 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved1; uint32_t 210 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t vm_context_cntl; uint32_t 212 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved2; uint32_t 214 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t vm_context_page_table_end_addr_lo32; uint32_t 216 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t vm_context_page_table_end_addr_hi32; uint32_t 218 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t vm_context_page_table_start_addr_lo32; uint32_t 220 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t vm_context_page_table_start_addr_hi32; uint32_t 222 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved3; uint32_t 224 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved4; uint32_t 226 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved5; uint32_t 228 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved6; uint32_t 230 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved7; uint32_t 232 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved8; uint32_t 234 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t completion_signal_lo32; uint32_t 236 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t completion_signal_hi32; uint32_t 271 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal1; uint32_t 276 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved1:2; uint32_t 279 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved5:6; uint32_t 280 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t gws_control_queue:1; uint32_t 281 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved2:8; uint32_t 283 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved3:2; uint32_t 285 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t num_queues:3; uint32_t 287 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal2; uint32_t 292 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved3:1; uint32_t 293 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t check_disable:1; uint32_t 294 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t doorbell_offset:26; uint32_t 295 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved4:4; uint32_t 297 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal3; uint32_t 300 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t mqd_addr_lo; uint32_t 301 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t mqd_addr_hi; uint32_t 302 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t wptr_addr_lo; uint32_t 303 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t wptr_addr_hi; uint32_t 333 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal1; uint32_t 338 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t context_id:28; uint32_t 342 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal2; uint32_t 347 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t pasid:16; uint32_t 348 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved1:16; uint32_t 351 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved2:2; uint32_t 352 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t doorbell_offset:26; uint32_t 354 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved3:1; uint32_t 356 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal3; uint32_t 359 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t addr_lo; uint32_t 360 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t addr_hi; uint32_t 361 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t data_lo; uint32_t 362 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t data_hi; uint32_t 398 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal1; uint32_t 406 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved2:20; uint32_t 408 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t num_queues:3; uint32_t 410 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal2; uint32_t 415 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t pasid:16; uint32_t 416 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved3:16; uint32_t 419 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved4:2; uint32_t 420 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t doorbell_offset0:26; uint32_t 423 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal3; uint32_t 428 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved6:2; uint32_t 429 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t doorbell_offset1:26; uint32_t 430 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved7:4; uint32_t 432 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal4; uint32_t 437 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved8:2; uint32_t 438 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t doorbell_offset2:26; uint32_t 439 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved9:4; uint32_t 441 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal5; uint32_t 446 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved10:2; uint32_t 447 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t doorbell_offset3:26; uint32_t 448 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved11:4; uint32_t 450 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal6; uint32_t 516 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved3:1; uint32_t 517 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t tc_nc_action_ena:1; uint32_t 518 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t tc_wc_action_ena:1; uint32_t 519 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t tc_md_action_ena:1; uint32_t 520 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved4:3; uint32_t 522 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved5:2; uint32_t 524 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved6:2; uint32_t 531 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved7:16; uint32_t 533 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved8:6; uint32_t 535 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved9:2; uint32_t 543 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved10:2; uint32_t 547 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved11:3; uint32_t 548 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t address_lo_64b:29; uint32_t 550 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved12; uint32_t 555 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t address_hi; uint32_t 556 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved13; uint32_t 557 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal5; uint32_t 561 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t data_lo; uint32_t 562 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t cmp_data_lo; uint32_t 564 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t dw_offset:16; uint32_t 565 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t num_dwords:16; uint32_t 567 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved14; uint32_t 568 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal6; uint32_t 572 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t data_hi; uint32_t 573 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t cmp_data_hi; uint32_t 574 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved15; uint32_t 575 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t reserved16; uint32_t 576 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t ordinal7; uint32_t 579 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h uint32_t int_ctxid; uint32_t 31 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved1 : 8; /* < reserved */ uint32_t 32 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t opcode : 8; /* < IT opcode */ uint32_t 33 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t count : 14;/* < Number of DWORDS - 1 in the uint32_t 36 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t type : 2; /* < packet identifier uint32_t 40 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t u32All; uint32_t 58 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal1; uint32_t 63 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t vmid_mask:16; uint32_t 64 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t unmap_latency:8; uint32_t 65 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved1:5; uint32_t 68 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal2; uint32_t 71 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t queue_mask_lo; uint32_t 72 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t queue_mask_hi; uint32_t 73 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t gws_mask_lo; uint32_t 74 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t gws_mask_hi; uint32_t 78 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t oac_mask:16; uint32_t 79 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved2:16; uint32_t 81 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal7; uint32_t 86 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t gds_heap_base:6; uint32_t 87 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved3:5; uint32_t 88 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t gds_heap_size:6; uint32_t 89 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved4:15; uint32_t 91 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal8; uint32_t 105 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal1; uint32_t 110 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved1:2; uint32_t 111 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ib_base_lo:30; uint32_t 113 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal2; uint32_t 118 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ib_base_hi:16; uint32_t 119 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved2:16; uint32_t 121 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal3; uint32_t 126 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ib_size:20; uint32_t 127 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t chain:1; uint32_t 128 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t offload_polling:1; uint32_t 129 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved2:1; uint32_t 130 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t valid:1; uint32_t 131 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t process_cnt:4; uint32_t 132 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved3:4; uint32_t 134 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal4; uint32_t 148 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal1; uint32_t 153 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t pasid:16; uint32_t 154 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved1:8; uint32_t 155 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t diq_enable:1; uint32_t 156 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t process_quantum:7; uint32_t 158 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal2; uint32_t 163 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t page_table_base:28; uint32_t 164 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved3:4; uint32_t 166 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal3; uint32_t 169 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved; uint32_t 171 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t sh_mem_bases; uint32_t 172 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t sh_mem_config; uint32_t 173 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t sh_mem_ape1_base; uint32_t 174 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t sh_mem_ape1_limit; uint32_t 176 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t sh_hidden_private_base_vmid; uint32_t 178 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved2; uint32_t 179 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved3; uint32_t 181 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t gds_addr_lo; uint32_t 182 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t gds_addr_hi; uint32_t 186 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t num_gws:6; uint32_t 187 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved4:2; uint32_t 188 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t num_oac:4; uint32_t 189 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved5:4; uint32_t 190 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t gds_size:6; uint32_t 191 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t num_queues:10; uint32_t 193 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal10; uint32_t 196 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t completion_signal_lo; uint32_t 197 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t completion_signal_hi; uint32_t 229 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal1; uint32_t 234 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved1:4; uint32_t 236 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved2:15; uint32_t 238 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved3:2; uint32_t 240 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t num_queues:3; uint32_t 242 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal2; uint32_t 247 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved3:1; uint32_t 248 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t check_disable:1; uint32_t 249 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t doorbell_offset:21; uint32_t 250 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved4:3; uint32_t 251 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t queue:6; uint32_t 253 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal3; uint32_t 256 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t mqd_addr_lo; uint32_t 257 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t mqd_addr_hi; uint32_t 258 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t wptr_addr_lo; uint32_t 259 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t wptr_addr_hi; uint32_t 289 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal1; uint32_t 294 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t context_id:28; uint32_t 299 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal2; uint32_t 304 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t pasid:16; uint32_t 305 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved1:16; uint32_t 308 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved2:2; uint32_t 309 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t doorbell_offset:21; uint32_t 310 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved3:2; uint32_t 312 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved4:4; uint32_t 314 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal3; uint32_t 317 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t addr_lo; uint32_t 318 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t addr_hi; uint32_t 319 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t data_lo; uint32_t 320 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t data_hi; uint32_t 351 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal1; uint32_t 357 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved1:2; uint32_t 359 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved2:20; uint32_t 361 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t num_queues:3; uint32_t 363 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal2; uint32_t 368 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t pasid:16; uint32_t 369 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved3:16; uint32_t 372 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved4:2; uint32_t 373 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t doorbell_offset0:21; uint32_t 374 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved5:9; uint32_t 376 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal3; uint32_t 381 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved6:2; uint32_t 382 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t doorbell_offset1:21; uint32_t 383 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved7:9; uint32_t 385 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal4; uint32_t 390 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved8:2; uint32_t 391 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t doorbell_offset2:21; uint32_t 392 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved9:9; uint32_t 394 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal5; uint32_t 399 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved10:2; uint32_t 400 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t doorbell_offset3:21; uint32_t 401 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t reserved11:9; uint32_t 403 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h uint32_t ordinal6; uint32_t 190 drivers/gpu/drm/amd/amdkfd/kfd_priv.h const uint32_t *ih_ring_entry, uint32_t *patched_ihre, uint32_t 193 drivers/gpu/drm/amd/amdkfd/kfd_priv.h const uint32_t *ih_ring_entry); uint32_t 215 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t range_start; uint32_t 216 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t range_end; uint32_t 218 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t *cpu_ptr; uint32_t 223 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t first_vmid_kfd; uint32_t 224 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t last_vmid_kfd; uint32_t 225 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t vmid_num_kfd; uint32_t 423 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t priority; uint32_t 424 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t queue_percent; uint32_t 425 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t *read_ptr; uint32_t 426 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t *write_ptr; uint32_t 428 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t doorbell_off; uint32_t 435 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t sdma_engine_id; uint32_t 436 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t sdma_queue_id; uint32_t 437 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t sdma_vm_addr; uint32_t 440 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t eop_ring_buffer_size; uint32_t 442 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t ctx_save_restore_area_size; uint32_t 443 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t ctl_stack_size; uint32_t 447 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t cu_mask_count; /* Must be a multiple of 32 */ uint32_t 448 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t *cu_mask; uint32_t 496 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t mec; uint32_t 497 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t pipe; uint32_t 498 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t queue; uint32_t 531 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t oac_mask; uint32_t 532 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t gds_heap_base; uint32_t 533 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t gds_heap_size; uint32_t 567 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t sh_mem_config; uint32_t 568 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t sh_mem_bases; uint32_t 569 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t sh_mem_ape1_base; uint32_t 570 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t sh_mem_ape1_limit; uint32_t 571 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t gds_size; uint32_t 572 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t num_gws; uint32_t 573 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t num_oac; uint32_t 574 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t sh_hidden_private_base; uint32_t 847 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t proximity_domain); uint32_t 848 drivers/gpu/drm/amd/amdkfd/kfd_priv.h struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id); uint32_t 849 drivers/gpu/drm/amd/amdkfd/kfd_priv.h struct kfd_dev *kfd_device_by_id(uint32_t gpu_id); uint32_t 860 drivers/gpu/drm/amd/amdkfd/kfd_priv.h const uint32_t *ih_ring_entry, uint32_t 861 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t *patched_ihre, bool *flag); uint32_t 945 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int (*map_process)(struct packet_manager *pm, uint32_t *buffer, uint32_t 947 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int (*runlist)(struct packet_manager *pm, uint32_t *buffer, uint32_t 949 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int (*set_resources)(struct packet_manager *pm, uint32_t *buffer, uint32_t 951 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int (*map_queues)(struct packet_manager *pm, uint32_t *buffer, uint32_t 953 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, uint32_t 956 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t filter_param, bool reset, uint32_t 958 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int (*query_status)(struct packet_manager *pm, uint32_t *buffer, uint32_t 959 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint64_t fence_address, uint32_t fence_value); uint32_t 960 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); uint32_t 982 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t fence_value); uint32_t 986 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t filter_param, bool reset, uint32_t 993 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer, uint32_t 1009 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t num_events, void __user *data, uint32_t 1010 drivers/gpu/drm/amd/amdkfd/kfd_priv.h bool all, uint32_t user_timeout_ms, uint32_t 1011 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t *wait_result); uint32_t 1012 drivers/gpu/drm/amd/amdkfd/kfd_priv.h void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, uint32_t 1013 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t valid_id_bits); uint32_t 1018 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int kfd_set_event(struct kfd_process *p, uint32_t event_id); uint32_t 1019 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int kfd_reset_event(struct kfd_process *p, uint32_t event_id); uint32_t 1023 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t event_type, bool auto_reset, uint32_t node_id, uint32_t 1024 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint32_t *event_id, uint32_t *event_trigger_data, uint32_t 1025 drivers/gpu/drm/amd/amdkfd/kfd_priv.h uint64_t *event_page_offset, uint32_t *event_slot_index); uint32_t 1026 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); uint32_t 177 drivers/gpu/drm/amd/amdkfd/kfd_process.c uint64_t gpu_va, uint32_t size, uint32_t 178 drivers/gpu/drm/amd/amdkfd/kfd_process.c uint32_t flags, void **kptr) uint32_t 246 drivers/gpu/drm/amd/amdkfd/kfd_process.c uint32_t flags = ALLOC_MEM_FLAGS_GTT | uint32_t 592 drivers/gpu/drm/amd/amdkfd/kfd_process.c uint32_t flags = ALLOC_MEM_FLAGS_GTT | uint32_t 312 drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c (q->properties.doorbell_off * sizeof(uint32_t)) & uint32_t 50 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t proximity_domain) uint32_t 68 drivers/gpu/drm/amd/amdkfd/kfd_topology.c struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id) uint32_t 86 drivers/gpu/drm/amd/amdkfd/kfd_topology.c struct kfd_dev *kfd_device_by_id(uint32_t gpu_id) uint32_t 330 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t i, j; uint32_t 376 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t data; uint32_t 409 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t log_max_watch_addr; uint32_t 593 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t id) uint32_t 600 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t i, num_attrs; uint32_t 747 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t i = 0; uint32_t 1062 drivers/gpu/drm/amd/amdkfd/kfd_topology.c static uint32_t kfd_generate_gpu_id(struct kfd_dev *gpu) uint32_t 1064 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t hashout; uint32_t 1065 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t buf[7]; uint32_t 1121 drivers/gpu/drm/amd/amdkfd/kfd_topology.c static void kfd_notify_gpu_change(uint32_t gpu_id, int arrival) uint32_t 1156 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t cap; uint32_t 1157 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t cpu_flag = CRAT_IOLINK_FLAGS_ENABLED; uint32_t 1158 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t flag = CRAT_IOLINK_FLAGS_ENABLED; uint32_t 1192 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t gpu_id; uint32_t 1377 drivers/gpu/drm/amd/amdkfd/kfd_topology.c uint32_t gpu_id; uint32_t 57 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cpu_cores_count; uint32_t 58 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t simd_count; uint32_t 59 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t mem_banks_count; uint32_t 60 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t caches_count; uint32_t 61 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t io_links_count; uint32_t 62 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cpu_core_id_base; uint32_t 63 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t simd_id_base; uint32_t 64 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t capability; uint32_t 65 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t max_waves_per_simd; uint32_t 66 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t lds_size_in_kb; uint32_t 67 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t gds_size_in_kb; uint32_t 68 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t num_gws; uint32_t 69 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t wave_front_size; uint32_t 70 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t array_count; uint32_t 71 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t simd_arrays_per_engine; uint32_t 72 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cu_per_simd_array; uint32_t 73 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t simd_per_cu; uint32_t 74 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t max_slots_scratch_cu; uint32_t 75 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t engine_id; uint32_t 76 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t vendor_id; uint32_t 77 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t device_id; uint32_t 78 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t location_id; uint32_t 79 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t max_engine_clk_fcompute; uint32_t 80 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t max_engine_clk_ccompute; uint32_t 82 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t num_sdma_engines; uint32_t 83 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t num_sdma_xgmi_engines; uint32_t 100 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t heap_type; uint32_t 102 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t flags; uint32_t 103 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t width; uint32_t 104 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t mem_clk_max; uint32_t 117 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t processor_id_low; uint32_t 118 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cache_level; uint32_t 119 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cache_size; uint32_t 120 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cacheline_size; uint32_t 121 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cachelines_per_tag; uint32_t 122 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cache_assoc; uint32_t 123 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cache_latency; uint32_t 124 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cache_type; uint32_t 132 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t iolink_type; uint32_t 133 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t ver_maj; uint32_t 134 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t ver_min; uint32_t 135 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t node_from; uint32_t 136 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t node_to; uint32_t 137 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t weight; uint32_t 138 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t min_latency; uint32_t 139 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t max_latency; uint32_t 140 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t min_bandwidth; uint32_t 141 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t max_bandwidth; uint32_t 142 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t rec_transfer_size; uint32_t 143 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t flags; uint32_t 151 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t max_concurrent; uint32_t 157 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t gpu_id; uint32_t 158 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t proximity_domain; uint32_t 161 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t cache_count; uint32_t 163 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t io_link_count; uint32_t 177 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t oem_revision; uint32_t 181 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t num_devices; /* Number of H-NUMA nodes */ uint32_t 182 drivers/gpu/drm/amd/amdkfd/kfd_topology.h uint32_t generation_count; uint32_t 123 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t link_index); uint32_t 126 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t link_index, uint32_t 130 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t link_index); uint32_t 182 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t v_blank_start, v_blank_end, h_position, v_position; uint32_t 274 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t vpos, hpos, v_blank_start, v_blank_end; uint32_t 1067 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t i; uint32_t 2088 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t brightness = bd->props.brightness; uint32_t 2238 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t link_cnt; uint32_t 2692 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); uint32_t 2712 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); uint32_t 2713 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; uint32_t 2904 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c static const uint32_t alpha_formats[] = { uint32_t 2909 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t format = plane_state->fb->format->format; uint32_t 3562 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t link_bandwidth_kbps; uint32_t 4498 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t domain; uint32_t 4660 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c static const uint32_t rgb_formats[] = { uint32_t 4673 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c static const uint32_t overlay_formats[] = { uint32_t 4688 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t *formats, int max_formats) uint32_t 4738 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t formats[32]; uint32_t 4783 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t crtc_index) uint32_t 5188 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t link_index, uint32_t 5283 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t link_index) uint32_t 5675 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t i; uint32_t 5690 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t target_vblank, last_flip_vblank; uint32_t 6161 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t i, j; uint32_t 234 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h uint32_t dmcu_fw_version; uint32_t 247 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h uint32_t connector_id; uint32_t 287 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h uint32_t debugfs_dpcd_address; uint32_t 288 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h uint32_t debugfs_dpcd_size; uint32_t 87 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size) uint32_t 101 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size) uint32_t 104 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c uint32_t expected; uint32_t 129 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c uint32_t r, g, b; uint32_t 194 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c const struct drm_color_lut *lut, uint32_t lut_size, uint32_t 218 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c const struct drm_color_lut *lut, uint32_t lut_size, uint32_t 258 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c const struct drm_color_lut *lut, uint32_t lut_size) uint32_t 307 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c uint32_t degamma_size, regamma_size; uint32_t 420 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c uint32_t degamma_size; uint32_t 284 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c uint32_t crcs[3]; uint32_t 84 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c const uint32_t rd_buf_size = 100; uint32_t 85 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c uint32_t result = 0; uint32_t 152 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c const uint32_t wr_buf_size = 40; uint32_t 286 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c const uint32_t rd_buf_size = 20; uint32_t 287 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c uint32_t result = 0; uint32_t 328 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c uint32_t wr_buf_size = 40; uint32_t 487 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c uint32_t wr_buf_size = 100; uint32_t 488 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c uint32_t wr_buf_count = 0; uint32_t 781 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c uint32_t write_size = 36; uint32_t 840 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c uint32_t write_size = connector->debugfs_dpcd_size; uint32_t 864 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c uint32_t read_size = connector->debugfs_dpcd_size; uint32_t 471 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c uint32_t address, uint32_t 473 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c uint32_t size) uint32_t 490 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c uint32_t address, uint32_t 492 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c uint32_t size) uint32_t 45 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c static inline char *side_band_msg_type_to_str(uint32_t address) uint32_t 62 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c uint32_t address, uint32_t 64 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c uint32_t size, uint32_t 123 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c uint32_t disp_clks_in_khz[6] = { uint32_t 125 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c uint32_t sclks_in_khz[6] = { uint32_t 127 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c uint32_t mclks_in_khz[2] = { 333000, 800000 }; uint32_t 255 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c uint32_t i; uint32_t 281 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c uint32_t i; uint32_t 308 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c uint32_t i; uint32_t 340 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c uint32_t i; uint32_t 35 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h TP_PROTO(unsigned long *read_count, uint32_t reg, uint32_t value), uint32_t 38 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, reg) uint32_t 39 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, value) uint32_t 52 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h TP_PROTO(unsigned long *write_count, uint32_t reg, uint32_t value), uint32_t 55 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, reg) uint32_t 56 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, value) uint32_t 75 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, reads) uint32_t 76 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, writes) uint32_t 77 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, read_delta) uint32_t 78 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, write_delta) uint32_t 80 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, line) uint32_t 84 drivers/gpu/drm/amd/display/dc/basics/conversion.c uint32_t buffer_size) uint32_t 90 drivers/gpu/drm/amd/display/dc/basics/conversion.c uint32_t i; uint32_t 93 drivers/gpu/drm/amd/display/dc/basics/conversion.c uint32_t reg_value = uint32_t 39 drivers/gpu/drm/amd/display/dc/basics/conversion.h uint32_t buffer_size); uint32_t 34 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t capacity, uint32_t 35 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t struct_size) uint32_t 58 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t count, uint32_t 60 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t struct_size) uint32_t 62 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t i; uint32_t 96 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t size, uint32_t 98 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t struct_size) uint32_t 116 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t capacity, uint32_t 117 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t struct_size) uint32_t 150 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t dal_vector_get_count( uint32_t 158 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t index) uint32_t 167 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t index) uint32_t 185 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t index) uint32_t 199 drivers/gpu/drm/amd/display/dc/basics/vector.c static inline uint32_t calc_increased_capacity( uint32_t 200 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t old_capacity) uint32_t 208 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t position) uint32_t 248 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t count; uint32_t 282 drivers/gpu/drm/amd/display/dc/basics/vector.c uint32_t dal_vector_capacity(const struct vector *vector) uint32_t 287 drivers/gpu/drm/amd/display/dc/basics/vector.c bool dal_vector_reserve(struct vector *vector, uint32_t capacity) uint32_t 62 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object, uint32_t 72 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t signal_to_ss_id(enum as_signal_type signal); uint32_t 73 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_support_mask_for_device_id(struct device_id device_id); uint32_t 135 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint8_t get_number_of_objects(struct bios_parser *bp, uint32_t offset) uint32_t 139 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t object_table_offset = bp->object_info_tbl_offset + offset; uint32_t 166 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t connector_table_offset = bp->object_info_tbl_offset uint32_t 189 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c struct graphics_object_id object_id, uint32_t index, uint32_t 192 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t number; uint32_t 221 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t offset; uint32_t 296 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t offset; uint32_t 330 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t device_tag_index, uint32_t 465 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id, uint32_t 466 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t index, uint32_t 476 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t index; uint32_t 559 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t index; uint32_t 642 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t) (le32_to_cpu(firmware_info->ulGPUPLL_OutputFreq) * 10); uint32_t 649 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id, uint32_t 650 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t index, uint32_t 655 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t table_size; uint32_t 656 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i; uint32_t 657 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t table_index = 0; uint32_t 717 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage); uint32_t 719 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10); uint32_t 860 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t mask = get_support_mask_for_device_id(id); uint32_t 869 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t offset; uint32_t 901 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id, uint32_t 905 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id, uint32_t 923 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t index, uint32_t 928 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t clk_id_ss = 0; uint32_t 978 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id, uint32_t 995 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id, uint32_t 1020 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id, uint32_t 1026 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t tbl_size, i; uint32_t 1061 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage); uint32_t 1063 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10); uint32_t 1085 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id, uint32_t 1091 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t table_size; uint32_t 1092 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i; uint32_t 1093 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id_local = SS_ID_UNKNOWN; uint32_t 1135 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id) uint32_t 1150 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t)le16_to_cpu(tbl->asSS_Info[i].usSpreadSpectrumPercentage); uint32_t 1157 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t)tbl->asSS_Info[i].ucSS_Range * 10000; uint32_t 1266 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c ~(uint32_t) uint32_t 1269 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c ~(uint32_t) uint32_t 1312 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t) (ATOM_PANEL_MISC_GREY_LEVEL & uint32_t 1384 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c ~(uint32_t) uint32_t 1387 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c ~(uint32_t) uint32_t 1446 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL & uint32_t 1509 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t offset; uint32_t 1541 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_ss_entry_number( uint32_t 1543 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id); uint32_t 1544 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1( uint32_t 1546 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id); uint32_t 1547 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1( uint32_t 1549 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id); uint32_t 1550 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_ss_entry_number_from_ss_info_tbl( uint32_t 1552 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id); uint32_t 1562 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t bios_parser_get_ss_entry_number( uint32_t 1567 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t ss_id = 0; uint32_t 1615 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_ss_entry_number_from_ss_info_tbl( uint32_t 1617 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id) uint32_t 1621 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t table_size; uint32_t 1622 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i; uint32_t 1623 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t number = 0; uint32_t 1624 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id_local = SS_ID_UNKNOWN; uint32_t 1666 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (id_local == (uint32_t)tbl->asSS_Info[i].ucSS_Id) { uint32_t 1684 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_ss_entry_number(struct bios_parser *bp, uint32_t id) uint32_t 1701 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1( uint32_t 1703 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id) uint32_t 1707 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t size; uint32_t 1708 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i; uint32_t 1736 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1( uint32_t 1738 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t id) uint32_t 1740 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t number = 0; uint32_t 1743 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t size; uint32_t 1744 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i; uint32_t 1780 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t gpio_id, uint32_t 1785 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t count = 0; uint32_t 1786 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i = 0; uint32_t 1810 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t) le16_to_cpu(header->asGPIO_Pin[i].usGpioPin_AIndex); uint32_t 1815 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->mask = (uint32_t) (1 << uint32_t 1832 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t count = 0; uint32_t 1951 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t offset; uint32_t 1953 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i; uint32_t 1993 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object, uint32_t 1996 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t offset; uint32_t 2099 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t) GET_DATA_TABLE_MAJOR_REVISION(atom_data_tbl); uint32_t 2101 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c (uint32_t) GET_DATA_TABLE_MINOR_REVISION(atom_data_tbl); uint32_t 2104 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t signal_to_ss_id(enum as_signal_type signal) uint32_t 2106 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t clk_id_ss = 0; uint32_t 2130 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c static uint32_t get_support_mask_for_device_id(struct device_id device_id) uint32_t 2133 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t enum_id = device_id.enum_id; uint32_t 2233 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i; uint32_t 2383 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i; uint32_t 2547 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t i; uint32_t 2548 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t j; uint32_t 150 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c (uint32_t) atom_data_tbl->format_revision & 0x3f; uint32_t 152 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c (uint32_t) atom_data_tbl->content_revision & 0x3f; uint32_t 195 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c struct graphics_object_id object_id, uint32_t index, uint32_t 293 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t offset; uint32_t 342 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t count = 0; uint32_t 447 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t offset; uint32_t 493 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t gpio_id, uint32_t 498 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t count = 0; uint32_t 499 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t i = 0; uint32_t 542 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c (uint32_t) le16_to_cpu( uint32_t 548 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->mask = (uint32_t) (1 << uint32_t 614 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t device_tag_index, uint32_t 639 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t id, uint32_t 640 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t index, uint32_t 719 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t id, uint32_t 720 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t index, uint32_t 807 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t index, uint32_t 895 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo uint32_t 897 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo uint32_t 955 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c static uint32_t get_support_mask_for_device_id(struct device_id device_id) uint32_t 958 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t enum_id = device_id.enum_id; uint32_t 1001 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t mask = get_support_mask_for_device_id(id); uint32_t 1007 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c static uint32_t bios_parser_get_ss_entry_number( uint32_t 1330 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t offset; uint32_t 1381 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t i; uint32_t 1618 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t i; uint32_t 1619 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t j; uint32_t 29 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id) uint32_t 31 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK) uint32_t 59 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id) uint32_t 61 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c uint32_t bios_enum_id = uint32_t 95 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id) uint32_t 100 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id) uint32_t 102 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id); uint32_t 173 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c uint32_t bios_object_id) uint32_t 175 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c uint32_t bios_connector_id = gpu_id_from_bios_object_id(bios_object_id); uint32_t 224 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c static enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id) uint32_t 226 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c uint32_t bios_generic_id = gpu_id_from_bios_object_id(bios_object_id); uint32_t 248 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c static uint32_t id_from_bios_object_id(enum object_type type, uint32_t 249 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c uint32_t bios_object_id) uint32_t 255 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c return (uint32_t)encoder_id_from_bios_object_id(bios_object_id); uint32_t 257 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c return (uint32_t)connector_id_from_bios_object_id( uint32_t 266 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c struct graphics_object_id object_id_from_bios_object_id(uint32_t bios_object_id) uint32_t 32 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.h struct graphics_object_id object_id_from_bios_object_id(uint32_t bios_object_id); uint32_t 37 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c uint32_t offset, uint32_t 38 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c uint32_t size) uint32_t 60 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c uint32_t acc_mode; uint32_t 77 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c uint32_t critial_state = state ? 1 : 0; uint32_t 81 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c uint32_t bios_get_vga_enabled_displays( uint32_t 84 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c uint32_t active_disp = 1; uint32_t 31 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset, uint32_t 32 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h uint32_t size); uint32_t 37 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h uint32_t bios_get_vga_enabled_displays(struct dc_bios *bios); uint32_t 33 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal.h uint32_t major; uint32_t 34 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal.h uint32_t minor; uint32_t 57 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal.h uint32_t object_info_tbl_offset; uint32_t 35 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h uint32_t major; uint32_t 36 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h uint32_t minor; uint32_t 58 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h uint32_t object_info_tbl_offset; uint32_t 40 drivers/gpu/drm/amd/display/dc/bios/command_table.c (uint32_t *)¶ms) == 0) uint32_t 83 drivers/gpu/drm/amd/display/dc/bios/command_table.c static uint32_t bios_cmd_table_para_revision(void *dev, uint32_t 84 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t index) uint32_t 120 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t version = uint32_t 522 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pll_id; uint32_t 656 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t ref_clk_src_id; uint32_t 1018 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pll_id; uint32_t 1075 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pll_id; uint32_t 1153 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pll_id; uint32_t 1463 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10; uint32_t 1482 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pixel_clk_10_kHz_in = bp_params->pixel_clock / 10; uint32_t 1540 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pixel_clock, uint32_t 1545 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pixel_clock, uint32_t 1571 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pixel_clock, uint32_t 1589 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pixel_clock, uint32_t 1610 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t pixel_clock, uint32_t 1713 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t dtd_version = uint32_t 2038 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t atom_pll_id; uint32_t 2069 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t atom_pll_id; uint32_t 2094 drivers/gpu/drm/amd/display/dc/bios/command_table.c (uint32_t)(le32_to_cpu(params.sPCLKInput.ulDispEngClkFreq) * 10); uint32_t 2313 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t atom_pll_id; uint32_t 2314 drivers/gpu/drm/amd/display/dc/bios/command_table.c uint32_t atom_clock_type; uint32_t 58 drivers/gpu/drm/amd/display/dc/bios/command_table.h uint32_t pixel_clock, uint32_t 63 drivers/gpu/drm/amd/display/dc/bios/command_table.h uint32_t pixel_clock, uint32_t 52 drivers/gpu/drm/amd/display/dc/bios/command_table2.c (uint32_t *)¶ms) == 0) uint32_t 64 drivers/gpu/drm/amd/display/dc/bios/command_table2.c static uint32_t bios_cmd_table_para_revision(void *dev, uint32_t 65 drivers/gpu/drm/amd/display/dc/bios/command_table2.c uint32_t index) uint32_t 92 drivers/gpu/drm/amd/display/dc/bios/command_table2.c uint32_t version = uint32_t 267 drivers/gpu/drm/amd/display/dc/bios/command_table2.c uint32_t pll_id; uint32_t 354 drivers/gpu/drm/amd/display/dc/bios/command_table2.c uint32_t dtd_version = uint32_t 646 drivers/gpu/drm/amd/display/dc/bios/command_table2.c uint32_t atom_pll_id; uint32_t 647 drivers/gpu/drm/amd/display/dc/bios/command_table2.c uint32_t atom_clock_type; uint32_t 58 drivers/gpu/drm/amd/display/dc/bios/command_table2.h uint32_t pixel_clock, uint32_t 63 drivers/gpu/drm/amd/display/dc/bios/command_table2.h uint32_t pixel_clock, uint32_t 142 drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom( uint32_t 210 drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c uint32_t *ref_clk_src_id) uint32_t 41 drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom( uint32_t 52 drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h uint32_t *ref_clk_src_id); uint32_t 165 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2( uint32_t 194 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c uint32_t *ref_clk_src_id) uint32_t 41 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2( uint32_t 47 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h uint32_t *ref_clk_src_id); uint32_t 38 drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h uint32_t (*encoder_mode_bp_to_atom)(enum signal_type s, uint32_t 41 drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h uint32_t *atom_engine_id); uint32_t 47 drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h uint32_t *atom_pll_id); uint32_t 50 drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h uint32_t *ref_clk_src_id); uint32_t 62 drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h uint32_t *atom_clock_type); uint32_t 166 drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c uint32_t *atom_pll_id) uint32_t 210 drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id) uint32_t 163 drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c uint32_t *atom_pll_id) uint32_t 212 drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id) uint32_t 307 drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c uint32_t *atom_clock_type) uint32_t 163 drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c uint32_t *atom_pll_id) uint32_t 212 drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id) uint32_t 307 drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c uint32_t *atom_clock_type) uint32_t 61 drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id) uint32_t 108 drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c uint32_t *atom_pll_id) uint32_t 79 drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c uint32_t i = BW_FIXED_BITS_PER_FRACTIONAL_PART; uint32_t 33 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t *mantissa, uint32_t 34 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t *exponenta) uint32_t 36 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; uint32_t 66 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t i = 1; uint32_t 87 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t i = 1; uint32_t 125 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t mantissa, uint32_t 126 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t exponenta, uint32_t 127 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t *result) uint32_t 129 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t i = 0; uint32_t 130 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t j = 0; uint32_t 132 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t value = 0; uint32_t 138 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c const uint32_t mantissa_mask = uint32_t 141 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c const uint32_t exponenta_mask = uint32_t 157 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t mask = 1 << i; uint32_t 166 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t mask = 1 << j; uint32_t 185 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t *result) uint32_t 187 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t mantissa; uint32_t 188 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t exponenta; uint32_t 87 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const uint32_t s_low = 0; uint32_t 88 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const uint32_t s_mid1 = 1; uint32_t 89 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const uint32_t s_mid2 = 2; uint32_t 90 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const uint32_t s_mid3 = 3; uint32_t 91 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const uint32_t s_mid4 = 4; uint32_t 92 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const uint32_t s_mid5 = 5; uint32_t 93 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const uint32_t s_mid6 = 6; uint32_t 94 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const uint32_t s_high = 7; uint32_t 95 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c const uint32_t dmif_chunk_buff_margin = 1; uint32_t 97 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c uint32_t max_chunks_fbc_mode; uint32_t 2744 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c uint32_t int_max_clk; uint32_t 709 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev) uint32_t 165 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context) uint32_t 167 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c uint32_t max_pix_clk = 0; uint32_t 39 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context); uint32_t 92 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) uint32_t 95 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c uint32_t min_vertical_blank_time = -1; uint32_t 99 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c uint32_t vertical_blank_in_pixels = 0; uint32_t 100 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c uint32_t vertical_blank_time = 0; uint32_t 101 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c uint32_t vertical_total_min = stream->timing.v_total; uint32_t 200 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c (uint32_t) div64_s64( uint32_t 42 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); uint32_t 71 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c uint32_t dentist_get_did_from_divider(int divider) uint32_t 73 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c uint32_t divider_id; uint32_t 125 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); uint32_t 137 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); uint32_t 460 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ); uint32_t 46 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h uint32_t dentist_get_did_from_divider(int divider); uint32_t 30 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */ uint32_t 87 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c uint32_t clk = requested_dispclk_khz / 1000; uint32_t 165 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c uint32_t clk = requested_dpp_khz / 1000; uint32_t 138 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t i; uint32_t 148 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t num_virtual_links) uint32_t 393 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) uint32_t 1878 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t old_dsc_enabled = stream->timing.flags.DSC; uint32_t 1879 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 && uint32_t 2278 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t src_id, uint32_t 2279 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t ext_id) uint32_t 2356 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t i; uint32_t 2393 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t link_index, uint32_t 2527 drivers/gpu/drm/amd/display/dc/core/dc.c enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping) uint32_t 206 drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c uint32_t *array_size) uint32_t 214 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t is_hpd_high = 0; uint32_t 351 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t clock_pin = 0; uint32_t 528 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t read_dpcd_retry_cnt = 10; uint32_t 1053 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t state; uint32_t 1679 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint8_t address, uint8_t *buffer, uint32_t length) uint32_t 2185 drivers/gpu/drm/amd/display/dc/core/dc_link.c static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing) uint32_t 2188 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t pxl_clk = timing->pix_clk_100hz; uint32_t 2274 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10; uint32_t 2318 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t backlight_pwm_u16_16, uint32_t 2319 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t frame_ramp) uint32_t 2410 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link, uint32_t 2434 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t bpc; uint32_t 2437 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t numerator; uint32_t 2438 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t denominator; uint32_t 2913 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t dc_bandwidth_in_kbps_from_timing( uint32_t 2916 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t bits_per_channel = 0; uint32_t 2917 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t kbps; uint32_t 3091 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t dc_link_bandwidth_kbps( uint32_t 3095 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t link_bw_kbps = uint32_t 129 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c static struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count) uint32_t 152 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c static uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p) uint32_t 171 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t address, uint32_t 172 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t len, uint32_t 176 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t payload_size = EDID_SEGMENT_SIZE; uint32_t 177 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t pos; uint32_t 291 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c static uint32_t defer_delay_converter_wa( uint32_t 293 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t defer_delay) uint32_t 309 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t get_defer_delay(struct ddc_service *ddc) uint32_t 311 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t defer_delay = 0; uint32_t 339 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t address, uint32_t 341 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t len) uint32_t 440 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t max_tmds_clk = uint32_t 505 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t address, uint32_t 507 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t write_size, uint32_t 509 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t read_size) uint32_t 512 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t payload_size = uint32_t 516 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t write_payloads = uint32_t 519 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t read_payloads = uint32_t 522 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t payloads_num = write_payloads + read_payloads; uint32_t 630 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t pix_clk, uint32_t 52 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c static uint32_t get_training_aux_rd_interval( uint32_t 54 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t default_wait_in_micro_secs) uint32_t 79 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t wait_in_micro_secs) uint32_t 230 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c const uint32_t dpcd_base_lt_offset = uint32_t 234 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 235 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t size_in_bytes; uint32_t 256 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(lt_settings->link_settings.lane_count); lane++) { uint32_t 320 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 322 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < (uint32_t)(ln_count); lane++) { uint32_t 335 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 339 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < (uint32_t)(ln_count); lane++) { uint32_t 353 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 373 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t index) uint32_t 403 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 503 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 514 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(link_training_setting->link_settings.lane_count); uint32_t 546 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(link_training_setting->link_settings.lane_count); uint32_t 577 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 580 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(link_training_setting-> uint32_t 638 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 640 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(lt_settings->link_settings.lane_count); uint32_t 668 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t adj_req_count; uint32_t 669 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t adj_req_timer; uint32_t 671 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 708 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < (uint32_t)(lane_count); lane++) { uint32_t 772 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t retries_ch_eq; uint32_t 832 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t retries_cr; uint32_t 833 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t retry_count; uint32_t 971 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 1479 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; uint32_t 1868 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t req_bw; uint32_t 1869 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t max_bw; uint32_t 1874 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 && uint32_t 1875 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c timing->h_addressable == (uint32_t) 640 && uint32_t 1876 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c timing->v_addressable == (uint32_t) 480) uint32_t 1909 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw) uint32_t 1915 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t link_bw; uint32_t 1948 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw) uint32_t 1952 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t link_bw; uint32_t 2005 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t req_bw; uint32_t 2722 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t read_dpcd_retry_cnt = 3; uint32_t 2950 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) uint32_t 2989 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t entry; uint32_t 2990 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t link_rate_in_khz; uint32_t 3220 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)cust_pattern_size); uint32_t 3256 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)cust_pattern_size); uint32_t 24 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c uint32_t address, uint32_t 26 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c uint32_t size) uint32_t 39 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c uint32_t address, uint32_t 41 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c uint32_t size) uint32_t 255 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c uint32_t custom_pattern_size) uint32_t 348 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c uint32_t precision = 1 << 28; uint32_t 349 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; uint32_t 350 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; uint32_t 361 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); uint32_t 1809 drivers/gpu/drm/amd/display/dc/core/dc_resource.c uint32_t pix_clk = timing->pix_clk_100hz; uint32_t 1810 drivers/gpu/drm/amd/display/dc/core/dc_resource.c uint32_t normalized_pix_clk = pix_clk; uint32_t 2123 drivers/gpu/drm/amd/display/dc/core/dc_resource.c uint32_t pixel_encoding = 0; uint32_t 64 drivers/gpu/drm/amd/display/dc/core/dc_stream.c uint32_t i = 0; uint32_t 438 drivers/gpu/drm/amd/display/dc/core/dc_stream.c uint32_t dwb_pipe_inst) uint32_t 485 drivers/gpu/drm/amd/display/dc/core/dc_stream.c uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) uint32_t 540 drivers/gpu/drm/amd/display/dc/core/dc_stream.c uint32_t *v_blank_start, uint32_t 541 drivers/gpu/drm/amd/display/dc/core/dc_stream.c uint32_t *v_blank_end, uint32_t 542 drivers/gpu/drm/amd/display/dc/core/dc_stream.c uint32_t *h_position, uint32_t 543 drivers/gpu/drm/amd/display/dc/core/dc_stream.c uint32_t *v_position) uint32_t 107 drivers/gpu/drm/amd/display/dc/core/dc_surface.c uint32_t controller_id) uint32_t 66 drivers/gpu/drm/amd/display/dc/dc.h uint32_t blends_with_above : 1; uint32_t 67 drivers/gpu/drm/amd/display/dc/dc.h uint32_t blends_with_below : 1; uint32_t 68 drivers/gpu/drm/amd/display/dc/dc.h uint32_t per_pixel_alpha : 1; uint32_t 70 drivers/gpu/drm/amd/display/dc/dc.h uint32_t argb8888 : 1; uint32_t 71 drivers/gpu/drm/amd/display/dc/dc.h uint32_t nv12 : 1; uint32_t 72 drivers/gpu/drm/amd/display/dc/dc.h uint32_t fp16 : 1; uint32_t 73 drivers/gpu/drm/amd/display/dc/dc.h uint32_t p010 : 1; uint32_t 74 drivers/gpu/drm/amd/display/dc/dc.h uint32_t ayuv : 1; uint32_t 80 drivers/gpu/drm/amd/display/dc/dc.h uint32_t argb8888; uint32_t 81 drivers/gpu/drm/amd/display/dc/dc.h uint32_t nv12; uint32_t 82 drivers/gpu/drm/amd/display/dc/dc.h uint32_t fp16; uint32_t 88 drivers/gpu/drm/amd/display/dc/dc.h uint32_t argb8888; uint32_t 89 drivers/gpu/drm/amd/display/dc/dc.h uint32_t nv12; uint32_t 90 drivers/gpu/drm/amd/display/dc/dc.h uint32_t fp16; uint32_t 95 drivers/gpu/drm/amd/display/dc/dc.h uint32_t max_streams; uint32_t 96 drivers/gpu/drm/amd/display/dc/dc.h uint32_t max_links; uint32_t 97 drivers/gpu/drm/amd/display/dc/dc.h uint32_t max_audios; uint32_t 98 drivers/gpu/drm/amd/display/dc/dc.h uint32_t max_slave_planes; uint32_t 99 drivers/gpu/drm/amd/display/dc/dc.h uint32_t max_planes; uint32_t 100 drivers/gpu/drm/amd/display/dc/dc.h uint32_t max_downscale_ratio; uint32_t 101 drivers/gpu/drm/amd/display/dc/dc.h uint32_t i2c_speed_in_khz; uint32_t 102 drivers/gpu/drm/amd/display/dc/dc.h uint32_t dmdata_alloc_size; uint32_t 360 drivers/gpu/drm/amd/display/dc/dc.h uint32_t underflow_assert_delay_us; uint32_t 404 drivers/gpu/drm/amd/display/dc/dc.h uint32_t ltFailCount; uint32_t 405 drivers/gpu/drm/amd/display/dc/dc.h uint32_t i2cErrorCount; uint32_t 406 drivers/gpu/drm/amd/display/dc/dc.h uint32_t auxErrorCount; uint32_t 436 drivers/gpu/drm/amd/display/dc/dc.h uint32_t page_table_block_size_in_bytes; uint32_t 545 drivers/gpu/drm/amd/display/dc/dc.h uint32_t log_mask; uint32_t 589 drivers/gpu/drm/amd/display/dc/dc.h uint32_t min_luminance; uint32_t 590 drivers/gpu/drm/amd/display/dc/dc.h uint32_t max_luminance; uint32_t 591 drivers/gpu/drm/amd/display/dc/dc.h uint32_t maximum_content_light_level; uint32_t 592 drivers/gpu/drm/amd/display/dc/dc.h uint32_t maximum_frame_average_light_level; uint32_t 632 drivers/gpu/drm/amd/display/dc/dc.h uint32_t sdr_ref_white_level; uint32_t 644 drivers/gpu/drm/amd/display/dc/dc.h uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ uint32_t 645 drivers/gpu/drm/amd/display/dc/dc.h uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ uint32_t 646 drivers/gpu/drm/amd/display/dc/dc.h uint32_t rmu_mux_num:3; /*index of mux to use*/ uint32_t 647 drivers/gpu/drm/amd/display/dc/dc.h uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ uint32_t 648 drivers/gpu/drm/amd/display/dc/dc.h uint32_t mpc_rmu1_mux:4; uint32_t 649 drivers/gpu/drm/amd/display/dc/dc.h uint32_t mpc_rmu2_mux:4; uint32_t 650 drivers/gpu/drm/amd/display/dc/dc.h uint32_t reserved:15; uint32_t 652 drivers/gpu/drm/amd/display/dc/dc.h uint32_t raw; uint32_t 659 drivers/gpu/drm/amd/display/dc/dc.h uint32_t hdr_multiplier; uint32_t 680 drivers/gpu/drm/amd/display/dc/dc.h uint32_t addr_update:1; uint32_t 682 drivers/gpu/drm/amd/display/dc/dc.h uint32_t dcc_change:1; uint32_t 683 drivers/gpu/drm/amd/display/dc/dc.h uint32_t color_space_change:1; uint32_t 684 drivers/gpu/drm/amd/display/dc/dc.h uint32_t horizontal_mirror_change:1; uint32_t 685 drivers/gpu/drm/amd/display/dc/dc.h uint32_t per_pixel_alpha_change:1; uint32_t 686 drivers/gpu/drm/amd/display/dc/dc.h uint32_t global_alpha_change:1; uint32_t 687 drivers/gpu/drm/amd/display/dc/dc.h uint32_t sdr_white_level:1; uint32_t 688 drivers/gpu/drm/amd/display/dc/dc.h uint32_t rotation_change:1; uint32_t 689 drivers/gpu/drm/amd/display/dc/dc.h uint32_t swizzle_change:1; uint32_t 690 drivers/gpu/drm/amd/display/dc/dc.h uint32_t scaling_change:1; uint32_t 691 drivers/gpu/drm/amd/display/dc/dc.h uint32_t position_change:1; uint32_t 692 drivers/gpu/drm/amd/display/dc/dc.h uint32_t in_transfer_func_change:1; uint32_t 693 drivers/gpu/drm/amd/display/dc/dc.h uint32_t input_csc_change:1; uint32_t 694 drivers/gpu/drm/amd/display/dc/dc.h uint32_t coeff_reduction_change:1; uint32_t 695 drivers/gpu/drm/amd/display/dc/dc.h uint32_t output_tf_change:1; uint32_t 696 drivers/gpu/drm/amd/display/dc/dc.h uint32_t pixel_format_change:1; uint32_t 697 drivers/gpu/drm/amd/display/dc/dc.h uint32_t plane_size_change:1; uint32_t 700 drivers/gpu/drm/amd/display/dc/dc.h uint32_t new_plane:1; uint32_t 701 drivers/gpu/drm/amd/display/dc/dc.h uint32_t bpp_change:1; uint32_t 702 drivers/gpu/drm/amd/display/dc/dc.h uint32_t gamma_change:1; uint32_t 703 drivers/gpu/drm/amd/display/dc/dc.h uint32_t bandwidth_change:1; uint32_t 704 drivers/gpu/drm/amd/display/dc/dc.h uint32_t clock_change:1; uint32_t 705 drivers/gpu/drm/amd/display/dc/dc.h uint32_t stereo_format_change:1; uint32_t 706 drivers/gpu/drm/amd/display/dc/dc.h uint32_t full_update:1; uint32_t 709 drivers/gpu/drm/amd/display/dc/dc.h uint32_t raw; uint32_t 733 drivers/gpu/drm/amd/display/dc/dc.h uint32_t sdr_white_level; uint32_t 945 drivers/gpu/drm/amd/display/dc/dc.h uint32_t sink_dev_id; uint32_t 950 drivers/gpu/drm/amd/display/dc/dc.h uint32_t branch_dev_id; uint32_t 1000 drivers/gpu/drm/amd/display/dc/dc.h uint32_t dongle_max_pix_clk; uint32_t 1013 drivers/gpu/drm/amd/display/dc/dc.h uint32_t sink_id; uint32_t 1028 drivers/gpu/drm/amd/display/dc/dc.h uint32_t dongle_max_pix_clk; uint32_t 1046 drivers/gpu/drm/amd/display/dc/dc.h uint32_t src_id, uint32_t 1047 drivers/gpu/drm/amd/display/dc/dc.h uint32_t ext_id); uint32_t 1051 drivers/gpu/drm/amd/display/dc/dc.h struct dc *dc, uint32_t link_index); uint32_t 1066 drivers/gpu/drm/amd/display/dc/dc.h enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); uint32_t 49 drivers/gpu/drm/amd/display/dc/dc_bios_types.h struct graphics_object_id object_id, uint32_t index, uint32_t 62 drivers/gpu/drm/amd/display/dc/dc_bios_types.h uint32_t device_tag_index, uint32_t 67 drivers/gpu/drm/amd/display/dc/dc_bios_types.h uint32_t index, uint32_t 69 drivers/gpu/drm/amd/display/dc/dc_bios_types.h uint32_t (*get_ss_entry_number)( uint32_t 77 drivers/gpu/drm/amd/display/dc/dc_bios_types.h uint32_t gpio_id, uint32_t 137 drivers/gpu/drm/amd/display/dc/dc_bios_types.h uint32_t BIOS_SCRATCH_3; uint32_t 138 drivers/gpu/drm/amd/display/dc/dc_bios_types.h uint32_t BIOS_SCRATCH_6; uint32_t 145 drivers/gpu/drm/amd/display/dc/dc_bios_types.h uint32_t bios_size; uint32_t 60 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t address; uint32_t 63 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t length; uint32_t 85 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t length; uint32_t 92 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t length; uint32_t 110 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t speed; uint32_t 115 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t ddc_channel; uint32_t 127 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t DP_SKIP_POWER_OFF:1; uint32_t 128 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t DP_AUX_POWER_UP_WA_DELAY:1; uint32_t 130 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t raw; uint32_t 171 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t address; uint32_t 172 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h uint32_t edid_buf_len; uint32_t 35 drivers/gpu/drm/amd/display/dc/dc_dsc.h uint32_t min_kbps; /* Bandwidth if min_target_bpp_x16 is used */ uint32_t 36 drivers/gpu/drm/amd/display/dc/dc_dsc.h uint32_t min_target_bpp_x16; uint32_t 37 drivers/gpu/drm/amd/display/dc/dc_dsc.h uint32_t max_kbps; /* Bandwidth if max_target_bpp_x16 is used */ uint32_t 38 drivers/gpu/drm/amd/display/dc/dc_dsc.h uint32_t max_target_bpp_x16; uint32_t 39 drivers/gpu/drm/amd/display/dc/dc_dsc.h uint32_t stream_kbps; /* Uncompressed stream bandwidth */ uint32_t 49 drivers/gpu/drm/amd/display/dc/dc_dsc.h const uint32_t min_kbps, uint32_t 50 drivers/gpu/drm/amd/display/dc/dc_dsc.h const uint32_t max_kbps, uint32_t 58 drivers/gpu/drm/amd/display/dc/dc_dsc.h uint32_t target_bandwidth_kbps, uint32_t 36 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t value; uint32_t 37 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t mask; uint32_t 41 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr; uint32_t 47 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t value, uint32_t 48 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t mask, uint32_t 58 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr, int n, uint32_t 59 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, uint32_t 62 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t shift, mask, field_value; uint32_t 70 drivers/gpu/drm/amd/display/dc/dc_helper.c shift = va_arg(ap, uint32_t); uint32_t 71 drivers/gpu/drm/amd/display/dc/dc_helper.c mask = va_arg(ap, uint32_t); uint32_t 72 drivers/gpu/drm/amd/display/dc/dc_helper.c field_value = va_arg(ap, uint32_t); uint32_t 80 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_update_ex(const struct dc_context *ctx, uint32_t 81 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr, int n, uint32_t 82 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, uint32_t 86 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val; uint32_t 103 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_set_ex(const struct dc_context *ctx, uint32_t 104 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr, uint32_t reg_val, int n, uint32_t 105 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, uint32_t 125 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t dm_read_reg_func( uint32_t 127 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t address, uint32_t 130 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t value; uint32_t 143 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr, uint32_t 144 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift, uint32_t mask, uint32_t *field_value) uint32_t 146 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); uint32_t 151 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr, uint32_t 152 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 153 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift2, uint32_t mask2, uint32_t *field_value2) uint32_t 155 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); uint32_t 161 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint32_t 162 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 163 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 164 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift3, uint32_t mask3, uint32_t *field_value3) uint32_t 166 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); uint32_t 173 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, uint32_t 174 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 175 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 176 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 177 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift4, uint32_t mask4, uint32_t *field_value4) uint32_t 179 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); uint32_t 187 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint32_t 188 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 189 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 190 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 191 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint32_t 192 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift5, uint32_t mask5, uint32_t *field_value5) uint32_t 194 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); uint32_t 203 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr, uint32_t 204 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 205 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 206 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 207 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint32_t 208 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint32_t 209 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift6, uint32_t mask6, uint32_t *field_value6) uint32_t 211 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); uint32_t 221 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr, uint32_t 222 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 223 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 224 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 225 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint32_t 226 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint32_t 227 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint32_t 228 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift7, uint32_t mask7, uint32_t *field_value7) uint32_t 230 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); uint32_t 241 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr, uint32_t 242 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 243 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 244 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 245 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint32_t 246 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint32_t 247 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint32_t 248 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift7, uint32_t mask7, uint32_t *field_value7, uint32_t 249 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift8, uint32_t mask8, uint32_t *field_value8) uint32_t 251 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); uint32_t 294 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value, uint32_t 298 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t field_value; uint32_t 299 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val; uint32_t 336 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr_index, uint32_t addr_data, uint32_t 337 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t index, uint32_t data) uint32_t 343 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_read_indirect_reg(const struct dc_context *ctx, uint32_t 344 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr_index, uint32_t addr_data, uint32_t 345 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t index) uint32_t 347 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t value = 0; uint32_t 356 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, uint32_t 357 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr_index, uint32_t addr_data, uint32_t 358 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t index, uint32_t reg_val, int n, uint32_t 359 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, uint32_t 362 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t shift, mask, field_value; uint32_t 372 drivers/gpu/drm/amd/display/dc/dc_helper.c shift = va_arg(ap, uint32_t); uint32_t 373 drivers/gpu/drm/amd/display/dc/dc_helper.c mask = va_arg(ap, uint32_t); uint32_t 374 drivers/gpu/drm/amd/display/dc/dc_helper.c field_value = va_arg(ap, uint32_t); uint32_t 47 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t low_part; uint32_t 52 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t low_part; uint32_t 412 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t x; uint32_t 413 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t y; uint32_t 415 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t x_hotspot; uint32_t 416 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t y_hotspot; uint32_t 512 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t ENABLE_MAGNIFICATION:1; uint32_t 513 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t INVERSE_TRANSPARENT_CLAMPING:1; uint32_t 514 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t HORIZONTAL_MIRROR:1; uint32_t 515 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t VERTICAL_MIRROR:1; uint32_t 516 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t INVERT_PIXEL_DATA:1; uint32_t 517 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t ZERO_EXPANSION:1; uint32_t 518 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t MIN_MAX_INVERT:1; uint32_t 519 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t ENABLE_CURSOR_DEGAMMA:1; uint32_t 520 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t RESERVED:24; uint32_t 522 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t value; uint32_t 527 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t pitch; uint32_t 530 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t width; uint32_t 531 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t height; uint32_t 534 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode uint32_t 612 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_taps; uint32_t 613 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_taps; uint32_t 614 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_taps_c; uint32_t 615 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_taps_c; uint32_t 683 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t INTERLACE :1; uint32_t 684 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1, uint32_t 686 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1, uint32_t 689 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t HORZ_COUNT_BY_TWO:1; uint32_t 691 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t EXCLUSIVE_3D :1; /* if this bit set, uint32_t 694 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity uint32_t 696 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled uint32_t 698 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View, uint32_t 700 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing uint32_t 702 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t Y_ONLY :1; uint32_t 704 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */ uint32_t 705 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t DTD_COUNTER :5; /* values 1 to 16 */ uint32_t 707 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t FORCE_HDR :1; uint32_t 711 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t LTE_340MCSC_SCRAMBLE:1; uint32_t 714 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t DSC : 1; /* Use DSC with this timing */ uint32_t 758 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_total_min; uint32_t 759 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_total_max; uint32_t 760 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_total_mid; uint32_t 761 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_total_mid_frame_num; uint32_t 766 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t num_slices_h; /* Number of DSC slices - horizontal */ uint32_t 767 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t num_slices_v; /* Number of DSC slices - vertical */ uint32_t 768 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ uint32_t 770 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t linebuf_depth; /* DSC line buffer depth */ uint32_t 771 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ uint32_t 777 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_total; uint32_t 778 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_border_left; uint32_t 779 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_addressable; uint32_t 780 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_border_right; uint32_t 781 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_front_porch; uint32_t 782 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_sync_width; uint32_t 784 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_total; uint32_t 785 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_border_top; uint32_t 786 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_addressable; uint32_t 787 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_border_bottom; uint32_t 788 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_front_porch; uint32_t 789 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t v_sync_width; uint32_t 791 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t pix_clk_100hz; uint32_t 793 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t vic; uint32_t 794 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t hdmi_vic; uint32_t 125 drivers/gpu/drm/amd/display/dc/dc_link.h uint32_t dongle_max_pix_clk; uint32_t 156 drivers/gpu/drm/amd/display/dc/dc_link.h static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) uint32_t 166 drivers/gpu/drm/amd/display/dc/dc_link.h uint32_t backlight_pwm_u16_16, uint32_t 167 drivers/gpu/drm/amd/display/dc/dc_link.h uint32_t frame_ramp); uint32_t 175 drivers/gpu/drm/amd/display/dc/dc_link.h bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); uint32_t 282 drivers/gpu/drm/amd/display/dc/dc_link.h uint32_t dc_link_bandwidth_kbps( uint32_t 291 drivers/gpu/drm/amd/display/dc/dc_link.h uint32_t link_index, uint32_t 294 drivers/gpu/drm/amd/display/dc/dc_link.h uint32_t dc_bandwidth_in_kbps_from_timing( uint32_t 69 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t dmdata_size; uint32_t 77 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t dmdata_qos_level; uint32_t 81 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t dmdata_dl_delta; uint32_t 83 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t *dmdata_sw_data; uint32_t 184 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode uint32_t 213 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t stream_id; uint32_t 282 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); uint32_t 296 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t *v_blank_start, uint32_t 297 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t *v_blank_end, uint32_t 298 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t *h_position, uint32_t 299 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t *v_position); uint32_t 342 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t dwb_pipe_inst); uint32_t 425 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t *r_cr, uint32_t 426 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t *g_y, uint32_t 427 drivers/gpu/drm/amd/display/dc/dc_stream.h uint32_t *b_cb); uint32_t 65 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t chip_id; uint32_t 66 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t chip_family; uint32_t 67 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t pci_revision_id; uint32_t 68 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t hw_internal_rev; uint32_t 69 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t vram_type; uint32_t 70 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t vram_width; uint32_t 71 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t feature_flags; uint32_t 72 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t fake_paths_num; uint32_t 100 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t dc_sink_id_count; uint32_t 101 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t dc_stream_id_count; uint32_t 176 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t length; uint32_t 212 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t serial_number; uint32_t 219 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t audio_mode_count; uint32_t 221 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t audio_latency; uint32_t 222 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t video_latency; uint32_t 239 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t width; uint32_t 240 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t height; uint32_t 245 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t INTERLACE :1; uint32_t 247 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t NATIVE :1; uint32_t 249 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t PREFERRED :1; uint32_t 252 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t REDUCED_BLANKING :1; uint32_t 254 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t VIDEO_OPTIMIZED_RATE :1; uint32_t 256 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t PACKED_PIXEL_FORMAT :1; uint32_t 258 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t PREFERRED_VIEW :1; uint32_t 260 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t TILED_MODE :1; uint32_t 261 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t DSE_MODE :1; uint32_t 266 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t MIRACAST_REFRESH_DIVIDER; uint32_t 328 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t pixel_width; uint32_t 329 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t pixel_height; uint32_t 330 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t field_rate; uint32_t 398 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t dp_hdmi_max_bpc; uint32_t 399 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t dp_hdmi_max_pixel_clk_in_khz; uint32_t 475 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t FL_FR:1; uint32_t 476 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t LFE:1; uint32_t 477 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t FC:1; uint32_t 478 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t RL_RR:1; uint32_t 479 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t RC:1; uint32_t 480 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t FLC_FRC:1; uint32_t 481 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t RLC_RRC:1; uint32_t 482 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t SUPPORT_AI:1; uint32_t 486 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t ALLSPEAKERS:7; uint32_t 487 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t SUPPORT_AI:1; uint32_t 546 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t video_latency; uint32_t 547 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t audio_latency; uint32_t 548 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t display_index; uint32_t 550 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t manufacture_id; uint32_t 551 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t product_id; uint32_t 553 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t port_id[2]; uint32_t 554 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t mode_count; uint32_t 736 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t max_clock_khz; uint32_t 737 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t min_clock_khz; uint32_t 738 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t bw_requirequired_clock_khz; uint32_t 739 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t current_clock_khz;/*current clock in use*/ uint32_t 805 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ uint32_t 808 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t branch_overall_throughput_0_mps; /* In MPs */ uint32_t 809 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t branch_overall_throughput_1_mps; /* In MPs */ uint32_t 810 drivers/gpu/drm/amd/display/dc/dc_types.h uint32_t branch_max_line_width; uint32_t 58 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id) uint32_t 61 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t rampingBoundary = 0xFFFF; uint32_t 89 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t round_result; uint32_t 90 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t pwm_period_cntl, bl_period, bl_int_count; uint32_t 91 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en; uint32_t 92 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t bl_period_mask, bl_pwm_mask; uint32_t 99 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); uint32_t 125 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c round_result = (uint32_t)(current_backlight & 0xFFFFFFFF); uint32_t 132 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c return (uint32_t)(current_backlight); uint32_t 136 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t backlight_pwm_u16_16) uint32_t 138 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t backlight_16bit; uint32_t 139 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t masked_pwm_period; uint32_t 142 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t pwm_period_bitcnt; uint32_t 202 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t backlight_pwm_u16_16, uint32_t 203 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t frame_ramp, uint32_t 204 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t controller_id) uint32_t 207 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t s2; uint32_t 313 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c static bool dce_abm_set_level(struct abm *abm, uint32_t level) uint32_t 358 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c uint32_t value; uint32_t 204 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_REG_FIELD_LIST(uint32_t); uint32_t 208 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t BL_PWM_PERIOD_CNTL; uint32_t 209 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t BL_PWM_CNTL; uint32_t 210 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t BL_PWM_CNTL2; uint32_t 211 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t LVTMA_PWRSEQ_REF_DIV; uint32_t 212 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t DC_ABM1_HG_SAMPLE_RATE; uint32_t 213 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t DC_ABM1_LS_SAMPLE_RATE; uint32_t 214 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; uint32_t 215 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t DC_ABM1_HG_MISC_CTRL; uint32_t 216 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t DC_ABM1_IPCSC_COEFF_SEL; uint32_t 217 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t BL1_PWM_CURRENT_ABM_LEVEL; uint32_t 218 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t BL1_PWM_TARGET_ABM_LEVEL; uint32_t 219 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t BL1_PWM_USER_LEVEL; uint32_t 220 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES; uint32_t 221 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS; uint32_t 222 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t MASTER_COMM_CNTL_REG; uint32_t 223 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t MASTER_COMM_CMD_REG; uint32_t 224 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t MASTER_COMM_DATA_REG1; uint32_t 225 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t BIOS_SCRATCH_2; uint32_t 226 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t BL_PWM_GRP1_REG_LOCK; uint32_t 58 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t reg_index, uint32_t 59 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t reg_data) uint32_t 75 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) uint32_t 79 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t value = 0; uint32_t 97 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t *format_index) uint32_t 99 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t index; uint32_t 100 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t max_channe_index = 0; uint32_t 134 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t channel_count, uint32_t 137 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t samples; uint32_t 138 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t h_blank; uint32_t 252 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t channel_count, uint32_t 261 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t channel_count, uint32_t 269 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t channel_count, uint32_t 297 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t value = 0; uint32_t 314 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t value = 0; uint32_t 334 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t value = 0; uint32_t 354 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); uint32_t 376 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t value; uint32_t 407 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; uint32_t 408 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t value; uint32_t 409 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t field = 0; uint32_t 411 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t format_index; uint32_t 412 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t index; uint32_t 415 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t strlen = 0; uint32_t 742 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t crtc_pixel_clock_100hz, uint32_t 743 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t actual_pixel_clock_100Hz, uint32_t 758 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t requested_pixel_clock_100Hz, uint32_t 788 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t src_sel; uint32_t 870 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t value; uint32_t 871 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t port_connectivity; uint32_t 887 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c uint32_t value; uint32_t 69 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t AZALIA_F0_CODEC_ENDPOINT_INDEX; uint32_t 70 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t AZALIA_F0_CODEC_ENDPOINT_DATA; uint32_t 72 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS; uint32_t 73 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES; uint32_t 74 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES; uint32_t 76 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO_SOURCE; uint32_t 77 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO0_MODULE; uint32_t 78 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO0_PHASE; uint32_t 79 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO1_MODULE; uint32_t 80 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO1_PHASE; uint32_t 82 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t AUDIO_RATE_CAPABILITIES; uint32_t 100 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO; uint32_t 101 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO; uint32_t 105 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t AZALIA_ENDPOINT_REG_INDEX; uint32_t 106 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t AZALIA_ENDPOINT_REG_DATA; uint32_t 108 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t AUDIO_RATE_CAPABILITIES; uint32_t 109 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t CLKSTOP; uint32_t 110 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t EPSS; uint32_t 112 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO0_SOURCE_SEL; uint32_t 113 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO_SEL; uint32_t 114 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO0_MODULE; uint32_t 115 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO0_PHASE; uint32_t 116 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO1_MODULE; uint32_t 117 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO1_PHASE; uint32_t 118 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO2_USE_512FBR_DTO; uint32_t 119 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO; uint32_t 120 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO; uint32_t 78 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t value = REG_READ(AUX_ARB_CONTROL); uint32_t 79 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t field = get_reg_field_value( uint32_t 91 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t value = REG_READ(AUX_ARB_CONTROL); uint32_t 92 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t field = get_reg_field_value( uint32_t 167 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t value; uint32_t 168 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t length; uint32_t 245 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t i = 0; uint32_t 260 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c static int read_channel_reply(struct dce_aux *engine, uint32_t size, uint32_t 262 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t *sw_status) uint32_t 265 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t bytes_replied; uint32_t 266 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t reply_result_32; uint32_t 290 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t i = 0; uint32_t 300 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t aux_sw_data_val; uint32_t 319 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t value; uint32_t 419 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t inst, uint32_t 420 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t timeout_period, uint32_t 461 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t status; uint32_t 53 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUX_CONTROL; uint32_t 54 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUX_ARB_CONTROL; uint32_t 55 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUX_SW_DATA; uint32_t 56 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUX_SW_CONTROL; uint32_t 57 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUX_INTERRUPT_CONTROL; uint32_t 58 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUX_SW_STATUS; uint32_t 59 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUXN_IMPCAL; uint32_t 60 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUXP_IMPCAL; uint32_t 62 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUX_RESET_MASK; uint32_t 92 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t inst; uint32_t 96 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t delay; uint32_t 97 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t max_defer_write_retry; uint32_t 106 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t aux_control; uint32_t 107 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t aux_arb_control; uint32_t 108 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t aux_sw_data; uint32_t 109 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t aux_sw_control; uint32_t 110 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t aux_interrupt_control; uint32_t 111 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t aux_sw_status; uint32_t 113 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t timeout_period; uint32_t 117 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t engine_id; uint32_t 118 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t timeout_period; uint32_t 126 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t inst, uint32_t 127 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t timeout_period, uint32_t 184 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context) uint32_t 186 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c uint32_t max_pix_clk = 0; uint32_t 544 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) uint32_t 547 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c uint32_t min_vertical_blank_time = -1; uint32_t 551 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c uint32_t vertical_blank_in_pixels = 0; uint32_t 552 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c uint32_t vertical_blank_time = 0; uint32_t 63 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t pix_clk_khz) uint32_t 66 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t entrys_num; uint32_t 67 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t i; uint32_t 137 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t target_pix_clk_100hz, uint32_t 138 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t ref_divider, uint32_t 139 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t post_divider, uint32_t 140 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t *feedback_divider_param, uint32_t 141 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t *fract_feedback_divider_param) uint32_t 197 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t ref_divider, uint32_t 198 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t post_divider, uint32_t 199 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t tolerance) uint32_t 201 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t feedback_divider; uint32_t 202 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t fract_feedback_divider; uint32_t 203 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t actual_calculated_clock_100hz; uint32_t 204 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t abs_err; uint32_t 225 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz); uint32_t 253 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t min_ref_divider, uint32_t 254 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t max_ref_divider, uint32_t 255 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t min_post_divider, uint32_t 256 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t max_post_divider, uint32_t 257 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t err_tolerance) uint32_t 259 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t ref_divider; uint32_t 260 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t post_divider; uint32_t 261 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t tolerance; uint32_t 292 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c static uint32_t calculate_pixel_clock_pll_dividers( uint32_t 296 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t err_tolerance; uint32_t 297 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t min_post_divider; uint32_t 298 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t max_post_divider; uint32_t 299 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t min_ref_divider; uint32_t 300 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t max_ref_divider; uint32_t 400 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t actual_pix_clk_100hz = 0; uint32_t 401 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t requested_clk_100hz = 0; uint32_t 474 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c static uint32_t dce110_get_pix_clk_dividers_helper ( uint32_t 479 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t field = 0; uint32_t 480 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; uint32_t 541 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t actual_pixel_clock_100hz; uint32_t 565 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c static uint32_t dce110_get_pix_clk_dividers( uint32_t 571 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; uint32_t 598 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c static uint32_t dce112_get_pix_clk_dividers( uint32_t 801 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t deep_color_cntl = 0; uint32_t 802 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t double_rate_enable = 0; uint32_t 1091 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t *ss_entries_num) uint32_t 1098 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t i; uint32_t 1237 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t i; uint32_t 147 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_REG_FIELD_LIST(uint32_t) uint32_t 151 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t RESYNC_CNTL; uint32_t 152 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t PIXCLK_RESYNC_CNTL; uint32_t 153 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t PLL_CNTL; uint32_t 158 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t PHASE[MAX_PIPES]; uint32_t 159 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t MODULO[MAX_PIPES]; uint32_t 160 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t PIXEL_RATE_CNTL[MAX_PIPES]; uint32_t 171 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t dp_ss_params_cnt; uint32_t 173 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t hdmi_ss_params_cnt; uint32_t 175 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t dvi_ss_params_cnt; uint32_t 177 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t lvds_ss_params_cnt; uint32_t 179 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t ext_clk_khz; uint32_t 180 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h uint32_t ref_freq_khz; uint32_t 96 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) uint32_t 100 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c uint32_t psr_state_offset = 0xf0; uint32_t 126 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c uint32_t psr_state = 0; uint32_t 325 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c uint32_t dmcu_version_offset = 0xf1; uint32_t 349 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c uint32_t fractional_pwm) uint32_t 481 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) uint32_t 485 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c uint32_t psr_state_offset = 0xf0; uint32_t 515 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c uint32_t psr_state = 0; uint32_t 156 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_REG_FIELD_LIST(uint32_t); uint32_t 160 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DMCU_CTRL; uint32_t 161 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DMCU_STATUS; uint32_t 162 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DMCU_RAM_ACCESS_CTRL; uint32_t 163 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DCI_MEM_PWR_STATUS; uint32_t 164 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DMU_MEM_PWR_CNTL; uint32_t 165 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DMCU_IRAM_WR_CTRL; uint32_t 166 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DMCU_IRAM_WR_DATA; uint32_t 168 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t MASTER_COMM_DATA_REG1; uint32_t 169 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t MASTER_COMM_DATA_REG2; uint32_t 170 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t MASTER_COMM_DATA_REG3; uint32_t 171 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t MASTER_COMM_CMD_REG; uint32_t 172 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t MASTER_COMM_CNTL_REG; uint32_t 173 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DMCU_IRAM_RD_CTRL; uint32_t 174 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DMCU_IRAM_RD_DATA; uint32_t 175 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; uint32_t 176 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t SMU_INTERRUPT_CONTROL; uint32_t 177 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t DC_DMCU_SCRATCH; uint32_t 274 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h static const uint32_t abm_gain_stepsize = 0x0060; uint32_t 51 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t lock_val = lock ? 1 : 0; uint32_t 52 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t dcp_grph, scl, blnd, update_lock_mode, val; uint32_t 82 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); uint32_t 92 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t feedthrough = 1; uint32_t 93 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t blnd_mode = 0; uint32_t 94 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t multiplied_mode = 0; uint32_t 95 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t alpha_mode = 2; uint32_t 175 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0; uint32_t 185 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0; uint32_t 337 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t LVTMA_PWRSEQ_CNTL; uint32_t 338 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t LVTMA_PWRSEQ_STATE; uint32_t 340 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCFE_CLOCK_CONTROL[6]; uint32_t 341 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCFEV_CLOCK_CONTROL; uint32_t 342 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; uint32_t 343 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t BLND_V_UPDATE_LOCK[6]; uint32_t 344 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t BLND_CONTROL[6]; uint32_t 345 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t BLNDV_CONTROL; uint32_t 346 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t CRTC_H_BLANK_START_END[6]; uint32_t 347 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t PIXEL_RATE_CNTL[6]; uint32_t 348 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; uint32_t 350 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUB_FB_LOCATION; uint32_t 351 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUB_AGP_BASE; uint32_t 352 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUB_AGP_BOT; uint32_t 353 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUB_AGP_TOP; uint32_t 355 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t REFCLK_CNTL; uint32_t 357 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; uint32_t 358 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUBBUB_SDPIF_FB_BASE; uint32_t 359 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUBBUB_SDPIF_FB_OFFSET; uint32_t 360 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUBBUB_SDPIF_AGP_BASE; uint32_t 361 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUBBUB_SDPIF_AGP_BOT; uint32_t 362 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUBBUB_SDPIF_AGP_TOP; uint32_t 363 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DC_IP_REQUEST_CNTL; uint32_t 364 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN0_PG_CONFIG; uint32_t 365 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN1_PG_CONFIG; uint32_t 366 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN2_PG_CONFIG; uint32_t 367 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN3_PG_CONFIG; uint32_t 368 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN4_PG_CONFIG; uint32_t 369 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN5_PG_CONFIG; uint32_t 370 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN6_PG_CONFIG; uint32_t 371 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN7_PG_CONFIG; uint32_t 372 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN8_PG_CONFIG; uint32_t 373 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN9_PG_CONFIG; uint32_t 374 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN10_PG_CONFIG; uint32_t 375 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN11_PG_CONFIG; uint32_t 376 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN16_PG_CONFIG; uint32_t 377 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN17_PG_CONFIG; uint32_t 378 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN18_PG_CONFIG; uint32_t 379 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN19_PG_CONFIG; uint32_t 380 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN20_PG_CONFIG; uint32_t 381 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN21_PG_CONFIG; uint32_t 382 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN0_PG_STATUS; uint32_t 383 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN1_PG_STATUS; uint32_t 384 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN2_PG_STATUS; uint32_t 385 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN3_PG_STATUS; uint32_t 386 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN4_PG_STATUS; uint32_t 387 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN5_PG_STATUS; uint32_t 388 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN6_PG_STATUS; uint32_t 389 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN7_PG_STATUS; uint32_t 390 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN8_PG_STATUS; uint32_t 391 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN9_PG_STATUS; uint32_t 392 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN10_PG_STATUS; uint32_t 393 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN11_PG_STATUS; uint32_t 394 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN16_PG_STATUS; uint32_t 395 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN17_PG_STATUS; uint32_t 396 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN18_PG_STATUS; uint32_t 397 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN19_PG_STATUS; uint32_t 398 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN20_PG_STATUS; uint32_t 399 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN21_PG_STATUS; uint32_t 400 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DIO_MEM_PWR_CTRL; uint32_t 401 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCCG_GATE_DISABLE_CNTL; uint32_t 402 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCCG_GATE_DISABLE_CNTL2; uint32_t 403 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCFCLK_CNTL; uint32_t 404 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MICROSECOND_TIME_BASE_DIV; uint32_t 405 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MILLISECOND_TIME_BASE_DIV; uint32_t 406 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DISPCLK_FREQ_CHANGE_CNTL; uint32_t 407 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t RBBMIF_TIMEOUT_DIS; uint32_t 408 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t RBBMIF_TIMEOUT_DIS_2; uint32_t 409 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DCHUBBUB_CRC_CTRL; uint32_t 410 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DPP_TOP0_DPP_CRC_CTRL; uint32_t 411 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; uint32_t 412 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; uint32_t 413 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MPC_CRC_CTRL; uint32_t 414 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MPC_CRC_RESULT_GB; uint32_t 415 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MPC_CRC_RESULT_C; uint32_t 416 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MPC_CRC_RESULT_AR; uint32_t 417 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t D1VGA_CONTROL; uint32_t 418 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t D2VGA_CONTROL; uint32_t 419 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t D3VGA_CONTROL; uint32_t 420 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t D4VGA_CONTROL; uint32_t 421 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t D5VGA_CONTROL; uint32_t 422 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t D6VGA_CONTROL; uint32_t 423 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t VGA_TEST_CONTROL; uint32_t 425 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; uint32_t 426 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; uint32_t 427 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; uint32_t 428 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; uint32_t 429 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; uint32_t 430 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; uint32_t 431 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; uint32_t 432 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; uint32_t 433 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; uint32_t 434 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; uint32_t 435 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; uint32_t 436 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; uint32_t 437 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t MC_VM_XGMI_LFB_CNTL; uint32_t 438 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t AZALIA_AUDIO_DTO; uint32_t 439 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t AZALIA_CONTROLLER_CLOCK_GATING; uint32_t 811 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_REG_FIELD_LIST(uint32_t) uint32_t 812 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_DCN_REG_FIELD_LIST(uint32_t) uint32_t 75 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t i2c_sw_status = 0; uint32_t 76 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t value = uint32_t 96 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c static uint32_t get_hw_buffer_available_size( uint32_t 103 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c static uint32_t get_speed( uint32_t 106 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t pre_scale = 0; uint32_t 121 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t length = reply->length; uint32_t 136 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t i2c_data; uint32_t 163 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t i2c_sw_status = 0; uint32_t 179 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t length = request->length; uint32_t 183 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t value = 0; uint32_t 279 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t speed) uint32_t 298 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE; uint32_t 300 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t reset_length = 0; uint32_t 357 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t i2c_sw_status = 0; uint32_t 383 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t counter = 0; uint32_t 385 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t current_speed; uint32_t 439 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t timeout, uint32_t 443 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t i = 0; uint32_t 483 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c static uint32_t get_transaction_timeout_hw( uint32_t 485 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t length) uint32_t 488 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t speed = get_speed(dce_i2c_hw); uint32_t 492 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t period_timeout; uint32_t 493 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t num_of_clock_stretches; uint32_t 516 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t transaction_timeout; uint32_t 618 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t engine_id, uint32_t 642 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t engine_id, uint32_t 648 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t xtal_ref_div = 0; uint32_t 677 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t engine_id, uint32_t 694 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t engine_id, uint32_t 712 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t engine_id, uint32_t 187 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_ENABLE; uint32_t 188 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_TIME_LIMIT; uint32_t 189 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_DATA_DRIVE_EN; uint32_t 190 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_CLK_DRIVE_EN; uint32_t 191 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL; uint32_t 192 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY; uint32_t 193 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY; uint32_t 194 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_HW_STATUS; uint32_t 195 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_DONE_USING_I2C_REG; uint32_t 196 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_USE_I2C_REG_REQ; uint32_t 197 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_NO_QUEUED_SW_GO; uint32_t 198 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_PRIORITY; uint32_t 199 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SOFT_RESET; uint32_t 200 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_STATUS_RESET; uint32_t 201 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_GO; uint32_t 202 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SEND_RESET; uint32_t 203 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_TRANSACTION_COUNT; uint32_t 204 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC_SELECT; uint32_t 205 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_PRESCALE; uint32_t 206 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_THRESHOLD; uint32_t 207 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL; uint32_t 208 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_STOPPED_ON_NACK; uint32_t 209 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_TIMEOUT; uint32_t 210 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_ABORTED; uint32_t 211 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_DONE; uint32_t 212 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_STATUS; uint32_t 213 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_STOP_ON_NACK0; uint32_t 214 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_START0; uint32_t 215 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_RW0; uint32_t 216 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_STOP0; uint32_t 217 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_COUNT0; uint32_t 218 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DATA_RW; uint32_t 219 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DATA; uint32_t 220 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_INDEX; uint32_t 221 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_INDEX_WRITE; uint32_t 222 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t XTAL_REF_DIV; uint32_t 224 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH; uint32_t 226 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_REG_RW_CNTL_STATUS; uint32_t 236 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t SETUP; uint32_t 237 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t SPEED; uint32_t 238 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t HW_STATUS; uint32_t 239 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_ARBITRATION; uint32_t 240 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_CONTROL; uint32_t 241 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_SW_STATUS; uint32_t 242 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_TRANSACTION0; uint32_t 243 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_TRANSACTION1; uint32_t 244 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_TRANSACTION2; uint32_t 245 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_TRANSACTION3; uint32_t 246 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t DC_I2C_DATA; uint32_t 247 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t MICROSECOND_TIME_BASE_DIV; uint32_t 259 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t length; uint32_t 265 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t original_speed; uint32_t 266 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t engine_keep_power_up_count; uint32_t 267 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t transaction_count; uint32_t 268 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t buffer_used_bytes; uint32_t 269 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t buffer_used_write; uint32_t 270 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t reference_frequency; uint32_t 271 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t default_speed; uint32_t 272 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t engine_id; uint32_t 273 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t setup_limit; uint32_t 274 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t send_reset_length; uint32_t 275 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t buffer_size; uint32_t 286 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t engine_id, uint32_t 294 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t engine_id, uint32_t 302 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t engine_id, uint32_t 310 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t engine_id, uint32_t 319 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h uint32_t engine_id, uint32_t 45 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t value = 0; uint32_t 60 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t value = bit ? 1 : 0; uint32_t 106 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t scl_retry = 0; uint32_t 107 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4; uint32_t 244 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t retry = 0; uint32_t 281 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t length, uint32_t 284 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t i = 0; uint32_t 303 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t length, uint32_t 306 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t i = 0; uint32_t 328 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t retry = 0; uint32_t 369 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t speed) uint32_t 401 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c uint32_t counter = 0; uint32_t 38 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h uint32_t clock_delay; uint32_t 39 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h uint32_t speed; uint32_t 224 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; uint32_t 195 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_REG_FIELD_LIST(uint32_t); uint32_t 199 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_UPDATE; uint32_t 200 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_CONTROL; uint32_t 201 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_POSITION; uint32_t 202 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_HOT_SPOT; uint32_t 203 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_COLOR1; uint32_t 204 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_COLOR2; uint32_t 205 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_SIZE; uint32_t 206 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_SURFACE_ADDRESS_HIGH; uint32_t 207 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_SURFACE_ADDRESS; uint32_t 208 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t PRESCALE_GRPH_CONTROL; uint32_t 209 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t PRESCALE_VALUES_GRPH_R; uint32_t 210 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t PRESCALE_VALUES_GRPH_G; uint32_t 211 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t PRESCALE_VALUES_GRPH_B; uint32_t 212 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t INPUT_GAMMA_CONTROL; uint32_t 213 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t DCFE_MEM_PWR_CTRL; uint32_t 214 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t DC_LUT_WRITE_EN_MASK; uint32_t 215 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t DC_LUT_RW_MODE; uint32_t 216 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t DC_LUT_CONTROL; uint32_t 217 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t DC_LUT_RW_INDEX; uint32_t 218 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t DC_LUT_SEQ_COLOR; uint32_t 219 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t DEGAMMA_CONTROL; uint32_t 239 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t index) uint32_t 262 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t value; uint32_t 497 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t addr = AUX_REG(AUX_CONTROL); uint32_t 498 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t value = dm_read_reg(ctx, addr); uint32_t 551 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t value; uint32_t 585 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; uint32_t 920 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t pixel_clock) uint32_t 956 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t pixel_clock) uint32_t 1212 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t *src, uint32_t 1213 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t *slots) uint32_t 1232 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t value0 = 0; uint32_t 1233 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t value1 = 0; uint32_t 1234 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t value2 = 0; uint32_t 1235 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t slots = 0; uint32_t 1236 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t src = 0; uint32_t 1237 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t retries = 0; uint32_t 1354 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t field; uint32_t 1373 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t addr = HPD_REG(DC_HPD_CONTROL); uint32_t 1374 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t hpd_enable = 0; uint32_t 1375 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t value = dm_read_reg(ctx, addr); uint32_t 1387 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t addr = HPD_REG(DC_HPD_CONTROL); uint32_t 1388 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t value = dm_read_reg(ctx, addr); uint32_t 108 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t AUX_CONTROL; uint32_t 109 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t AUX_DPHY_RX_CONTROL0; uint32_t 113 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DC_HPD_CONTROL; uint32_t 118 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t MASTER_COMM_DATA_REG1; uint32_t 119 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t MASTER_COMM_DATA_REG2; uint32_t 120 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t MASTER_COMM_DATA_REG3; uint32_t 121 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t MASTER_COMM_CMD_REG; uint32_t 122 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t MASTER_COMM_CNTL_REG; uint32_t 123 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DMCU_RAM_ACCESS_CTRL; uint32_t 124 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DCI_MEM_PWR_STATUS; uint32_t 125 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DMU_MEM_PWR_CNTL; uint32_t 126 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DMCU_IRAM_RD_CTRL; uint32_t 127 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DMCU_IRAM_RD_DATA; uint32_t 128 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; uint32_t 131 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DIG_BE_CNTL; uint32_t 132 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DIG_BE_EN_CNTL; uint32_t 133 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_CONFIG; uint32_t 134 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_CNTL; uint32_t 135 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_INTERNAL_CTRL; uint32_t 136 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_PRBS_CNTL; uint32_t 137 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_SCRAM_CNTL; uint32_t 138 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_SYM0; uint32_t 139 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_SYM1; uint32_t 140 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_SYM2; uint32_t 141 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_TRAINING_PATTERN_SEL; uint32_t 142 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_LINK_CNTL; uint32_t 143 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_LINK_FRAMING_CNTL; uint32_t 144 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_MSE_SAT0; uint32_t 145 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_MSE_SAT1; uint32_t 146 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_MSE_SAT2; uint32_t 147 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_MSE_SAT_UPDATE; uint32_t 148 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_SEC_CNTL; uint32_t 149 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_VID_STREAM_CNTL; uint32_t 150 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_FAST_TRAINING; uint32_t 151 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_BS_SR_SWAP_CNTL; uint32_t 152 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; uint32_t 153 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_SEC_CNTL1; uint32_t 214 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t pixel_clock); uint32_t 232 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t pixel_clock); uint32_t 260 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t index); uint32_t 165 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t wm_select, uint32_t 166 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t urgency_low_wm, uint32_t 167 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t urgency_high_wm) uint32_t 179 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t wm_select, uint32_t 180 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t urgency_low_wm, uint32_t 181 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t urgency_high_wm) uint32_t 198 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t wm_select, uint32_t 199 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t nbp_wm) uint32_t 230 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t wm_select, uint32_t 231 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t stutter_mark, uint32_t 232 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t stutter_entry) uint32_t 249 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t wm_select, uint32_t 250 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t stutter_mark) uint32_t 269 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t total_dest_line_time_ns) uint32_t 272 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1; uint32_t 294 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t total_dest_line_time_ns) uint32_t 297 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1; uint32_t 327 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t total_dest_line_time_ns) uint32_t 330 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1; uint32_t 398 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = { uint32_t 436 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t red_xbar = 0, blue_xbar = 0; /* no swap */ uint32_t 437 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t grph_depth = 0, grph_format = 0; uint32_t 438 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t sign = 0, floating = 0; uint32_t 524 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c static uint32_t get_dmif_switch_time_us( uint32_t 525 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t h_total, uint32_t 526 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t v_total, uint32_t 527 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t pix_clk_khz) uint32_t 529 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t frame_time; uint32_t 530 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t pixels_per_second; uint32_t 531 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t pixels_per_frame; uint32_t 532 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t refresh_rate; uint32_t 533 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c const uint32_t us_in_sec = 1000000; uint32_t 534 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c const uint32_t min_single_frame_time_us = 30000; uint32_t 536 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c const uint32_t single_frame_time_multiplier = 2; uint32_t 572 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t h_total, uint32_t 573 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t v_total, uint32_t 574 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t pix_clk_khz, uint32_t 575 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t total_stream_num) uint32_t 578 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c const uint32_t retry_delay = 10; uint32_t 579 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t retry_count = get_dmif_switch_time_us( uint32_t 584 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t pix_dur; uint32_t 585 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t buffers_allocated; uint32_t 586 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t dmif_buffer_control; uint32_t 609 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t eanble = (total_stream_num > 1) ? 0 : uint32_t 619 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t total_stream_num) uint32_t 622 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t buffers_allocated; uint32_t 623 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t dmif_buffer_control; uint32_t 639 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t eanble = (total_stream_num > 1) ? 0 : uint32_t 680 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c uint32_t update_pending; uint32_t 86 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_ENABLE; uint32_t 87 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_CONTROL; uint32_t 88 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_X_START; uint32_t 89 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_Y_START; uint32_t 90 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_X_END; uint32_t 91 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_Y_END; uint32_t 92 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_PITCH; uint32_t 93 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t HW_ROTATION; uint32_t 94 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_SWAP_CNTL; uint32_t 95 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t PRESCALE_GRPH_CONTROL; uint32_t 96 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; uint32_t 97 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DVMM_PTE_CONTROL; uint32_t 98 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DVMM_PTE_ARB_CONTROL; uint32_t 99 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_UPDATE; uint32_t 100 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_FLIP_CONTROL; uint32_t 101 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_PRIMARY_SURFACE_ADDRESS; uint32_t 102 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; uint32_t 103 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_SECONDARY_SURFACE_ADDRESS; uint32_t 104 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; uint32_t 106 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_PIPE_ARBITRATION_CONTROL1; uint32_t 107 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_WATERMARK_MASK_CONTROL; uint32_t 108 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_PIPE_URGENCY_CONTROL; uint32_t 109 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL; uint32_t 110 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL; uint32_t 111 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_PIPE_LOW_POWER_CONTROL; uint32_t 112 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_PIPE_STUTTER_CONTROL; uint32_t 113 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_PIPE_STUTTER_CONTROL2; uint32_t 115 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DMIF_BUFFER_CONTROL; uint32_t 117 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t MC_HUB_RDREQ_DMIF_LIMIT; uint32_t 119 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DCHUB_FB_LOCATION; uint32_t 120 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DCHUB_AGP_BASE; uint32_t 121 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DCHUB_AGP_BOT; uint32_t 122 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DCHUB_AGP_TOP; uint32_t 323 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_REG_FIELD_LIST(uint32_t) uint32_t 435 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c uint32_t fmt_mem_cntl_value; uint32_t 546 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c uint32_t inst, uint32_t 244 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_REG_FIELD_LIST(uint32_t) uint32_t 248 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_DYNAMIC_EXP_CNTL; uint32_t 249 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_BIT_DEPTH_CONTROL; uint32_t 250 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_CONTROL; uint32_t 251 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_DITHER_RAND_R_SEED; uint32_t 252 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_DITHER_RAND_G_SEED; uint32_t 253 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_DITHER_RAND_B_SEED; uint32_t 254 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL; uint32_t 255 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX; uint32_t 256 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX; uint32_t 257 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t CONTROL; uint32_t 258 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_CLAMP_CNTL; uint32_t 259 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_CLAMP_COMPONENT_R; uint32_t 260 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_CLAMP_COMPONENT_G; uint32_t 261 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_CLAMP_COMPONENT_B; uint32_t 277 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t inst, uint32_t 67 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t packet_index, uint32_t 70 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t regval; uint32_t 74 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t max_retries = 50; uint32_t 121 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c const uint32_t *content = uint32_t 122 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c (const uint32_t *) &info_packet->sb[0]; uint32_t 184 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t packet_index, uint32_t 187 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t cont, send, line; uint32_t 278 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t enable_sdp_splitting) uint32_t 281 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t h_active_start; uint32_t 282 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t v_active_start; uint32_t 283 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t misc0 = 0; uint32_t 284 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t misc1 = 0; uint32_t 285 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t h_blank; uint32_t 286 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t h_back_porch; uint32_t 717 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t x = dc_fixpt_floor( uint32_t 719 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t y = dc_fixpt_ceil( uint32_t 750 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c const uint32_t *content = uint32_t 751 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c (const uint32_t *) &info_frame->avi.sb[0]; uint32_t 854 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t value = 0; uint32_t 898 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t value = 0; uint32_t 924 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t reg1 = 0; uint32_t 925 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; uint32_t 975 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t n_vid = 0x8000; uint32_t 976 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t m_vid; uint32_t 989 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c m_vid = (uint32_t) m_vid_l; uint32_t 1136 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t FL:1; uint32_t 1137 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t FR:1; uint32_t 1138 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t LFE:1; uint32_t 1139 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t FC:1; uint32_t 1140 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t RL_RC:1; uint32_t 1141 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t RR:1; uint32_t 1142 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t RC_RLC_FLC:1; uint32_t 1143 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t RRC_FRC:1; uint32_t 1249 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c static uint32_t calc_max_audio_packets_per_line( uint32_t 1252 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t max_packets_per_line; uint32_t 1272 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t crtc_pixel_clock_100Hz, uint32_t 1273 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t actual_pixel_clock_100Hz, uint32_t 1277 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t index; uint32_t 1278 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; uint32_t 1279 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t audio_array_size; uint32_t 1338 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t speakers = 0; uint32_t 1339 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t channels = 0; uint32_t 1363 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t max_packets_per_line; uint32_t 1519 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t value = 0; uint32_t 1608 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t tg_inst = 0; uint32_t 503 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_INDEX; uint32_t 504 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC0_UPDATE; uint32_t 505 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC2_UPDATE; uint32_t 506 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_HB0; uint32_t 507 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_HB1; uint32_t 508 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_HB2; uint32_t 509 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_HB3; uint32_t 510 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_LOCK_STATUS; uint32_t 511 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_CONFLICT; uint32_t 512 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_CONFLICT_CLR; uint32_t 513 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING; uint32_t 514 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING; uint32_t 515 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING; uint32_t 516 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING; uint32_t 517 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING; uint32_t 518 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING; uint32_t 519 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING; uint32_t 520 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING; uint32_t 521 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC0_FRAME_UPDATE; uint32_t 522 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC1_FRAME_UPDATE; uint32_t 523 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC2_FRAME_UPDATE; uint32_t 524 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC3_FRAME_UPDATE; uint32_t 525 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC4_FRAME_UPDATE; uint32_t 526 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC5_FRAME_UPDATE; uint32_t 527 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC6_FRAME_UPDATE; uint32_t 528 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC7_FRAME_UPDATE; uint32_t 529 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC0_CONT; uint32_t 530 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC0_SEND; uint32_t 531 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC0_LINE; uint32_t 532 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC1_CONT; uint32_t 533 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC1_SEND; uint32_t 534 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC1_LINE; uint32_t 535 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_PIXEL_ENCODING; uint32_t 536 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_COMPONENT_DEPTH; uint32_t 537 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_DYN_RANGE; uint32_t 538 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_YCBCR_RANGE; uint32_t 539 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_PACKET_GEN_VERSION; uint32_t 540 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_KEEPOUT_MODE; uint32_t 541 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_DEEP_COLOR_ENABLE; uint32_t 542 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_CLOCK_CHANNEL_RATE; uint32_t 543 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_DEEP_COLOR_DEPTH; uint32_t 544 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GC_CONT; uint32_t 545 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GC_SEND; uint32_t 546 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_NULL_SEND; uint32_t 547 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_DATA_SCRAMBLE_EN; uint32_t 548 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_AUDIO_INFO_SEND; uint32_t 549 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AUDIO_INFO_UPDATE; uint32_t 550 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_AUDIO_INFO_LINE; uint32_t 551 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GC_AVMUTE; uint32_t 552 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSE_RATE_X; uint32_t 553 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSE_RATE_Y; uint32_t 554 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSE_RATE_UPDATE_PENDING; uint32_t 555 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AVI_INFO_VERSION; uint32_t 556 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_AVI_INFO_SEND; uint32_t 557 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_AVI_INFO_CONT; uint32_t 558 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_AVI_INFO_LINE; uint32_t 559 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_GSP0_ENABLE; uint32_t 560 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_STREAM_ENABLE; uint32_t 561 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_GSP1_ENABLE; uint32_t 562 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_GSP2_ENABLE; uint32_t 563 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_GSP3_ENABLE; uint32_t 564 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_GSP4_ENABLE; uint32_t 565 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_GSP5_ENABLE; uint32_t 566 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_GSP6_ENABLE; uint32_t 567 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_GSP7_ENABLE; uint32_t 568 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_AVI_ENABLE; uint32_t 569 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_MPG_ENABLE; uint32_t 570 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_STREAM_DIS_DEFER; uint32_t 571 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_STREAM_ENABLE; uint32_t 572 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_STREAM_STATUS; uint32_t 573 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_STEER_FIFO_RESET; uint32_t 574 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_M_N_GEN_EN; uint32_t 575 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_N; uint32_t 576 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_M; uint32_t 577 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DIG_START; uint32_t 578 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AUDIO_SRC_SELECT; uint32_t 579 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AUDIO_CHANNEL_ENABLE; uint32_t 580 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_AUDIO_PACKETS_PER_LINE; uint32_t 581 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_AUDIO_DELAY_EN; uint32_t 582 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_UPDATE; uint32_t 583 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AUDIO_LAYOUT_OVRD; uint32_t 584 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_OSF_OVRD; uint32_t 585 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_AUTO_SEND; uint32_t 586 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_SOURCE; uint32_t 587 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_AUDIO_PRIORITY; uint32_t 588 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_CTS_32; uint32_t 589 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_N_32; uint32_t 590 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_CTS_44; uint32_t 591 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_N_44; uint32_t 592 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_CTS_48; uint32_t 593 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_N_48; uint32_t 594 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L; uint32_t 595 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_CLOCK_ACCURACY; uint32_t 596 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R; uint32_t 597 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2; uint32_t 598 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3; uint32_t 599 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4; uint32_t 600 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5; uint32_t 601 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6; uint32_t 602 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7; uint32_t 603 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_AUD_N; uint32_t 604 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_TIMESTAMP_MODE; uint32_t 605 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_ASP_ENABLE; uint32_t 606 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_ATP_ENABLE; uint32_t 607 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_AIP_ENABLE; uint32_t 608 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_ACM_ENABLE; uint32_t 609 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AUDIO_SAMPLE_SEND; uint32_t 610 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AUDIO_CLOCK_EN; uint32_t 611 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t TMDS_PIXEL_ENCODING; uint32_t 612 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DIG_STEREOSYNC_SELECT; uint32_t 613 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DIG_STEREOSYNC_GATE_EN; uint32_t 614 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t TMDS_COLOR_FORMAT; uint32_t 615 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_DB_DISABLE; uint32_t 616 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_MISC0; uint32_t 617 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_HTOTAL; uint32_t 618 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_VTOTAL; uint32_t 619 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_HSTART; uint32_t 620 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_VSTART; uint32_t 621 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_HSYNCWIDTH; uint32_t 622 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_HSYNCPOLARITY; uint32_t 623 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_VSYNCWIDTH; uint32_t 624 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_VSYNCPOLARITY; uint32_t 625 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_HWIDTH; uint32_t 626 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_VHEIGHT; uint32_t 627 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_DB_DISABLE; uint32_t 628 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_N_MUL; uint32_t 629 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_M_DOUBLE_VALUE_EN; uint32_t 630 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DIG_SOURCE_SELECT; uint32_t 634 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_CNTL; uint32_t 635 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AVI_INFO0; uint32_t 636 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AVI_INFO1; uint32_t 637 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AVI_INFO2; uint32_t 638 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AVI_INFO3; uint32_t 639 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_0; uint32_t 640 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_1; uint32_t 641 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_2; uint32_t 642 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_3; uint32_t 643 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_4; uint32_t 644 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_5; uint32_t 645 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_6; uint32_t 646 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_7; uint32_t 647 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_GENERIC_HDR; uint32_t 648 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_INFOFRAME_CONTROL0; uint32_t 649 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_VBI_PACKET_CONTROL; uint32_t 650 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_VBI_PACKET_CONTROL1; uint32_t 651 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AUDIO_PACKET_CONTROL; uint32_t 652 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AUDIO_PACKET_CONTROL2; uint32_t 653 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_AUDIO_SRC_CONTROL; uint32_t 654 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_0; uint32_t 655 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_1; uint32_t 656 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t AFMT_60958_2; uint32_t 657 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DIG_FE_CNTL; uint32_t 658 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSE_RATE_CNTL; uint32_t 659 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSE_RATE_UPDATE; uint32_t 660 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_PIXEL_FORMAT; uint32_t 661 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_CNTL; uint32_t 662 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_STEER_FIFO; uint32_t 663 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_M; uint32_t 664 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_N; uint32_t 665 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_STREAM_CNTL; uint32_t 666 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_VID_TIMING; uint32_t 667 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_AUD_N; uint32_t 668 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_TIMESTAMP; uint32_t 669 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_CONTROL; uint32_t 670 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GC; uint32_t 671 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL0; uint32_t 672 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL1; uint32_t 673 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL2; uint32_t 674 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL3; uint32_t 675 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_INFOFRAME_CONTROL0; uint32_t 676 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_INFOFRAME_CONTROL1; uint32_t 677 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_VBI_PACKET_CONTROL; uint32_t 678 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_AUDIO_PACKET_CONTROL; uint32_t 679 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_PACKET_CONTROL; uint32_t 680 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_32_0; uint32_t 681 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_32_1; uint32_t 682 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_44_0; uint32_t 683 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_44_1; uint32_t 684 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_48_0; uint32_t 685 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_48_1; uint32_t 686 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t TMDS_CNTL; uint32_t 687 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_DB_CNTL; uint32_t 688 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_MISC; uint32_t 689 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_COLORIMETRY; uint32_t 690 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_TIMING_PARAM1; uint32_t 691 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_TIMING_PARAM2; uint32_t 692 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_TIMING_PARAM3; uint32_t 693 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_MSA_TIMING_PARAM4; uint32_t 694 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_DB_CONTROL; uint32_t 191 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c uint32_t power_ctl = 0; uint32_t 869 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c static uint32_t decide_taps(struct fixed31_32 ratio, uint32_t in_taps, bool chroma) uint32_t 871 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c uint32_t taps; uint32_t 1106 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c uint32_t i; uint32_t 1143 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c uint32_t i = 0; uint32_t 1345 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c uint32_t inst, uint32_t 382 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_REG_FIELD_LIST(uint32_t); uint32_t 386 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t LB_DATA_FORMAT; uint32_t 387 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t GAMUT_REMAP_CONTROL; uint32_t 388 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t GAMUT_REMAP_C11_C12; uint32_t 389 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t GAMUT_REMAP_C13_C14; uint32_t 390 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t GAMUT_REMAP_C21_C22; uint32_t 391 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t GAMUT_REMAP_C23_C24; uint32_t 392 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t GAMUT_REMAP_C31_C32; uint32_t 393 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t GAMUT_REMAP_C33_C34; uint32_t 394 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUTPUT_CSC_C11_C12; uint32_t 395 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUTPUT_CSC_C13_C14; uint32_t 396 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUTPUT_CSC_C21_C22; uint32_t 397 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUTPUT_CSC_C23_C24; uint32_t 398 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUTPUT_CSC_C31_C32; uint32_t 399 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUTPUT_CSC_C33_C34; uint32_t 400 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUTPUT_CSC_CONTROL; uint32_t 401 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL; uint32_t 402 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_START_CNTL; uint32_t 403 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_SLOPE_CNTL; uint32_t 404 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_END_CNTL1; uint32_t 405 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_END_CNTL2; uint32_t 406 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_REGION_0_1; uint32_t 407 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_REGION_2_3; uint32_t 408 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_REGION_4_5; uint32_t 409 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_REGION_6_7; uint32_t 410 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_REGION_8_9; uint32_t 411 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_REGION_10_11; uint32_t 412 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_REGION_12_13; uint32_t 413 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CNTLA_REGION_14_15; uint32_t 414 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_LUT_WRITE_EN_MASK; uint32_t 415 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_LUT_INDEX; uint32_t 416 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_LUT_DATA; uint32_t 417 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t REGAMMA_CONTROL; uint32_t 418 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t DENORM_CONTROL; uint32_t 419 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t DCP_SPATIAL_DITHER_CNTL; uint32_t 420 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUT_ROUND_CONTROL; uint32_t 421 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUT_CLAMP_CONTROL_R_CR; uint32_t 422 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUT_CLAMP_CONTROL_G_Y; uint32_t 423 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t OUT_CLAMP_CONTROL_B_CB; uint32_t 424 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_MODE; uint32_t 425 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_TAP_CONTROL; uint32_t 426 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_CONTROL; uint32_t 427 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_BYPASS_CONTROL; uint32_t 428 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t EXT_OVERSCAN_LEFT_RIGHT; uint32_t 429 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t EXT_OVERSCAN_TOP_BOTTOM; uint32_t 430 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_VERT_FILTER_CONTROL; uint32_t 431 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_HORZ_FILTER_CONTROL; uint32_t 432 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t DCFE_MEM_PWR_CTRL; uint32_t 433 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t DCFE_MEM_PWR_STATUS; uint32_t 434 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_COEF_RAM_SELECT; uint32_t 435 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_COEF_RAM_TAP_DATA; uint32_t 436 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t VIEWPORT_START; uint32_t 437 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t VIEWPORT_SIZE; uint32_t 438 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_HORZ_FILTER_SCALE_RATIO; uint32_t 439 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_VERT_FILTER_SCALE_RATIO; uint32_t 440 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_HORZ_FILTER_INIT; uint32_t 441 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_VERT_FILTER_INIT; uint32_t 442 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_AUTOMATIC_MODE_CONTROL; uint32_t 443 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t LB_MEMORY_CTRL; uint32_t 444 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_UPDATE; uint32_t 445 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_F_SHARP_CONTROL; uint32_t 449 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t integer; uint32_t 450 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t fraction; uint32_t 454 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t h_int_scale_ratio; uint32_t 455 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t v_int_scale_ratio; uint32_t 487 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t inst, uint32_t 40 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c uint32_t blnd; uint32_t 41 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c uint32_t crtc; uint32_t 422 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c uint32_t instance, uint32_t 511 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c uint32_t inst) uint32_t 534 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c uint32_t inst) uint32_t 548 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 589 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c uint32_t inst) uint32_t 604 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c uint32_t inst) uint32_t 639 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c uint32_t inst) uint32_t 68 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c static uint32_t align_to_chunks_number_per_line(uint32_t pixels) uint32_t 73 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c static void reset_lb_on_vblank(struct compressor *compressor, uint32_t crtc_inst) uint32_t 75 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t value; uint32_t 76 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t frame_count; uint32_t 77 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t status_pos; uint32_t 78 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t retry = 0; uint32_t 117 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t counter = 0; uint32_t 118 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t addr = mmFBC_STATUS; uint32_t 119 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t value; uint32_t 144 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t value; uint32_t 145 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t addr; uint32_t 197 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t addr; uint32_t 198 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t value, misc_value; uint32_t 244 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t crtc_inst = 0; uint32_t 248 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t reg_data; uint32_t 270 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t *inst) uint32_t 273 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t value; uint32_t 302 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t value = 0; uint32_t 303 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t fbc_pitch = 0; uint32_t 304 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t compressed_surf_address_low_part = uint32_t 348 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t fbc_trigger) uint32_t 353 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t addr = mmFBC_CLIENT_REGION_MASK; uint32_t 354 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t value = dm_read_reg(compressor->ctx, addr); uint32_t 34 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h uint32_t dcp_offset; uint32_t 35 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h uint32_t dmif_offset; uint32_t 59 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h uint32_t fbc_trigger); uint32_t 66 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h uint32_t *fbc_mapped_crtc_id); uint32_t 86 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t crtc; uint32_t 119 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t addr; uint32_t 120 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t value = 0; uint32_t 121 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t chunk_int = 0; uint32_t 122 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t chunk_mul = 0; uint32_t 324 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t hw_points_num) uint32_t 330 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t i = 0; uint32_t 441 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; uint32_t 659 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t active_total_with_borders; uint32_t 660 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t early_control = 0; uint32_t 700 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t value; uint32_t 709 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t pwr_seq_state, dig_on, dig_on_ovrd; uint32_t 742 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t time_elapsed = 0; uint32_t 743 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t timeout = power_up ? uint32_t 778 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t detected = 0; uint32_t 1196 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; uint32_t 1629 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static uint32_t compute_pstate_blackout_duration( uint32_t 1633 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t total_dest_line_time_ns; uint32_t 1634 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t pstate_blackout_duration_ns; uint32_t 1655 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t total_dest_line_time_ns; uint32_t 1792 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t *pipe_idx) uint32_t 1794 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t i; uint32_t 1858 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t pipe_idx = 0; uint32_t 2252 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c const uint32_t frames_to_wait_on_triggered_reset = 10; uint32_t 2253 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t i; uint32_t 42 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value = 0; uint32_t 63 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value = 0; uint32_t 64 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t temp = 0; uint32_t 98 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value = 0; uint32_t 99 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t temp = 0; uint32_t 155 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value = 0; uint32_t 169 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value = 0; uint32_t 234 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value = 0; uint32_t 366 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value; uint32_t 439 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value; uint32_t 474 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value; uint32_t 581 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value = 0; uint32_t 655 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c const uint32_t urgency_addr, uint32_t 656 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c const uint32_t wm_addr, uint32_t 658 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t total_dest_line_time_ns) uint32_t 661 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t urgency_cntl = 0; uint32_t 662 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t wm_mask_cntl = 0; uint32_t 713 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t total_dest_line_time_ns) uint32_t 726 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t total_dest_line_time_ns) uint32_t 738 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c const uint32_t stutter_addr, uint32_t 739 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c const uint32_t wm_addr, uint32_t 743 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t stutter_cntl = 0; uint32_t 744 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t wm_mask_cntl = 0; uint32_t 820 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c const uint32_t wm_mask_ctrl_addr, uint32_t 821 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c const uint32_t nbp_pstate_ctrl_addr, uint32_t 824 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value; uint32_t 928 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t total_dest_line_time_ns) uint32_t 950 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t total_dest_line_time_ns) uint32_t 968 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t h_total,/* for current stream */ uint32_t 969 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t v_total,/* for current stream */ uint32_t 970 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t pix_clk_khz,/* for current stream */ uint32_t 971 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t total_stream_num) uint32_t 973 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t addr; uint32_t 974 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t value; uint32_t 975 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t pix_dur; uint32_t 1010 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c uint32_t total_stream_num) uint32_t 114 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL); uint32_t 127 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 128 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C11_C12_A; uint32_t 145 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 146 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C13_C14_A; uint32_t 163 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 164 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C21_C22_A; uint32_t 181 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 182 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C23_C24_A; uint32_t 199 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 200 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C31_C32_A; uint32_t 217 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 218 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C33_C34_A; uint32_t 241 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 242 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C11_C12_B; uint32_t 259 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 260 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C13_C14_B; uint32_t 277 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 278 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C21_C22_B; uint32_t 295 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 296 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C23_C24_B; uint32_t 313 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 314 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C31_C32_B; uint32_t 331 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = 0; uint32_t 332 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmOUTPUT_CSC_C33_C34_B; uint32_t 365 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t addr = mmCOL_MAN_OUTPUT_CSC_CONTROL; uint32_t 366 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = dm_read_reg(ctx, addr); uint32_t 465 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL); uint32_t 508 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t regval[12]; uint32_t 536 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c const uint32_t *regval = NULL; uint32_t 538 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t value; uint32_t 684 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t i; uint32_t 39 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); uint32_t 88 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c uint32_t value; uint32_t 103 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c static void configure_regamma_mode(struct dce_transform *xfm_dce, uint32_t mode) uint32_t 105 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c uint32_t value = 0; uint32_t 136 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c uint32_t value = 0; uint32_t 456 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c uint32_t value = 0; uint32_t 472 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c const uint32_t addr = mmGAMMA_CORR_LUT_DATA; uint32_t 473 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c uint32_t i = 0; uint32_t 523 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); uint32_t 463 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c uint32_t instance, uint32_t 557 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c uint32_t inst) uint32_t 580 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c uint32_t inst) uint32_t 594 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 635 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c uint32_t inst) uint32_t 650 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c uint32_t inst) uint32_t 685 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c uint32_t inst) uint32_t 94 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = 0; uint32_t 95 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 96 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t field = 0; uint32_t 107 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t early_cntl) uint32_t 109 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t regval; uint32_t 111 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t address = CRTC_REG(mmCRTC_CONTROL); uint32_t 128 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 156 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR); uint32_t 157 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 192 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = CRTC_REG(mmCRTC_3D_STRUCTURE_CONTROL); uint32_t 193 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 194 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t test = 0; uint32_t 195 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t field = 0; uint32_t 196 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t struc_en = 0; uint32_t 197 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t struc_stereo_sel_ovr = 0; uint32_t 259 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t regval; uint32_t 290 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t vsync_offset = dc_crtc_timing->v_border_bottom + uint32_t 292 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t v_sync_start =dc_crtc_timing->v_addressable + vsync_offset; uint32_t 294 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t hsync_offset = dc_crtc_timing->h_border_right + uint32_t 296 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset; uint32_t 371 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t v_total_min = 0; uint32_t 372 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t v_total_max = 0; uint32_t 373 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t v_total_cntl = 0; uint32_t 376 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = 0; uint32_t 472 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value) uint32_t 475 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t static_screen_cntl = 0; uint32_t 476 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = 0; uint32_t 508 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg) uint32_t 511 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = CRTC_REG(mmCRTC_STATUS_FRAME_COUNT); uint32_t 512 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 513 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t field = get_reg_field_value( uint32_t 532 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value; uint32_t 567 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t *v_blank_start, uint32_t 568 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t *v_blank_end, uint32_t 569 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t *h_position, uint32_t 570 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t *v_position) uint32_t 575 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = dm_read_reg(tg->ctx, uint32_t 600 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t vsync_offset = timing->v_border_bottom + uint32_t 602 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t v_sync_start =timing->v_addressable + vsync_offset; uint32_t 604 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t hsync_offset = timing->h_border_right + uint32_t 606 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t h_sync_start = timing->h_addressable + hsync_offset; uint32_t 610 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 611 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = 0; uint32_t 612 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t tmp = 0; uint32_t 708 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value; uint32_t 709 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr; uint32_t 715 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t src_bpc = 16; uint32_t 717 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t dst_bpc; uint32_t 718 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t index; uint32_t 728 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t inc_base; uint32_t 1114 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t h_blank; uint32_t 1115 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t h_back_porch, hsync_offset, h_sync_start; uint32_t 1218 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value; uint32_t 1220 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t address = DCP_REG(mmDCP_GSL_CONTROL); uint32_t 1221 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t check_point = FLIP_READY_BACK_LOOKUP; uint32_t 1270 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value_crtc_vtotal; uint32_t 1319 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value; uint32_t 1321 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t address = DCP_REG(mmDCP_GSL_CONTROL); uint32_t 1349 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value_crtc_vtotal; uint32_t 1415 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL); uint32_t 1416 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 1477 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK); uint32_t 1478 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = dm_read_reg(ctx, addr); uint32_t 1493 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value; uint32_t 1494 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t rising_edge = 0; uint32_t 1495 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t falling_edge = 0; uint32_t 1501 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t pol_value = dm_read_reg(tg->ctx, uint32_t 1583 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 1584 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t rising_edge = 0; uint32_t 1585 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t falling_edge = 0; uint32_t 1713 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value; uint32_t 1778 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = dm_read_reg(tg->ctx, uint32_t 1780 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value1 = dm_read_reg(tg->ctx, uint32_t 1800 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = 0; uint32_t 1801 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 1851 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr; uint32_t 1852 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 1898 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR); uint32_t 1899 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 1927 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 1928 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr; uint32_t 1971 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL)); uint32_t 1989 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 2052 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t v_blank_start = 0; uint32_t 2053 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t v_blank_end = 0; uint32_t 2054 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t val = 0; uint32_t 2055 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t h_position, v_position; uint32_t 2087 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = 0; uint32_t 2088 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 2089 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t field = 0; uint32_t 2102 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t cntl_addr = 0; uint32_t 2103 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = 0; uint32_t 2104 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value; uint32_t 2177 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) uint32_t 2179 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t addr = 0; uint32_t 2180 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t value = 0; uint32_t 2181 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t field = 0; uint32_t 2247 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t instance, uint32_t 103 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t max_h_total; uint32_t 104 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t max_v_total; uint32_t 106 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t min_h_blank; uint32_t 107 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t min_h_front_porch; uint32_t 108 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t min_h_back_porch; uint32_t 111 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t min_h_sync_width; uint32_t 112 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t min_v_sync_width; uint32_t 113 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t min_v_blank; uint32_t 123 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t instance, uint32_t 145 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t early_cntl); uint32_t 150 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t dce110_timing_generator_get_vblank_counter( uint32_t 234 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t value); uint32_t 238 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t *v_blank_start, uint32_t 239 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t *v_blank_end, uint32_t 240 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t *h_position, uint32_t 241 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t *v_position); uint32_t 288 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); uint32_t 60 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value; uint32_t 83 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value; uint32_t 102 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr = mmCRTCV_BLANK_CONTROL; uint32_t 103 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 122 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr = mmCRTCV_BLANK_CONTROL; uint32_t 123 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 143 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr = 0; uint32_t 144 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = 0; uint32_t 145 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t field = 0; uint32_t 155 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value; uint32_t 156 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t h1 = 0; uint32_t 157 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t h2 = 0; uint32_t 158 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t v1 = 0; uint32_t 159 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t v2 = 0; uint32_t 246 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t vsync_offset = timing->v_border_bottom + uint32_t 248 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t v_sync_start = timing->v_addressable + vsync_offset; uint32_t 250 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t hsync_offset = timing->h_border_right + uint32_t 252 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t h_sync_start = timing->h_addressable + hsync_offset; uint32_t 255 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = 0; uint32_t 256 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr = 0; uint32_t 257 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t tmp = 0; uint32_t 389 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr = mmCRTCV_START_LINE_CONTROL; uint32_t 390 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 455 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr = mmCRTCV_BLACK_COLOR; uint32_t 456 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 482 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr; uint32_t 483 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = 0; uint32_t 526 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr = mmCRTCV_BLACK_COLOR; uint32_t 527 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 555 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = 0; uint32_t 556 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr; uint32_t 592 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t early_cntl) uint32_t 594 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t regval; uint32_t 595 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t address = mmCRTC_CONTROL; uint32_t 603 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg) uint32_t 605 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t addr = mmCRTCV_STATUS_FRAME_COUNT; uint32_t 606 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 607 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t field = get_reg_field_value( uint32_t 39 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t h_int_scale_ratio_luma; uint32_t 40 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t h_int_scale_ratio_chroma; uint32_t 41 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t v_int_scale_ratio_luma; uint32_t 42 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t v_int_scale_ratio_chroma; uint32_t 85 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t value = 0; uint32_t 86 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t addr = 0; uint32_t 165 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t value = 0; uint32_t 234 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t overscan_left_right = 0; uint32_t 235 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t overscan_top_bottom = 0; uint32_t 278 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t value; uint32_t 297 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t select = 0; uint32_t 298 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t power_ctl, power_ctl_off; uint32_t 327 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t data = 0; uint32_t 397 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t addr = mmSCLV_HORZ_FILTER_SCALE_RATIO; uint32_t 398 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t value = 0; uint32_t 509 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t value; uint32_t 636 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c uint32_t reg_data = 0; uint32_t 67 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600; uint32_t 101 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c static uint32_t lpt_size_alignment(struct dce112_compressor *cp110) uint32_t 108 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110, uint32_t 109 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t lpt_control) uint32_t 273 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t source_view_width, uint32_t 274 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t source_view_height) uint32_t 286 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c static uint32_t align_to_chunks_number_per_line( uint32_t 288 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t pixels) uint32_t 298 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t addr = mmFBC_STATUS; uint32_t 299 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value; uint32_t 321 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value; uint32_t 322 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t addr; uint32_t 367 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t paths_num, uint32_t 380 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t addr; uint32_t 381 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value; uint32_t 423 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t reg_data; uint32_t 444 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t *inst) uint32_t 447 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value; uint32_t 473 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value = dm_read_reg(compressor->ctx, uint32_t 487 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value = 0; uint32_t 488 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t fbc_pitch = 0; uint32_t 489 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t compressed_surf_address_low_part = uint32_t 501 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t lpt_alignment = lpt_size_alignment(cp110); uint32_t 546 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value; uint32_t 547 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t addr; uint32_t 548 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t inx; uint32_t 600 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value; uint32_t 601 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t addr; uint32_t 602 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value_control; uint32_t 603 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t channels; uint32_t 661 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t rows_per_channel; uint32_t 662 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t lpt_alignment; uint32_t 663 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t source_view_width; uint32_t 664 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t source_view_height; uint32_t 665 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t lpt_control = 0; uint32_t 735 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t fbc_trigger) uint32_t 740 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t addr = mmFBC_CLIENT_REGION_MASK; uint32_t 741 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value = dm_read_reg(compressor->ctx, addr); uint32_t 34 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h uint32_t dcp_offset; uint32_t 35 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h uint32_t dmif_offset; uint32_t 53 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h void dce112_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num, uint32_t 59 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h uint32_t fbc_trigger); uint32_t 66 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h uint32_t *fbc_mapped_crtc_id); uint32_t 38 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c uint32_t crtc; uint32_t 71 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c uint32_t addr; uint32_t 72 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c uint32_t value = 0; uint32_t 73 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c uint32_t chunk_int = 0; uint32_t 74 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c uint32_t chunk_mul = 0; uint32_t 441 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c uint32_t instance, uint32_t 526 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c uint32_t inst) uint32_t 548 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c uint32_t inst) uint32_t 592 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 608 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c uint32_t inst) uint32_t 623 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c uint32_t inst) uint32_t 658 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c uint32_t inst) uint32_t 50 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c uint32_t crtc; uint32_t 85 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c uint32_t addr; uint32_t 86 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c uint32_t value = 0; uint32_t 87 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c uint32_t chunk_int = 0; uint32_t 88 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c uint32_t chunk_mul = 0; uint32_t 255 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c uint32_t pf_max_region; uint32_t 383 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t inst) uint32_t 397 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t inst) uint32_t 432 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t inst) uint32_t 529 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t instance, uint32_t 620 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); uint32_t 673 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 795 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t inst) uint32_t 811 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t inst) uint32_t 973 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c static uint32_t read_pipe_fuses(struct dc_context *ctx) uint32_t 975 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); uint32_t 992 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t pipe_fuses; uint32_t 88 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t field = 0; uint32_t 90 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value = dm_read_reg_soc15( uint32_t 106 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; uint32_t 107 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t v_blank = uint32_t 158 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t early_cntl) uint32_t 169 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t dce120_timing_generator_get_vblank_counter( uint32_t 173 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value = dm_read_reg_soc15( uint32_t 177 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t field = get_reg_field_value( uint32_t 189 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value = dm_read_reg_soc15( uint32_t 250 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value_crtc_vtotal = uint32_t 255 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t check_point = uint32_t 309 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t rising_edge = 0; uint32_t 310 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t falling_edge = 0; uint32_t 312 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t pol_value = dm_read_reg_soc15( uint32_t 374 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value = dm_read_reg_soc15( uint32_t 389 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t offset = 0; uint32_t 390 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value = 0; uint32_t 432 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t tmp1 = 0; uint32_t 433 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t tmp2 = 0; uint32_t 434 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t vsync_offset = timing->v_border_bottom + uint32_t 436 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t v_sync_start = timing->v_addressable + vsync_offset; uint32_t 438 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t hsync_offset = timing->h_border_right + uint32_t 440 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t h_sync_start = timing->h_addressable + hsync_offset; uint32_t 506 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value = 0; uint32_t 605 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value; uint32_t 637 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t *v_blank_start, uint32_t 638 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t *v_blank_end, uint32_t 639 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t *h_position, uint32_t 640 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t *v_position) uint32_t 645 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t v_blank_start_end = dm_read_reg_soc15( uint32_t 670 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t v_sync_width_and_b_porch = uint32_t 673 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value = dm_read_reg_soc15( uint32_t 706 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value = 0; uint32_t 755 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value = dm_read_reg_soc15( uint32_t 822 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value) uint32_t 840 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value; uint32_t 846 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t src_bpc = 16; uint32_t 848 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t dst_bpc; uint32_t 849 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t index; uint32_t 859 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t inc_base; uint32_t 1097 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t v_blank_start, v_blank_end, h_position, v_position; uint32_t 1121 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value, field; uint32_t 1177 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c static bool dce120_get_crc(struct timing_generator *tg, uint32_t *r_cr, uint32_t 1178 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t *g_y, uint32_t *b_cb) uint32_t 1181 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t value, field; uint32_t 1243 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t instance, uint32_t 37 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h uint32_t instance, uint32_t 40 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c uint32_t crtc; uint32_t 454 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c uint32_t instance, uint32_t 469 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c uint32_t inst) uint32_t 484 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c uint32_t inst) uint32_t 519 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c uint32_t inst) uint32_t 623 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c uint32_t inst) uint32_t 646 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c uint32_t inst) uint32_t 716 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 87 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) uint32_t 90 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 uint32_t 92 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 129 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL); uint32_t 130 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c uint32_t value = dm_read_reg(tg->ctx, addr); uint32_t 227 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c uint32_t instance, uint32_t 36 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h uint32_t instance, uint32_t 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c uint32_t cur_csc_reg; uint32_t 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c uint32_t reg_region_cur; uint32_t 131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c uint32_t hw_points_num, uint32_t 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c uint32_t i = 0; uint32_t 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; uint32_t 509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; uint32_t 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_cntl_b; \ uint32_t 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_cntl_g; \ uint32_t 44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_cntl_r; \ uint32_t 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_slope_cntl_b; \ uint32_t 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_slope_cntl_g; \ uint32_t 47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_slope_cntl_r; \ uint32_t 48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_end_cntl1_b; \ uint32_t 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_end_cntl2_b; \ uint32_t 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_end_cntl1_g; \ uint32_t 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_end_cntl2_g; \ uint32_t 52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_end_cntl1_r; \ uint32_t 53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_end_cntl2_r; \ uint32_t 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t region_start; \ uint32_t 55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t region_end uint32_t 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h TF_HELPER_REG_FIELD_LIST(uint32_t); uint32_t 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h TF_CM_REG_FIELD_LIST(uint32_t); uint32_t 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t csc_c11_c12; uint32_t 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t csc_c33_c34; uint32_t 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t hw_points_num, uint32_t 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c uint32_t pixel_width; uint32_t 222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c uint32_t re_mode = 0; uint32_t 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c uint32_t pixel_format; uint32_t 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c uint32_t alpha_en; uint32_t 452 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c uint32_t width, uint32_t 453 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c uint32_t height) uint32_t 458 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c uint32_t cur_en = pos->enable ? 1 : 0; uint32_t 564 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c uint32_t inst, uint32_t 1091 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_REG_FIELD_LIST(uint32_t) uint32_t 1095 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \ uint32_t 1096 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \ uint32_t 1097 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t OTG_H_BLANK; \ uint32_t 1098 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t OTG_V_BLANK; \ uint32_t 1099 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_MODE; \ uint32_t 1100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t LB_DATA_FORMAT; \ uint32_t 1101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t LB_MEMORY_CTRL; \ uint32_t 1102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t DSCL_AUTOCAL; \ uint32_t 1103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_BLACK_OFFSET; \ uint32_t 1104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_TAP_CONTROL; \ uint32_t 1105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_COEF_RAM_TAP_SELECT; \ uint32_t 1106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_COEF_RAM_TAP_DATA; \ uint32_t 1107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t DSCL_2TAP_CONTROL; \ uint32_t 1108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t MPC_SIZE; \ uint32_t 1109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \ uint32_t 1110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_VERT_FILTER_SCALE_RATIO; \ uint32_t 1111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \ uint32_t 1112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \ uint32_t 1113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_HORZ_FILTER_INIT; \ uint32_t 1114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_HORZ_FILTER_INIT_C; \ uint32_t 1115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_VERT_FILTER_INIT; \ uint32_t 1116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_VERT_FILTER_INIT_BOT; \ uint32_t 1117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_VERT_FILTER_INIT_C; \ uint32_t 1118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t SCL_VERT_FILTER_INIT_BOT_C; \ uint32_t 1119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t RECOUT_START; \ uint32_t 1120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t RECOUT_SIZE; \ uint32_t 1121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_GAMUT_REMAP_CONTROL; \ uint32_t 1122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_GAMUT_REMAP_C11_C12; \ uint32_t 1123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_GAMUT_REMAP_C13_C14; \ uint32_t 1124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_GAMUT_REMAP_C21_C22; \ uint32_t 1125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_GAMUT_REMAP_C23_C24; \ uint32_t 1126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_GAMUT_REMAP_C31_C32; \ uint32_t 1127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_GAMUT_REMAP_C33_C34; \ uint32_t 1128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_COMA_C11_C12; \ uint32_t 1129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_COMA_C33_C34; \ uint32_t 1130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_COMB_C11_C12; \ uint32_t 1131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_COMB_C33_C34; \ uint32_t 1132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_OCSC_CONTROL; \ uint32_t 1133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_OCSC_C11_C12; \ uint32_t 1134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_OCSC_C33_C34; \ uint32_t 1135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_MEM_PWR_CTRL; \ uint32_t 1136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_LUT_DATA; \ uint32_t 1137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \ uint32_t 1138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_LUT_INDEX; \ uint32_t 1139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_START_CNTL_B; \ uint32_t 1140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_START_CNTL_G; \ uint32_t 1141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_START_CNTL_R; \ uint32_t 1142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \ uint32_t 1143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \ uint32_t 1144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \ uint32_t 1145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_END_CNTL1_B; \ uint32_t 1146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_END_CNTL2_B; \ uint32_t 1147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_END_CNTL1_G; \ uint32_t 1148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_END_CNTL2_G; \ uint32_t 1149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_END_CNTL1_R; \ uint32_t 1150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_END_CNTL2_R; \ uint32_t 1151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_REGION_0_1; \ uint32_t 1152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMB_REGION_32_33; \ uint32_t 1153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_START_CNTL_B; \ uint32_t 1154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_START_CNTL_G; \ uint32_t 1155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_START_CNTL_R; \ uint32_t 1156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \ uint32_t 1157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \ uint32_t 1158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \ uint32_t 1159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_END_CNTL1_B; \ uint32_t 1160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_END_CNTL2_B; \ uint32_t 1161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_END_CNTL1_G; \ uint32_t 1162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_END_CNTL2_G; \ uint32_t 1163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_END_CNTL1_R; \ uint32_t 1164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_END_CNTL2_R; \ uint32_t 1165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_REGION_0_1; \ uint32_t 1166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_RAMA_REGION_32_33; \ uint32_t 1167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_RGAM_CONTROL; \ uint32_t 1168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_CMOUT_CONTROL; \ uint32_t 1169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \ uint32_t 1170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_CONTROL; \ uint32_t 1171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \ uint32_t 1172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \ uint32_t 1173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; \ uint32_t 1174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; \ uint32_t 1175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; \ uint32_t 1176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; \ uint32_t 1177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; \ uint32_t 1178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; \ uint32_t 1179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; \ uint32_t 1180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; \ uint32_t 1181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; \ uint32_t 1182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; \ uint32_t 1183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_0_1; \ uint32_t 1184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_2_3; \ uint32_t 1185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_4_5; \ uint32_t 1186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_6_7; \ uint32_t 1187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_8_9; \ uint32_t 1188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_10_11; \ uint32_t 1189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_12_13; \ uint32_t 1190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_14_15; \ uint32_t 1191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_16_17; \ uint32_t 1192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_18_19; \ uint32_t 1193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_20_21; \ uint32_t 1194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_22_23; \ uint32_t 1195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_24_25; \ uint32_t 1196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_26_27; \ uint32_t 1197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_28_29; \ uint32_t 1198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_30_31; \ uint32_t 1199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMB_REGION_32_33; \ uint32_t 1200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; \ uint32_t 1201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; \ uint32_t 1202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; \ uint32_t 1203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; \ uint32_t 1204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; \ uint32_t 1205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; \ uint32_t 1206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; \ uint32_t 1207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; \ uint32_t 1208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; \ uint32_t 1209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; \ uint32_t 1210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; \ uint32_t 1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; \ uint32_t 1212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_0_1; \ uint32_t 1213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_2_3; \ uint32_t 1214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_4_5; \ uint32_t 1215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_6_7; \ uint32_t 1216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_8_9; \ uint32_t 1217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_10_11; \ uint32_t 1218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_12_13; \ uint32_t 1219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_14_15; \ uint32_t 1220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_16_17; \ uint32_t 1221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_18_19; \ uint32_t 1222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_20_21; \ uint32_t 1223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_22_23; \ uint32_t 1224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_24_25; \ uint32_t 1225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_26_27; \ uint32_t 1226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_28_29; \ uint32_t 1227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \ uint32_t 1228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \ uint32_t 1229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BLNDGAM_LUT_INDEX; \ uint32_t 1230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_3DLUT_MODE; \ uint32_t 1231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_3DLUT_INDEX; \ uint32_t 1232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_3DLUT_DATA; \ uint32_t 1233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_3DLUT_DATA_30BIT; \ uint32_t 1234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_3DLUT_READ_WRITE_CONTROL; \ uint32_t 1235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \ uint32_t 1236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_CONTROL; \ uint32_t 1237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_START_CNTL_B; \ uint32_t 1238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_START_CNTL_G; \ uint32_t 1239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_START_CNTL_R; \ uint32_t 1240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_END_CNTL_B; \ uint32_t 1241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_END_CNTL_G; \ uint32_t 1242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_END_CNTL_R; \ uint32_t 1243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_0_1; \ uint32_t 1244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_2_3; \ uint32_t 1245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_4_5; \ uint32_t 1246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_6_7; \ uint32_t 1247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_8_9; \ uint32_t 1248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_10_11; \ uint32_t 1249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_12_13; \ uint32_t 1250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_14_15; \ uint32_t 1251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_16_17; \ uint32_t 1252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_18_19; \ uint32_t 1253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_20_21; \ uint32_t 1254 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_22_23; \ uint32_t 1255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_24_25; \ uint32_t 1256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_26_27; \ uint32_t 1257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_28_29; \ uint32_t 1258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_30_31; \ uint32_t 1259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMB_REGION_32_33; \ uint32_t 1260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_START_CNTL_B; \ uint32_t 1261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_START_CNTL_G; \ uint32_t 1262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_START_CNTL_R; \ uint32_t 1263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_END_CNTL_B; \ uint32_t 1264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_END_CNTL_G; \ uint32_t 1265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_END_CNTL_R; \ uint32_t 1266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_0_1; \ uint32_t 1267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_2_3; \ uint32_t 1268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_4_5; \ uint32_t 1269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_6_7; \ uint32_t 1270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_8_9; \ uint32_t 1271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_10_11; \ uint32_t 1272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_12_13; \ uint32_t 1273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_14_15; \ uint32_t 1274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_16_17; \ uint32_t 1275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_18_19; \ uint32_t 1276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_20_21; \ uint32_t 1277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_22_23; \ uint32_t 1278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_24_25; \ uint32_t 1279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_26_27; \ uint32_t 1280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_28_29; \ uint32_t 1281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_30_31; \ uint32_t 1282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_RAMA_REGION_32_33; \ uint32_t 1283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_LUT_INDEX; \ uint32_t 1284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_SHAPER_LUT_DATA; \ uint32_t 1285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_ICSC_CONTROL; \ uint32_t 1286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_ICSC_C11_C12; \ uint32_t 1287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_ICSC_C33_C34; \ uint32_t 1288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BNS_VALUES_R; \ uint32_t 1289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BNS_VALUES_G; \ uint32_t 1290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_BNS_VALUES_B; \ uint32_t 1291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_START_CNTL_B; \ uint32_t 1292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_START_CNTL_G; \ uint32_t 1293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_START_CNTL_R; \ uint32_t 1294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; \ uint32_t 1295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; \ uint32_t 1296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; \ uint32_t 1297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_END_CNTL1_B; \ uint32_t 1298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_END_CNTL2_B; \ uint32_t 1299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_END_CNTL1_G; \ uint32_t 1300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_END_CNTL2_G; \ uint32_t 1301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_END_CNTL1_R; \ uint32_t 1302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_END_CNTL2_R; \ uint32_t 1303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_REGION_0_1; \ uint32_t 1304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMB_REGION_14_15; \ uint32_t 1305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_START_CNTL_B; \ uint32_t 1306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_START_CNTL_G; \ uint32_t 1307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_START_CNTL_R; \ uint32_t 1308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; \ uint32_t 1309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; \ uint32_t 1310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; \ uint32_t 1311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_END_CNTL1_B; \ uint32_t 1312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_END_CNTL2_B; \ uint32_t 1313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_END_CNTL1_G; \ uint32_t 1314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_END_CNTL2_G; \ uint32_t 1315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_END_CNTL1_R; \ uint32_t 1316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_END_CNTL2_R; \ uint32_t 1317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_REGION_0_1; \ uint32_t 1318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_RAMA_REGION_14_15; \ uint32_t 1319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \ uint32_t 1320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_LUT_INDEX; \ uint32_t 1321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_LUT_DATA; \ uint32_t 1322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_CONTROL; \ uint32_t 1323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_DGAM_CONTROL; \ uint32_t 1324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_IGAM_CONTROL; \ uint32_t 1325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_IGAM_LUT_RW_CONTROL; \ uint32_t 1326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_IGAM_LUT_RW_INDEX; \ uint32_t 1327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_IGAM_LUT_SEQ_COLOR; \ uint32_t 1328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_TEST_DEBUG_INDEX; \ uint32_t 1329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_TEST_DEBUG_DATA; \ uint32_t 1330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t FORMAT_CONTROL; \ uint32_t 1331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CNVC_SURFACE_PIXEL_FORMAT; \ uint32_t 1332 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CURSOR_CONTROL; \ uint32_t 1333 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CURSOR0_CONTROL; \ uint32_t 1334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CURSOR0_COLOR0; \ uint32_t 1335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CURSOR0_COLOR1; \ uint32_t 1336 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t DPP_CONTROL; \ uint32_t 1337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CM_HDR_MULT_COEF; \ uint32_t 1338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t CURSOR0_FP_SCALE_BIAS; uint32_t 1377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t width, uint32_t 1378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t height); uint32_t 1410 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t num, uint32_t 1449 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t num); uint32_t 1505 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t multiplier); uint32_t 1509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h uint32_t inst, uint32_t 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t ocsc_mode; uint32_t 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t cur_mode; uint32_t 350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t num) uint32_t 352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t i; uint32_t 448 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t cur_select = 0; uint32_t 653 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t status_reg = 0; uint32_t 672 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t num, uint32_t 675 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t i; uint32_t 747 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t status_reg = 0; uint32_t 781 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t ram_num; uint32_t 825 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t multiplier) uint32_t 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t left = data->recout.x; uint32_t 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t top = data->recout.y; uint32_t 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t h_blank_start = data->h_active; uint32_t 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t h_blank_end = 0; uint32_t 121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t v_blank_start = data->v_active; uint32_t 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t v_blank_end = 0; uint32_t 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth); uint32_t 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth; uint32_t 262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t taps, uint32_t 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; uint32_t 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; uint32_t 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t scl_mode = REG_READ(SCL_MODE); uint32_t 582 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t init_frac = 0; uint32_t 583 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t init_int = 0; uint32_t 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t WB_ENABLE; uint32_t 218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t WB_EC_CONFIG; uint32_t 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t CNV_MODE; uint32_t 220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t WB_SOFT_RESET; uint32_t 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUFMGR_SW_CONTROL; uint32_t 222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_PITCH; uint32_t 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_ARBITRATION_CONTROL; uint32_t 224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_SCLK_CHANGE; uint32_t 225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_1_ADDR_Y; uint32_t 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET; uint32_t 227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_1_ADDR_C; uint32_t 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET; uint32_t 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_2_ADDR_Y; uint32_t 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET; uint32_t 231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_2_ADDR_C; uint32_t 232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET; uint32_t 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_3_ADDR_Y; uint32_t 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET; uint32_t 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_3_ADDR_C; uint32_t 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET; uint32_t 237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_4_ADDR_Y; uint32_t 238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET; uint32_t 239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_4_ADDR_C; uint32_t 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET; uint32_t 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUFMGR_VCE_CONTROL; uint32_t 242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK; uint32_t 243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_NB_PSTATE_CONTROL; uint32_t 244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_WATERMARK; uint32_t 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_WARM_UP_CNTL; uint32_t 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_LUMA_SIZE; uint32_t 247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h uint32_t MCIF_WB_BUF_CHROMA_SIZE; uint32_t 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h DWBC_REG_FIELD_LIST(uint32_t) uint32_t 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t enable = 0; uint32_t 278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c static uint32_t convert_and_clamp( uint32_t 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t wm_ns, uint32_t 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t refclk_mhz, uint32_t 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t clamp_value) uint32_t 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t ret_val = 0; uint32_t 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t prog_wm_value; uint32_t 413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t prog_wm_value; uint32_t 540 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t prog_wm_value; uint32_t 699 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t watermark_change_req; uint32_t 717 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c uint32_t reset_en = reset ? 1 : 0; uint32_t 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; uint32_t 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; uint32_t 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; uint32_t 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; uint32_t 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; uint32_t 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; uint32_t 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; uint32_t 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; uint32_t 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; uint32_t 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; uint32_t 91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; uint32_t 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; uint32_t 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; uint32_t 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; uint32_t 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; uint32_t 96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; uint32_t 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; uint32_t 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; uint32_t 99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; uint32_t 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; uint32_t 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; uint32_t 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_SAT_LEVEL; uint32_t 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; uint32_t 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; uint32_t 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; uint32_t 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_TEST_DEBUG_INDEX; uint32_t 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_TEST_DEBUG_DATA; uint32_t 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_SDPIF_FB_TOP; uint32_t 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_SDPIF_FB_BASE; uint32_t 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_SDPIF_FB_OFFSET; uint32_t 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_SDPIF_AGP_BASE; uint32_t 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_SDPIF_AGP_BOT; uint32_t 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_SDPIF_AGP_TOP; uint32_t 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_CRC_CTRL; uint32_t 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_SOFT_RESET; uint32_t 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCN_VM_FB_LOCATION_BASE; uint32_t 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCN_VM_FB_LOCATION_TOP; uint32_t 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCN_VM_FB_OFFSET; uint32_t 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCN_VM_AGP_BOT; uint32_t 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCN_VM_AGP_TOP; uint32_t 121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCN_VM_AGP_BASE; uint32_t 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB; uint32_t 123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB; uint32_t 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A; uint32_t 126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B; uint32_t 127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C; uint32_t 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D; uint32_t 129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A; uint32_t 130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B; uint32_t 131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C; uint32_t 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D; uint32_t 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A; uint32_t 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B; uint32_t 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C; uint32_t 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D; uint32_t 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; uint32_t 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHVM_CTRL0; uint32_t 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHVM_MEM_CTRL; uint32_t 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHVM_CLK_CTRL; uint32_t 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHVM_RIOMMU_CTRL0; uint32_t 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h uint32_t DCHVM_RIOMMU_STAT0; uint32_t 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h DCN_HUBBUB_REG_FIELD_LIST(uint32_t); uint32_t 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); uint32_t 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_HVM_REG_FIELD_LIST(uint32_t); uint32_t 44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t blank_en = blank ? 1 : 0; uint32_t 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t reg_val = REG_READ(DCHUBP_CNTL); uint32_t 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t disable = disable_hubp ? 1 : 0; uint32_t 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t hubp_underflow = 0; uint32_t 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t blank_en = blank ? 1 : 0; uint32_t 121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t value = 0; uint32_t 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; uint32_t 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t mirror; uint32_t 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t red_bar = 3; uint32_t 242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t blue_bar = 2; uint32_t 514 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t dcc_en = enable ? 1 : 0; uint32_t 515 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; uint32_t 723 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t flip_pending = 0; uint32_t 745 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t aperture_default_system = 1; uint32_t 746 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t context0_default_system; /* = 0;*/ uint32_t 1133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t dst_x_offset; uint32_t 1134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t cur_en = pos->enable ? 1 : 0; uint32_t 1202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t clk_enable = enable ? 1 : 0; uint32_t 1207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) uint32_t 1256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t inst, uint32_t 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCHUBP_CNTL; \ uint32_t 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t HUBPREQ_DEBUG_DB; \ uint32_t 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t HUBPREQ_DEBUG; \ uint32_t 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_ADDR_CONFIG; \ uint32_t 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_TILING_CONFIG; \ uint32_t 143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_PITCH; \ uint32_t 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_PITCH_C; \ uint32_t 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_CONFIG; \ uint32_t 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_FLIP_CONTROL; \ uint32_t 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \ uint32_t 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRI_VIEWPORT_START; \ uint32_t 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \ uint32_t 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SEC_VIEWPORT_START; \ uint32_t 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \ uint32_t 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRI_VIEWPORT_START_C; \ uint32_t 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \ uint32_t 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \ uint32_t 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \ uint32_t 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \ uint32_t 157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \ uint32_t 158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \ uint32_t 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \ uint32_t 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \ uint32_t 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \ uint32_t 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \ uint32_t 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \ uint32_t 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \ uint32_t 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_INUSE; \ uint32_t 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_INUSE_HIGH; \ uint32_t 167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_INUSE_C; \ uint32_t 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \ uint32_t 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \ uint32_t 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \ uint32_t 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \ uint32_t 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \ uint32_t 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_SURFACE_CONTROL; \ uint32_t 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t HUBPRET_CONTROL; \ uint32_t 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_EXPANSION_MODE; \ uint32_t 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCHUBP_REQ_SIZE_CONFIG; \ uint32_t 177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \ uint32_t 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t BLANK_OFFSET_0; \ uint32_t 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t BLANK_OFFSET_1; \ uint32_t 180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DST_DIMENSIONS; \ uint32_t 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DST_AFTER_SCALER; \ uint32_t 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t PREFETCH_SETTINS; \ uint32_t 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t PREFETCH_SETTINGS; \ uint32_t 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t VBLANK_PARAMETERS_0; \ uint32_t 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t REF_FREQ_TO_PIX_FREQ; \ uint32_t 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t VBLANK_PARAMETERS_1; \ uint32_t 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t VBLANK_PARAMETERS_3; \ uint32_t 188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t NOM_PARAMETERS_0; \ uint32_t 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t NOM_PARAMETERS_1; \ uint32_t 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t NOM_PARAMETERS_4; \ uint32_t 191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t NOM_PARAMETERS_5; \ uint32_t 192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t PER_LINE_DELIVERY_PRE; \ uint32_t 193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t PER_LINE_DELIVERY; \ uint32_t 194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t PREFETCH_SETTINS_C; \ uint32_t 195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t PREFETCH_SETTINGS_C; \ uint32_t 196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t VBLANK_PARAMETERS_2; \ uint32_t 197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t VBLANK_PARAMETERS_4; \ uint32_t 198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t NOM_PARAMETERS_2; \ uint32_t 199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t NOM_PARAMETERS_3; \ uint32_t 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t NOM_PARAMETERS_6; \ uint32_t 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t NOM_PARAMETERS_7; \ uint32_t 202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_TTU_QOS_WM; \ uint32_t 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_GLOBAL_TTU_CNTL; \ uint32_t 204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_SURF0_TTU_CNTL0; \ uint32_t 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_SURF0_TTU_CNTL1; \ uint32_t 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_SURF1_TTU_CNTL0; \ uint32_t 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_SURF1_TTU_CNTL1; \ uint32_t 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_CUR0_TTU_CNTL0; \ uint32_t 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_CUR0_TTU_CNTL1; \ uint32_t 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \ uint32_t 211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \ uint32_t 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \ uint32_t 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \ uint32_t 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \ uint32_t 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \ uint32_t 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \ uint32_t 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \ uint32_t 218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_MX_L1_TLB_CNTL; \ uint32_t 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \ uint32_t 220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \ uint32_t 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \ uint32_t 222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \ uint32_t 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \ uint32_t 224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \ uint32_t 225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \ uint32_t 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \ uint32_t 227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t CURSOR_SETTINS; \ uint32_t 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t CURSOR_SETTINGS; \ uint32_t 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \ uint32_t 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t CURSOR_SURFACE_ADDRESS; \ uint32_t 231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t CURSOR_SIZE; \ uint32_t 232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t CURSOR_CONTROL; \ uint32_t 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t CURSOR_POSITION; \ uint32_t 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t CURSOR_HOT_SPOT; \ uint32_t 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t CURSOR_DST_OFFSET; \ uint32_t 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t HUBP_CLK_CNTL uint32_t 628 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h DCN_HUBP_REG_FIELD_LIST(uint32_t); uint32_t 635 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t pixel_format; uint32_t 636 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t inuse_addr_hi; uint32_t 637 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t inuse_addr_lo; uint32_t 638 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t viewport_width; uint32_t 639 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t viewport_height; uint32_t 640 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t rotation_angle; uint32_t 641 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t h_mirror_en; uint32_t 642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t sw_mode; uint32_t 643 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t dcc_en; uint32_t 644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t blank_en; uint32_t 645 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t underflow_status; uint32_t 646 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t ttu_disable; uint32_t 647 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t min_ttu_vblank; uint32_t 648 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t qos_level_low_wm; uint32_t 649 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t qos_level_high_wm; uint32_t 728 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst); uint32_t 733 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t inst, uint32_t 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t ref_cycle) uint32_t 75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; uint32_t 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz; uint32_t 501 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t power_gate = power_on ? 0 : 1; uint32_t 502 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t pwr_status = power_on ? 0 : 2; uint32_t 553 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t power_gate = power_on ? 0 : 1; uint32_t 554 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t pwr_status = power_on ? 0 : 2; uint32_t 1442 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_transfer_func *tf, uint32_t hw_points_num) uint32_t 1536 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c const uint32_t frames_to_wait_on_triggered_reset = 10; uint32_t 1747 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t logical_addr_low; uint32_t 1748 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t logical_addr_high; uint32_t 1773 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t fb_base_value; uint32_t 1774 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t fb_offset_value; uint32_t 2029 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t color_value = MAX_TG_COLOR_VALUE; uint32_t 2065 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t color_value = MAX_TG_COLOR_VALUE; uint32_t 2456 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t hw_mult = 0x1f000; // 1.0 default multiplier uint32_t 2558 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t underflow_check_delay_us; uint32_t 2968 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x; uint32_t 2969 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y; uint32_t 2970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t x_offset = min(x_plane, pos_cpy.x); uint32_t 2971 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t y_offset = min(y_plane, pos_cpy.y); uint32_t 2984 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t temp_x = pos_cpy.x; uint32_t 2991 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t temp_y = pos_cpy.y; uint32_t 3006 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t temp_x = pos_cpy.x; uint32_t 3032 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level; uint32_t 3035 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t hw_scale = 0x3c00; // 1.0 default multiplier uint32_t 3133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t *start_line, uint32_t 3134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t *end_line) uint32_t 3163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t *start_line, uint32_t 3164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t *end_line) uint32_t 3196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t start_line = 0; uint32_t 3197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t end_line = 0; uint32_t 3260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t clk_khz, uint32_t 3261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c uint32_t stepping) uint32_t 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; uint32_t 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; uint32_t 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_DCN10_REG_FIELD_LIST(uint32_t); uint32_t 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR_SETTINS; uint32_t 167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR_SETTINGS; uint32_t 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CNVC_SURFACE_PIXEL_FORMAT; uint32_t 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR0_CONTROL; uint32_t 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR0_COLOR0; uint32_t 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR0_COLOR1; uint32_t 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t FORMAT_CONTROL; uint32_t 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR_SURFACE_ADDRESS_HIGH; uint32_t 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR_SURFACE_ADDRESS; uint32_t 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR_SIZE; uint32_t 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR_CONTROL; uint32_t 177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR_POSITION; uint32_t 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR_HOT_SPOT; uint32_t 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h uint32_t CURSOR_DST_OFFSET; uint32_t 211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t index) uint32_t 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t value; uint32_t 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t value; uint32_t 573 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; uint32_t 914 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t pixel_clock) uint32_t 1178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t *src, uint32_t 1179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t *slots) uint32_t 1198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t value0 = 0; uint32_t 1199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t value1 = 0; uint32_t 1200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t value2 = 0; uint32_t 1201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t slots = 0; uint32_t 1202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t src = 0; uint32_t 1203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t retries = 0; uint32_t 1321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t field; uint32_t 1406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c uint32_t value; uint32_t 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t AUX_CONTROL; uint32_t 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t AUX_DPHY_RX_CONTROL0; uint32_t 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t AUX_DPHY_TX_CONTROL; uint32_t 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DC_HPD_CONTROL; uint32_t 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DIG_BE_CNTL; uint32_t 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DIG_BE_EN_CNTL; uint32_t 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_CONFIG; uint32_t 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_CNTL; uint32_t 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_INTERNAL_CTRL; uint32_t 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_PRBS_CNTL; uint32_t 91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_SCRAM_CNTL; uint32_t 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_SYM0; uint32_t 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_SYM1; uint32_t 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_SYM2; uint32_t 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_TRAINING_PATTERN_SEL; uint32_t 96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_LINK_CNTL; uint32_t 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_LINK_FRAMING_CNTL; uint32_t 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_MSE_SAT0; uint32_t 99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_MSE_SAT1; uint32_t 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_MSE_SAT2; uint32_t 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_MSE_SAT_UPDATE; uint32_t 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_SEC_CNTL; uint32_t 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_VID_STREAM_CNTL; uint32_t 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_FAST_TRAINING; uint32_t 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_BS_SR_SWAP_CNTL; uint32_t 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; uint32_t 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_SEC_CNTL1; uint32_t 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t TMDS_CTL_BITS; uint32_t 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t CLOCK_ENABLE; uint32_t 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DIG_LANE_ENABLE; uint32_t 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t CHANNEL_XBAR_CNTL; uint32_t 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2; uint32_t 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3; uint32_t 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2; uint32_t 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3; uint32_t 121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2; uint32_t 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3; uint32_t 123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2; uint32_t 124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3; uint32_t 388 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t); uint32_t 390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t); uint32_t 460 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t pixel_clock); uint32_t 500 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t index); uint32_t 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c uint32_t bg_r_cr = bg_color->color_r_cr << 2; uint32_t 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c uint32_t bg_g_y = bg_color->color_g_y << 2; uint32_t 52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c uint32_t bg_b_cb = bg_color->color_b_cb << 2; uint32_t 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_TOP_SEL[MAX_MPCC]; \ uint32_t 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_BOT_SEL[MAX_MPCC]; \ uint32_t 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_CONTROL[MAX_MPCC]; \ uint32_t 52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_STATUS[MAX_MPCC]; \ uint32_t 53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_OPP_ID[MAX_MPCC]; \ uint32_t 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_BG_G_Y[MAX_MPCC]; \ uint32_t 55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_BG_R_CR[MAX_MPCC]; \ uint32_t 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_BG_B_CB[MAX_MPCC]; \ uint32_t 57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \ uint32_t 58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MUX[MAX_OPP]; uint32_t 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h MPC_REG_FIELD_LIST(uint32_t) uint32_t 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; uint32_t 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t space1_size = timing->v_total - timing->v_addressable; uint32_t 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t space2_size = timing->v_total - timing->v_addressable; uint32_t 380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t regval = enable ? 1 : 0; uint32_t 409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t inst, uint32_t 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t FMT_BIT_DEPTH_CONTROL; \ uint32_t 55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t FMT_CONTROL; \ uint32_t 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t FMT_DITHER_RAND_R_SEED; \ uint32_t 57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t FMT_DITHER_RAND_G_SEED; \ uint32_t 58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t FMT_DITHER_RAND_B_SEED; \ uint32_t 59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t FMT_CLAMP_CNTL; \ uint32_t 60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t FMT_DYNAMIC_EXP_CNTL; \ uint32_t 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t FMT_MAP420_MEMORY_CONTROL; \ uint32_t 62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t OPPBUF_CONTROL; \ uint32_t 63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t OPPBUF_CONTROL1; \ uint32_t 64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t OPPBUF_3D_PARAMETERS_0; \ uint32_t 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t OPPBUF_3D_PARAMETERS_1; \ uint32_t 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t OPP_PIPE_CONTROL uint32_t 143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_DCN10_REG_FIELD_LIST(uint32_t); uint32_t 158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t inst, uint32_t 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t start_line, uint32_t 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t end_line) uint32_t 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t start_line) uint32_t 126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t start_line) uint32_t 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t asic_blank_end; uint32_t 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t asic_blank_start; uint32_t 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t v_total; uint32_t 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t v_sync_end; uint32_t 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t h_sync_polarity, v_sync_polarity; uint32_t 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t start_point = 0; uint32_t 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t field_num = 0; uint32_t 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t asic_blank_end; uint32_t 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t v_init; uint32_t 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t v_fp2 = 0; uint32_t 341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; uint32_t 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t blank_en; uint32_t 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t blank_state; uint32_t 508 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t v_blank; uint32_t 509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t h_blank; uint32_t 510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t min_v_blank; uint32_t 574 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t optc1_get_vblank_counter(struct timing_generator *optc) uint32_t 577 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t frame_count; uint32_t 588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t regval = 0; uint32_t 649 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t occurred_force, occurred_vsync; uint32_t 676 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t falling_edge; uint32_t 713 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t falling_edge = 0; uint32_t 714 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t rising_edge = 0; uint32_t 777 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t early_cntl) uint32_t 787 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t value) uint32_t 908 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t pattern_mask; uint32_t 909 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t pattern_data; uint32_t 911 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t src_bpc = 16; uint32_t 913 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t dst_bpc; uint32_t 914 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t index; uint32_t 924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t inc_base; uint32_t 1157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t *v_blank_start, uint32_t 1158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t *v_blank_end, uint32_t 1159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t *h_position, uint32_t 1160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t *v_position) uint32_t 1181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t stereo_en; uint32_t 1220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t left_eye = 0; uint32_t 1342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t *otg_active_width, uint32_t 1343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t *otg_active_height) uint32_t 1345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t otg_enabled; uint32_t 1346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t v_blank_start; uint32_t 1347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t v_blank_end; uint32_t 1348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t h_blank_start; uint32_t 1349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t h_blank_end; uint32_t 1388 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t otg_enabled = 0; uint32_t 1399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t underflow_occurred = 0; uint32_t 1453 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) uint32_t 1455 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t field = 0; uint32_t 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_GLOBAL_CONTROL1; uint32_t 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_GLOBAL_CONTROL2; uint32_t 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VERT_SYNC_CONTROL; uint32_t 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_MASTER_UPDATE_MODE; uint32_t 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_GSL_CONTROL; uint32_t 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VSTARTUP_PARAM; uint32_t 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VUPDATE_PARAM; uint32_t 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VREADY_PARAM; uint32_t 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_BLANK_CONTROL; uint32_t 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_MASTER_UPDATE_LOCK; uint32_t 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_GLOBAL_CONTROL0; uint32_t 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_DOUBLE_BUFFER_CONTROL; uint32_t 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_H_TOTAL; uint32_t 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_H_BLANK_START_END; uint32_t 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_H_SYNC_A; uint32_t 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_H_SYNC_A_CNTL; uint32_t 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_H_TIMING_CNTL; uint32_t 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_V_TOTAL; uint32_t 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_V_BLANK_START_END; uint32_t 121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_V_SYNC_A; uint32_t 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_V_SYNC_A_CNTL; uint32_t 123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_INTERLACE_CONTROL; uint32_t 124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_CONTROL; uint32_t 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_STEREO_CONTROL; uint32_t 126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_3D_STRUCTURE_CONTROL; uint32_t 127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_STEREO_STATUS; uint32_t 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_V_TOTAL_MAX; uint32_t 129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_V_TOTAL_MID; uint32_t 130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_V_TOTAL_MIN; uint32_t 131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_V_TOTAL_CONTROL; uint32_t 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_TRIGA_CNTL; uint32_t 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_TRIGA_MANUAL_TRIG; uint32_t 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_MANUAL_FLOW_CONTROL; uint32_t 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_FORCE_COUNT_NOW_CNTL; uint32_t 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_STATIC_SCREEN_CONTROL; uint32_t 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_STATUS_FRAME_COUNT; uint32_t 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_STATUS; uint32_t 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_STATUS_POSITION; uint32_t 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_NOM_VERT_POSITION; uint32_t 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_BLACK_COLOR; uint32_t 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_TEST_PATTERN_PARAMETERS; uint32_t 143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_TEST_PATTERN_CONTROL; uint32_t 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_TEST_PATTERN_COLOR; uint32_t 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_CLOCK_CONTROL; uint32_t 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; uint32_t 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; uint32_t 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL; uint32_t 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VERTICAL_INTERRUPT1_POSITION; uint32_t 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; uint32_t 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; uint32_t 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OPTC_INPUT_CLOCK_CONTROL; uint32_t 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OPTC_DATA_SOURCE_SELECT; uint32_t 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OPTC_MEMORY_CONFIG; uint32_t 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OPTC_INPUT_GLOBAL_CONTROL; uint32_t 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t CONTROL; uint32_t 157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_GSL_WINDOW_X; uint32_t 158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_GSL_WINDOW_Y; uint32_t 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_VUPDATE_KEEPOUT; uint32_t 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_CRC_CNTL; uint32_t 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_CRC0_DATA_RG; uint32_t 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_CRC0_DATA_B; uint32_t 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_CRC0_WINDOWA_X_CONTROL; uint32_t 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; uint32_t 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_CRC0_WINDOWB_X_CONTROL; uint32_t 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; uint32_t 167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t GSL_SOURCE_SELECT; uint32_t 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t DWB_SOURCE_SELECT; uint32_t 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_DSC_START_POSITION; uint32_t 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OPTC_DATA_FORMAT_CONTROL; uint32_t 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OPTC_BYTES_PER_PIXEL; uint32_t 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OPTC_WIDTH_CONTROL; uint32_t 495 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h TG_REG_FIELD_LIST(uint32_t) uint32_t 507 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t max_h_total; uint32_t 508 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t max_v_total; uint32_t 510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t min_h_blank; uint32_t 512 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t min_h_sync_width; uint32_t 513 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t min_v_sync_width; uint32_t 514 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t min_v_blank; uint32_t 515 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t min_v_blank_interlace; uint32_t 527 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_blank_start; uint32_t 528 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_blank_end; uint32_t 529 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_sync_a_pol; uint32_t 530 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_total; uint32_t 531 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_total_max; uint32_t 532 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_total_min; uint32_t 533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_total_min_sel; uint32_t 534 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_total_max_sel; uint32_t 535 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_sync_a_start; uint32_t 536 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t v_sync_a_end; uint32_t 537 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t h_blank_start; uint32_t 538 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t h_blank_end; uint32_t 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t h_sync_a_start; uint32_t 540 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t h_sync_a_end; uint32_t 541 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t h_sync_a_pol; uint32_t 542 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t h_total; uint32_t 543 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t underflow_occurred_status; uint32_t 544 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t otg_enabled; uint32_t 570 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t start_line, uint32_t 571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t end_line); uint32_t 574 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t start_line); uint32_t 577 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t start_line); uint32_t 593 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t optc1_get_vblank_counter(struct timing_generator *optc); uint32_t 597 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t *v_blank_start, uint32_t 598 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t *v_blank_end, uint32_t 599 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t *h_position, uint32_t 600 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t *v_position); uint32_t 604 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t early_cntl); uint32_t 637 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t value); uint32_t 655 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t *otg_active_width, uint32_t 656 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t *otg_active_height); uint32_t 667 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); uint32_t 587 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c uint32_t inst) uint32_t 601 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 618 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 635 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c uint32_t inst) uint32_t 670 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c uint32_t inst) uint32_t 718 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c uint32_t instance) uint32_t 972 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c uint32_t inst) uint32_t 1263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static uint32_t read_pipe_fuses(struct dc_context *ctx) uint32_t 1265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); uint32_t 1279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c uint32_t pipe_fuses = read_pipe_fuses(ctx); uint32_t 58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t packet_index, uint32_t 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t regval; uint32_t 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t max_retries = 50; uint32_t 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c const uint32_t *content = uint32_t 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c (const uint32_t *) &info_packet->sb[0]; uint32_t 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t packet_index, uint32_t 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t cont, send, line; uint32_t 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t enable_sdp_splitting) uint32_t 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t h_active_start; uint32_t 253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t v_active_start; uint32_t 254 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t misc0 = 0; uint32_t 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t misc1 = 0; uint32_t 256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t h_blank; uint32_t 257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t h_back_porch; uint32_t 629 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t x = dc_fixpt_floor( uint32_t 631 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t y = dc_fixpt_ceil( uint32_t 712 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t value = 0; uint32_t 762 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t value = 0; uint32_t 767 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t max_retries = 50; uint32_t 810 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c const uint32_t *content = uint32_t 811 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c (const uint32_t *) &custom_sdp_message[4]; uint32_t 855 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t value = 0; uint32_t 882 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t reg1 = 0; uint32_t 883 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; uint32_t 935 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t n_vid = 0x8000; uint32_t 936 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t m_vid; uint32_t 937 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t n_multiply = 0; uint32_t 954 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c m_vid = (uint32_t) m_vid_l; uint32_t 1098 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t FL:1; uint32_t 1099 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t FR:1; uint32_t 1100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t LFE:1; uint32_t 1101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t FC:1; uint32_t 1102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t RL_RC:1; uint32_t 1103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t RR:1; uint32_t 1104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t RC_RLC_FLC:1; uint32_t 1105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t RRC_FRC:1; uint32_t 1213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t crtc_pixel_clock_100Hz, uint32_t 1214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t actual_pixel_clock_100Hz, uint32_t 1218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t index; uint32_t 1219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; uint32_t 1220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t audio_array_size; uint32_t 1279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t speakers = 0; uint32_t 1280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t channels = 0; uint32_t 1458 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t value = 0; uint32_t 1548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t tg_inst = 0; uint32_t 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_CNTL; uint32_t 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_AVI_INFO0; uint32_t 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_AVI_INFO1; uint32_t 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_AVI_INFO2; uint32_t 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_AVI_INFO3; uint32_t 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_GENERIC_0; uint32_t 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_GENERIC_1; uint32_t 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_GENERIC_2; uint32_t 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_GENERIC_3; uint32_t 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_GENERIC_4; uint32_t 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_GENERIC_5; uint32_t 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_GENERIC_6; uint32_t 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_GENERIC_7; uint32_t 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_GENERIC_HDR; uint32_t 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_INFOFRAME_CONTROL0; uint32_t 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_VBI_PACKET_CONTROL; uint32_t 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_VBI_PACKET_CONTROL1; uint32_t 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_AUDIO_PACKET_CONTROL; uint32_t 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_AUDIO_PACKET_CONTROL2; uint32_t 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_AUDIO_SRC_CONTROL; uint32_t 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_60958_0; uint32_t 121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_60958_1; uint32_t 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t AFMT_60958_2; uint32_t 123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DIG_FE_CNTL; uint32_t 124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DIG_FE_CNTL2; uint32_t 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_MSE_RATE_CNTL; uint32_t 126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_MSE_RATE_UPDATE; uint32_t 127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_PIXEL_FORMAT; uint32_t 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_SEC_CNTL; uint32_t 129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_SEC_CNTL2; uint32_t 130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_SEC_CNTL6; uint32_t 131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_STEER_FIFO; uint32_t 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_VID_M; uint32_t 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_VID_N; uint32_t 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_VID_STREAM_CNTL; uint32_t 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_VID_TIMING; uint32_t 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_SEC_AUD_N; uint32_t 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_SEC_TIMESTAMP; uint32_t 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_CONTROL; uint32_t 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_GC; uint32_t 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL0; uint32_t 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL1; uint32_t 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL2; uint32_t 143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL3; uint32_t 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL4; uint32_t 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL5; uint32_t 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_INFOFRAME_CONTROL0; uint32_t 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_INFOFRAME_CONTROL1; uint32_t 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_VBI_PACKET_CONTROL; uint32_t 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_AUDIO_PACKET_CONTROL; uint32_t 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_ACR_PACKET_CONTROL; uint32_t 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_ACR_32_0; uint32_t 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_ACR_32_1; uint32_t 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_ACR_44_0; uint32_t 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_ACR_44_1; uint32_t 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_ACR_48_0; uint32_t 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_ACR_48_1; uint32_t 157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_DB_CNTL; uint32_t 158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_MSA_MISC; uint32_t 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_MSA_VBID_MISC; uint32_t 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_MSA_COLORIMETRY; uint32_t 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_MSA_TIMING_PARAM1; uint32_t 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_MSA_TIMING_PARAM2; uint32_t 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_MSA_TIMING_PARAM3; uint32_t 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_MSA_TIMING_PARAM4; uint32_t 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_DB_CONTROL; uint32_t 167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_DSC_CNTL; uint32_t 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_DSC_BYTES_PER_PIXEL; uint32_t 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DME_CONTROL; uint32_t 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_SEC_METADATA_TRANSMISSION; uint32_t 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_METADATA_PACKET_CONTROL; uint32_t 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DP_SEC_FRAMING4; uint32_t 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t DIG_CLOCK_PATTERN; uint32_t 498 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_REG_FIELD_LIST_DCN1_0(uint32_t); uint32_t 500 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_REG_FIELD_LIST_DCN2_0(uint32_t); uint32_t 522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t packet_index, uint32_t 529 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t enable_sdp_splitting); uint32_t 617 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t crtc_pixel_clock_100Hz, uint32_t 618 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t actual_pixel_clock_100Hz, uint32_t 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c uint32_t clk_en = 0; uint32_t 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c uint32_t clk_sel = 0; uint32_t 84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_REG_FIELD_LIST(uint32_t) uint32_t 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h uint32_t DPPCLK_DTO_CTRL; uint32_t 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h uint32_t DPPCLK_DTO_PARAM[6]; uint32_t 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h uint32_t REFCLK_CNTL; uint32_t 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c uint32_t pixel_format = 0; uint32_t 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c uint32_t alpha_en = 1; uint32_t 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c uint32_t is_2bit = 0; uint32_t 379 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c uint32_t pixel_width; uint32_t 497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c uint32_t inst, uint32_t 601 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_REG_FIELD_LIST_DCN2_0(uint32_t); uint32_t 606 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t CM_BLNDGAM_LUT_DATA; \ uint32_t 607 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t ALPHA_2BIT_LUT; \ uint32_t 608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t FCNV_FP_BIAS_R; \ uint32_t 609 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t FCNV_FP_BIAS_G; \ uint32_t 610 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t FCNV_FP_BIAS_B; \ uint32_t 611 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t FCNV_FP_SCALE_R; \ uint32_t 612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t FCNV_FP_SCALE_G; \ uint32_t 613 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t FCNV_FP_SCALE_B; \ uint32_t 614 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t COLOR_KEYER_CONTROL; \ uint32_t 615 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t COLOR_KEYER_ALPHA; \ uint32_t 616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t COLOR_KEYER_RED; \ uint32_t 617 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t COLOR_KEYER_GREEN; \ uint32_t 618 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t COLOR_KEYER_BLUE; \ uint32_t 619 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t OBUF_MEM_PWR_CTRL;\ uint32_t 620 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t DSCL_MEM_PWR_CTRL uint32_t 692 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t multiplier); uint32_t 701 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h uint32_t inst, uint32_t 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t status_reg = 0; uint32_t 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t num, uint32_t 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t i; uint32_t 185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t num) uint32_t 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t i; uint32_t 292 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t state_mode; uint32_t 353 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t num) uint32_t 355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t i, red, green, blue; uint32_t 356 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t red_delta, green_delta, blue_delta; uint32_t 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t red_value, green_value, blue_value; uint32_t 385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t state_mode; uint32_t 765 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t i_mode, i_enable_10bits, lut_size; uint32_t 812 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t lut_mode; uint32_t 845 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t entries) uint32_t 847 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t i, red, green, blue, red1, green1, blue1; uint32_t 879 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t entries) uint32_t 881 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t i, red, green, blue, value; uint32_t 899 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t ram_selection_mask) uint32_t 990 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c uint32_t multiplier) uint32_t 518 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c uint32_t temp_int; uint32_t 461 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSC_TOP_CONTROL; uint32_t 462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSC_DEBUG_CONTROL; uint32_t 463 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_CONFIG0; uint32_t 464 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_CONFIG1; uint32_t 465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_STATUS; uint32_t 466 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_INTERRUPT_CONTROL_STATUS; uint32_t 467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG0; uint32_t 468 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG1; uint32_t 469 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG2; uint32_t 470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG3; uint32_t 471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG4; uint32_t 472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG5; uint32_t 473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG6; uint32_t 474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG7; uint32_t 475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG8; uint32_t 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG9; uint32_t 477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG10; uint32_t 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG11; uint32_t 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG12; uint32_t 480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG13; uint32_t 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG14; uint32_t 482 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG15; uint32_t 483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG16; uint32_t 484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG17; uint32_t 485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG18; uint32_t 486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG19; uint32_t 487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG20; uint32_t 488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG21; uint32_t 489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_PPS_CONFIG22; uint32_t 490 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_MEM_POWER_CONTROL; uint32_t 491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER; uint32_t 492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER; uint32_t 493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER; uint32_t 494 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER; uint32_t 495 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER; uint32_t 496 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER; uint32_t 497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_MAX_ABS_ERROR0; uint32_t 498 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_MAX_ABS_ERROR1; uint32_t 499 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL; uint32_t 500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL; uint32_t 501 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL; uint32_t 502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL; uint32_t 503 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL; uint32_t 504 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL; uint32_t 505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL; uint32_t 506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL; uint32_t 507 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCC_TEST_DEBUG_BUS_ROTATE; uint32_t 508 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCCIF_CONFIG0; uint32_t 509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCCIF_CONFIG1; uint32_t 510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t DSCRM_DSC_FORWARD_CONFIG; uint32_t 519 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_FIELD_LIST_DCN20(uint32_t); uint32_t 537 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t dsc_clock_enable; uint32_t 538 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t dsc_clock_gating_disable; uint32_t 539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t underflow_recovery_en; uint32_t 540 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t underflow_occurred_int_en; uint32_t 541 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t underflow_occurred_status; uint32_t 543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t ich_reset_at_eol; uint32_t 544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t alternate_ich_encoding_en; uint32_t 545 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t num_slices_h; uint32_t 546 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t num_slices_v; uint32_t 547 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t rc_buffer_model_size; uint32_t 548 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t disable_ich; uint32_t 549 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t bpp_x32; uint32_t 550 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t dsc_dbg_en; uint32_t 551 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t rc_buffer_model_overflow_int_en[4]; uint32_t 358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WB_ENABLE; uint32_t 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WB_EC_CONFIG; uint32_t 360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_MODE; uint32_t 361 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_WINDOW_START; uint32_t 362 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_WINDOW_SIZE; uint32_t 363 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_UPDATE; uint32_t 364 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_SOURCE_SIZE; uint32_t 365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_TEST_CNTL; uint32_t 366 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_TEST_CRC_RED; uint32_t 367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_TEST_CRC_GREEN; uint32_t 368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_TEST_CRC_BLUE; uint32_t 369 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WB_DEBUG_CTRL; uint32_t 370 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WB_DBG_MODE; uint32_t 371 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WB_HW_DEBUG; uint32_t 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_TEST_DEBUG_INDEX; uint32_t 373 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t CNV_TEST_DEBUG_DATA; uint32_t 374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WB_SOFT_RESET; uint32_t 375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_COEF_RAM_SELECT; uint32_t 376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_COEF_RAM_TAP_DATA; uint32_t 377 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_MODE; uint32_t 378 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_TAP_CONTROL; uint32_t 379 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_DEST_SIZE; uint32_t 380 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO; uint32_t 381 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB; uint32_t 382 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_HORZ_FILTER_INIT_CBCR; uint32_t 383 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_VERT_FILTER_SCALE_RATIO; uint32_t 384 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB; uint32_t 385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_VERT_FILTER_INIT_CBCR; uint32_t 386 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_ROUND_OFFSET; uint32_t 387 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_OVERFLOW_STATUS; uint32_t 388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS; uint32_t 389 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_TEST_CNTL; uint32_t 390 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_TEST_CRC_RED; uint32_t 391 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_TEST_CRC_GREEN; uint32_t 392 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_TEST_CRC_BLUE; uint32_t 393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_BACKPRESSURE_CNT_EN; uint32_t 394 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WB_MCIF_BACKPRESSURE_CNT; uint32_t 395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_CLAMP_Y_RGB; uint32_t 396 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_CLAMP_CBCR; uint32_t 397 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_OUTSIDE_PIX_STRATEGY; uint32_t 398 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR; uint32_t 399 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_DEBUG; uint32_t 400 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_TEST_DEBUG_INDEX; uint32_t 401 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_TEST_DEBUG_DATA; uint32_t 402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WB_WARM_UP_MODE_CTL1; uint32_t 403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WB_WARM_UP_MODE_CTL2; uint32_t 408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h DWBC_REG_FIELD_LIST_DCN2_0(uint32_t) uint32_t 445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t src_height, uint32_t 446 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t dest_height, uint32_t 451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t src_width, uint32_t 452 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t dest_width, uint32_t 684 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t taps, uint32_t 720 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t src_width, uint32_t 721 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t dest_width, uint32_t 724 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t h_ratio_luma = 1; uint32_t 725 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t h_ratio_chroma = 1; uint32_t 726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t h_taps_luma = num_taps.h_taps; uint32_t 727 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t h_taps_chroma = num_taps.h_taps_c; uint32_t 730 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t h_init_phase_luma_int = 0; uint32_t 731 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t h_init_phase_luma_frac = 0; uint32_t 732 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t h_init_phase_chroma_int = 0; uint32_t 733 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t h_init_phase_chroma_frac = 0; uint32_t 800 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t src_height, uint32_t 801 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t dest_height, uint32_t 805 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t v_ratio_luma = 1; uint32_t 806 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t v_ratio_chroma = 1; uint32_t 807 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t v_taps_luma = num_taps.v_taps; uint32_t 808 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t v_taps_chroma = num_taps.v_taps_c; uint32_t 811 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t v_init_phase_luma_int = 0; uint32_t 812 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t v_init_phase_luma_frac = 0; uint32_t 813 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t v_init_phase_chroma_int = 0; uint32_t 814 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t v_init_phase_chroma_frac = 0; uint32_t 535 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c uint32_t ref_div = 0; uint32_t 536 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c uint32_t ref_en = 0; uint32_t 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t value = 0; uint32_t 329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; uint32_t 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t mirror; uint32_t 402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t dcc_en = enable ? 1 : 0; uint32_t 403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; uint32_t 418 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t red_bar = 3; uint32_t 419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t blue_bar = 2; uint32_t 657 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t dmdata_sw_size, uint32_t 658 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c const uint32_t *dmdata_sw_data) uint32_t 670 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t status; uint32_t 856 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t triple_buffer_en = 0; uint32_t 871 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t triple_buffer_en = 0; uint32_t 887 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t flip_pending = 0; uint32_t 912 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t blank_en = blank ? 1 : 0; uint32_t 919 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t reg_val = REG_READ(DCHUBP_CNTL); uint32_t 950 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t dst_x_offset; uint32_t 951 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t cur_en = pos->enable ? 1 : 0; uint32_t 1025 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t clk_enable = enable ? 1 : 0; uint32_t 1030 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) uint32_t 1275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t inst, uint32_t 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DMDATA_ADDRESS_HIGH; \ uint32_t 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DMDATA_ADDRESS_LOW; \ uint32_t 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DMDATA_CNTL; \ uint32_t 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DMDATA_SW_CNTL; \ uint32_t 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DMDATA_QOS_CNTL; \ uint32_t 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DMDATA_SW_DATA; \ uint32_t 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DMDATA_STATUS;\ uint32_t 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DCSURF_FLIP_CONTROL2;\ uint32_t 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t FLIP_PARAMETERS_0;\ uint32_t 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t FLIP_PARAMETERS_1;\ uint32_t 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t FLIP_PARAMETERS_2;\ uint32_t 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DCN_CUR1_TTU_CNTL0;\ uint32_t 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t DCN_CUR1_TTU_CNTL1;\ uint32_t 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t VMID_SETTINGS_0 uint32_t 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t FLIP_PARAMETERS_3;\ uint32_t 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t FLIP_PARAMETERS_4;\ uint32_t 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t FLIP_PARAMETERS_5;\ uint32_t 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t FLIP_PARAMETERS_6;\ uint32_t 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t VBLANK_PARAMETERS_5;\ uint32_t 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t VBLANK_PARAMETERS_6 uint32_t 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); uint32_t 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); uint32_t 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t inst, uint32_t 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h uint32_t dmdata_sw_size, uint32_t 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h const uint32_t *dmdata_sw_data); uint32_t 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst); uint32_t 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t num_opps, opp_id_src0, opp_id_src1; uint32_t 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t otg_active_width, otg_active_height; uint32_t 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t power_gate = power_on ? 0 : 1; uint32_t 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t pwr_status = power_on ? 0 : 2; uint32_t 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t org_ip_request_cntl = 0; uint32_t 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t power_gate = power_on ? 0 : 1; uint32_t 331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t pwr_status = power_on ? 0 : 2; uint32_t 404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t power_gate = power_on ? 0 : 1; uint32_t 405 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t pwr_status = power_on ? 0 : 2; uint32_t 1929 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t active_total_with_borders; uint32_t 1930 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c uint32_t early_control = 0; uint32_t 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c uint32_t active = 0; uint32_t 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_ana_v2i; uint32_t 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_ana_freq_vco; uint32_t 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_ana_cp_int; uint32_t 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_ana_cp_prop; uint32_t 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_multiplier; uint32_t 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t ref_clk_mpllb_div; uint32_t 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_div_multiplier; uint32_t 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_tx_clk_div; uint32_t 81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_fracn_quot; uint32_t 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_fracn_den; uint32_t 83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_ssc_peak; uint32_t 84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_ssc_stepsize; uint32_t 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_ssc_up_spread; uint32_t 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_fracn_rem; uint32_t 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t mpllb_hdmi_div; uint32_t 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t tx_vboost_lvl; uint32_t 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t hdmi_pixel_clk_div; uint32_t 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t ref_range; uint32_t 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t ref_clk; uint32_t 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx0_term_ctrl; uint32_t 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx1_term_ctrl; uint32_t 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx2_term_ctrl; uint32_t 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx3_term_ctrl; uint32_t 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t fw_data[0x1000]; uint32_t 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx0_width; uint32_t 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx1_width; uint32_t 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx2_width; uint32_t 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx3_width; uint32_t 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx0_rate; uint32_t 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx1_rate; uint32_t 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx2_rate; uint32_t 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx3_rate; uint32_t 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx0_eq_main; uint32_t 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx0_eq_pre; uint32_t 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx0_eq_post; uint32_t 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx1_eq_main; uint32_t 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx1_eq_pre; uint32_t 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx1_eq_post; uint32_t 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx2_eq_main; uint32_t 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx2_eq_pre; uint32_t 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx2_eq_post; uint32_t 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx3_eq_main; uint32_t 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx3_eq_pre; uint32_t 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t dp_tx3_eq_post; uint32_t 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t ldpcs_fifo_start_delay; uint32_t 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h uint32_t rdpcs_fifo_start_delay; uint32_t 442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUFMGR_SW_CONTROL;\ uint32_t 443 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUFMGR_CUR_LINE_R;\ uint32_t 444 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUFMGR_STATUS;\ uint32_t 445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_PITCH;\ uint32_t 446 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_1_STATUS;\ uint32_t 447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_1_STATUS2;\ uint32_t 448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_2_STATUS;\ uint32_t 449 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_2_STATUS2;\ uint32_t 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_3_STATUS;\ uint32_t 451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_3_STATUS2;\ uint32_t 452 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_4_STATUS;\ uint32_t 453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_4_STATUS2;\ uint32_t 454 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_ARBITRATION_CONTROL;\ uint32_t 455 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_SCLK_CHANGE;\ uint32_t 456 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_TEST_DEBUG_INDEX;\ uint32_t 457 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_TEST_DEBUG_DATA;\ uint32_t 458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_1_ADDR_Y;\ uint32_t 459 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;\ uint32_t 460 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_1_ADDR_C;\ uint32_t 461 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;\ uint32_t 462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_2_ADDR_Y;\ uint32_t 463 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;\ uint32_t 464 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_2_ADDR_C;\ uint32_t 465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;\ uint32_t 466 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_3_ADDR_Y;\ uint32_t 467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;\ uint32_t 468 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_3_ADDR_C;\ uint32_t 469 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;\ uint32_t 470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_4_ADDR_Y;\ uint32_t 471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;\ uint32_t 472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_4_ADDR_C;\ uint32_t 473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;\ uint32_t 474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\ uint32_t 475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;\ uint32_t 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_NB_PSTATE_CONTROL;\ uint32_t 477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_WATERMARK;\ uint32_t 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_CLOCK_GATER_CONTROL;\ uint32_t 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_WARM_UP_CNTL;\ uint32_t 480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_SELF_REFRESH_CONTROL;\ uint32_t 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MULTI_LEVEL_QOS_CTRL;\ uint32_t 482 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_SECURITY_LEVEL;\ uint32_t 483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_LUMA_SIZE;\ uint32_t 484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_CHROMA_SIZE;\ uint32_t 485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_1_ADDR_Y_HIGH;\ uint32_t 486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_1_ADDR_C_HIGH;\ uint32_t 487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_2_ADDR_Y_HIGH;\ uint32_t 488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_2_ADDR_C_HIGH;\ uint32_t 489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_3_ADDR_Y_HIGH;\ uint32_t 490 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_3_ADDR_C_HIGH;\ uint32_t 491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_4_ADDR_Y_HIGH;\ uint32_t 492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_4_ADDR_C_HIGH;\ uint32_t 493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_1_RESOLUTION;\ uint32_t 494 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_2_RESOLUTION;\ uint32_t 495 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_3_RESOLUTION;\ uint32_t 496 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t MCIF_WB_BUF_4_RESOLUTION;\ uint32_t 497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h uint32_t SMU_WM_CONTROL uint32_t 505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h MCIF_WB_REG_FIELD_LIST_DCN2_0(uint32_t); uint32_t 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c uint32_t arr_size; uint32_t 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c uint32_t state_mode; uint32_t 343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c uint32_t num) uint32_t 345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c uint32_t i; uint32_t 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \ uint32_t 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \ uint32_t 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \ uint32_t 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \ uint32_t 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \ uint32_t 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \ uint32_t 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \ uint32_t 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \ uint32_t 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \ uint32_t 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \ uint32_t 95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL2_B[MAX_MPCC]; \ uint32_t 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL1_G[MAX_MPCC]; \ uint32_t 97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \ uint32_t 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL1_R[MAX_MPCC]; \ uint32_t 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \ uint32_t 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \ uint32_t 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_REGION_32_33[MAX_MPCC]; \ uint32_t 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_START_CNTL_B[MAX_MPCC]; \ uint32_t 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_START_CNTL_G[MAX_MPCC]; \ uint32_t 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_START_CNTL_R[MAX_MPCC]; \ uint32_t 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_B[MAX_MPCC]; \ uint32_t 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_G[MAX_MPCC]; \ uint32_t 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_R[MAX_MPCC]; \ uint32_t 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL1_B[MAX_MPCC]; \ uint32_t 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL2_B[MAX_MPCC]; \ uint32_t 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \ uint32_t 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL2_G[MAX_MPCC]; \ uint32_t 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \ uint32_t 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL2_R[MAX_MPCC]; \ uint32_t 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \ uint32_t 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_REGION_32_33[MAX_MPCC];\ uint32_t 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\ uint32_t 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\ uint32_t 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\ uint32_t 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\ uint32_t 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_MODE[MAX_MPCC];\ uint32_t 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t CSC_MODE[MAX_OPP]; \ uint32_t 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t CSC_C11_C12_A[MAX_OPP]; \ uint32_t 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t CSC_C33_C34_A[MAX_OPP]; \ uint32_t 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t CSC_C11_C12_B[MAX_OPP]; \ uint32_t 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t CSC_C33_C34_B[MAX_OPP]; \ uint32_t 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t DENORM_CONTROL[MAX_OPP]; \ uint32_t 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t DENORM_CLAMP_G_Y[MAX_OPP]; \ uint32_t 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t DENORM_CLAMP_B_CB[MAX_OPP]; uint32_t 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h MPC_REG_FIELD_LIST_DCN2_0(uint32_t) uint32_t 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c uint32_t src_bpc = 16; uint32_t 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c uint32_t dst_bpc; uint32_t 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c uint32_t index; uint32_t 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c uint32_t inc_base; uint32_t 295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c uint32_t dpg_en, dpg_mode; uint32_t 296 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c uint32_t double_buffer_pending; uint32_t 341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c uint32_t inst, uint32_t 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h uint32_t FMT_422_CONTROL; \ uint32_t 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h uint32_t DPG_CONTROL; \ uint32_t 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h uint32_t DPG_DIMENSIONS; \ uint32_t 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h uint32_t DPG_COLOUR_B_CB; \ uint32_t 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h uint32_t DPG_COLOUR_G_Y; \ uint32_t 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h uint32_t DPG_COLOUR_R_CR; \ uint32_t 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h uint32_t DPG_RAMP_CONTROL; \ uint32_t 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h uint32_t DPG_STATUS uint32_t 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_DCN20_REG_FIELD_LIST(uint32_t); uint32_t 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h uint32_t inst, uint32_t 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; uint32_t 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t gsl_ready_signal) uint32_t 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t dsc_bytes_per_pixel, uint32_t 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t dsc_slice_width) uint32_t 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t h_div_2 = 0; uint32_t 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t memory_mask; uint32_t 239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t data_fmt = 0; uint32_t 282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t *num_of_src_opp, uint32_t 283 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t *src_opp_id_0, uint32_t 284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t *src_opp_id_1) uint32_t 286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t num_of_input_segments; uint32_t 305 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t dwb_pipe_inst) uint32_t 351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t v_blank_start = 0; uint32_t 352 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c uint32_t h_blank_start = 0; uint32_t 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h uint32_t gsl_ready_signal); uint32_t 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h uint32_t dsc_bytes_per_pixel, uint32_t 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h uint32_t dsc_slice_width); uint32_t 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h uint32_t *num_of_src_opp, uint32_t 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h uint32_t *src_opp_id_0, uint32_t 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h uint32_t *src_opp_id_1); uint32_t 974 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c uint32_t inst) uint32_t 992 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 1009 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 1026 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c uint32_t inst) uint32_t 1061 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c uint32_t inst) uint32_t 1120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c uint32_t instance) uint32_t 1282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 1417 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c uint32_t inst) uint32_t 3020 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c uint32_t pipe_count = pool->res_cap->num_dwb; uint32_t 3045 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c uint32_t pipe_count = pool->res_cap->num_dwb; uint32_t 3247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c uint32_t hw_internal_rev) uint32_t 3259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c uint32_t hw_internal_rev) uint32_t 3265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) uint32_t 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h uint32_t inst); uint32_t 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct dc_context *ctx, uint32_t inst); uint32_t 83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct dc_context *ctx, uint32_t inst); uint32_t 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct dc_context *ctx, uint32_t inst); uint32_t 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h uint32_t inst); uint32_t 95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct dc_context *ctx, uint32_t inst); uint32_t 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h uint32_t inst); uint32_t 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h uint32_t instance); uint32_t 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t packet_index, uint32_t 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t cont, send, line; uint32_t 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t i; uint32_t 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t max_retries = 50; uint32_t 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c const uint32_t *content = (const uint32_t *) &info_packet->sb[0]; uint32_t 255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t packet_index = 7 + i; uint32_t 278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t dsc_bytes_per_pixel, uint32_t 279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t dsc_slice_width) uint32_t 375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t hubp_requestor_id, uint32_t 427 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t dmdata_packet_enabled = 0; uint32_t 457 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t n_vid = 0x8000; uint32_t 458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t m_vid; uint32_t 459 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t n_multiply = 0; uint32_t 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c m_vid = (uint32_t) m_vid_l; uint32_t 544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c uint32_t enable_sdp_splitting) uint32_t 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h uint32_t enable_sdp_splitting); uint32_t 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h uint32_t hubp_requestor_id, uint32_t 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c uint32_t entry_lo32; uint32_t 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h DCN20_VMID_REG_FIELD_LIST(uint32_t); uint32_t 57 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c static uint32_t convert_and_clamp( uint32_t 58 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c uint32_t wm_ns, uint32_t 59 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c uint32_t refclk_mhz, uint32_t 60 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c uint32_t clamp_value) uint32_t 62 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c uint32_t ret_val = 0; uint32_t 75 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c uint32_t riommu_active; uint32_t 140 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c uint32_t prog_wm_value; uint32_t 275 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c uint32_t prog_wm_value; uint32_t 409 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c uint32_t prog_wm_value; uint32_t 76 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c uint32_t cur_value; uint32_t 229 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c uint32_t inst, uint32_t 116 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h uint32_t inst, uint32_t 641 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 658 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c uint32_t inst) uint32_t 677 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c uint32_t inst) uint32_t 712 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c uint32_t inst) uint32_t 1147 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c uint32_t inst) uint32_t 1193 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 1210 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c uint32_t instance) uint32_t 1259 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dc_context *ctx, uint32_t inst) uint32_t 102 drivers/gpu/drm/amd/display/dc/dm_helpers.h uint32_t address, uint32_t 104 drivers/gpu/drm/amd/display/dc/dm_helpers.h uint32_t size); uint32_t 112 drivers/gpu/drm/amd/display/dc/dm_helpers.h uint32_t address, uint32_t 114 drivers/gpu/drm/amd/display/dc/dm_helpers.h uint32_t size); uint32_t 260 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h uint32_t Freq; // In MHz uint32_t 261 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h uint32_t Vol; // Millivolts with 2 fractional bits uint32_t 55 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t dm_read_reg_func( uint32_t 57 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t address, uint32_t 72 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t address, uint32_t 73 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t value, uint32_t 86 drivers/gpu/drm/amd/display/dc/dm_services.h static inline uint32_t dm_read_index_reg( uint32_t 89 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t index) uint32_t 97 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t index, uint32_t 98 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t value) uint32_t 103 drivers/gpu/drm/amd/display/dc/dm_services.h static inline uint32_t get_reg_field_value_ex( uint32_t 104 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t reg_value, uint32_t 105 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t mask, uint32_t 117 drivers/gpu/drm/amd/display/dc/dm_services.h static inline uint32_t set_reg_field_value_ex( uint32_t 118 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t reg_value, uint32_t 119 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t value, uint32_t 120 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t mask, uint32_t 134 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t generic_reg_set_ex(const struct dc_context *ctx, uint32_t 135 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t addr, uint32_t reg_val, int n, uint32_t 136 drivers/gpu/drm/amd/display/dc/dm_services.h uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); uint32_t 138 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t generic_reg_update_ex(const struct dc_context *ctx, uint32_t 139 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t addr, int n, uint32_t 140 drivers/gpu/drm/amd/display/dc/dm_services.h uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); uint32_t 150 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t 98 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t num_levels; uint32_t 99 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS]; uint32_t 103 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t clocks_in_khz; uint32_t 104 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t latency_in_us; uint32_t 108 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t num_levels; uint32_t 113 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t clocks_in_khz; uint32_t 114 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t voltage_in_mv; uint32_t 118 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t num_levels; uint32_t 127 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t src_height; uint32_t 128 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t src_width; uint32_t 129 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t v_refresh; uint32_t 130 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t sym_clock; /* HDMI only */ uint32_t 146 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_min_eng_clk_in_khz; uint32_t 147 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_max_eng_clk_in_khz; uint32_t 148 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_min_mem_clk_in_khz; uint32_t 149 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_max_mem_clk_in_khz; uint32_t 153 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t num_wm_sets; uint32_t 159 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_min_dcfclk_clk_in_khz; uint32_t 160 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_max_dcfclk_clk_in_khz; uint32_t 161 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_min_mem_clk_in_khz; uint32_t 162 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_max_mem_clk_in_khz; uint32_t 167 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_min_socclk_clk_in_khz; uint32_t 168 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_max_socclk_clk_in_khz; uint32_t 169 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_min_mem_clk_in_khz; uint32_t 170 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t wm_max_mem_clk_in_khz; uint32_t 174 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t num_wm_dmif_sets; uint32_t 175 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t num_wm_mcif_sets; uint32_t 188 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t cpu_pstate_separation_time; uint32_t 190 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t min_memory_clock_khz; uint32_t 191 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t min_engine_clock_khz; uint32_t 192 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t min_engine_clock_deep_sleep_khz; uint32_t 194 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t avail_mclk_switch_time_us; uint32_t 195 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t avail_mclk_switch_time_in_disp_active_us; uint32_t 196 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t min_dcfclock_khz; uint32_t 197 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t min_dcfc_deep_sleep_clock_khz; uint32_t 199 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t disp_clk_khz; uint32_t 210 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t line_time_in_us; uint32_t 254 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t clocks_in_khz; uint32_t 258 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t max_sclk_khz; uint32_t 259 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t max_mclk_khz; uint32_t 266 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t disp_clk_khz; uint32_t 267 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t min_engine_clock_khz; uint32_t 268 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint32_t min_memory_clock_khz; uint32_t 152 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c static bool dsc_bpp_increment_div_from_dpcd(int bpp_increment_dpcd, uint32_t *bpp_increment_div) uint32_t 256 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_common_caps->bpp_increment_div = min(dsc_common_caps->bpp_increment_div, (uint32_t)8); uint32_t 261 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c static inline uint32_t dsc_div_by_10_round_up(uint32_t value) uint32_t 266 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c static inline uint32_t calc_dsc_bpp_x16(uint32_t stream_bandwidth_kbps, uint32_t pix_clk_100hz, uint32_t bpp_increment_div) uint32_t 268 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c uint32_t dsc_target_bpp_x16; uint32_t 271 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c uint32_t precision = bpp_increment_div; // bpp_increment_div is actually precision uint32_t 276 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_target_bpp_x16 = (uint32_t)(f_dsc_target_bpp * precision); uint32_t 286 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c const uint32_t min_bpp, uint32_t 287 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c const uint32_t max_bpp, uint32_t 806 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c const uint32_t min_bpp, uint32_t 807 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c const uint32_t max_bpp, uint32_t 837 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c uint32_t target_bandwidth_kbps, uint32_t 46 drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h uint32_t bytes_per_pixel; /* In u3.28 format */ uint32_t 47 drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h uint32_t rc_buffer_model_size; uint32_t 123 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_params->bytes_per_pixel = (uint32_t)dsc_ceil(d_bytes_per_pixel * 0x10000000); uint32_t 118 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c uint32_t en) uint32_t 141 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) uint32_t 40 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c uint32_t offset, uint32_t 41 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c uint32_t mask, uint32_t 43 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c uint32_t *en) uint32_t 183 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c uint32_t en, uint32_t 131 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c uint32_t en) uint32_t 154 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) uint32_t 62 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c uint32_t offset, uint32_t 63 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c uint32_t mask, uint32_t 65 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c uint32_t *en) uint32_t 205 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c uint32_t en, uint32_t 118 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c uint32_t en) uint32_t 141 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) uint32_t 44 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c static uint32_t index_from_vector( uint32_t 45 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c uint32_t vector) uint32_t 47 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c uint32_t result = 0; uint32_t 48 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c uint32_t mask = 1; uint32_t 64 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c uint32_t offset, uint32_t 65 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c uint32_t mask, uint32_t 67 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c uint32_t *en) uint32_t 212 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c uint32_t en, uint32_t 151 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) uint32_t 163 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c uint32_t en) uint32_t 186 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) uint32_t 62 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c uint32_t offset, uint32_t 63 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c uint32_t mask, uint32_t 65 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c uint32_t *en) uint32_t 205 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c uint32_t en, uint32_t 170 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c uint32_t en) uint32_t 193 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) uint32_t 203 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) uint32_t 67 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c uint32_t offset, uint32_t 68 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c uint32_t mask, uint32_t 70 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c uint32_t *en) uint32_t 192 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c uint32_t en, uint32_t 160 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) uint32_t 172 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c uint32_t en) uint32_t 195 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) uint32_t 66 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c uint32_t offset, uint32_t 67 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c uint32_t mask, uint32_t 69 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c uint32_t *en) uint32_t 197 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c uint32_t en, uint32_t 124 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t ddc_setup; uint32_t 126 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t phy_aux_cntl; uint32_t 127 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t dc_gpio_aux_ctrl_5; uint32_t 133 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t DC_I2C_DDC1_ENABLE; uint32_t 134 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE; uint32_t 135 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t DC_I2C_DDC1_EDID_DETECT_MODE; uint32_t 137 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t DC_GPIO_DDC1DATA_PD_EN; uint32_t 138 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t DC_GPIO_DDC1CLK_PD_EN; uint32_t 139 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t AUX_PAD1_MODE; uint32_t 141 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t DC_GPIO_SDA_PD_DIS; uint32_t 142 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t DC_GPIO_SCL_PD_DIS; uint32_t 145 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t AUX_PAD_RXSEL; uint32_t 146 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h uint32_t DDC_PAD_I2CMODE; uint32_t 54 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h uint32_t mux; uint32_t 59 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h uint32_t GENERIC_EN; uint32_t 61 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h uint32_t GENERIC_SEL; uint32_t 82 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c uint32_t *value) uint32_t 94 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c uint32_t value) uint32_t 140 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c uint32_t dal_gpio_get_enum( uint32_t 272 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c uint32_t en, uint32_t 30 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t MASK_reg; uint32_t 31 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t MASK_mask; uint32_t 32 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t MASK_shift; uint32_t 33 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t A_reg; uint32_t 34 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t A_mask; uint32_t 35 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t A_shift; uint32_t 36 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t EN_reg; uint32_t 37 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t EN_mask; uint32_t 38 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t EN_shift; uint32_t 39 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t Y_reg; uint32_t 40 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t Y_mask; uint32_t 41 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h uint32_t Y_shift; uint32_t 61 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t index_of_id; uint32_t 88 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t number_of_bits = uint32_t 90 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t i = 0; uint32_t 130 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t offset, uint32_t 131 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t mask) uint32_t 134 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en; uint32_t 146 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t offset, uint32_t 147 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t mask) uint32_t 150 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en; uint32_t 182 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en) uint32_t 206 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t index_of_id = 0; uint32_t 243 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en) uint32_t 251 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en) uint32_t 259 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en) uint32_t 267 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en) uint32_t 281 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en) uint32_t 297 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en = gpio->en; uint32_t 431 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en) uint32_t 472 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t offset, uint32_t 473 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t mask, uint32_t 477 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t en; uint32_t 54 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h uint32_t en); uint32_t 59 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h uint32_t en); uint32_t 65 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h uint32_t int_status; uint32_t 66 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h uint32_t toggle_filt_cntl; uint32_t 71 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h uint32_t DC_HPD_SENSE_DELAYED; uint32_t 72 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h uint32_t DC_HPD_SENSE; uint32_t 74 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h uint32_t DC_HPD_CONNECT_INT_DELAY; uint32_t 75 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h uint32_t DC_HPD_DISCONNECT_INT_DELAY; uint32_t 75 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t regval; uint32_t 76 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t ddc_data_pd_en = 0; uint32_t 77 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t ddc_clk_pd_en = 0; uint32_t 78 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t aux_pad_mode = 0; uint32_t 110 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t reg2; uint32_t 111 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t sda_pd_dis = 0; uint32_t 112 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t scl_pd_dis = 0; uint32_t 226 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t en, uint32_t 237 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t en) uint32_t 45 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h uint32_t en); uint32_t 36 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h uint32_t number_of_pins[GPIO_ID_COUNT]; uint32_t 43 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h uint32_t en); uint32_t 48 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h uint32_t en); uint32_t 53 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h uint32_t en); uint32_t 62 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h uint32_t en); uint32_t 65 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h uint32_t en); uint32_t 68 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h uint32_t en); uint32_t 52 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c uint32_t en, uint32_t 105 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c uint32_t en, uint32_t 116 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c uint32_t en) uint32_t 46 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h uint32_t en); uint32_t 75 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c uint32_t *value) uint32_t 97 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c uint32_t value) uint32_t 182 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c uint32_t en, uint32_t 35 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t addr; uint32_t 36 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t mask; uint32_t 42 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t en; uint32_t 56 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t *value); uint32_t 59 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t value); uint32_t 98 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t mask; uint32_t 99 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t a; uint32_t 100 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t en; uint32_t 101 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t mux; uint32_t 115 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t en, uint32_t 124 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t *value); uint32_t 135 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t value); uint32_t 52 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c uint32_t en, uint32_t 85 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c uint32_t *value) uint32_t 88 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c uint32_t hpd_delayed = 0; uint32_t 135 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c uint32_t en, uint32_t 146 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c uint32_t en) uint32_t 45 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h uint32_t en); uint32_t 31 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.h uint32_t offset, uint32_t 32 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.h uint32_t mask, uint32_t 34 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.h uint32_t *en); uint32_t 37 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.h uint32_t en, uint32_t 36 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t percentage; /*> In unit of 0.01% or 0.001%*/ uint32_t 37 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t percentage_divider; /*> 100 or 1000 */ uint32_t 38 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t freq_range_khz; uint32_t 39 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t modulation_freq_hz; uint32_t 45 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t feedback_amount; uint32_t 46 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t nfrac_amount; uint32_t 47 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t ds_frac_size; uint32_t 48 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t ds_frac_amount; uint32_t 57 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t ENABLE_SS:1; uint32_t 58 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t DISPLAY_BLANKED:1; uint32_t 59 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t PROGRAM_PIXEL_CLOCK:1; uint32_t 60 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t PROGRAM_ID_CLOCK:1; uint32_t 61 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t SUPPORT_YCBCR420:1; uint32_t 71 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t avg_dp_ref_clk_khz; uint32_t 73 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t ss_percentage_on_dp_ref_clk; uint32_t 76 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t ss_percentage_divider; uint32_t 81 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t requested_pix_clk_100hz; uint32_t 84 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t requested_sym_clk; /* in KHz */ uint32_t 86 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t dp_ref_clk; /* in KHz */ uint32_t 107 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t actual_pix_clk_100hz; uint32_t 108 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t adjusted_pix_clk_100hz; uint32_t 109 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t calculated_pix_clk_100hz; uint32_t 110 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t vco_freq; uint32_t 111 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t reference_freq; uint32_t 112 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t reference_divider; uint32_t 113 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t feedback_divider; uint32_t 114 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t fract_feedback_divider; uint32_t 115 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t pix_clk_post_divider; uint32_t 116 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t ss_percentage; uint32_t 122 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t min_pix_clk_pll_post_divider; uint32_t 123 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t max_pix_clk_pll_post_divider; uint32_t 124 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t min_pll_ref_divider; uint32_t 125 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t max_pll_ref_divider; uint32_t 126 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t min_override_input_pxl_clk_pll_freq_khz; uint32_t 129 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t max_override_input_pxl_clk_pll_freq_khz; uint32_t 132 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t num_fract_fb_divider_decimal_point; uint32_t 135 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t num_fract_fb_divider_decimal_point_precision; uint32_t 142 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t ref_freq_khz; uint32_t 143 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t min_pix_clock_pll_post_divider; uint32_t 144 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t max_pix_clock_pll_post_divider; uint32_t 145 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t min_pll_ref_divider; uint32_t 146 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t max_pll_ref_divider; uint32_t 148 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t max_vco_khz; uint32_t 149 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t min_vco_khz; uint32_t 150 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t min_pll_input_freq_khz; uint32_t 151 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t max_pll_input_freq_khz; uint32_t 153 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t fract_fb_divider_decimal_points_num; uint32_t 154 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t fract_fb_divider_factor; uint32_t 155 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t fract_fb_divider_precision; uint32_t 156 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t fract_fb_divider_precision_factor; uint32_t 165 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t (*get_pix_clk_dividers)( uint32_t 42 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t low_part; uint32_t 50 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t inst; uint32_t 51 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t source_view_width; uint32_t 52 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t source_view_height; uint32_t 71 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t fbc_trigger); uint32_t 76 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t *fbc_mapped_crtc_id); uint32_t 81 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t attached_inst; uint32_t 85 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t raw; uint32_t 87 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t FBC_SUPPORT:1; uint32_t 88 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t FB_POOL:1; uint32_t 89 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t DYNAMIC_ALLOC:1; uint32_t 90 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t LPT_SUPPORT:1; uint32_t 91 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t LPT_MC_CONFIG:1; uint32_t 92 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t DUMMY_BACKEND:1; uint32_t 93 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t CLK_GATING_DISABLED:1; uint32_t 100 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t embedded_panel_h_size; uint32_t 101 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t embedded_panel_v_size; uint32_t 102 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t memory_bus_width; uint32_t 103 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t banks_num; uint32_t 104 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t raw_size; uint32_t 105 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t channel_interleave_size; uint32_t 106 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t dram_channels_num; uint32_t 108 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t allocated_size; uint32_t 109 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t preferred_requested_size; uint32_t 110 drivers/gpu/drm/amd/display/dc/inc/compressor.h uint32_t lpt_channels_num; uint32_t 47 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t controller_id); uint32_t 61 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t connector_index; /* this will be mapped to the HPD pins */ uint32_t 62 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t link_index; /* this is mapped to DAL display_index uint32_t 271 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t enable : 1; uint32_t 272 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t disable : 1; uint32_t 273 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t odm : 1; uint32_t 274 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t global_sync : 1; uint32_t 275 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t opp_changed : 1; uint32_t 276 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t tg_changed : 1; uint32_t 277 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t mpcc : 1; uint32_t 278 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t dppclk : 1; uint32_t 279 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t hubp_interdependent : 1; uint32_t 280 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t hubp_rq_dlg_ttu : 1; uint32_t 281 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t gamut_remap : 1; uint32_t 282 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t scaler : 1; uint32_t 283 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t viewport : 1; uint32_t 285 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint32_t raw; uint32_t 37 drivers/gpu/drm/amd/display/dc/inc/custom_float.h uint32_t *result); uint32_t 62 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h uint32_t address, uint32_t 63 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h uint32_t len, uint32_t 92 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h uint32_t address, uint32_t 94 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h uint32_t write_size, uint32_t 96 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h uint32_t read_size); uint32_t 107 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h uint32_t pix_clk, uint32_t 122 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h uint32_t get_defer_delay(struct ddc_service *ddc); uint32_t 135 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t percent_of_ideal_port_bw_received_after_urgent_latency; uint32_t 136 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation; uint32_t 137 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation; uint32_t 139 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t cursor_max_outstanding_group_num; uint32_t 142 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t lines_interleaved_into_lb; uint32_t 143 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t low_power_tiling_mode; uint32_t 144 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t chunk_width; uint32_t 145 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t number_of_graphics_pipes; uint32_t 146 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t number_of_underlay_pipes; uint32_t 158 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t max_dmif_buffer_allocated; uint32_t 159 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t graphics_dmif_size; uint32_t 160 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t underlay_luma_dmif_size; uint32_t 161 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t underlay_chroma_dmif_size; uint32_t 181 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode; uint32_t 182 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t display_write_back420_luma_mcifwr_buffer_size; uint32_t 183 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t display_write_back420_chroma_mcifwr_buffer_size; uint32_t 188 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t scatter_gather_pte_request_rows_in_tiling_mode; uint32_t 194 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t dram_channel_width_in_bits; uint32_t 195 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t number_of_dram_channels; uint32_t 196 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t number_of_dram_banks; uint32_t 223 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t cursor_width; uint32_t 224 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t average_compression_rate; uint32_t 225 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel; uint32_t 239 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t number_of_displays; uint32_t 243 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t graphics_lb_bpc; uint32_t 244 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t underlay_lb_bpc; uint32_t 255 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t y_clk_level; uint32_t 256 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t sclk_level; uint32_t 257 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t number_of_underlay_surfaces; uint32_t 258 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t number_of_dram_wrchannels; uint32_t 259 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t chunk_request_delay; uint32_t 260 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t number_of_dram_channels; uint32_t 357 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t total_stutter_dmif_buffer_size; uint32_t 358 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t total_bytes_requested; uint32_t 359 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t min_stutter_dmif_buffer_size; uint32_t 360 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t num_stutter_bursts; uint32_t 374 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t bytes_per_pixel[maximum_number_of_surfaces]; uint32_t 375 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces]; uint32_t 376 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t lb_bpc[maximum_number_of_surfaces]; uint32_t 377 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t output_bpphdmi[maximum_number_of_surfaces]; uint32_t 378 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces]; uint32_t 379 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces]; uint32_t 380 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces]; uint32_t 452 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t num_displays_with_margin[3][8]; uint32_t 44 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t address; uint32_t 45 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t length; uint32_t 85 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t inst; uint32_t 90 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t delay; uint32_t 91 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t max_defer_write_retry; uint32_t 97 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t current_read_length; uint32_t 98 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t offset; uint32_t 106 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t timed_out_retry_aux; uint32_t 107 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t invalid_reply_retry_aux; uint32_t 108 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t defer_retry_aux; uint32_t 109 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t defer_retry_i2c; uint32_t 110 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t invalid_reply_retry_aux_on_ack; uint32_t 120 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t current_write_length; uint32_t 128 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t timed_out_retry_aux; uint32_t 129 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t invalid_reply_retry_aux; uint32_t 130 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t defer_retry_aux; uint32_t 131 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t defer_retry_i2c; uint32_t 132 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t max_defer_retry; uint32_t 133 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t ack_m_retry; uint32_t 158 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t size, uint32_t 161 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h uint32_t *sw_status); uint32_t 84 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dcfclk; uint32_t 85 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dcf_deep_sleep_divider; uint32_t 86 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dcf_deep_sleep_allow; uint32_t 87 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dprefclk; uint32_t 88 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dispclk; uint32_t 89 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dppclk; uint32_t 91 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dppclk_bypass; uint32_t 92 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dcfclk_bypass; uint32_t 93 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dprefclk_bypass; uint32_t 94 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dispclk_bypass; uint32_t 98 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk uint32_t 99 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider uint32_t 100 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow uint32_t 101 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk uint32_t 102 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk uint32_t 104 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass uint32_t 105 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass uint32_t 106 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass uint32_t 110 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk uint32_t 111 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk uint32_t 112 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk uint32_t 113 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk uint32_t 114 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider uint32_t 115 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow uint32_t 117 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass uint32_t 118 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass uint32_t 119 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass uint32_t 120 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass uint32_t 126 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk uint32_t 127 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider uint32_t 128 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow uint32_t 129 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk uint32_t 130 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk uint32_t 135 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dcfclk_bypass; uint32_t 136 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dispclk_pypass; uint32_t 137 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dprefclk_bypass; uint32_t 159 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h uint32_t dprefclk_khz; uint32_t 162 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h VBIOS_SMU_REG_FIELD_LIST(uint32_t) uint32_t 166 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_REG_FIELD_LIST(uint32_t) uint32_t 168 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK20_REG_FIELD_LIST(uint32_t) uint32_t 170 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h VBIOS_SMU_REG_FIELD_LIST(uint32_t) uint32_t 174 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h uint32_t DPREFCLK_CNTL; uint32_t 175 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h uint32_t DENTIST_DISPCLK_CNTL; uint32_t 178 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h uint32_t CLK3_CLK2_DFS_CNTL; uint32_t 179 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h uint32_t CLK3_CLK_PLL_REQ; uint32_t 182 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h uint32_t MP1_SMN_C2PMSG_67; uint32_t 183 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h uint32_t MP1_SMN_C2PMSG_83; uint32_t 184 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h uint32_t MP1_SMN_C2PMSG_91; uint32_t 220 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h uint32_t dfs_ref_freq_khz; uint32_t 43 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h uint32_t wm_set; uint32_t 44 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h uint32_t data_urgent; uint32_t 45 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h uint32_t pte_meta_urgent; uint32_t 46 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h uint32_t sr_enter; uint32_t 47 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h uint32_t sr_exit; uint32_t 48 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h uint32_t dram_clk_chanage; uint32_t 67 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state); uint32_t 88 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t is_enabled; uint32_t 89 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t igam_lut_mode; uint32_t 90 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t igam_input_format; uint32_t 91 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t dgam_lut_mode; uint32_t 92 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t rgam_lut_mode; uint32_t 93 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t gamut_remap_mode; uint32_t 94 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t gamut_remap_c11_c12; uint32_t 95 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t gamut_remap_c13_c14; uint32_t 96 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t gamut_remap_c21_c22; uint32_t 97 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t gamut_remap_c23_c24; uint32_t 98 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t gamut_remap_c31_c32; uint32_t 99 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t gamut_remap_c33_c34; uint32_t 103 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t cm_bias_cr_r; uint32_t 104 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t cm_bias_y_g; uint32_t 105 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t cm_bias_cb_b; uint32_t 106 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t cm_bias_format; uint32_t 112 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t enable, uint32_t additive_blending); uint32_t 154 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t num); uint32_t 210 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t width, uint32_t 211 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t height uint32_t 216 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint32_t multiplier); uint32_t 35 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h uint32_t pic_width; uint32_t 36 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h uint32_t pic_height; uint32_t 45 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h uint32_t slice_width; /* Slice width in pixels */ uint32_t 46 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h uint32_t bytes_per_pixel; /* Bytes per pixel in u3.28 format */ uint32_t 52 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h uint32_t dsc_clock_en; uint32_t 53 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h uint32_t dsc_slice_width; uint32_t 54 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h uint32_t dsc_bytes_per_pixel; uint32_t 81 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ uint32_t 123 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h uint32_t mask_id; uint32_t 42 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t en; uint32_t 57 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t en); uint32_t 61 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t en); uint32_t 65 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t en); uint32_t 69 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t en); uint32_t 73 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t en); uint32_t 77 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t en); uint32_t 81 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t en); uint32_t 85 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t offset, uint32_t 86 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t mask, uint32_t 88 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t *en); uint32_t 91 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t en, uint32_t 135 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst); uint32_t 149 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h uint32_t dmdata_sw_size, uint32_t 150 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h const uint32_t *dmdata_sw_data); uint32_t 44 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t offset; uint32_t 45 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t segments_num; uint32_t 54 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t custom_float_x; uint32_t 55 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t custom_float_y; uint32_t 56 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t custom_float_offset; uint32_t 57 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t custom_float_slope; uint32_t 75 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t red_reg; uint32_t 76 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t green_reg; uint32_t 77 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t blue_reg; uint32_t 79 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t delta_red_reg; uint32_t 80 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t delta_green_reg; uint32_t 81 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t delta_blue_reg; uint32_t 86 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t red; uint32_t 87 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t green; uint32_t 88 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t blue; uint32_t 127 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint32_t hw_points_num; uint32_t 57 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t IS_HBR2_CAPABLE:1; uint32_t 58 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t IS_HBR3_CAPABLE:1; uint32_t 59 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t IS_TPS3_CAPABLE:1; uint32_t 60 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t IS_TPS4_CAPABLE:1; uint32_t 61 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t HDMI_6GB_EN:1; uint32_t 62 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t DP_IS_USB_C:1; uint32_t 64 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t raw; uint32_t 111 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t output_signals; uint32_t 124 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t dphy_fec_en; uint32_t 125 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t dphy_fec_ready_shadow; uint32_t 126 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t dphy_fec_active_status; uint32_t 145 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t pixel_clock); uint32_t 154 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h uint32_t pixel_clock); uint32_t 35 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t cstate_exit_ns; uint32_t 36 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t cstate_enter_plus_exit_ns; uint32_t 37 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t pstate_change_ns; uint32_t 41 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t pte_meta_urgent_ns; uint32_t 42 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t urgent_ns; uint32_t 44 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t frac_urg_bw_nom; uint32_t 45 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t frac_urg_bw_flip; uint32_t 113 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t total_dest_line_time_ns); uint32_t 120 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t total_dest_line_time_ns); uint32_t 124 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t h_total,/* for current target */ uint32_t 125 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t v_total,/* for current target */ uint32_t 126 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t pix_clk_khz,/* for current target */ uint32_t 127 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t total_streams_num); uint32_t 131 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h uint32_t paths_num); uint32_t 136 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t opp_id; uint32_t 137 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t dpp_id; uint32_t 138 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t bot_mpcc_id; uint32_t 139 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t mode; uint32_t 140 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t alpha_mode; uint32_t 141 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t pre_multiplied_alpha; uint32_t 142 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t overlap_only; uint32_t 143 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t idle; uint32_t 144 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t busy; uint32_t 56 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t TRUNCATE_ENABLED:1; uint32_t 58 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t TRUNCATE_DEPTH:2; uint32_t 60 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t TRUNCATE_MODE:1; uint32_t 64 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t SPATIAL_DITHER_ENABLED:1; uint32_t 66 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t SPATIAL_DITHER_DEPTH:2; uint32_t 68 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t SPATIAL_DITHER_MODE:2; uint32_t 70 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t RGB_RANDOM:1; uint32_t 72 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t FRAME_RANDOM:1; uint32_t 74 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t HIGHPASS_RANDOM:1; uint32_t 78 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t FRAME_MODULATION_ENABLED:1; uint32_t 80 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t FRAME_MODULATION_DEPTH:2; uint32_t 82 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t TEMPORAL_LEVEL:1; uint32_t 83 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t FRC25:2; uint32_t 84 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t FRC50:2; uint32_t 85 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t FRC75:2; uint32_t 88 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t r_seed_value; uint32_t 89 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t b_seed_value; uint32_t 90 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t g_seed_value; uint32_t 130 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t mantissa_bits; uint32_t 131 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t exponenta_bits; uint32_t 136 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t mantissa; uint32_t 137 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t exponenta; uint32_t 138 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t value; uint32_t 143 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t custom_float_x; uint32_t 206 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t inst; uint32_t 238 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t divider; /* (actually HW range is min/divider; divider !=0) */ uint32_t 261 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t active_width; uint32_t 263 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t mso_overlap_pixel_num; uint32_t 264 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t pixel_repetition; uint32_t 266 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h uint32_t num_segment_padded_pixels; uint32_t 57 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t pixel_clock_in_10khz; uint32_t 59 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t n_32khz; uint32_t 61 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t cts_32khz; uint32_t 62 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t n_44khz; uint32_t 63 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t cts_44khz; uint32_t 64 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t n_48khz; uint32_t 65 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t cts_48khz; uint32_t 101 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t custom_pattern_size; uint32_t 114 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t dsc_mode; // DISABLED 0; 1 or 2 indicate enabled state. uint32_t 115 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t dsc_slice_width; uint32_t 116 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t sec_gsp_pps_line_num; uint32_t 117 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t vbid6_line_reference; uint32_t 118 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t vbid6_line_num; uint32_t 119 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t sec_gsp_pps_enable; uint32_t 120 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t sec_stream_enable; uint32_t 129 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t enable_sdp_splitting); uint32_t 224 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t dsc_bytes_per_pixel, uint32_t 225 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t dsc_slice_width); uint32_t 234 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h uint32_t hubp_requestor_id, uint32_t 60 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t vertical_total_min; uint32_t 61 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t vertical_total_max; uint32_t 62 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t vertical_total_mid; uint32_t 63 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t vertical_total_mid_frame_num; uint32_t 150 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t start_line, uint32_t 151 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t end_line); uint32_t 154 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t start_line); uint32_t 157 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t start_line); uint32_t 165 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t (*get_frame_count)(struct timing_generator *tg); uint32_t 168 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *v_blank_start, uint32_t 169 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *v_blank_end, uint32_t 170 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *h_position, uint32_t 171 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *v_position); uint32_t 173 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *otg_active_width, uint32_t 174 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *otg_active_height); uint32_t 178 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t early_cntl); uint32_t 213 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t value); uint32_t 240 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t dwb_pipe_inst); uint32_t 243 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *num_of_input_segments, uint32_t 244 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *seg0_src_sel, uint32_t 245 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *seg1_src_sel); uint32_t 260 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); uint32_t 272 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t dsc_bytes_per_pixel, uint32_t 273 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t dsc_slice_width); uint32_t 281 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h uint32_t gsl_ready_signal); uint32_t 219 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h uint32_t num); uint32_t 33 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h uint32_t CNTL; uint32_t 34 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h uint32_t PAGE_TABLE_BASE_ADDR_HI32; uint32_t 35 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h uint32_t PAGE_TABLE_BASE_ADDR_LO32; uint32_t 36 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h uint32_t PAGE_TABLE_START_ADDR_HI32; uint32_t 37 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h uint32_t PAGE_TABLE_START_ADDR_LO32; uint32_t 38 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h uint32_t PAGE_TABLE_END_ADDR_HI32; uint32_t 39 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h uint32_t PAGE_TABLE_END_ADDR_LO32; uint32_t 335 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h uint32_t clk_khz, uint32_t 336 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h uint32_t stepping); uint32_t 354 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h uint32_t *array_size); uint32_t 33 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h uint32_t address, uint32_t 35 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h uint32_t size); uint32_t 39 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h uint32_t address, uint32_t 41 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h uint32_t size); uint32_t 73 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h uint32_t custom_pattern_size); uint32_t 383 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h { uint32_t val = REG_UPDATE(reg, f1, v1); \ uint32_t 387 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h { uint32_t val = REG_UPDATE(reg, f1, v1); \ uint32_t 391 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr, uint32_t 392 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift, uint32_t mask, uint32_t *field_value); uint32_t 394 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr, uint32_t 395 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 396 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift2, uint32_t mask2, uint32_t *field_value2); uint32_t 398 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint32_t 399 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 400 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 401 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift3, uint32_t mask3, uint32_t *field_value3); uint32_t 403 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, uint32_t 404 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 405 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 406 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 407 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift4, uint32_t mask4, uint32_t *field_value4); uint32_t 409 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint32_t 410 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 411 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 412 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 413 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint32_t 414 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift5, uint32_t mask5, uint32_t *field_value5); uint32_t 416 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr, uint32_t 417 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 418 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 419 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 420 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint32_t 421 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint32_t 422 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift6, uint32_t mask6, uint32_t *field_value6); uint32_t 424 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr, uint32_t 425 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 426 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 427 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 428 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint32_t 429 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint32_t 430 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint32_t 431 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift7, uint32_t mask7, uint32_t *field_value7); uint32_t 433 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr, uint32_t 434 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint32_t 435 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint32_t 436 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint32_t 437 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint32_t 438 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint32_t 439 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint32_t 440 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift7, uint32_t mask7, uint32_t *field_value7, uint32_t 441 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift8, uint32_t mask8, uint32_t *field_value8); uint32_t 475 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t addr_index, uint32_t addr_data, uint32_t 476 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t index, uint32_t data); uint32_t 478 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_read_indirect_reg(const struct dc_context *ctx, uint32_t 479 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t addr_index, uint32_t addr_data, uint32_t 480 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t index); uint32_t 482 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, uint32_t 483 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t addr_index, uint32_t addr_data, uint32_t 484 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t index, uint32_t reg_val, int n, uint32_t 485 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t field_value1, uint32_t 58 drivers/gpu/drm/amd/display/dc/inc/resource.h uint32_t hdmi_disable; uint32_t 59 drivers/gpu/drm/amd/display/dc/inc/resource.h uint32_t dc_pinstraps_audio; uint32_t 60 drivers/gpu/drm/amd/display/dc/inc/resource.h uint32_t audio_stream_number; uint32_t 47 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c uint32_t addr = info->status_reg; uint32_t 48 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c uint32_t value = dm_read_reg(irq_service->ctx, addr); uint32_t 49 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c uint32_t current_status = get_reg_field_value(value, uint32_t 324 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c uint32_t src_id, uint32_t 325 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c uint32_t ext_id) uint32_t 36 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h uint32_t src_id, uint32_t 37 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h uint32_t ext_id); uint32_t 46 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c uint32_t addr = info->status_reg; uint32_t 47 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c uint32_t value = dm_read_reg(irq_service->ctx, addr); uint32_t 48 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c uint32_t current_status = uint32_t 46 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c uint32_t addr = info->status_reg; uint32_t 47 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c uint32_t value = dm_read_reg(irq_service->ctx, addr); uint32_t 48 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c uint32_t current_status = uint32_t 45 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c uint32_t src_id, uint32_t 46 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c uint32_t ext_id) uint32_t 127 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c uint32_t addr = info->status_reg; uint32_t 128 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c uint32_t value = dm_read_reg(irq_service->ctx, addr); uint32_t 129 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c uint32_t current_status = uint32_t 45 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c uint32_t src_id, uint32_t 46 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c uint32_t ext_id) uint32_t 127 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c uint32_t addr = info->status_reg; uint32_t 128 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c uint32_t value = dm_read_reg(irq_service->ctx, addr); uint32_t 129 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c uint32_t current_status = uint32_t 45 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c uint32_t src_id, uint32_t 46 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c uint32_t ext_id) uint32_t 128 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c uint32_t addr = info->status_reg; uint32_t 129 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c uint32_t value = dm_read_reg(irq_service->ctx, addr); uint32_t 130 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c uint32_t current_status = uint32_t 94 drivers/gpu/drm/amd/display/dc/irq/irq_service.c uint32_t addr = info->enable_reg; uint32_t 95 drivers/gpu/drm/amd/display/dc/irq/irq_service.c uint32_t value = dm_read_reg(irq_service->ctx, addr); uint32_t 131 drivers/gpu/drm/amd/display/dc/irq/irq_service.c uint32_t addr = info->ack_reg; uint32_t 132 drivers/gpu/drm/amd/display/dc/irq/irq_service.c uint32_t value = dm_read_reg(irq_service->ctx, addr); uint32_t 163 drivers/gpu/drm/amd/display/dc/irq/irq_service.c uint32_t src_id, uint32_t 164 drivers/gpu/drm/amd/display/dc/irq/irq_service.c uint32_t ext_id) uint32_t 47 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t src_id; uint32_t 48 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t ext_id; uint32_t 49 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t enable_reg; uint32_t 50 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t enable_mask; uint32_t 51 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t enable_value[2]; uint32_t 52 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t ack_reg; uint32_t 53 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t ack_mask; uint32_t 54 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t ack_value; uint32_t 55 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t status_reg; uint32_t 62 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t src_id, uint32_t 63 drivers/gpu/drm/amd/display/dc/irq/irq_service.h uint32_t ext_id); uint32_t 192 drivers/gpu/drm/amd/display/dc/irq_types.h uint32_t micro_sec_interval; uint32_t 48 drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c uint32_t pixel_clock) {} uint32_t 35 drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c uint32_t enable_sdp_splitting) {} uint32_t 37 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t h_total; uint32_t 38 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t h_active; uint32_t 39 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t v_active; uint32_t 40 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t pixel_repetition; uint32_t 41 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t requested_pixel_clock_100Hz; /* in 100Hz */ uint32_t 42 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t calculated_pixel_clock_100Hz; /* in 100Hz */ uint32_t 43 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t refresh_rate; uint32_t 48 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t pixel_clock_in_10khz; uint32_t 49 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t audio_dto_phase; uint32_t 50 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t audio_dto_module; uint32_t 51 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t audio_dto_wall_clock_ratio; uint32_t 67 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t dp_dto_source_clock_in_khz; uint32_t 68 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t feed_back_divider; uint32_t 71 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ss_percentage; uint32_t 72 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ss_percentage_divider; uint32_t 78 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ALL_CHANNEL_FL:4; uint32_t 79 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ALL_CHANNEL_FR:4; uint32_t 80 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ALL_CHANNEL_FC:4; uint32_t 81 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ALL_CHANNEL_Sub:4; uint32_t 82 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ALL_CHANNEL_SL:4; uint32_t 83 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ALL_CHANNEL_SR:4; uint32_t 84 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ALL_CHANNEL_BL:4; uint32_t 85 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t ALL_CHANNEL_BR:4; uint32_t 87 drivers/gpu/drm/amd/display/include/audio_types.h uint32_t u32all; uint32_t 112 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t pixel_clock; /* khz */ uint32_t 125 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t pixel_clock; /* in KHz */ uint32_t 152 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t pixel_clock; uint32_t 153 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t lane_select; uint32_t 154 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t lane_settings; uint32_t 163 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t h_total; uint32_t 164 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t h_addressable; uint32_t 165 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t h_overscan_left; uint32_t 166 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t h_overscan_right; uint32_t 167 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t h_sync_start; uint32_t 168 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t h_sync_width; uint32_t 171 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t v_total; uint32_t 172 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t v_addressable; uint32_t 173 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t v_overscan_top; uint32_t 174 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t v_overscan_bottom; uint32_t 175 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t v_sync_start; uint32_t 176 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t v_sync_width; uint32_t 179 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t INTERLACE:1; uint32_t 180 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t PIXEL_REPETITION:4; uint32_t 181 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t HSYNC_POSITIVE_POLARITY:1; uint32_t 182 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t VSYNC_POSITIVE_POLARITY:1; uint32_t 183 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t HORZ_COUNT_BY_TWO:1; uint32_t 195 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t pixel_clock; uint32_t 197 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t adjusted_pixel_clock; uint32_t 200 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t reference_divider; uint32_t 203 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t pixel_clock_post_divider; uint32_t 215 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t target_pixel_clock_100hz; uint32_t 217 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t reference_divider; uint32_t 219 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t feedback_divider; uint32_t 221 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t fractional_feedback_divider; uint32_t 223 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t pixel_clock_post_divider; uint32_t 227 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t dfs_bypass_display_clock; uint32_t 232 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t FORCE_PROGRAMMING_OF_PLL:1; uint32_t 235 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1; uint32_t 237 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t SET_EXTERNAL_REF_DIV_SRC:1; uint32_t 239 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t SET_DISPCLK_DFS_BYPASS:1; uint32_t 241 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t PROGRAM_PHY_PLL_ONLY:1; uint32_t 243 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t SUPPORT_YUV_420:1; uint32_t 245 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t SET_XTALIN_REF_SRC:1; uint32_t 247 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t SET_GENLOCK_REF_DIV_SRC:1; uint32_t 260 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t target_clock_frequency; uint32_t 265 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1; uint32_t 267 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1; uint32_t 269 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1; uint32_t 271 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1; uint32_t 277 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t CENTER_SPREAD:1; uint32_t 279 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t EXTERNAL_SS:1; uint32_t 281 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t DS_TYPE:1; uint32_t 286 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t percentage; uint32_t 287 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t ds_frac_amount; uint32_t 291 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t step; uint32_t 292 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t delay; uint32_t 293 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t range; /* In Hz unit */ uint32_t 296 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t feedback_amount; uint32_t 297 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t nfrac_amount; uint32_t 298 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t ds_frac_size; uint32_t 306 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t DP_HBR2_CAP:1; uint32_t 307 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t DP_HBR2_EN:1; uint32_t 308 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t DP_HBR3_EN:1; uint32_t 309 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t HDMI_6GB_EN:1; uint32_t 310 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t DP_IS_USB_C:1; uint32_t 311 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t RESERVED:27; uint32_t 67 drivers/gpu/drm/amd/display/include/ddc_service_types.h uint32_t downstrm_sink_count; uint32_t 73 drivers/gpu/drm/amd/display/include/ddc_service_types.h uint32_t additional_audio_delay; uint32_t 75 drivers/gpu/drm/amd/display/include/ddc_service_types.h uint32_t audio_latency; uint32_t 77 drivers/gpu/drm/amd/display/include/ddc_service_types.h uint32_t video_latency_interlace; uint32_t 79 drivers/gpu/drm/amd/display/include/ddc_service_types.h uint32_t video_latency_progressive; uint32_t 81 drivers/gpu/drm/amd/display/include/ddc_service_types.h uint32_t max_hdmi_pixel_clock; uint32_t 91 drivers/gpu/drm/amd/display/include/ddc_service_types.h uint32_t dp_link_lane_count; uint32_t 92 drivers/gpu/drm/amd/display/include/ddc_service_types.h uint32_t dp_link_rate; uint32_t 93 drivers/gpu/drm/amd/display/include/ddc_service_types.h uint32_t dp_link_spead; uint32_t 46 drivers/gpu/drm/amd/display/include/gpio_interface.h uint32_t *value); uint32_t 51 drivers/gpu/drm/amd/display/include/gpio_interface.h uint32_t value); uint32_t 75 drivers/gpu/drm/amd/display/include/gpio_interface.h uint32_t dal_gpio_get_enum( uint32_t 38 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t en, uint32_t 51 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t offset, uint32_t 52 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t mask); uint32_t 56 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t offset, uint32_t 57 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t mask); uint32_t 69 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t en); uint32_t 73 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t offset, uint32_t 74 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t mask, uint32_t 96 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t en); uint32_t 77 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t offset; uint32_t 78 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t offset_y; uint32_t 79 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t offset_en; uint32_t 80 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t offset_mask; uint32_t 82 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t mask; uint32_t 83 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t mask_y; uint32_t 84 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t mask_en; uint32_t 85 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t mask_mask; uint32_t 299 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t delay_on_connect; /* milliseconds */ uint32_t 300 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t delay_on_disconnect; /* milliseconds */ uint32_t 319 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t gsl_group; uint32_t 67 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t enum_id:16; /* 1 based enum */ uint32_t 73 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t clk_mask_register_index; uint32_t 74 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t clk_en_register_index; uint32_t 75 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t clk_y_register_index; uint32_t 76 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t clk_a_register_index; uint32_t 77 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t data_mask_register_index; uint32_t 78 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t data_en_register_index; uint32_t 79 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t data_y_register_index; uint32_t 80 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t data_a_register_index; uint32_t 82 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t clk_mask_shift; uint32_t 83 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t clk_en_shift; uint32_t 84 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t clk_y_shift; uint32_t 85 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t clk_a_shift; uint32_t 86 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t data_mask_shift; uint32_t 87 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t data_en_shift; uint32_t 88 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t data_y_shift; uint32_t 89 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t data_a_shift; uint32_t 93 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t i2c_line; uint32_t 94 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t i2c_engine_id; uint32_t 95 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t i2c_slave_address; uint32_t 104 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t acpi_device; uint32_t 110 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t HORIZONTAL_CUT_OFF:1; uint32_t 112 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t H_SYNC_POLARITY:1; uint32_t 114 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t V_SYNC_POLARITY:1; uint32_t 115 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t VERTICAL_CUT_OFF:1; uint32_t 116 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t H_REPLICATION_BY2:1; uint32_t 117 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t V_REPLICATION_BY2:1; uint32_t 118 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t COMPOSITE_SYNC:1; uint32_t 119 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t INTERLACE:1; uint32_t 120 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t DOUBLE_CLOCK:1; uint32_t 121 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t RGB888:1; uint32_t 122 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t GREY_LEVEL:2; uint32_t 123 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t SPATIAL:1; uint32_t 124 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t TEMPORAL:1; uint32_t 125 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t API_ENABLED:1; uint32_t 128 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t pixel_clk; /* in KHz */ uint32_t 129 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t horizontal_addressable; uint32_t 130 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t horizontal_blanking_time; uint32_t 131 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t vertical_addressable; uint32_t 132 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t vertical_blanking_time; uint32_t 133 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t horizontal_sync_offset; uint32_t 134 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t horizontal_sync_width; uint32_t 135 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t vertical_sync_offset; uint32_t 136 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t vertical_sync_width; uint32_t 137 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t horizontal_border; uint32_t 138 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t vertical_border; uint32_t 142 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t REFRESH_RATE_30HZ:1; uint32_t 143 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t REFRESH_RATE_40HZ:1; uint32_t 144 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t REFRESH_RATE_48HZ:1; uint32_t 145 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t REFRESH_RATE_50HZ:1; uint32_t 146 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t REFRESH_RATE_60HZ:1; uint32_t 151 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t ss_id; uint32_t 153 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t drr_enabled; uint32_t 154 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t min_drr_refresh_rate; uint32_t 160 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t crystal_frequency; /* in KHz */ uint32_t 161 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */ uint32_t 162 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */ uint32_t 163 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */ uint32_t 164 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */ uint32_t 168 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t memory_clk_ss_percentage; uint32_t 169 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t engine_clk_ss_percentage; uint32_t 172 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t default_display_engine_pll_frequency; /* in KHz */ uint32_t 173 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t external_clock_source_frequency_for_dp; /* in KHz */ uint32_t 174 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t smu_gpu_pll_output_freq; /* in KHz */ uint32_t 177 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t default_memory_clk; /* in KHz */ uint32_t 178 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t default_engine_clk; /* in KHz */ uint32_t 179 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */ uint32_t 180 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */ uint32_t 186 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t step; uint32_t 187 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t delay; uint32_t 188 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t recommended_ref_div; uint32_t 200 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t spread_spectrum_percentage; uint32_t 201 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t spread_percentage_divider; /* 100 or 1000 */ uint32_t 202 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t spread_spectrum_range; /* modulation freq (HZ)*/ uint32_t 209 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t target_clock_range; /* in KHz */ uint32_t 215 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t dp_hbr2_cap:1; uint32_t 216 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t dp_hbr2_validated:1; uint32_t 220 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t reserved:15; uint32_t 224 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t gpio_id; uint32_t 287 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t voltage_index; uint32_t 289 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t max_supported_clk; /* in KHz */ uint32_t 295 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t device_tag; uint32_t 297 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t device_acpi_enum; uint32_t 319 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t supported_s_clk; /* in KHz */ uint32_t 321 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t voltage_index; uint32_t 323 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t voltage_id; uint32_t 328 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t boot_up_engine_clock; /* in KHz */ uint32_t 329 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t dentist_vco_freq; /* in KHz */ uint32_t 330 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t boot_up_uma_clock; /* in KHz */ uint32_t 331 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t boot_up_req_display_vector; uint32_t 332 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t other_display_misc; uint32_t 333 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t gpu_cap_info; uint32_t 334 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t sb_mmio_base_addr; uint32_t 335 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t system_config; uint32_t 336 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t cpu_cap_info; uint32_t 337 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t max_nb_voltage; uint32_t 338 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t min_nb_voltage; uint32_t 339 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t boot_up_nb_voltage; uint32_t 340 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t ext_disp_conn_info_offset; uint32_t 341 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB]; uint32_t 342 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB]; uint32_t 343 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB]; uint32_t 344 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t gmc_restore_reset_time; uint32_t 345 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t minimum_n_clk; uint32_t 346 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t idle_n_clk; uint32_t 347 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t ddr_dll_power_up_time; uint32_t 348 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t ddr_pll_power_up_time; uint32_t 350 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t pcie_clk_ss_type; uint32_t 351 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_ss_percentage; uint32_t 352 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_sspread_rate_in_10hz; uint32_t 353 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t hdmi_ss_percentage; uint32_t 354 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t hdmi_sspread_rate_in_10hz; uint32_t 355 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t dvi_ss_percentage; uint32_t 356 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t dvi_sspread_rate_in_10_hz; uint32_t 357 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t sclk_dpm_boost_margin; uint32_t 358 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t sclk_dpm_throttle_margin; uint32_t 359 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t sclk_dpm_tdp_limit_pg; uint32_t 360 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t sclk_dpm_tdp_limit_boost; uint32_t 361 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t boost_engine_clock; uint32_t 362 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t boost_vid_2bit; uint32_t 363 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t enable_boost; uint32_t 364 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t gnb_tdp_limit; uint32_t 366 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t max_lvds_pclk_freq_in_single_link; uint32_t 367 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_misc; uint32_t 368 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms; uint32_t 369 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms; uint32_t 370 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms; uint32_t 371 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms; uint32_t 372 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_off_to_on_delay_in_4ms; uint32_t 373 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms; uint32_t 374 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms; uint32_t 375 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_reserved1; uint32_t 376 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t lvds_bit_depth_control_val; uint32_t 399 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t dp_ss_control; uint32_t 414 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t thermal_state; uint32_t 415 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t backlight_level; uint32_t 437 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t min_signal_level; uint32_t 438 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h uint32_t max_signal_level; uint32_t 221 drivers/gpu/drm/amd/display/include/grph_object_id.h uint32_t id:8; uint32_t 222 drivers/gpu/drm/amd/display/include/grph_object_id.h uint32_t enum_id:4; uint32_t 223 drivers/gpu/drm/amd/display/include/grph_object_id.h uint32_t type:4; uint32_t 224 drivers/gpu/drm/amd/display/include/grph_object_id.h uint32_t reserved:16; /* for padding. total size should be u32 */ uint32_t 230 drivers/gpu/drm/amd/display/include/grph_object_id.h uint32_t id, uint32_t 242 drivers/gpu/drm/amd/display/include/grph_object_id.h static inline uint32_t dal_graphics_object_id_to_uint( uint32_t 44 drivers/gpu/drm/amd/display/include/i2caux_interface.h uint32_t address; uint32_t 55 drivers/gpu/drm/amd/display/include/i2caux_interface.h uint32_t defer_delay; uint32_t 64 drivers/gpu/drm/amd/display/include/i2caux_interface.h uint32_t defer_delay; uint32_t 67 drivers/gpu/drm/amd/display/include/i2caux_interface.h uint32_t max_defer_write_retry; uint32_t 74 drivers/gpu/drm/amd/display/include/i2caux_interface.h uint32_t ALLOW_AUX_WHEN_HPD_LOW:1; uint32_t 76 drivers/gpu/drm/amd/display/include/i2caux_interface.h uint32_t raw; uint32_t 48 drivers/gpu/drm/amd/display/include/irq_service_interface.h uint32_t src_id, uint32_t 49 drivers/gpu/drm/amd/display/include/irq_service_interface.h uint32_t ext_id); uint32_t 31 drivers/gpu/drm/amd/display/include/vector.h uint32_t struct_size; uint32_t 32 drivers/gpu/drm/amd/display/include/vector.h uint32_t count; uint32_t 33 drivers/gpu/drm/amd/display/include/vector.h uint32_t capacity; uint32_t 40 drivers/gpu/drm/amd/display/include/vector.h uint32_t capacity, uint32_t 41 drivers/gpu/drm/amd/display/include/vector.h uint32_t struct_size); uint32_t 45 drivers/gpu/drm/amd/display/include/vector.h uint32_t capacity, uint32_t 46 drivers/gpu/drm/amd/display/include/vector.h uint32_t struct_size); uint32_t 52 drivers/gpu/drm/amd/display/include/vector.h uint32_t size, uint32_t 54 drivers/gpu/drm/amd/display/include/vector.h uint32_t struct_size); uint32_t 62 drivers/gpu/drm/amd/display/include/vector.h uint32_t dal_vector_get_count( uint32_t 75 drivers/gpu/drm/amd/display/include/vector.h uint32_t position); uint32_t 84 drivers/gpu/drm/amd/display/include/vector.h uint32_t index); uint32_t 89 drivers/gpu/drm/amd/display/include/vector.h uint32_t index); uint32_t 100 drivers/gpu/drm/amd/display/include/vector.h uint32_t index); uint32_t 102 drivers/gpu/drm/amd/display/include/vector.h uint32_t dal_vector_capacity(const struct vector *vector); uint32_t 104 drivers/gpu/drm/amd/display/include/vector.h bool dal_vector_reserve(struct vector *vector, uint32_t capacity); uint32_t 116 drivers/gpu/drm/amd/display/include/vector.h uint32_t position) \ uint32_t 136 drivers/gpu/drm/amd/display/include/vector.h uint32_t index) \ uint32_t 145 drivers/gpu/drm/amd/display/include/vector.h uint32_t index) \ uint32_t 77 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t seg_offset; uint32_t 78 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t index; uint32_t 180 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t sdr_white_level, uint32_t max_luminance_nits) uint32_t 211 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t sdr_white_level, uint32_t max_luminance_nits) uint32_t 266 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t begin_index, end_index; uint32_t 297 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i = 0; uint32_t 298 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t index = 0; uint32_t 426 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t color_index) uint32_t 442 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t color_index) uint32_t 459 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t *index_to_start, uint32_t 460 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t *index_left, uint32_t 461 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t *index_right, uint32_t 464 drivers/gpu/drm/amd/display/modules/color/color_gamma.c const uint32_t max_number = ramp->num_entries + 3; uint32_t 468 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i = *index_to_start; uint32_t 539 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t number_of_points) uint32_t 541 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i = 0; uint32_t 546 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t index_to_start = 0; uint32_t 547 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t index_left = 0; uint32_t 548 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t index_right = 0; uint32_t 629 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t max_index) uint32_t 689 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 691 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t sdr_white_level) uint32_t 693 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i, start_index; uint32_t 741 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 744 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 769 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 772 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 889 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 893 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 979 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 982 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 984 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t begin_index, end_index; uint32_t 1028 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 1030 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t sdr_white_level, uint32_t max_luminance_nits) uint32_t 1032 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 1051 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 1053 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t sdr_white_level, uint32_t max_luminance_nits) uint32_t 1055 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 1080 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 1140 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 1211 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 1286 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t num_hw_points, uint32_t 1348 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t numberof_points, uint32_t 1354 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i = 0; uint32_t 1391 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 1395 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i = 0; uint32_t 1415 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t number_of_points, uint32_t 1420 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t max_entries = 3 - 1; uint32_t 1422 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i = 0; uint32_t 1470 drivers/gpu/drm/amd/display/modules/color/color_gamma.c static void interpolate_user_regamma(uint32_t hw_points_num, uint32_t 1475 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 1476 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t color = 0; uint32_t 1548 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 1551 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 1571 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num) uint32_t 1573 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 1600 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t hw_points_num, uint32_t 1766 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i = 0; uint32_t 1880 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 1993 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t sdr_ref_white_level) uint32_t 1995 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 2094 drivers/gpu/drm/amd/display/modules/color/color_gamma.c uint32_t i; uint32_t 108 drivers/gpu/drm/amd/display/modules/color/color_gamma.h uint32_t sdr_ref_white_level); uint32_t 31 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t custom_float_x; uint32_t 32 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t custom_float_y; uint32_t 33 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t custom_float_slope; uint32_t 37 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t red; uint32_t 38 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t green; uint32_t 39 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t blue; uint32_t 40 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t delta_red; uint32_t 41 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t delta_green; uint32_t 42 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t delta_blue; uint32_t 49 drivers/gpu/drm/amd/display/modules/color/luts_1d.h uint32_t hw_points_num; uint32_t 1018 drivers/gpu/drm/amd/display/modules/freesync/freesync.c uint32_t min_refresh_cap_in_uhz, uint32_t 1019 drivers/gpu/drm/amd/display/modules/freesync/freesync.c uint32_t max_refresh_cap_in_uhz, uint32_t 1020 drivers/gpu/drm/amd/display/modules/freesync/freesync.c uint32_t min_refresh_request_in_uhz, uint32_t 1021 drivers/gpu/drm/amd/display/modules/freesync/freesync.c uint32_t max_refresh_request_in_uhz) uint32_t 91 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t mid_point_in_us; uint32_t 92 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t inserted_duration_in_us; uint32_t 93 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t frames_to_insert; uint32_t 94 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t frame_counter; uint32_t 101 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t target_refresh_in_uhz; uint32_t 102 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t frame_counter; uint32_t 110 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t min_refresh_in_uhz; uint32_t 111 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t max_duration_in_us; uint32_t 112 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t max_refresh_in_uhz; uint32_t 113 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t min_duration_in_us; uint32_t 171 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t min_refresh_cap_in_uhz, uint32_t 172 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t max_refresh_cap_in_uhz, uint32_t 173 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t min_refresh_request_in_uhz, uint32_t 174 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h uint32_t max_refresh_request_in_uhz); uint32_t 28 drivers/gpu/drm/amd/include/amd_pcie_helpers.h static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap) uint32_t 36 drivers/gpu/drm/amd/include/amd_pcie_helpers.h static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap) uint32_t 45 drivers/gpu/drm/amd/include/amd_pcie_helpers.h static inline uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint32_t 48 drivers/gpu/drm/amd/include/amd_pcie_helpers.h uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap & uint32_t 50 drivers/gpu/drm/amd/include/amd_pcie_helpers.h uint32_t sys_pcie_link_speed_cap = (pcie_link_speed_cap & uint32_t 76 drivers/gpu/drm/amd/include/amd_pcie_helpers.h static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint32_t 40 drivers/gpu/drm/amd/include/atom-bits.h static inline uint32_t get_u32(void *bios, int ptr) uint32_t 42 drivers/gpu/drm/amd/include/atom-bits.h return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16); uint32_t 31 drivers/gpu/drm/amd/include/atom-types.h typedef uint32_t ULONG; uint32_t 44 drivers/gpu/drm/amd/include/atomfirmware.h #ifndef uint32_t uint32_t 253 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pspdirtableoffset; uint32_t 474 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t firmware_revision; uint32_t 475 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_sclk_in10khz; uint32_t 476 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_mclk_in10khz; uint32_t 477 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t 478 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ uint32_t 479 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint32_t 487 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mc_baseaddr_high; uint32_t 488 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mc_baseaddr_low; uint32_t 489 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved2[6]; uint32_t 510 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t firmware_revision; uint32_t 511 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_sclk_in10khz; uint32_t 512 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_mclk_in10khz; uint32_t 513 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t 514 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ uint32_t 515 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint32_t 523 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mc_baseaddr_high; uint32_t 524 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mc_baseaddr_low; uint32_t 531 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t zfbstartaddrin16mb; uint32_t 532 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved2[3]; uint32_t 538 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t firmware_revision; uint32_t 539 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_sclk_in10khz; uint32_t 540 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_mclk_in10khz; uint32_t 541 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t 542 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ uint32_t 543 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint32_t 551 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mc_baseaddr_high; uint32_t 552 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mc_baseaddr_low; uint32_t 559 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t zfbstartaddrin16mb; uint32_t 560 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS uint32_t 561 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved2[2]; uint32_t 596 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved1[8]; uint32_t 621 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t data_a_reg_index; uint32_t 669 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t start_address_in_kb; uint32_t 728 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t encodercaps; uint32_t 740 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t connectcaps; uint32_t 878 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t display_caps; uint32_t 879 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_dispclk_10khz; uint32_t 911 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t display_caps; uint32_t 912 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_dispclk_10khz; uint32_t 1003 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t param; uint32_t 1026 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t versionCode; uint32_t 1030 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t crc_val; // CRC uint32_t 1036 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t max_symclk_in10khz; uint32_t 1096 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def uint32_t 1097 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def uint32_t 1098 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t system_config; uint32_t 1099 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t cpucapinfo; uint32_t 1139 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[66]; uint32_t 1208 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable uint32_t 1229 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_src_addr; uint32_t 1230 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_src_addr_hi; uint32_t 1231 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_dst_addr; uint32_t 1232 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_dst_addr_hi; uint32_t 1233 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_command; uint32_t 1234 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_status; uint32_t 1235 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_rlc_gpu_clock_32; uint32_t 1236 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t rlc_gpu_timer_refclk; uint32_t 1249 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_src_addr; uint32_t 1250 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_src_addr_hi; uint32_t 1251 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_dst_addr; uint32_t 1252 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_dst_addr_hi; uint32_t 1253 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_command; uint32_t 1254 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_status; uint32_t 1255 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_rlc_gpu_clock_32; uint32_t 1256 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t rlc_gpu_timer_refclk; uint32_t 1260 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t rm21_sram_vmin_value; uint32_t 1274 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_src_addr; uint32_t 1275 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_src_addr_hi; uint32_t 1276 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_dst_addr; uint32_t 1277 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_dst_addr_hi; uint32_t 1278 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_dma_command; uint32_t 1279 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_cp_status; uint32_t 1280 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t regaddr_rlc_gpu_clock_32; uint32_t 1281 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t rlc_gpu_timer_refclk; uint32_t 1295 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t sram_rm_fuses_val; uint32_t 1296 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t sram_custom_rm_fuses_val; uint32_t 1315 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t core_refclk_10khz; uint32_t 1336 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t core_refclk_10khz; uint32_t 1348 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gpupll_vco_freq_10khz; uint32_t 1349 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_smnclk_10khz; uint32_t 1350 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_socclk_10khz; uint32_t 1351 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_mp0clk_10khz; uint32_t 1352 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_mp1clk_10khz; uint32_t 1353 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_lclk_10khz; uint32_t 1354 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_dcefclk_10khz; uint32_t 1355 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ctf_threshold_override_value; uint32_t 1356 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[5]; uint32_t 1369 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t core_refclk_10khz; uint32_t 1381 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gpupll_vco_freq_10khz; uint32_t 1382 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_smnclk_10khz; uint32_t 1383 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_socclk_10khz; uint32_t 1384 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_mp0clk_10khz; uint32_t 1385 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_mp1clk_10khz; uint32_t 1386 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_lclk_10khz; uint32_t 1387 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_dcefclk_10khz; uint32_t 1388 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ctf_threshold_override_value; uint32_t 1389 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t syspll3_0_vco_freq_10khz; uint32_t 1390 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t syspll3_1_vco_freq_10khz; uint32_t 1391 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_fclk_10khz; uint32_t 1392 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t bootup_waflclk_10khz; uint32_t 1393 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t smu_info_caps; uint32_t 1396 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved; uint32_t 1484 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t boardreserved[9]; uint32_t 1570 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t boardreserved[10]; uint32_t 1574 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t enabled; uint32_t 1575 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t slaveaddress; uint32_t 1576 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t controllerport; uint32_t 1577 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t controllername; uint32_t 1578 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t thermalthrottler; uint32_t 1579 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t i2cprotocol; uint32_t 1580 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t i2cspeed; uint32_t 1586 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t i2c_padding[3]; uint32_t 1658 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t boardreserved[10]; uint32_t 1700 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t SlaveAddress; uint32_t 1786 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) uint32_t 1788 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t BoardReserved[9]; uint32_t 1796 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t i2c_padding[3]; // old i2c control are moved to new area uint32_t 1858 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. uint32_t 1875 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t boardreserved[10]; uint32_t 1886 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t maxvddc; uint32_t 1887 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t minvddc; uint32_t 1888 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfs_meannsigma_acontant0; uint32_t 1889 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfs_meannsigma_acontant1; uint32_t 1890 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfs_meannsigma_acontant2; uint32_t 1894 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_cksoff_a0; uint32_t 1895 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_cksoff_a1; uint32_t 1896 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_cksoff_a2; uint32_t 1897 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_ckson_a0; uint32_t 1898 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_ckson_a1; uint32_t 1899 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_ckson_a2; uint32_t 1900 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_cksoff_m1; uint32_t 1901 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_cksoff_m2; uint32_t 1902 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_cksoff_b; uint32_t 1903 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_ckson_m1; uint32_t 1904 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_ckson_m2; uint32_t 1905 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_ckson_b; uint32_t 1914 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dispclk2gfxclk_a; uint32_t 1915 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dispclk2gfxclk_b; uint32_t 1916 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dispclk2gfxclk_c; uint32_t 1917 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pixclk2gfxclk_a; uint32_t 1918 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pixclk2gfxclk_b; uint32_t 1919 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pixclk2gfxclk_c; uint32_t 1920 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dcefclk2gfxclk_a; uint32_t 1921 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dcefclk2gfxclk_b; uint32_t 1922 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dcefclk2gfxclk_c; uint32_t 1923 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t phyclk2gfxclk_a; uint32_t 1924 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t phyclk2gfxclk_b; uint32_t 1925 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t phyclk2gfxclk_c; uint32_t 1930 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t maxvddc; uint32_t 1931 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t minvddc; uint32_t 1932 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfs_meannsigma_acontant0; uint32_t 1933 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfs_meannsigma_acontant1; uint32_t 1934 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfs_meannsigma_acontant2; uint32_t 1938 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_cksoff_a0; uint32_t 1939 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_cksoff_a1; uint32_t 1940 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_cksoff_a2; uint32_t 1941 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_ckson_a0; uint32_t 1942 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_ckson_a1; uint32_t 1943 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gb_vdroop_table_ckson_a2; uint32_t 1944 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_cksoff_m1; uint32_t 1945 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_cksoff_m2; uint32_t 1946 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_cksoff_b; uint32_t 1947 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_ckson_m1; uint32_t 1948 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_ckson_m2; uint32_t 1949 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t avfsgb_fuse_table_ckson_b; uint32_t 1958 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dispclk2gfxclk_a; uint32_t 1959 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dispclk2gfxclk_b; uint32_t 1960 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dispclk2gfxclk_c; uint32_t 1961 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pixclk2gfxclk_a; uint32_t 1962 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pixclk2gfxclk_b; uint32_t 1963 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pixclk2gfxclk_c; uint32_t 1964 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dcefclk2gfxclk_a; uint32_t 1965 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dcefclk2gfxclk_b; uint32_t 1966 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dcefclk2gfxclk_c; uint32_t 1967 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t phyclk2gfxclk_a; uint32_t 1968 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t phyclk2gfxclk_b; uint32_t 1969 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t phyclk2gfxclk_c; uint32_t 1970 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_gb_vdroop_table_a0; uint32_t 1971 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_gb_vdroop_table_a1; uint32_t 1972 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_gb_vdroop_table_a2; uint32_t 1973 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_avfsgb_fuse_table_m1; uint32_t 1974 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_avfsgb_fuse_table_m2; uint32_t 1975 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_avfsgb_fuse_table_b; uint32_t 1978 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_dispclk2gfxclk_a; uint32_t 1979 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_dispclk2gfxclk_b; uint32_t 1980 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_dispclk2gfxclk_c; uint32_t 1981 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_pixclk2gfxclk_a; uint32_t 1982 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_pixclk2gfxclk_b; uint32_t 1983 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_pixclk2gfxclk_c; uint32_t 1984 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_dcefclk2gfxclk_a; uint32_t 1985 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_dcefclk2gfxclk_b; uint32_t 1986 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_dcefclk2gfxclk_c; uint32_t 1987 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_phyclk2gfxclk_a; uint32_t 1988 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_phyclk2gfxclk_b; uint32_t 1989 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t acg_phyclk2gfxclk_c; uint32_t 2008 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent uint32_t 2009 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent uint32_t 2021 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ucode_version; uint32_t 2022 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ucode_rom_startaddr; uint32_t 2023 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ucode_length; uint32_t 2032 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mem_refclk_10khz; uint32_t 2048 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ucode_version; uint32_t 2049 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ucode_rom_startaddr; uint32_t 2050 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ucode_length; uint32_t 2059 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mem_refclk_10khz; uint32_t 2060 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pstate_uclk_10khz[4]; uint32_t 2068 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ucode_reserved; uint32_t 2069 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ucode_rom_startaddr; uint32_t 2070 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ucode_length; uint32_t 2079 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mem_refclk_10khz; uint32_t 2080 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pstate_uclk_10khz[4]; uint32_t 2083 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[4]; uint32_t 2093 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros uint32_t 2094 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not uint32_t 2095 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined uint32_t 2130 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t umc_register_addr:24; uint32_t 2131 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t umc_reg_type_ind:1; uint32_t 2132 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t umc_reg_rsvd:7; uint32_t 2143 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t u32umc_reg_addr; uint32_t 2147 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t memclockrange:24; uint32_t 2148 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mem_blk_id:8; uint32_t 2154 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t u32umc_id_access; uint32_t 2159 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t u32umc_reg_data[1]; uint32_t 2171 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros uint32_t 2172 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not uint32_t 2173 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined uint32_t 2262 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register uint32_t 2273 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gpio_mask_val; // GPIO Mask value uint32_t 2324 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t sclkfreqin10khz:24; uint32_t 2325 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ uint32_t 2330 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mclkfreqin10khz:24; uint32_t 2331 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ uint32_t 2343 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[16]; uint32_t 2368 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t sclkfreqin10khz:24; uint32_t 2369 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ uint32_t 2370 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[10]; uint32_t 2376 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[10]; uint32_t 2394 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t sclk_10khz; // current engine speed in 10KHz unit uint32_t 2395 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved; uint32_t 2405 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mclkfreqin10khz:24; uint32_t 2406 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ uint32_t 2407 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[10]; uint32_t 2413 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[10]; uint32_t 2424 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mclk_10khz; // current engine speed in 10KHz unit uint32_t 2425 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved; uint32_t 2454 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[10]; uint32_t 2474 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock uint32_t 2475 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type uint32_t 2476 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[5]; uint32_t 2482 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock uint32_t 2483 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly uint32_t 2484 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac uint32_t 2485 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac uint32_t 2489 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved1[2]; uint32_t 2511 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t efusevalue; uint32_t 2600 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t smu_clock_freq_hz; uint32_t 2601 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t syspllvcofreq_10khz; uint32_t 2602 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t sysspllrefclk_10khz; uint32_t 2624 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mclk_10khz:24; //Input= target mclk uint32_t 2625 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t command:8; //command enum of atom_dynamic_memory_setting_command uint32_t 2626 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved; uint32_t 2632 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t sclk_10khz:24; //Input= target mclk uint32_t 2633 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t command:8; //command enum of atom_dynamic_memory_setting_command uint32_t 2634 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t mclk_10khz; uint32_t 2635 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved; uint32_t 2664 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[5]; uint32_t 2676 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. uint32_t 2686 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved2; uint32_t 2723 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. uint32_t 2762 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ulReserved[2]; uint32_t 2774 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved1; uint32_t 2807 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t ulReserved[4]; uint32_t 2947 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pclk_10khz; // Pixel Clock in 10Khz uint32_t 2971 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved2[2]; uint32_t 2979 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved2[2]; uint32_t 3004 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t symclk_10khz; // Symbol Clock in 10Khz uint32_t 3009 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved1; uint32_t 3015 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[4]; uint32_t 3125 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[2]; uint32_t 3137 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t signature; uint32_t 3138 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t tableLength; //Length uint32_t 3143 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t oemRevision; uint32_t 3144 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t creatorId; uint32_t 3145 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t creatorRevision; uint32_t 3151 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. uint32_t 3152 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. uint32_t 3153 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t reserved[4]; //0x3C uint32_t 3157 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pcibus; //0x4C uint32_t 3158 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pcidevice; //0x50 uint32_t 3159 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t pcifunction; //0x54 uint32_t 3164 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t revision; //0x60 uint32_t 3165 drivers/gpu/drm/amd/include/atomfirmware.h uint32_t imagelength; //0x64 uint32_t 72 drivers/gpu/drm/amd/include/cgs_common.h uint32_t image_size; uint32_t 76 drivers/gpu/drm/amd/include/cgs_common.h uint32_t ucode_start_address; uint32_t 91 drivers/gpu/drm/amd/include/cgs_common.h typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); uint32_t 100 drivers/gpu/drm/amd/include/cgs_common.h uint32_t value); uint32_t 109 drivers/gpu/drm/amd/include/cgs_common.h typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, uint32_t 119 drivers/gpu/drm/amd/include/cgs_common.h unsigned index, uint32_t value); uint32_t 28 drivers/gpu/drm/amd/include/cik_structs.h uint32_t header; uint32_t 29 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_dispatch_initiator; uint32_t 30 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_dim_x; uint32_t 31 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_dim_y; uint32_t 32 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_dim_z; uint32_t 33 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_start_x; uint32_t 34 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_start_y; uint32_t 35 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_start_z; uint32_t 36 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_num_thread_x; uint32_t 37 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_num_thread_y; uint32_t 38 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_num_thread_z; uint32_t 39 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_pipelinestat_enable; uint32_t 40 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_perfcount_enable; uint32_t 41 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_pgm_lo; uint32_t 42 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_pgm_hi; uint32_t 43 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_tba_lo; uint32_t 44 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_tba_hi; uint32_t 45 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_tma_lo; uint32_t 46 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_tma_hi; uint32_t 47 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_pgm_rsrc1; uint32_t 48 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_pgm_rsrc2; uint32_t 49 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_vmid; uint32_t 50 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_resource_limits; uint32_t 51 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_static_thread_mgmt_se0; uint32_t 52 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_static_thread_mgmt_se1; uint32_t 53 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_tmpring_size; uint32_t 54 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_static_thread_mgmt_se2; uint32_t 55 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_static_thread_mgmt_se3; uint32_t 56 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_restart_x; uint32_t 57 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_restart_y; uint32_t 58 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_restart_z; uint32_t 59 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_thread_trace_enable; uint32_t 60 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_misc_reserved; uint32_t 61 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_0; uint32_t 62 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_1; uint32_t 63 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_2; uint32_t 64 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_3; uint32_t 65 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_4; uint32_t 66 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_5; uint32_t 67 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_6; uint32_t 68 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_7; uint32_t 69 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_8; uint32_t 70 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_9; uint32_t 71 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_10; uint32_t 72 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_11; uint32_t 73 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_12; uint32_t 74 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_13; uint32_t 75 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_14; uint32_t 76 drivers/gpu/drm/amd/include/cik_structs.h uint32_t compute_user_data_15; uint32_t 77 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_compute_csinvoc_count_lo; uint32_t 78 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_compute_csinvoc_count_hi; uint32_t 79 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_base_addr_lo; uint32_t 80 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_base_addr_hi; uint32_t 81 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_active; uint32_t 82 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_vmid; uint32_t 83 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_persistent_state; uint32_t 84 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pipe_priority; uint32_t 85 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_queue_priority; uint32_t 86 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_quantum; uint32_t 87 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_base_lo; uint32_t 88 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_base_hi; uint32_t 89 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_rptr; uint32_t 90 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_rptr_report_addr_lo; uint32_t 91 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_rptr_report_addr_hi; uint32_t 92 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_wptr_poll_addr_lo; uint32_t 93 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_wptr_poll_addr_hi; uint32_t 94 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_doorbell_control; uint32_t 95 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_wptr; uint32_t 96 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_control; uint32_t 97 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_ib_base_addr_lo; uint32_t 98 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_ib_base_addr_hi; uint32_t 99 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_ib_rptr; uint32_t 100 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_ib_control; uint32_t 101 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_iq_timer; uint32_t 102 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_iq_rptr; uint32_t 103 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_dequeue_request; uint32_t 104 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_dma_offload; uint32_t 105 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_sema_cmd; uint32_t 106 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_msg_type; uint32_t 107 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_atomic0_preop_lo; uint32_t 108 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_atomic0_preop_hi; uint32_t 109 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_atomic1_preop_lo; uint32_t 110 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_atomic1_preop_hi; uint32_t 111 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_hq_status0; uint32_t 112 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_hq_control0; uint32_t 113 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_control; uint32_t 114 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_query_time_lo; uint32_t 115 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_query_time_hi; uint32_t 116 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_connect_start_time_lo; uint32_t 117 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_connect_start_time_hi; uint32_t 118 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_connect_end_time_lo; uint32_t 119 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_connect_end_time_hi; uint32_t 120 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_connect_end_wf_count; uint32_t 121 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_connect_end_pq_rptr; uint32_t 122 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_connect_end_pq_wptr; uint32_t 123 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_mqd_connect_end_ib_rptr; uint32_t 124 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_96; uint32_t 125 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_97; uint32_t 126 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_98; uint32_t 127 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_99; uint32_t 128 drivers/gpu/drm/amd/include/cik_structs.h uint32_t iqtimer_pkt_header; uint32_t 129 drivers/gpu/drm/amd/include/cik_structs.h uint32_t iqtimer_pkt_dw0; uint32_t 130 drivers/gpu/drm/amd/include/cik_structs.h uint32_t iqtimer_pkt_dw1; uint32_t 131 drivers/gpu/drm/amd/include/cik_structs.h uint32_t iqtimer_pkt_dw2; uint32_t 132 drivers/gpu/drm/amd/include/cik_structs.h uint32_t iqtimer_pkt_dw3; uint32_t 133 drivers/gpu/drm/amd/include/cik_structs.h uint32_t iqtimer_pkt_dw4; uint32_t 134 drivers/gpu/drm/amd/include/cik_structs.h uint32_t iqtimer_pkt_dw5; uint32_t 135 drivers/gpu/drm/amd/include/cik_structs.h uint32_t iqtimer_pkt_dw6; uint32_t 136 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_108; uint32_t 137 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_109; uint32_t 138 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_110; uint32_t 139 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_111; uint32_t 140 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id0; uint32_t 141 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id1; uint32_t 142 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id2; uint32_t 143 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id3; uint32_t 144 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id4; uint32_t 145 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id5; uint32_t 146 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id6; uint32_t 147 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id7; uint32_t 148 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id8; uint32_t 149 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id9; uint32_t 150 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id10; uint32_t 151 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id11; uint32_t 152 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id12; uint32_t 153 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id13; uint32_t 154 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id14; uint32_t 155 drivers/gpu/drm/amd/include/cik_structs.h uint32_t queue_doorbell_id15; uint32_t 159 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_cntl; uint32_t 160 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_base; uint32_t 161 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_base_hi; uint32_t 162 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_rptr; uint32_t 163 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_wptr; uint32_t 164 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_wptr_poll_cntl; uint32_t 165 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_wptr_poll_addr_hi; uint32_t 166 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_wptr_poll_addr_lo; uint32_t 167 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_rptr_addr_hi; uint32_t 168 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_rb_rptr_addr_lo; uint32_t 169 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_ib_cntl; uint32_t 170 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_ib_rptr; uint32_t 171 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_ib_offset; uint32_t 172 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_ib_base_lo; uint32_t 173 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_ib_base_hi; uint32_t 174 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_ib_size; uint32_t 175 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_skip_cntl; uint32_t 176 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_context_status; uint32_t 177 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_doorbell; uint32_t 178 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_virtual_addr; uint32_t 179 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_ape1_cntl; uint32_t 180 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_rlc_doorbell_log; uint32_t 181 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_22; uint32_t 182 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_23; uint32_t 183 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_24; uint32_t 184 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_25; uint32_t 185 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_26; uint32_t 186 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_27; uint32_t 187 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_28; uint32_t 188 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_29; uint32_t 189 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_30; uint32_t 190 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_31; uint32_t 191 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_32; uint32_t 192 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_33; uint32_t 193 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_34; uint32_t 194 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_35; uint32_t 195 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_36; uint32_t 196 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_37; uint32_t 197 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_38; uint32_t 198 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_39; uint32_t 199 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_40; uint32_t 200 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_41; uint32_t 201 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_42; uint32_t 202 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_43; uint32_t 203 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_44; uint32_t 204 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_45; uint32_t 205 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_46; uint32_t 206 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_47; uint32_t 207 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_48; uint32_t 208 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_49; uint32_t 209 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_50; uint32_t 210 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_51; uint32_t 211 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_52; uint32_t 212 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_53; uint32_t 213 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_54; uint32_t 214 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_55; uint32_t 215 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_56; uint32_t 216 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_57; uint32_t 217 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_58; uint32_t 218 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_59; uint32_t 219 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_60; uint32_t 220 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_61; uint32_t 221 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_62; uint32_t 222 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_63; uint32_t 223 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_64; uint32_t 224 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_65; uint32_t 225 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_66; uint32_t 226 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_67; uint32_t 227 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_68; uint32_t 228 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_69; uint32_t 229 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_70; uint32_t 230 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_71; uint32_t 231 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_72; uint32_t 232 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_73; uint32_t 233 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_74; uint32_t 234 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_75; uint32_t 235 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_76; uint32_t 236 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_77; uint32_t 237 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_78; uint32_t 238 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_79; uint32_t 239 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_80; uint32_t 240 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_81; uint32_t 241 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_82; uint32_t 242 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_83; uint32_t 243 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_84; uint32_t 244 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_85; uint32_t 245 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_86; uint32_t 246 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_87; uint32_t 247 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_88; uint32_t 248 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_89; uint32_t 249 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_90; uint32_t 250 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_91; uint32_t 251 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_92; uint32_t 252 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_93; uint32_t 253 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_94; uint32_t 254 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_95; uint32_t 255 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_96; uint32_t 256 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_97; uint32_t 257 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_98; uint32_t 258 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_99; uint32_t 259 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_100; uint32_t 260 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_101; uint32_t 261 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_102; uint32_t 262 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_103; uint32_t 263 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_104; uint32_t 264 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_105; uint32_t 265 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_106; uint32_t 266 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_107; uint32_t 267 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_108; uint32_t 268 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_109; uint32_t 269 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_110; uint32_t 270 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_111; uint32_t 271 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_112; uint32_t 272 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_113; uint32_t 273 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_114; uint32_t 274 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_115; uint32_t 275 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_116; uint32_t 276 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_117; uint32_t 277 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_118; uint32_t 278 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_119; uint32_t 279 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_120; uint32_t 280 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_121; uint32_t 281 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_122; uint32_t 282 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_123; uint32_t 283 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_124; uint32_t 284 drivers/gpu/drm/amd/include/cik_structs.h uint32_t reserved_125; uint32_t 286 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_engine_id; uint32_t 287 drivers/gpu/drm/amd/include/cik_structs.h uint32_t sdma_queue_id; uint32_t 55 drivers/gpu/drm/amd/include/discovery.h uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */ uint32_t 72 drivers/gpu/drm/amd/include/discovery.h uint32_t signature; /* Table Signature */ uint32_t 75 drivers/gpu/drm/amd/include/discovery.h uint32_t id; /* Table ID */ uint32_t 96 drivers/gpu/drm/amd/include/discovery.h uint32_t base_address[1]; /* variable number of Addresses */ uint32_t 116 drivers/gpu/drm/amd/include/discovery.h uint32_t table_id; /* table ID */ uint32_t 119 drivers/gpu/drm/amd/include/discovery.h uint32_t size; /* size of the entire header+data in bytes */ uint32_t 125 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_se; uint32_t 126 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_wgp0_per_sa; uint32_t 127 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_wgp1_per_sa; uint32_t 128 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_rb_per_se; uint32_t 129 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_gl2c; uint32_t 130 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_gprs; uint32_t 131 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_max_gs_thds; uint32_t 132 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_gs_table_depth; uint32_t 133 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_gsprim_buff_depth; uint32_t 134 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_parameter_cache_depth; uint32_t 135 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_double_offchip_lds_buffer; uint32_t 136 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_wave_size; uint32_t 137 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_max_waves_per_simd; uint32_t 138 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_max_scratch_slots_per_cu; uint32_t 139 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_lds_size; uint32_t 140 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_sc_per_se; uint32_t 141 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_sa_per_se; uint32_t 142 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_packer_per_sc; uint32_t 143 drivers/gpu/drm/amd/include/discovery.h uint32_t gc_num_gl2a; uint32_t 147 drivers/gpu/drm/amd/include/discovery.h uint32_t signature; /* Table Signature */ uint32_t 148 drivers/gpu/drm/amd/include/discovery.h uint32_t version; /* Table Version */ uint32_t 50 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t controller_index; uint32_t 51 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t controller_id; uint32_t 52 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t signal_type; uint32_t 53 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t display_state; uint32_t 63 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t config_flags; uint32_t 64 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t display_type; uint32_t 65 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t view_resolution_cx; uint32_t 66 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t view_resolution_cy; uint32_t 68 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t vertical_refresh; /* for active display */ uint32_t 77 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t cpu_pstate_separation_time; uint32_t 79 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t num_display; /* total number of display*/ uint32_t 80 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t num_path_including_non_display; uint32_t 81 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t crossfire_display_index; uint32_t 82 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_mem_set_clock; uint32_t 83 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_core_set_clock; uint32_t 85 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_bus_bandwidth; uint32_t 87 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_core_set_clock_in_sr; uint32_t 91 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t vrefresh; /* for active display*/ uint32_t 93 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_vblank_time; /* for active display*/ uint32_t 97 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t crtc_index; uint32_t 99 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t line_time_in_us; uint32_t 102 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t display_clk; uint32_t 108 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t dce_tolerable_mclk_in_active_latency; uint32_t 109 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_dcef_set_clk; uint32_t 110 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_dcef_deep_sleep_set_clk; uint32_t 114 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t engine_max_clock; uint32_t 115 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t memory_max_clock; uint32_t 116 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t level; uint32_t 137 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_engine_clock; uint32_t 138 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t max_engine_clock; uint32_t 139 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_memory_clock; uint32_t 140 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t max_memory_clock; uint32_t 141 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_bus_bandwidth; uint32_t 142 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t max_bus_bandwidth; uint32_t 143 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t max_engine_clock_in_sr; uint32_t 144 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t min_engine_clock_in_sr; uint32_t 164 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t count; uint32_t 165 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t clock[MAX_NUM_CLOCKS]; uint32_t 166 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t latency[MAX_NUM_CLOCKS]; uint32_t 170 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t clocks_in_khz; uint32_t 171 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t latency_in_us; uint32_t 175 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t num_levels; uint32_t 180 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t clocks_in_khz; uint32_t 181 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t voltage_in_mv; uint32_t 185 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t num_levels; uint32_t 191 drivers/gpu/drm/amd/include/dm_pp_interface.h uint32_t clock_freq_in_khz; uint32_t 51 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t vmid; uint32_t 52 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t mc_id; uint32_t 53 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t status; uint32_t 61 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_shader_engines; uint32_t 62 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_shader_arrays_per_engine; uint32_t 63 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_cu_per_sh; uint32_t 64 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t cu_active_number; uint32_t 65 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t cu_ao_mask; uint32_t 66 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t simd_per_cu; uint32_t 67 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t max_waves_per_simd; uint32_t 68 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t wave_front_size; uint32_t 69 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t max_scratch_slots_per_cu; uint32_t 70 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t lds_size; uint32_t 71 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t cu_bitmap[4][4]; uint32_t 78 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t vram_width; uint32_t 79 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t mem_clk_max; uint32_t 120 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_pipe_per_mec; uint32_t 123 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_queue_per_pipe; uint32_t 132 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t *sdma_doorbell_idx; uint32_t 137 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t non_cp_doorbells_start; uint32_t 138 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t non_cp_doorbells_end; uint32_t 157 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t *tile_config_ptr; uint32_t 158 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t *macro_tile_config_ptr; uint32_t 159 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_tile_configs; uint32_t 160 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_macro_tile_configs; uint32_t 162 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t gb_addr_config; uint32_t 163 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_banks; uint32_t 164 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_ranks; uint32_t 245 drivers/gpu/drm/amd/include/kgd_kfd_interface.h void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid, uint32_t 246 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, uint32_t 247 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases); uint32_t 252 drivers/gpu/drm/amd/include/kgd_kfd_interface.h int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id); uint32_t 254 drivers/gpu/drm/amd/include/kgd_kfd_interface.h int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t 255 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t queue_id, uint32_t __user *wptr, uint32_t 256 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t wptr_shift, uint32_t wptr_mask, uint32_t 260 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t __user *wptr, struct mm_struct *mm); uint32_t 263 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t pipe_id, uint32_t queue_id, uint32_t 264 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t (**dump)[2], uint32_t *n_regs); uint32_t 267 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t engine_id, uint32_t queue_id, uint32_t 268 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t (**dump)[2], uint32_t *n_regs); uint32_t 271 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t pipe_id, uint32_t queue_id); uint32_t 273 drivers/gpu/drm/amd/include/kgd_kfd_interface.h int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type, uint32_t 274 drivers/gpu/drm/amd/include/kgd_kfd_interface.h unsigned int timeout, uint32_t pipe_id, uint32_t 275 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t queue_id); uint32_t 285 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t cntl_val, uint32_t 286 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t addr_hi, uint32_t 287 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t addr_lo); uint32_t 289 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t gfx_index_val, uint32_t 290 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t sq_cmd); uint32_t 291 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd, uint32_t 302 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint64_t va, uint32_t vmid); uint32_t 306 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t vmid, uint64_t page_table_base); uint32_t 309 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd); uint32_t 164 drivers/gpu/drm/amd/include/kgd_pp_interface.h uint32_t nums; uint32_t 165 drivers/gpu/drm/amd/include/kgd_pp_interface.h uint32_t states[16]; uint32_t 246 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); uint32_t 250 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_sclk_od)(void *handle, uint32_t value); uint32_t 252 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_mclk_od)(void *handle, uint32_t value); uint32_t 256 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); uint32_t 257 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); uint32_t 270 drivers/gpu/drm/amd/include/kgd_pp_interface.h uint32_t block_type, bool gate); uint32_t 271 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); uint32_t 272 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_power_limit)(void *handle, uint32_t n); uint32_t 273 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit); uint32_t 275 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); uint32_t 276 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size); uint32_t 305 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_active_display_count)(void *handle, uint32_t count); uint32_t 306 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); uint32_t 307 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); uint32_t 308 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); uint32_t 29 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_0; // offset: 0 (0x0) uint32_t 30 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_1; // offset: 1 (0x1) uint32_t 31 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_2; // offset: 2 (0x2) uint32_t 32 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_3; // offset: 3 (0x3) uint32_t 33 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_4; // offset: 4 (0x4) uint32_t 34 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_5; // offset: 5 (0x5) uint32_t 35 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_6; // offset: 6 (0x6) uint32_t 36 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_7; // offset: 7 (0x7) uint32_t 37 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_8; // offset: 8 (0x8) uint32_t 38 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_9; // offset: 9 (0x9) uint32_t 39 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_10; // offset: 10 (0xA) uint32_t 40 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_11; // offset: 11 (0xB) uint32_t 41 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_12; // offset: 12 (0xC) uint32_t 42 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_13; // offset: 13 (0xD) uint32_t 43 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_14; // offset: 14 (0xE) uint32_t 44 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_15; // offset: 15 (0xF) uint32_t 45 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_16; // offset: 16 (0x10) uint32_t 46 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_17; // offset: 17 (0x11) uint32_t 47 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_18; // offset: 18 (0x12) uint32_t 48 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_19; // offset: 19 (0x13) uint32_t 49 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_20; // offset: 20 (0x14) uint32_t 50 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_21; // offset: 21 (0x15) uint32_t 51 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_22; // offset: 22 (0x16) uint32_t 52 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_23; // offset: 23 (0x17) uint32_t 53 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_24; // offset: 24 (0x18) uint32_t 54 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_25; // offset: 25 (0x19) uint32_t 55 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_26; // offset: 26 (0x1A) uint32_t 56 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_27; // offset: 27 (0x1B) uint32_t 57 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_28; // offset: 28 (0x1C) uint32_t 58 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_29; // offset: 29 (0x1D) uint32_t 59 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_30; // offset: 30 (0x1E) uint32_t 60 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_31; // offset: 31 (0x1F) uint32_t 61 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_32; // offset: 32 (0x20) uint32_t 62 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_33; // offset: 33 (0x21) uint32_t 63 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_34; // offset: 34 (0x22) uint32_t 64 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_35; // offset: 35 (0x23) uint32_t 65 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_36; // offset: 36 (0x24) uint32_t 66 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_37; // offset: 37 (0x25) uint32_t 67 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_38; // offset: 38 (0x26) uint32_t 68 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_39; // offset: 39 (0x27) uint32_t 69 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_40; // offset: 40 (0x28) uint32_t 70 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_41; // offset: 41 (0x29) uint32_t 71 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_42; // offset: 42 (0x2A) uint32_t 72 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_43; // offset: 43 (0x2B) uint32_t 73 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_44; // offset: 44 (0x2C) uint32_t 74 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_45; // offset: 45 (0x2D) uint32_t 75 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_46; // offset: 46 (0x2E) uint32_t 76 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_47; // offset: 47 (0x2F) uint32_t 77 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_48; // offset: 48 (0x30) uint32_t 78 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_49; // offset: 49 (0x31) uint32_t 79 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_50; // offset: 50 (0x32) uint32_t 80 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_51; // offset: 51 (0x33) uint32_t 81 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_52; // offset: 52 (0x34) uint32_t 82 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_53; // offset: 53 (0x35) uint32_t 83 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_54; // offset: 54 (0x36) uint32_t 84 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_55; // offset: 55 (0x37) uint32_t 85 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_56; // offset: 56 (0x38) uint32_t 86 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_57; // offset: 57 (0x39) uint32_t 87 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_58; // offset: 58 (0x3A) uint32_t 88 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_59; // offset: 59 (0x3B) uint32_t 89 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_60; // offset: 60 (0x3C) uint32_t 90 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_61; // offset: 61 (0x3D) uint32_t 91 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_62; // offset: 62 (0x3E) uint32_t 92 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_63; // offset: 63 (0x3F) uint32_t 93 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_64; // offset: 64 (0x40) uint32_t 94 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_65; // offset: 65 (0x41) uint32_t 95 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_66; // offset: 66 (0x42) uint32_t 96 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_67; // offset: 67 (0x43) uint32_t 97 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_68; // offset: 68 (0x44) uint32_t 98 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_69; // offset: 69 (0x45) uint32_t 99 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_70; // offset: 70 (0x46) uint32_t 100 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_71; // offset: 71 (0x47) uint32_t 101 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_72; // offset: 72 (0x48) uint32_t 102 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_73; // offset: 73 (0x49) uint32_t 103 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_74; // offset: 74 (0x4A) uint32_t 104 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_75; // offset: 75 (0x4B) uint32_t 105 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_76; // offset: 76 (0x4C) uint32_t 106 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_77; // offset: 77 (0x4D) uint32_t 107 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_78; // offset: 78 (0x4E) uint32_t 108 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_79; // offset: 79 (0x4F) uint32_t 109 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_80; // offset: 80 (0x50) uint32_t 110 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_81; // offset: 81 (0x51) uint32_t 111 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_82; // offset: 82 (0x52) uint32_t 112 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_83; // offset: 83 (0x53) uint32_t 113 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_84; // offset: 84 (0x54) uint32_t 114 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_85; // offset: 85 (0x55) uint32_t 115 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_86; // offset: 86 (0x56) uint32_t 116 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_87; // offset: 87 (0x57) uint32_t 117 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_88; // offset: 88 (0x58) uint32_t 118 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_89; // offset: 89 (0x59) uint32_t 119 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_90; // offset: 90 (0x5A) uint32_t 120 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_91; // offset: 91 (0x5B) uint32_t 121 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_92; // offset: 92 (0x5C) uint32_t 122 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_93; // offset: 93 (0x5D) uint32_t 123 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_94; // offset: 94 (0x5E) uint32_t 124 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_95; // offset: 95 (0x5F) uint32_t 125 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_96; // offset: 96 (0x60) uint32_t 126 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_97; // offset: 97 (0x61) uint32_t 127 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_98; // offset: 98 (0x62) uint32_t 128 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_99; // offset: 99 (0x63) uint32_t 129 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_100; // offset: 100 (0x64) uint32_t 130 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_101; // offset: 101 (0x65) uint32_t 131 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_102; // offset: 102 (0x66) uint32_t 132 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_103; // offset: 103 (0x67) uint32_t 133 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_104; // offset: 104 (0x68) uint32_t 134 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_105; // offset: 105 (0x69) uint32_t 135 drivers/gpu/drm/amd/include/v10_structs.h uint32_t disable_queue; // offset: 106 (0x6A) uint32_t 136 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_107; // offset: 107 (0x6B) uint32_t 137 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_108; // offset: 108 (0x6C) uint32_t 138 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_109; // offset: 109 (0x6D) uint32_t 139 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_110; // offset: 110 (0x6E) uint32_t 140 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_111; // offset: 111 (0x6F) uint32_t 141 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_112; // offset: 112 (0x70) uint32_t 142 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_113; // offset: 113 (0x71) uint32_t 143 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_114; // offset: 114 (0x72) uint32_t 144 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_115; // offset: 115 (0x73) uint32_t 145 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_116; // offset: 116 (0x74) uint32_t 146 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_117; // offset: 117 (0x75) uint32_t 147 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_118; // offset: 118 (0x76) uint32_t 148 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_119; // offset: 119 (0x77) uint32_t 149 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_120; // offset: 120 (0x78) uint32_t 150 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_121; // offset: 121 (0x79) uint32_t 151 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_122; // offset: 122 (0x7A) uint32_t 152 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_123; // offset: 123 (0x7B) uint32_t 153 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_124; // offset: 124 (0x7C) uint32_t 154 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_125; // offset: 125 (0x7D) uint32_t 155 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_126; // offset: 126 (0x7E) uint32_t 156 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_127; // offset: 127 (0x7F) uint32_t 157 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_base_addr; // offset: 128 (0x80) uint32_t 158 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) uint32_t 159 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_active; // offset: 130 (0x82) uint32_t 160 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83) uint32_t 161 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_131; // offset: 132 (0x84) uint32_t 162 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_132; // offset: 133 (0x85) uint32_t 163 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86) uint32_t 164 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87) uint32_t 165 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_base; // offset: 136 (0x88) uint32_t 166 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89) uint32_t 167 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A) uint32_t 168 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B) uint32_t 169 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C) uint32_t 170 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D) uint32_t 171 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E) uint32_t 172 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F) uint32_t 173 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90) uint32_t 174 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91) uint32_t 175 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_146; // offset: 146 (0x92) uint32_t 176 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_147; // offset: 147 (0x93) uint32_t 177 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94) uint32_t 178 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95) uint32_t 179 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96) uint32_t 180 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_151; // offset: 151 (0x97) uint32_t 181 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_152; // offset: 152 (0x98) uint32_t 182 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_153; // offset: 153 (0x99) uint32_t 183 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_154; // offset: 154 (0x9A) uint32_t 184 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_155; // offset: 155 (0x9B) uint32_t 185 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C) uint32_t 186 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D) uint32_t 187 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_158; // offset: 158 (0x9E) uint32_t 188 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_159; // offset: 159 (0x9F) uint32_t 189 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0) uint32_t 190 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1) uint32_t 191 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2) uint32_t 192 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_163; // offset: 163 (0xA3) uint32_t 193 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_164; // offset: 164 (0xA4) uint32_t 194 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_165; // offset: 165 (0xA5) uint32_t 195 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_166; // offset: 166 (0xA6) uint32_t 196 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_167; // offset: 167 (0xA7) uint32_t 197 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_168; // offset: 168 (0xA8) uint32_t 198 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_169; // offset: 169 (0xA9) uint32_t 199 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_needed_count0_lo; // offset: 170 (0xAA) uint32_t 200 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_needed_count0_hi; // offset: 171 (0xAB) uint32_t 201 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_needed_count1_lo; // offset: 172 (0xAC) uint32_t 202 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_needed_count1_hi; // offset: 173 (0xAD) uint32_t 203 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_needed_count2_lo; // offset: 174 (0xAE) uint32_t 204 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_needed_count2_hi; // offset: 175 (0xAF) uint32_t 205 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_needed_count3_lo; // offset: 176 (0xB0) uint32_t 206 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_needed_count3_hi; // offset: 177 (0xB1) uint32_t 207 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_written_count0_lo; // offset: 178 (0xB2) uint32_t 208 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_written_count0_hi; // offset: 179 (0xB3) uint32_t 209 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_written_count1_lo; // offset: 180 (0xB4) uint32_t 210 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_written_count1_hi; // offset: 181 (0xB5) uint32_t 211 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_written_count2_lo; // offset: 182 (0xB6) uint32_t 212 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_written_count2_hi; // offset: 183 (0xB7) uint32_t 213 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_written_count3_lo; // offset: 184 (0xB8) uint32_t 214 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_num_prim_written_count3_hi; // offset: 185 (0xB9) uint32_t 215 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_186; // offset: 186 (0xBA) uint32_t 216 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_187; // offset: 187 (0xBB) uint32_t 217 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_188; // offset: 188 (0xBC) uint32_t 218 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_189; // offset: 189 (0xBD) uint32_t 219 drivers/gpu/drm/amd/include/v10_structs.h uint32_t mp1_smn_fps_cnt; // offset: 190 (0xBE) uint32_t 220 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_buf0_base; // offset: 191 (0xBF) uint32_t 221 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_buf0_size; // offset: 192 (0xC0) uint32_t 222 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_buf1_base; // offset: 193 (0xC1) uint32_t 223 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_buf1_size; // offset: 194 (0xC2) uint32_t 224 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_wptr; // offset: 195 (0xC3) uint32_t 225 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_mask; // offset: 196 (0xC4) uint32_t 226 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_token_mask; // offset: 197 (0xC5) uint32_t 227 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_ctrl; // offset: 198 (0xC6) uint32_t 228 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_status; // offset: 199 (0xC7) uint32_t 229 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_dropped_cntr; // offset: 200 (0xC8) uint32_t 230 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_finish_done_debug; // offset: 201 (0xC9) uint32_t 231 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_gfx_draw_cntr; // offset: 202 (0xCA) uint32_t 232 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_gfx_marker_cntr; // offset: 203 (0xCB) uint32_t 233 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_hp3d_draw_cntr; // offset: 204 (0xCC) uint32_t 234 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sq_thread_trace_hp3d_marker_cntr; // offset: 205 (0xCD) uint32_t 235 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_206; // offset: 206 (0xCE) uint32_t 236 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_207; // offset: 207 (0xCF) uint32_t 237 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_sc_psinvoc_count0_lo; // offset: 208 (0xD0) uint32_t 238 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_sc_psinvoc_count0_hi; // offset: 209 (0xD1) uint32_t 239 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_pa_cprim_count_lo; // offset: 210 (0xD2) uint32_t 240 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_pa_cprim_count_hi; // offset: 211 (0xD3) uint32_t 241 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_pa_cinvoc_count_lo; // offset: 212 (0xD4) uint32_t 242 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_pa_cinvoc_count_hi; // offset: 213 (0xD5) uint32_t 243 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_vsinvoc_count_lo; // offset: 214 (0xD6) uint32_t 244 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_vsinvoc_count_hi; // offset: 215 (0xD7) uint32_t 245 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_gsinvoc_count_lo; // offset: 216 (0xD8) uint32_t 246 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_gsinvoc_count_hi; // offset: 217 (0xD9) uint32_t 247 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_gsprim_count_lo; // offset: 218 (0xDA) uint32_t 248 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_gsprim_count_hi; // offset: 219 (0xDB) uint32_t 249 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_iaprim_count_lo; // offset: 220 (0xDC) uint32_t 250 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_iaprim_count_hi; // offset: 221 (0xDD) uint32_t 251 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_iavert_count_lo; // offset: 222 (0xDE) uint32_t 252 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_iavert_count_hi; // offset: 223 (0xDF) uint32_t 253 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_hsinvoc_count_lo; // offset: 224 (0xE0) uint32_t 254 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_hsinvoc_count_hi; // offset: 225 (0xE1) uint32_t 255 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_dsinvoc_count_lo; // offset: 226 (0xE2) uint32_t 256 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_dsinvoc_count_hi; // offset: 227 (0xE3) uint32_t 257 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_csinvoc_count_lo; // offset: 228 (0xE4) uint32_t 258 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_vgt_csinvoc_count_hi; // offset: 229 (0xE5) uint32_t 259 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_230; // offset: 230 (0xE6) uint32_t 260 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_231; // offset: 231 (0xE7) uint32_t 261 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_232; // offset: 232 (0xE8) uint32_t 262 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_233; // offset: 233 (0xE9) uint32_t 263 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_234; // offset: 234 (0xEA) uint32_t 264 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_235; // offset: 235 (0xEB) uint32_t 265 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_236; // offset: 236 (0xEC) uint32_t 266 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_237; // offset: 237 (0xED) uint32_t 267 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_238; // offset: 238 (0xEE) uint32_t 268 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_239; // offset: 239 (0xEF) uint32_t 269 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_240; // offset: 240 (0xF0) uint32_t 270 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_241; // offset: 241 (0xF1) uint32_t 271 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_242; // offset: 242 (0xF2) uint32_t 272 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_243; // offset: 243 (0xF3) uint32_t 273 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_244; // offset: 244 (0xF4) uint32_t 274 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_245; // offset: 245 (0xF5) uint32_t 275 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_246; // offset: 246 (0xF6) uint32_t 276 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_247; // offset: 247 (0xF7) uint32_t 277 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_248; // offset: 248 (0xF8) uint32_t 278 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_249; // offset: 249 (0xF9) uint32_t 279 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_250; // offset: 250 (0xFA) uint32_t 280 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_251; // offset: 251 (0xFB) uint32_t 281 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_252; // offset: 252 (0xFC) uint32_t 282 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_253; // offset: 253 (0xFD) uint32_t 283 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_254; // offset: 254 (0xFE) uint32_t 284 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_255; // offset: 255 (0xFF) uint32_t 285 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_256; // offset: 256 (0x100) uint32_t 286 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_257; // offset: 257 (0x101) uint32_t 287 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_258; // offset: 258 (0x102) uint32_t 288 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_259; // offset: 259 (0x103) uint32_t 289 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_260; // offset: 260 (0x104) uint32_t 290 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_261; // offset: 261 (0x105) uint32_t 291 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_262; // offset: 262 (0x106) uint32_t 292 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_263; // offset: 263 (0x107) uint32_t 293 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_264; // offset: 264 (0x108) uint32_t 294 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_265; // offset: 265 (0x109) uint32_t 295 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_266; // offset: 266 (0x10A) uint32_t 296 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_267; // offset: 267 (0x10B) uint32_t 297 drivers/gpu/drm/amd/include/v10_structs.h uint32_t vgt_strmout_buffer_filled_size_0; // offset: 268 (0x10C) uint32_t 298 drivers/gpu/drm/amd/include/v10_structs.h uint32_t vgt_strmout_buffer_filled_size_1; // offset: 269 (0x10D) uint32_t 299 drivers/gpu/drm/amd/include/v10_structs.h uint32_t vgt_strmout_buffer_filled_size_2; // offset: 270 (0x10E) uint32_t 300 drivers/gpu/drm/amd/include/v10_structs.h uint32_t vgt_strmout_buffer_filled_size_3; // offset: 271 (0x10F) uint32_t 301 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_272; // offset: 272 (0x110) uint32_t 302 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_273; // offset: 273 (0x111) uint32_t 303 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_274; // offset: 274 (0x112) uint32_t 304 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_275; // offset: 275 (0x113) uint32_t 305 drivers/gpu/drm/amd/include/v10_structs.h uint32_t vgt_dma_max_size; // offset: 276 (0x114) uint32_t 306 drivers/gpu/drm/amd/include/v10_structs.h uint32_t vgt_dma_num_instances; // offset: 277 (0x115) uint32_t 307 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_278; // offset: 278 (0x116) uint32_t 308 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_279; // offset: 279 (0x117) uint32_t 309 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_280; // offset: 280 (0x118) uint32_t 310 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_281; // offset: 281 (0x119) uint32_t 311 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_282; // offset: 282 (0x11A) uint32_t 312 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_283; // offset: 283 (0x11B) uint32_t 313 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_284; // offset: 284 (0x11C) uint32_t 314 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_285; // offset: 285 (0x11D) uint32_t 315 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_286; // offset: 286 (0x11E) uint32_t 316 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_287; // offset: 287 (0x11F) uint32_t 317 drivers/gpu/drm/amd/include/v10_structs.h uint32_t it_set_base_ib_addr_lo; // offset: 288 (0x120) uint32_t 318 drivers/gpu/drm/amd/include/v10_structs.h uint32_t it_set_base_ib_addr_hi; // offset: 289 (0x121) uint32_t 319 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_290; // offset: 290 (0x122) uint32_t 320 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_291; // offset: 291 (0x123) uint32_t 321 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_292; // offset: 292 (0x124) uint32_t 322 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_293; // offset: 293 (0x125) uint32_t 323 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_294; // offset: 294 (0x126) uint32_t 324 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_295; // offset: 295 (0x127) uint32_t 325 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_296; // offset: 296 (0x128) uint32_t 326 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_297; // offset: 297 (0x129) uint32_t 327 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_298; // offset: 298 (0x12A) uint32_t 328 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_299; // offset: 299 (0x12B) uint32_t 329 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_300; // offset: 300 (0x12C) uint32_t 330 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_301; // offset: 301 (0x12D) uint32_t 331 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_302; // offset: 302 (0x12E) uint32_t 332 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_303; // offset: 303 (0x12F) uint32_t 333 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_304; // offset: 304 (0x130) uint32_t 334 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_305; // offset: 305 (0x131) uint32_t 335 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_306; // offset: 306 (0x132) uint32_t 336 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_307; // offset: 307 (0x133) uint32_t 337 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_308; // offset: 308 (0x134) uint32_t 338 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_309; // offset: 309 (0x135) uint32_t 339 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_310; // offset: 310 (0x136) uint32_t 340 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_311; // offset: 311 (0x137) uint32_t 341 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_312; // offset: 312 (0x138) uint32_t 342 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_313; // offset: 313 (0x139) uint32_t 343 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_314; // offset: 314 (0x13A) uint32_t 344 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_315; // offset: 315 (0x13B) uint32_t 345 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_316; // offset: 316 (0x13C) uint32_t 346 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_317; // offset: 317 (0x13D) uint32_t 347 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_318; // offset: 318 (0x13E) uint32_t 348 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_319; // offset: 319 (0x13F) uint32_t 349 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_320; // offset: 320 (0x140) uint32_t 350 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_321; // offset: 321 (0x141) uint32_t 351 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_322; // offset: 322 (0x142) uint32_t 352 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_323; // offset: 323 (0x143) uint32_t 353 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_324; // offset: 324 (0x144) uint32_t 354 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_325; // offset: 325 (0x145) uint32_t 355 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_326; // offset: 326 (0x146) uint32_t 356 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_327; // offset: 327 (0x147) uint32_t 357 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_328; // offset: 328 (0x148) uint32_t 358 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_329; // offset: 329 (0x149) uint32_t 359 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_330; // offset: 330 (0x14A) uint32_t 360 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_331; // offset: 331 (0x14B) uint32_t 361 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_332; // offset: 332 (0x14C) uint32_t 362 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_333; // offset: 333 (0x14D) uint32_t 363 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_334; // offset: 334 (0x14E) uint32_t 364 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_335; // offset: 335 (0x14F) uint32_t 365 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_336; // offset: 336 (0x150) uint32_t 366 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_337; // offset: 337 (0x151) uint32_t 367 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_338; // offset: 338 (0x152) uint32_t 368 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_339; // offset: 339 (0x153) uint32_t 369 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_340; // offset: 340 (0x154) uint32_t 370 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_341; // offset: 341 (0x155) uint32_t 371 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_342; // offset: 342 (0x156) uint32_t 372 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_343; // offset: 343 (0x157) uint32_t 373 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_344; // offset: 344 (0x158) uint32_t 374 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_345; // offset: 345 (0x159) uint32_t 375 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_346; // offset: 346 (0x15A) uint32_t 376 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_347; // offset: 347 (0x15B) uint32_t 377 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_348; // offset: 348 (0x15C) uint32_t 378 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_349; // offset: 349 (0x15D) uint32_t 379 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_350; // offset: 350 (0x15E) uint32_t 380 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_351; // offset: 351 (0x15F) uint32_t 381 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_352; // offset: 352 (0x160) uint32_t 382 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_353; // offset: 353 (0x161) uint32_t 383 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_354; // offset: 354 (0x162) uint32_t 384 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_355; // offset: 355 (0x163) uint32_t 385 drivers/gpu/drm/amd/include/v10_structs.h uint32_t spi_shader_pgm_rsrc3_ps; // offset: 356 (0x164) uint32_t 386 drivers/gpu/drm/amd/include/v10_structs.h uint32_t spi_shader_pgm_rsrc3_vs; // offset: 357 (0x165) uint32_t 387 drivers/gpu/drm/amd/include/v10_structs.h uint32_t spi_shader_pgm_rsrc3_gs; // offset: 358 (0x166) uint32_t 388 drivers/gpu/drm/amd/include/v10_structs.h uint32_t spi_shader_pgm_rsrc3_hs; // offset: 359 (0x167) uint32_t 389 drivers/gpu/drm/amd/include/v10_structs.h uint32_t spi_shader_pgm_rsrc4_ps; // offset: 360 (0x168) uint32_t 390 drivers/gpu/drm/amd/include/v10_structs.h uint32_t spi_shader_pgm_rsrc4_vs; // offset: 361 (0x169) uint32_t 391 drivers/gpu/drm/amd/include/v10_structs.h uint32_t spi_shader_pgm_rsrc4_gs; // offset: 362 (0x16A) uint32_t 392 drivers/gpu/drm/amd/include/v10_structs.h uint32_t spi_shader_pgm_rsrc4_hs; // offset: 363 (0x16B) uint32_t 393 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_00; // offset: 364 (0x16C) uint32_t 394 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_00; // offset: 365 (0x16D) uint32_t 395 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_00; // offset: 366 (0x16E) uint32_t 396 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_00; // offset: 367 (0x16F) uint32_t 397 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_00; // offset: 368 (0x170) uint32_t 398 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_00; // offset: 369 (0x171) uint32_t 399 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_00; // offset: 370 (0x172) uint32_t 400 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_00; // offset: 371 (0x173) uint32_t 401 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_01; // offset: 372 (0x174) uint32_t 402 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_01; // offset: 373 (0x175) uint32_t 403 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_01; // offset: 374 (0x176) uint32_t 404 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_01; // offset: 375 (0x177) uint32_t 405 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_01; // offset: 376 (0x178) uint32_t 406 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_01; // offset: 377 (0x179) uint32_t 407 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_01; // offset: 378 (0x17A) uint32_t 408 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_01; // offset: 379 (0x17B) uint32_t 409 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_02; // offset: 380 (0x17C) uint32_t 410 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_02; // offset: 381 (0x17D) uint32_t 411 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_02; // offset: 382 (0x17E) uint32_t 412 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_02; // offset: 383 (0x17F) uint32_t 413 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_02; // offset: 384 (0x180) uint32_t 414 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_02; // offset: 385 (0x181) uint32_t 415 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_02; // offset: 386 (0x182) uint32_t 416 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_02; // offset: 387 (0x183) uint32_t 417 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_03; // offset: 388 (0x184) uint32_t 418 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_03; // offset: 389 (0x185) uint32_t 419 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_03; // offset: 390 (0x186) uint32_t 420 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_03; // offset: 391 (0x187) uint32_t 421 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_03; // offset: 392 (0x188) uint32_t 422 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_03; // offset: 393 (0x189) uint32_t 423 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_03; // offset: 394 (0x18A) uint32_t 424 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_03; // offset: 395 (0x18B) uint32_t 425 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_04; // offset: 396 (0x18C) uint32_t 426 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_04; // offset: 397 (0x18D) uint32_t 427 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_04; // offset: 398 (0x18E) uint32_t 428 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_04; // offset: 399 (0x18F) uint32_t 429 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_04; // offset: 400 (0x190) uint32_t 430 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_04; // offset: 401 (0x191) uint32_t 431 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_04; // offset: 402 (0x192) uint32_t 432 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_04; // offset: 403 (0x193) uint32_t 433 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_05; // offset: 404 (0x194) uint32_t 434 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_05; // offset: 405 (0x195) uint32_t 435 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_05; // offset: 406 (0x196) uint32_t 436 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_05; // offset: 407 (0x197) uint32_t 437 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_05; // offset: 408 (0x198) uint32_t 438 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_05; // offset: 409 (0x199) uint32_t 439 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_05; // offset: 410 (0x19A) uint32_t 440 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_05; // offset: 411 (0x19B) uint32_t 441 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_06; // offset: 412 (0x19C) uint32_t 442 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_06; // offset: 413 (0x19D) uint32_t 443 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_06; // offset: 414 (0x19E) uint32_t 444 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_06; // offset: 415 (0x19F) uint32_t 445 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_06; // offset: 416 (0x1A0) uint32_t 446 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_06; // offset: 417 (0x1A1) uint32_t 447 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_06; // offset: 418 (0x1A2) uint32_t 448 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_06; // offset: 419 (0x1A3) uint32_t 449 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_07; // offset: 420 (0x1A4) uint32_t 450 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_07; // offset: 421 (0x1A5) uint32_t 451 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_07; // offset: 422 (0x1A6) uint32_t 452 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_07; // offset: 423 (0x1A7) uint32_t 453 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_07; // offset: 424 (0x1A8) uint32_t 454 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_07; // offset: 425 (0x1A9) uint32_t 455 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_07; // offset: 426 (0x1AA) uint32_t 456 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_07; // offset: 427 (0x1AB) uint32_t 457 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_10; // offset: 428 (0x1AC) uint32_t 458 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_10; // offset: 429 (0x1AD) uint32_t 459 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_10; // offset: 430 (0x1AE) uint32_t 460 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_10; // offset: 431 (0x1AF) uint32_t 461 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_10; // offset: 432 (0x1B0) uint32_t 462 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_10; // offset: 433 (0x1B1) uint32_t 463 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_10; // offset: 434 (0x1B2) uint32_t 464 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_10; // offset: 435 (0x1B3) uint32_t 465 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_11; // offset: 436 (0x1B4) uint32_t 466 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_11; // offset: 437 (0x1B5) uint32_t 467 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_11; // offset: 438 (0x1B6) uint32_t 468 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_11; // offset: 439 (0x1B7) uint32_t 469 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_11; // offset: 440 (0x1B8) uint32_t 470 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_11; // offset: 441 (0x1B9) uint32_t 471 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_11; // offset: 442 (0x1BA) uint32_t 472 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_11; // offset: 443 (0x1BB) uint32_t 473 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_12; // offset: 444 (0x1BC) uint32_t 474 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_12; // offset: 445 (0x1BD) uint32_t 475 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_12; // offset: 446 (0x1BE) uint32_t 476 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_12; // offset: 447 (0x1BF) uint32_t 477 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_12; // offset: 448 (0x1C0) uint32_t 478 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_12; // offset: 449 (0x1C1) uint32_t 479 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_12; // offset: 450 (0x1C2) uint32_t 480 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_12; // offset: 451 (0x1C3) uint32_t 481 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_13; // offset: 452 (0x1C4) uint32_t 482 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_13; // offset: 453 (0x1C5) uint32_t 483 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_13; // offset: 454 (0x1C6) uint32_t 484 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_13; // offset: 455 (0x1C7) uint32_t 485 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_13; // offset: 456 (0x1C8) uint32_t 486 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_13; // offset: 457 (0x1C9) uint32_t 487 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_13; // offset: 458 (0x1CA) uint32_t 488 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_13; // offset: 459 (0x1CB) uint32_t 489 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_14; // offset: 460 (0x1CC) uint32_t 490 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_14; // offset: 461 (0x1CD) uint32_t 491 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_14; // offset: 462 (0x1CE) uint32_t 492 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_14; // offset: 463 (0x1CF) uint32_t 493 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_14; // offset: 464 (0x1D0) uint32_t 494 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_14; // offset: 465 (0x1D1) uint32_t 495 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_14; // offset: 466 (0x1D2) uint32_t 496 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_14; // offset: 467 (0x1D3) uint32_t 497 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_15; // offset: 468 (0x1D4) uint32_t 498 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_15; // offset: 469 (0x1D5) uint32_t 499 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_15; // offset: 470 (0x1D6) uint32_t 500 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_15; // offset: 471 (0x1D7) uint32_t 501 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_15; // offset: 472 (0x1D8) uint32_t 502 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_15; // offset: 473 (0x1D9) uint32_t 503 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_15; // offset: 474 (0x1DA) uint32_t 504 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_15; // offset: 475 (0x1DB) uint32_t 505 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_16; // offset: 476 (0x1DC) uint32_t 506 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_16; // offset: 477 (0x1DD) uint32_t 507 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_16; // offset: 478 (0x1DE) uint32_t 508 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_16; // offset: 479 (0x1DF) uint32_t 509 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_16; // offset: 480 (0x1E0) uint32_t 510 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_16; // offset: 481 (0x1E1) uint32_t 511 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_16; // offset: 482 (0x1E2) uint32_t 512 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_16; // offset: 483 (0x1E3) uint32_t 513 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_low_17; // offset: 484 (0x1E4) uint32_t 514 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count0_hi_17; // offset: 485 (0x1E5) uint32_t 515 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_low_17; // offset: 486 (0x1E6) uint32_t 516 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count1_hi_17; // offset: 487 (0x1E7) uint32_t 517 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_low_17; // offset: 488 (0x1E8) uint32_t 518 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count2_hi_17; // offset: 489 (0x1E9) uint32_t 519 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_low_17; // offset: 490 (0x1EA) uint32_t 520 drivers/gpu/drm/amd/include/v10_structs.h uint32_t db_occlusion_count3_hi_17; // offset: 491 (0x1EB) uint32_t 521 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_492; // offset: 492 (0x1EC) uint32_t 522 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_493; // offset: 493 (0x1ED) uint32_t 523 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_494; // offset: 494 (0x1EE) uint32_t 524 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_495; // offset: 495 (0x1EF) uint32_t 525 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_496; // offset: 496 (0x1F0) uint32_t 526 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_497; // offset: 497 (0x1F1) uint32_t 527 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_498; // offset: 498 (0x1F2) uint32_t 528 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_499; // offset: 499 (0x1F3) uint32_t 529 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_500; // offset: 500 (0x1F4) uint32_t 530 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_501; // offset: 501 (0x1F5) uint32_t 531 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_502; // offset: 502 (0x1F6) uint32_t 532 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_503; // offset: 503 (0x1F7) uint32_t 533 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_504; // offset: 504 (0x1F8) uint32_t 534 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_505; // offset: 505 (0x1F9) uint32_t 535 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_506; // offset: 506 (0x1FA) uint32_t 536 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_507; // offset: 507 (0x1FB) uint32_t 537 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_508; // offset: 508 (0x1FC) uint32_t 538 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_509; // offset: 509 (0x1FD) uint32_t 539 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_510; // offset: 510 (0x1FE) uint32_t 540 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_511; // offset: 511 (0x1FF) uint32_t 544 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_cntl; uint32_t 545 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_base; uint32_t 546 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_base_hi; uint32_t 547 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_rptr; uint32_t 548 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_rptr_hi; uint32_t 549 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_wptr; uint32_t 550 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_wptr_hi; uint32_t 551 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_wptr_poll_cntl; uint32_t 552 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_rptr_addr_hi; uint32_t 553 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_rptr_addr_lo; uint32_t 554 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_ib_cntl; uint32_t 555 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_ib_rptr; uint32_t 556 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_ib_offset; uint32_t 557 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_ib_base_lo; uint32_t 558 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_ib_base_hi; uint32_t 559 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_ib_size; uint32_t 560 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_skip_cntl; uint32_t 561 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_context_status; uint32_t 562 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_doorbell; uint32_t 563 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_status; uint32_t 564 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_doorbell_log; uint32_t 565 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_watermark; uint32_t 566 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_doorbell_offset; uint32_t 567 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_csa_addr_lo; uint32_t 568 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_csa_addr_hi; uint32_t 569 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_ib_sub_remain; uint32_t 570 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_preempt; uint32_t 571 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_dummy_reg; uint32_t 572 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; uint32_t 573 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; uint32_t 574 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_rb_aql_cntl; uint32_t 575 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_minor_ptr_update; uint32_t 576 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_data0; uint32_t 577 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_data1; uint32_t 578 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_data2; uint32_t 579 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_data3; uint32_t 580 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_data4; uint32_t 581 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_data5; uint32_t 582 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_data6; uint32_t 583 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_data7; uint32_t 584 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_data8; uint32_t 585 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdmax_rlcx_midcmd_cntl; uint32_t 586 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_42; uint32_t 587 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_43; uint32_t 588 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_44; uint32_t 589 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_45; uint32_t 590 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_46; uint32_t 591 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_47; uint32_t 592 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_48; uint32_t 593 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_49; uint32_t 594 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_50; uint32_t 595 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_51; uint32_t 596 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_52; uint32_t 597 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_53; uint32_t 598 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_54; uint32_t 599 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_55; uint32_t 600 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_56; uint32_t 601 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_57; uint32_t 602 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_58; uint32_t 603 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_59; uint32_t 604 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_60; uint32_t 605 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_61; uint32_t 606 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_62; uint32_t 607 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_63; uint32_t 608 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_64; uint32_t 609 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_65; uint32_t 610 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_66; uint32_t 611 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_67; uint32_t 612 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_68; uint32_t 613 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_69; uint32_t 614 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_70; uint32_t 615 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_71; uint32_t 616 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_72; uint32_t 617 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_73; uint32_t 618 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_74; uint32_t 619 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_75; uint32_t 620 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_76; uint32_t 621 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_77; uint32_t 622 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_78; uint32_t 623 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_79; uint32_t 624 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_80; uint32_t 625 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_81; uint32_t 626 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_82; uint32_t 627 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_83; uint32_t 628 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_84; uint32_t 629 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_85; uint32_t 630 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_86; uint32_t 631 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_87; uint32_t 632 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_88; uint32_t 633 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_89; uint32_t 634 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_90; uint32_t 635 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_91; uint32_t 636 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_92; uint32_t 637 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_93; uint32_t 638 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_94; uint32_t 639 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_95; uint32_t 640 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_96; uint32_t 641 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_97; uint32_t 642 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_98; uint32_t 643 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_99; uint32_t 644 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_100; uint32_t 645 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_101; uint32_t 646 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_102; uint32_t 647 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_103; uint32_t 648 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_104; uint32_t 649 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_105; uint32_t 650 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_106; uint32_t 651 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_107; uint32_t 652 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_108; uint32_t 653 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_109; uint32_t 654 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_110; uint32_t 655 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_111; uint32_t 656 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_112; uint32_t 657 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_113; uint32_t 658 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_114; uint32_t 659 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_115; uint32_t 660 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_116; uint32_t 661 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_117; uint32_t 662 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_118; uint32_t 663 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_119; uint32_t 664 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_120; uint32_t 665 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_121; uint32_t 666 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_122; uint32_t 667 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_123; uint32_t 668 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_124; uint32_t 669 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_125; uint32_t 670 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_126; uint32_t 671 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_127; uint32_t 672 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdma_engine_id; uint32_t 673 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sdma_queue_id; uint32_t 677 drivers/gpu/drm/amd/include/v10_structs.h uint32_t header; uint32_t 678 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_dispatch_initiator; uint32_t 679 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_dim_x; uint32_t 680 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_dim_y; uint32_t 681 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_dim_z; uint32_t 682 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_start_x; uint32_t 683 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_start_y; uint32_t 684 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_start_z; uint32_t 685 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_num_thread_x; uint32_t 686 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_num_thread_y; uint32_t 687 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_num_thread_z; uint32_t 688 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_pipelinestat_enable; uint32_t 689 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_perfcount_enable; uint32_t 690 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_pgm_lo; uint32_t 691 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_pgm_hi; uint32_t 692 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_tba_lo; uint32_t 693 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_tba_hi; uint32_t 694 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_tma_lo; uint32_t 695 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_tma_hi; uint32_t 696 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_pgm_rsrc1; uint32_t 697 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_pgm_rsrc2; uint32_t 698 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_vmid; uint32_t 699 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_resource_limits; uint32_t 700 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_static_thread_mgmt_se0; uint32_t 701 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_static_thread_mgmt_se1; uint32_t 702 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_tmpring_size; uint32_t 703 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_static_thread_mgmt_se2; uint32_t 704 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_static_thread_mgmt_se3; uint32_t 705 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_restart_x; uint32_t 706 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_restart_y; uint32_t 707 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_restart_z; uint32_t 708 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_thread_trace_enable; uint32_t 709 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_misc_reserved; uint32_t 710 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_dispatch_id; uint32_t 711 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_threadgroup_id; uint32_t 712 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_relaunch; uint32_t 713 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_wave_restore_addr_lo; uint32_t 714 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_wave_restore_addr_hi; uint32_t 715 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_wave_restore_control; uint32_t 716 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_39; uint32_t 717 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_40; uint32_t 718 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_41; uint32_t 719 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_42; uint32_t 720 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_43; uint32_t 721 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_44; uint32_t 722 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_45; uint32_t 723 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_46; uint32_t 724 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_47; uint32_t 725 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_48; uint32_t 726 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_49; uint32_t 727 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_50; uint32_t 728 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_51; uint32_t 729 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_52; uint32_t 730 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_53; uint32_t 731 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_54; uint32_t 732 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_55; uint32_t 733 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_56; uint32_t 734 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_57; uint32_t 735 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_58; uint32_t 736 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_59; uint32_t 737 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_60; uint32_t 738 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_61; uint32_t 739 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_62; uint32_t 740 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_63; uint32_t 741 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_64; uint32_t 742 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_0; uint32_t 743 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_1; uint32_t 744 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_2; uint32_t 745 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_3; uint32_t 746 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_4; uint32_t 747 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_5; uint32_t 748 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_6; uint32_t 749 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_7; uint32_t 750 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_8; uint32_t 751 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_9; uint32_t 752 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_10; uint32_t 753 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_11; uint32_t 754 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_12; uint32_t 755 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_13; uint32_t 756 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_14; uint32_t 757 drivers/gpu/drm/amd/include/v10_structs.h uint32_t compute_user_data_15; uint32_t 758 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_compute_csinvoc_count_lo; uint32_t 759 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_compute_csinvoc_count_hi; uint32_t 760 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_83; uint32_t 761 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_84; uint32_t 762 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_85; uint32_t 763 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_query_time_lo; uint32_t 764 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_query_time_hi; uint32_t 765 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_connect_start_time_lo; uint32_t 766 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_connect_start_time_hi; uint32_t 767 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_connect_end_time_lo; uint32_t 768 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_connect_end_time_hi; uint32_t 769 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_connect_end_wf_count; uint32_t 770 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_connect_end_pq_rptr; uint32_t 771 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_connect_end_pq_wptr; uint32_t 772 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_connect_end_ib_rptr; uint32_t 773 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_readindex_lo; uint32_t 774 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_readindex_hi; uint32_t 775 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_save_start_time_lo; uint32_t 776 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_save_start_time_hi; uint32_t 777 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_save_end_time_lo; uint32_t 778 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_save_end_time_hi; uint32_t 779 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_restore_start_time_lo; uint32_t 780 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_restore_start_time_hi; uint32_t 781 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_restore_end_time_lo; uint32_t 782 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_restore_end_time_hi; uint32_t 783 drivers/gpu/drm/amd/include/v10_structs.h uint32_t disable_queue; uint32_t 784 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_107; uint32_t 785 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_cs_ctxsw_cnt0; uint32_t 786 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_cs_ctxsw_cnt1; uint32_t 787 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_cs_ctxsw_cnt2; uint32_t 788 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_cs_ctxsw_cnt3; uint32_t 789 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_112; uint32_t 790 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_113; uint32_t 791 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_pq_exe_status_lo; uint32_t 792 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_pq_exe_status_hi; uint32_t 793 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_packet_id_lo; uint32_t 794 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_packet_id_hi; uint32_t 795 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_packet_exe_status_lo; uint32_t 796 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_packet_exe_status_hi; uint32_t 797 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_save_base_addr_lo; uint32_t 798 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_save_base_addr_hi; uint32_t 799 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_save_mask_lo; uint32_t 800 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_save_mask_hi; uint32_t 801 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ctx_save_base_addr_lo; uint32_t 802 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ctx_save_base_addr_hi; uint32_t 803 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_126; uint32_t 804 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_127; uint32_t 805 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_base_addr_lo; uint32_t 806 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_base_addr_hi; uint32_t 807 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_active; uint32_t 808 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_vmid; uint32_t 809 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_persistent_state; uint32_t 810 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pipe_priority; uint32_t 811 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_queue_priority; uint32_t 812 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_quantum; uint32_t 813 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_base_lo; uint32_t 814 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_base_hi; uint32_t 815 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_rptr; uint32_t 816 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_rptr_report_addr_lo; uint32_t 817 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_rptr_report_addr_hi; uint32_t 818 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_wptr_poll_addr_lo; uint32_t 819 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_wptr_poll_addr_hi; uint32_t 820 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_doorbell_control; uint32_t 821 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_144; uint32_t 822 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_control; uint32_t 823 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_ib_base_addr_lo; uint32_t 824 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_ib_base_addr_hi; uint32_t 825 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_ib_rptr; uint32_t 826 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_ib_control; uint32_t 827 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_iq_timer; uint32_t 828 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_iq_rptr; uint32_t 829 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_dequeue_request; uint32_t 830 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_dma_offload; uint32_t 831 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_sema_cmd; uint32_t 832 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_msg_type; uint32_t 833 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_atomic0_preop_lo; uint32_t 834 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_atomic0_preop_hi; uint32_t 835 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_atomic1_preop_lo; uint32_t 836 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_atomic1_preop_hi; uint32_t 837 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_hq_scheduler0; uint32_t 838 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_hq_scheduler1; uint32_t 839 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_mqd_control; uint32_t 840 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_hq_status1; uint32_t 841 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_hq_control1; uint32_t 842 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_eop_base_addr_lo; uint32_t 843 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_eop_base_addr_hi; uint32_t 844 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_eop_control; uint32_t 845 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_eop_rptr; uint32_t 846 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_eop_wptr; uint32_t 847 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_eop_done_events; uint32_t 848 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_ctx_save_base_addr_lo; uint32_t 849 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_ctx_save_base_addr_hi; uint32_t 850 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_ctx_save_control; uint32_t 851 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_cntl_stack_offset; uint32_t 852 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_cntl_stack_size; uint32_t 853 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_wg_state_offset; uint32_t 854 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_ctx_save_size; uint32_t 855 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_gds_resource_state; uint32_t 856 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_error; uint32_t 857 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_eop_wptr_mem; uint32_t 858 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_aql_control; uint32_t 859 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_wptr_lo; uint32_t 860 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_wptr_hi; uint32_t 861 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_suspend_cntl_stack_offset; uint32_t 862 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_suspend_cntl_stack_dw_cnt; uint32_t 863 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_suspend_wg_state_offset; uint32_t 864 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_187; uint32_t 865 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_188; uint32_t 866 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_189; uint32_t 867 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_190; uint32_t 868 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_191; uint32_t 869 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_header; uint32_t 870 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw0; uint32_t 871 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw1; uint32_t 872 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw2; uint32_t 873 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw3; uint32_t 874 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw4; uint32_t 875 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw5; uint32_t 876 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw6; uint32_t 877 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw7; uint32_t 878 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw8; uint32_t 879 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw9; uint32_t 880 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw10; uint32_t 881 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw11; uint32_t 882 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw12; uint32_t 883 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw13; uint32_t 884 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw14; uint32_t 885 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw15; uint32_t 886 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw16; uint32_t 887 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw17; uint32_t 888 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw18; uint32_t 889 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw19; uint32_t 890 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw20; uint32_t 891 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw21; uint32_t 892 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw22; uint32_t 893 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw23; uint32_t 894 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw24; uint32_t 895 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw25; uint32_t 896 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw26; uint32_t 897 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw27; uint32_t 898 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw28; uint32_t 899 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw29; uint32_t 900 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw30; uint32_t 901 drivers/gpu/drm/amd/include/v10_structs.h uint32_t iqtimer_pkt_dw31; uint32_t 902 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_225; uint32_t 903 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_226; uint32_t 904 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_227; uint32_t 905 drivers/gpu/drm/amd/include/v10_structs.h uint32_t set_resources_header; uint32_t 906 drivers/gpu/drm/amd/include/v10_structs.h uint32_t set_resources_dw1; uint32_t 907 drivers/gpu/drm/amd/include/v10_structs.h uint32_t set_resources_dw2; uint32_t 908 drivers/gpu/drm/amd/include/v10_structs.h uint32_t set_resources_dw3; uint32_t 909 drivers/gpu/drm/amd/include/v10_structs.h uint32_t set_resources_dw4; uint32_t 910 drivers/gpu/drm/amd/include/v10_structs.h uint32_t set_resources_dw5; uint32_t 911 drivers/gpu/drm/amd/include/v10_structs.h uint32_t set_resources_dw6; uint32_t 912 drivers/gpu/drm/amd/include/v10_structs.h uint32_t set_resources_dw7; uint32_t 913 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_236; uint32_t 914 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_237; uint32_t 915 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_238; uint32_t 916 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_239; uint32_t 917 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id0; uint32_t 918 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id1; uint32_t 919 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id2; uint32_t 920 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id3; uint32_t 921 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id4; uint32_t 922 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id5; uint32_t 923 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id6; uint32_t 924 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id7; uint32_t 925 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id8; uint32_t 926 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id9; uint32_t 927 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id10; uint32_t 928 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id11; uint32_t 929 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id12; uint32_t 930 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id13; uint32_t 931 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id14; uint32_t 932 drivers/gpu/drm/amd/include/v10_structs.h uint32_t queue_doorbell_id15; uint32_t 933 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_256; uint32_t 934 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_257; uint32_t 935 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_258; uint32_t 936 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_259; uint32_t 937 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_260; uint32_t 938 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_261; uint32_t 939 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_262; uint32_t 940 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_263; uint32_t 941 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_264; uint32_t 942 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_265; uint32_t 943 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_266; uint32_t 944 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_267; uint32_t 945 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_268; uint32_t 946 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_269; uint32_t 947 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_270; uint32_t 948 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_271; uint32_t 949 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_272; uint32_t 950 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_273; uint32_t 951 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_274; uint32_t 952 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_275; uint32_t 953 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_276; uint32_t 954 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_277; uint32_t 955 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_278; uint32_t 956 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_279; uint32_t 957 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_280; uint32_t 958 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_281; uint32_t 959 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_282; uint32_t 960 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_283; uint32_t 961 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_284; uint32_t 962 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_285; uint32_t 963 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_286; uint32_t 964 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_287; uint32_t 965 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_288; uint32_t 966 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_289; uint32_t 967 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_290; uint32_t 968 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_291; uint32_t 969 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_292; uint32_t 970 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_293; uint32_t 971 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_294; uint32_t 972 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_295; uint32_t 973 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_296; uint32_t 974 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_297; uint32_t 975 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_298; uint32_t 976 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_299; uint32_t 977 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_300; uint32_t 978 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_301; uint32_t 979 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_302; uint32_t 980 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_303; uint32_t 981 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_304; uint32_t 982 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_305; uint32_t 983 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_306; uint32_t 984 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_307; uint32_t 985 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_308; uint32_t 986 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_309; uint32_t 987 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_310; uint32_t 988 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_311; uint32_t 989 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_312; uint32_t 990 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_313; uint32_t 991 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_314; uint32_t 992 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_315; uint32_t 993 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_316; uint32_t 994 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_317; uint32_t 995 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_318; uint32_t 996 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_319; uint32_t 997 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_320; uint32_t 998 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_321; uint32_t 999 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_322; uint32_t 1000 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_323; uint32_t 1001 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_324; uint32_t 1002 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_325; uint32_t 1003 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_326; uint32_t 1004 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_327; uint32_t 1005 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_328; uint32_t 1006 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_329; uint32_t 1007 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_330; uint32_t 1008 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_331; uint32_t 1009 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_332; uint32_t 1010 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_333; uint32_t 1011 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_334; uint32_t 1012 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_335; uint32_t 1013 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_336; uint32_t 1014 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_337; uint32_t 1015 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_338; uint32_t 1016 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_339; uint32_t 1017 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_340; uint32_t 1018 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_341; uint32_t 1019 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_342; uint32_t 1020 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_343; uint32_t 1021 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_344; uint32_t 1022 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_345; uint32_t 1023 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_346; uint32_t 1024 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_347; uint32_t 1025 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_348; uint32_t 1026 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_349; uint32_t 1027 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_350; uint32_t 1028 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_351; uint32_t 1029 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_352; uint32_t 1030 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_353; uint32_t 1031 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_354; uint32_t 1032 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_355; uint32_t 1033 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_356; uint32_t 1034 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_357; uint32_t 1035 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_358; uint32_t 1036 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_359; uint32_t 1037 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_360; uint32_t 1038 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_361; uint32_t 1039 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_362; uint32_t 1040 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_363; uint32_t 1041 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_364; uint32_t 1042 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_365; uint32_t 1043 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_366; uint32_t 1044 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_367; uint32_t 1045 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_368; uint32_t 1046 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_369; uint32_t 1047 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_370; uint32_t 1048 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_371; uint32_t 1049 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_372; uint32_t 1050 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_373; uint32_t 1051 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_374; uint32_t 1052 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_375; uint32_t 1053 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_376; uint32_t 1054 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_377; uint32_t 1055 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_378; uint32_t 1056 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_379; uint32_t 1057 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_380; uint32_t 1058 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_381; uint32_t 1059 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_382; uint32_t 1060 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_383; uint32_t 1061 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_384; uint32_t 1062 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_385; uint32_t 1063 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_386; uint32_t 1064 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_387; uint32_t 1065 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_388; uint32_t 1066 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_389; uint32_t 1067 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_390; uint32_t 1068 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_391; uint32_t 1069 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_392; uint32_t 1070 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_393; uint32_t 1071 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_394; uint32_t 1072 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_395; uint32_t 1073 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_396; uint32_t 1074 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_397; uint32_t 1075 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_398; uint32_t 1076 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_399; uint32_t 1077 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_400; uint32_t 1078 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_401; uint32_t 1079 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_402; uint32_t 1080 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_403; uint32_t 1081 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_404; uint32_t 1082 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_405; uint32_t 1083 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_406; uint32_t 1084 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_407; uint32_t 1085 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_408; uint32_t 1086 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_409; uint32_t 1087 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_410; uint32_t 1088 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_411; uint32_t 1089 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_412; uint32_t 1090 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_413; uint32_t 1091 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_414; uint32_t 1092 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_415; uint32_t 1093 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_416; uint32_t 1094 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_417; uint32_t 1095 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_418; uint32_t 1096 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_419; uint32_t 1097 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_420; uint32_t 1098 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_421; uint32_t 1099 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_422; uint32_t 1100 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_423; uint32_t 1101 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_424; uint32_t 1102 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_425; uint32_t 1103 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_426; uint32_t 1104 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_427; uint32_t 1105 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_428; uint32_t 1106 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_429; uint32_t 1107 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_430; uint32_t 1108 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_431; uint32_t 1109 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_432; uint32_t 1110 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_433; uint32_t 1111 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_434; uint32_t 1112 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_435; uint32_t 1113 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_436; uint32_t 1114 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_437; uint32_t 1115 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_438; uint32_t 1116 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_439; uint32_t 1117 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_440; uint32_t 1118 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_441; uint32_t 1119 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_442; uint32_t 1120 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_443; uint32_t 1121 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_444; uint32_t 1122 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_445; uint32_t 1123 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_446; uint32_t 1124 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_447; uint32_t 1125 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_448; uint32_t 1126 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_449; uint32_t 1127 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_450; uint32_t 1128 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_451; uint32_t 1129 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_452; uint32_t 1130 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_453; uint32_t 1131 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_454; uint32_t 1132 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_455; uint32_t 1133 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_456; uint32_t 1134 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_457; uint32_t 1135 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_458; uint32_t 1136 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_459; uint32_t 1137 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_460; uint32_t 1138 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_461; uint32_t 1139 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_462; uint32_t 1140 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_463; uint32_t 1141 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_464; uint32_t 1142 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_465; uint32_t 1143 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_466; uint32_t 1144 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_467; uint32_t 1145 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_468; uint32_t 1146 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_469; uint32_t 1147 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_470; uint32_t 1148 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_471; uint32_t 1149 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_472; uint32_t 1150 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_473; uint32_t 1151 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_474; uint32_t 1152 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_475; uint32_t 1153 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_476; uint32_t 1154 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_477; uint32_t 1155 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_478; uint32_t 1156 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_479; uint32_t 1157 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_480; uint32_t 1158 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_481; uint32_t 1159 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_482; uint32_t 1160 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_483; uint32_t 1161 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_484; uint32_t 1162 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_485; uint32_t 1163 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_486; uint32_t 1164 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_487; uint32_t 1165 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_488; uint32_t 1166 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_489; uint32_t 1167 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_490; uint32_t 1168 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_491; uint32_t 1169 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_492; uint32_t 1170 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_493; uint32_t 1171 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_494; uint32_t 1172 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_495; uint32_t 1173 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_496; uint32_t 1174 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_497; uint32_t 1175 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_498; uint32_t 1176 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_499; uint32_t 1177 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_500; uint32_t 1178 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_501; uint32_t 1179 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_502; uint32_t 1180 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_503; uint32_t 1181 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_504; uint32_t 1182 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_505; uint32_t 1183 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_506; uint32_t 1184 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_507; uint32_t 1185 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_508; uint32_t 1186 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_509; uint32_t 1187 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_510; uint32_t 1188 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved_511; uint32_t 1193 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_ib_completion_status; uint32_t 1194 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_constegnine_count; uint32_t 1195 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_ibOffset_ib1; uint32_t 1196 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_ibOffset_ib2; uint32_t 1199 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_chainib_addrlo_ib1; uint32_t 1200 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_chainib_addrlo_ib2; uint32_t 1201 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_chainib_addrhi_ib1; uint32_t 1202 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_chainib_addrhi_ib2; uint32_t 1203 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_chainib_size_ib1; uint32_t 1204 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ce_chainib_size_ib2; uint32_t 1209 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ib_completion_status; uint32_t 1210 drivers/gpu/drm/amd/include/v10_structs.h uint32_t de_constEngine_count; uint32_t 1211 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ib_offset_ib1; uint32_t 1212 drivers/gpu/drm/amd/include/v10_structs.h uint32_t ib_offset_ib2; uint32_t 1215 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_addrlo_ib1; uint32_t 1216 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_addrlo_ib2; uint32_t 1217 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_addrhi_ib1; uint32_t 1218 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_addrhi_ib2; uint32_t 1219 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_size_ib1; uint32_t 1220 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_size_ib2; uint32_t 1223 drivers/gpu/drm/amd/include/v10_structs.h uint32_t preamble_begin_ib1; uint32_t 1224 drivers/gpu/drm/amd/include/v10_structs.h uint32_t preamble_begin_ib2; uint32_t 1225 drivers/gpu/drm/amd/include/v10_structs.h uint32_t preamble_end_ib1; uint32_t 1226 drivers/gpu/drm/amd/include/v10_structs.h uint32_t preamble_end_ib2; uint32_t 1229 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_pream_addrlo_ib1; uint32_t 1230 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_pream_addrlo_ib2; uint32_t 1231 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_pream_addrhi_ib1; uint32_t 1232 drivers/gpu/drm/amd/include/v10_structs.h uint32_t chain_ib_pream_addrhi_ib2; uint32_t 1235 drivers/gpu/drm/amd/include/v10_structs.h uint32_t draw_indirect_baseLo; uint32_t 1236 drivers/gpu/drm/amd/include/v10_structs.h uint32_t draw_indirect_baseHi; uint32_t 1237 drivers/gpu/drm/amd/include/v10_structs.h uint32_t disp_indirect_baseLo; uint32_t 1238 drivers/gpu/drm/amd/include/v10_structs.h uint32_t disp_indirect_baseHi; uint32_t 1239 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_backup_addrlo; uint32_t 1240 drivers/gpu/drm/amd/include/v10_structs.h uint32_t gds_backup_addrhi; uint32_t 1241 drivers/gpu/drm/amd/include/v10_structs.h uint32_t index_base_addrlo; uint32_t 1242 drivers/gpu/drm/amd/include/v10_structs.h uint32_t index_base_addrhi; uint32_t 1243 drivers/gpu/drm/amd/include/v10_structs.h uint32_t sample_cntl; uint32_t 1249 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved1[54]; uint32_t 1253 drivers/gpu/drm/amd/include/v10_structs.h uint32_t DeIbBaseAddrLo; uint32_t 1254 drivers/gpu/drm/amd/include/v10_structs.h uint32_t DeIbBaseAddrHi; uint32_t 1255 drivers/gpu/drm/amd/include/v10_structs.h uint32_t reserved2[931]; uint32_t 28 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_cntl; uint32_t 29 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_base; uint32_t 30 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_base_hi; uint32_t 31 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_rptr; uint32_t 32 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_rptr_hi; uint32_t 33 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_wptr; uint32_t 34 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_wptr_hi; uint32_t 35 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_wptr_poll_cntl; uint32_t 36 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_rptr_addr_hi; uint32_t 37 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_rptr_addr_lo; uint32_t 38 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_ib_cntl; uint32_t 39 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_ib_rptr; uint32_t 40 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_ib_offset; uint32_t 41 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_ib_base_lo; uint32_t 42 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_ib_base_hi; uint32_t 43 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_ib_size; uint32_t 44 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_skip_cntl; uint32_t 45 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_context_status; uint32_t 46 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_doorbell; uint32_t 47 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_status; uint32_t 48 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_doorbell_log; uint32_t 49 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_watermark; uint32_t 50 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_doorbell_offset; uint32_t 51 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_csa_addr_lo; uint32_t 52 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_csa_addr_hi; uint32_t 53 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_ib_sub_remain; uint32_t 54 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_preempt; uint32_t 55 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_dummy_reg; uint32_t 56 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; uint32_t 57 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; uint32_t 58 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_rb_aql_cntl; uint32_t 59 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_minor_ptr_update; uint32_t 60 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_data0; uint32_t 61 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_data1; uint32_t 62 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_data2; uint32_t 63 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_data3; uint32_t 64 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_data4; uint32_t 65 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_data5; uint32_t 66 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_data6; uint32_t 67 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_data7; uint32_t 68 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_data8; uint32_t 69 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdmax_rlcx_midcmd_cntl; uint32_t 70 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_42; uint32_t 71 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_43; uint32_t 72 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_44; uint32_t 73 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_45; uint32_t 74 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_46; uint32_t 75 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_47; uint32_t 76 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_48; uint32_t 77 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_49; uint32_t 78 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_50; uint32_t 79 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_51; uint32_t 80 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_52; uint32_t 81 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_53; uint32_t 82 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_54; uint32_t 83 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_55; uint32_t 84 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_56; uint32_t 85 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_57; uint32_t 86 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_58; uint32_t 87 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_59; uint32_t 88 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_60; uint32_t 89 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_61; uint32_t 90 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_62; uint32_t 91 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_63; uint32_t 92 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_64; uint32_t 93 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_65; uint32_t 94 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_66; uint32_t 95 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_67; uint32_t 96 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_68; uint32_t 97 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_69; uint32_t 98 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_70; uint32_t 99 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_71; uint32_t 100 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_72; uint32_t 101 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_73; uint32_t 102 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_74; uint32_t 103 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_75; uint32_t 104 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_76; uint32_t 105 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_77; uint32_t 106 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_78; uint32_t 107 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_79; uint32_t 108 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_80; uint32_t 109 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_81; uint32_t 110 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_82; uint32_t 111 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_83; uint32_t 112 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_84; uint32_t 113 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_85; uint32_t 114 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_86; uint32_t 115 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_87; uint32_t 116 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_88; uint32_t 117 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_89; uint32_t 118 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_90; uint32_t 119 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_91; uint32_t 120 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_92; uint32_t 121 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_93; uint32_t 122 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_94; uint32_t 123 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_95; uint32_t 124 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_96; uint32_t 125 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_97; uint32_t 126 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_98; uint32_t 127 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_99; uint32_t 128 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_100; uint32_t 129 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_101; uint32_t 130 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_102; uint32_t 131 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_103; uint32_t 132 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_104; uint32_t 133 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_105; uint32_t 134 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_106; uint32_t 135 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_107; uint32_t 136 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_108; uint32_t 137 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_109; uint32_t 138 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_110; uint32_t 139 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_111; uint32_t 140 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_112; uint32_t 141 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_113; uint32_t 142 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_114; uint32_t 143 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_115; uint32_t 144 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_116; uint32_t 145 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_117; uint32_t 146 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_118; uint32_t 147 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_119; uint32_t 148 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_120; uint32_t 149 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_121; uint32_t 150 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_122; uint32_t 151 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_123; uint32_t 152 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_124; uint32_t 153 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_125; uint32_t 155 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdma_engine_id; uint32_t 156 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sdma_queue_id; uint32_t 160 drivers/gpu/drm/amd/include/v9_structs.h uint32_t header; uint32_t 161 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_dispatch_initiator; uint32_t 162 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_dim_x; uint32_t 163 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_dim_y; uint32_t 164 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_dim_z; uint32_t 165 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_start_x; uint32_t 166 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_start_y; uint32_t 167 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_start_z; uint32_t 168 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_num_thread_x; uint32_t 169 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_num_thread_y; uint32_t 170 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_num_thread_z; uint32_t 171 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_pipelinestat_enable; uint32_t 172 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_perfcount_enable; uint32_t 173 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_pgm_lo; uint32_t 174 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_pgm_hi; uint32_t 175 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_tba_lo; uint32_t 176 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_tba_hi; uint32_t 177 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_tma_lo; uint32_t 178 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_tma_hi; uint32_t 179 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_pgm_rsrc1; uint32_t 180 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_pgm_rsrc2; uint32_t 181 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_vmid; uint32_t 182 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_resource_limits; uint32_t 183 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_static_thread_mgmt_se0; uint32_t 184 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_static_thread_mgmt_se1; uint32_t 185 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_tmpring_size; uint32_t 186 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_static_thread_mgmt_se2; uint32_t 187 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_static_thread_mgmt_se3; uint32_t 188 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_restart_x; uint32_t 189 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_restart_y; uint32_t 190 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_restart_z; uint32_t 191 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_thread_trace_enable; uint32_t 192 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_misc_reserved; uint32_t 193 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_dispatch_id; uint32_t 194 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_threadgroup_id; uint32_t 195 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_relaunch; uint32_t 196 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_wave_restore_addr_lo; uint32_t 197 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_wave_restore_addr_hi; uint32_t 198 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_wave_restore_control; uint32_t 199 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_static_thread_mgmt_se4; uint32_t 200 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_static_thread_mgmt_se5; uint32_t 201 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_static_thread_mgmt_se6; uint32_t 202 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_static_thread_mgmt_se7; uint32_t 203 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_43; uint32_t 204 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_44; uint32_t 205 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_45; uint32_t 206 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_46; uint32_t 207 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_47; uint32_t 208 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_48; uint32_t 209 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_49; uint32_t 210 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_50; uint32_t 211 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_51; uint32_t 212 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_52; uint32_t 213 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_53; uint32_t 214 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_54; uint32_t 215 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_55; uint32_t 216 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_56; uint32_t 217 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_57; uint32_t 218 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_58; uint32_t 219 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_59; uint32_t 220 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_60; uint32_t 221 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_61; uint32_t 222 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_62; uint32_t 223 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_63; uint32_t 224 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_64; uint32_t 225 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_0; uint32_t 226 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_1; uint32_t 227 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_2; uint32_t 228 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_3; uint32_t 229 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_4; uint32_t 230 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_5; uint32_t 231 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_6; uint32_t 232 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_7; uint32_t 233 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_8; uint32_t 234 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_9; uint32_t 235 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_10; uint32_t 236 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_11; uint32_t 237 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_12; uint32_t 238 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_13; uint32_t 239 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_14; uint32_t 240 drivers/gpu/drm/amd/include/v9_structs.h uint32_t compute_user_data_15; uint32_t 241 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_compute_csinvoc_count_lo; uint32_t 242 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_compute_csinvoc_count_hi; uint32_t 243 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_83; uint32_t 244 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_84; uint32_t 245 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_85; uint32_t 246 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_query_time_lo; uint32_t 247 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_query_time_hi; uint32_t 248 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_connect_start_time_lo; uint32_t 249 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_connect_start_time_hi; uint32_t 250 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_connect_end_time_lo; uint32_t 251 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_connect_end_time_hi; uint32_t 252 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_connect_end_wf_count; uint32_t 253 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_connect_end_pq_rptr; uint32_t 254 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_connect_end_pq_wptr; uint32_t 255 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_connect_end_ib_rptr; uint32_t 256 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_readindex_lo; uint32_t 257 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_readindex_hi; uint32_t 258 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_save_start_time_lo; uint32_t 259 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_save_start_time_hi; uint32_t 260 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_save_end_time_lo; uint32_t 261 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_save_end_time_hi; uint32_t 262 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_restore_start_time_lo; uint32_t 263 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_restore_start_time_hi; uint32_t 264 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_restore_end_time_lo; uint32_t 265 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_restore_end_time_hi; uint32_t 266 drivers/gpu/drm/amd/include/v9_structs.h uint32_t disable_queue; uint32_t 267 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_107; uint32_t 268 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_cs_ctxsw_cnt0; uint32_t 269 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_cs_ctxsw_cnt1; uint32_t 270 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_cs_ctxsw_cnt2; uint32_t 271 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_cs_ctxsw_cnt3; uint32_t 272 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_112; uint32_t 273 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_113; uint32_t 274 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_pq_exe_status_lo; uint32_t 275 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_pq_exe_status_hi; uint32_t 276 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_packet_id_lo; uint32_t 277 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_packet_id_hi; uint32_t 278 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_packet_exe_status_lo; uint32_t 279 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_packet_exe_status_hi; uint32_t 280 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_save_base_addr_lo; uint32_t 281 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_save_base_addr_hi; uint32_t 282 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_save_mask_lo; uint32_t 283 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_save_mask_hi; uint32_t 284 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ctx_save_base_addr_lo; uint32_t 285 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ctx_save_base_addr_hi; uint32_t 286 drivers/gpu/drm/amd/include/v9_structs.h uint32_t dynamic_cu_mask_addr_lo; uint32_t 287 drivers/gpu/drm/amd/include/v9_structs.h uint32_t dynamic_cu_mask_addr_hi; uint32_t 288 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_base_addr_lo; uint32_t 289 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_base_addr_hi; uint32_t 290 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_active; uint32_t 291 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_vmid; uint32_t 292 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_persistent_state; uint32_t 293 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pipe_priority; uint32_t 294 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_queue_priority; uint32_t 295 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_quantum; uint32_t 296 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_base_lo; uint32_t 297 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_base_hi; uint32_t 298 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_rptr; uint32_t 299 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_rptr_report_addr_lo; uint32_t 300 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_rptr_report_addr_hi; uint32_t 301 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_wptr_poll_addr_lo; uint32_t 302 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_wptr_poll_addr_hi; uint32_t 303 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_doorbell_control; uint32_t 304 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_144; uint32_t 305 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_control; uint32_t 306 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_ib_base_addr_lo; uint32_t 307 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_ib_base_addr_hi; uint32_t 308 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_ib_rptr; uint32_t 309 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_ib_control; uint32_t 310 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_iq_timer; uint32_t 311 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_iq_rptr; uint32_t 312 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_dequeue_request; uint32_t 313 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_dma_offload; uint32_t 314 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_sema_cmd; uint32_t 315 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_msg_type; uint32_t 316 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_atomic0_preop_lo; uint32_t 317 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_atomic0_preop_hi; uint32_t 318 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_atomic1_preop_lo; uint32_t 319 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_atomic1_preop_hi; uint32_t 320 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_hq_status0; uint32_t 321 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_hq_control0; uint32_t 322 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_mqd_control; uint32_t 323 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_hq_status1; uint32_t 324 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_hq_control1; uint32_t 325 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_eop_base_addr_lo; uint32_t 326 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_eop_base_addr_hi; uint32_t 327 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_eop_control; uint32_t 328 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_eop_rptr; uint32_t 329 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_eop_wptr; uint32_t 330 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_eop_done_events; uint32_t 331 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_ctx_save_base_addr_lo; uint32_t 332 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_ctx_save_base_addr_hi; uint32_t 333 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_ctx_save_control; uint32_t 334 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_cntl_stack_offset; uint32_t 335 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_cntl_stack_size; uint32_t 336 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_wg_state_offset; uint32_t 337 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_ctx_save_size; uint32_t 338 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_gds_resource_state; uint32_t 339 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_error; uint32_t 340 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_eop_wptr_mem; uint32_t 341 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_aql_control; uint32_t 342 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_wptr_lo; uint32_t 343 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_wptr_hi; uint32_t 344 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_184; uint32_t 345 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_185; uint32_t 346 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_186; uint32_t 347 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_187; uint32_t 348 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_188; uint32_t 349 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_189; uint32_t 350 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_190; uint32_t 351 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_191; uint32_t 352 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_header; uint32_t 353 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw0; uint32_t 354 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw1; uint32_t 355 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw2; uint32_t 356 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw3; uint32_t 357 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw4; uint32_t 358 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw5; uint32_t 359 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw6; uint32_t 360 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw7; uint32_t 361 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw8; uint32_t 362 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw9; uint32_t 363 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw10; uint32_t 364 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw11; uint32_t 365 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw12; uint32_t 366 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw13; uint32_t 367 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw14; uint32_t 368 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw15; uint32_t 369 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw16; uint32_t 370 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw17; uint32_t 371 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw18; uint32_t 372 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw19; uint32_t 373 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw20; uint32_t 374 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw21; uint32_t 375 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw22; uint32_t 376 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw23; uint32_t 377 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw24; uint32_t 378 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw25; uint32_t 379 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw26; uint32_t 380 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw27; uint32_t 381 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw28; uint32_t 382 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw29; uint32_t 383 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw30; uint32_t 384 drivers/gpu/drm/amd/include/v9_structs.h uint32_t iqtimer_pkt_dw31; uint32_t 385 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_225; uint32_t 386 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_226; uint32_t 387 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_227; uint32_t 388 drivers/gpu/drm/amd/include/v9_structs.h uint32_t set_resources_header; uint32_t 389 drivers/gpu/drm/amd/include/v9_structs.h uint32_t set_resources_dw1; uint32_t 390 drivers/gpu/drm/amd/include/v9_structs.h uint32_t set_resources_dw2; uint32_t 391 drivers/gpu/drm/amd/include/v9_structs.h uint32_t set_resources_dw3; uint32_t 392 drivers/gpu/drm/amd/include/v9_structs.h uint32_t set_resources_dw4; uint32_t 393 drivers/gpu/drm/amd/include/v9_structs.h uint32_t set_resources_dw5; uint32_t 394 drivers/gpu/drm/amd/include/v9_structs.h uint32_t set_resources_dw6; uint32_t 395 drivers/gpu/drm/amd/include/v9_structs.h uint32_t set_resources_dw7; uint32_t 396 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_236; uint32_t 397 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_237; uint32_t 398 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_238; uint32_t 399 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_239; uint32_t 400 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id0; uint32_t 401 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id1; uint32_t 402 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id2; uint32_t 403 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id3; uint32_t 404 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id4; uint32_t 405 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id5; uint32_t 406 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id6; uint32_t 407 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id7; uint32_t 408 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id8; uint32_t 409 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id9; uint32_t 410 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id10; uint32_t 411 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id11; uint32_t 412 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id12; uint32_t 413 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id13; uint32_t 414 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id14; uint32_t 415 drivers/gpu/drm/amd/include/v9_structs.h uint32_t queue_doorbell_id15; uint32_t 416 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_256; uint32_t 417 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_257; uint32_t 418 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_258; uint32_t 419 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_259; uint32_t 420 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_260; uint32_t 421 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_261; uint32_t 422 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_262; uint32_t 423 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_263; uint32_t 424 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_264; uint32_t 425 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_265; uint32_t 426 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_266; uint32_t 427 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_267; uint32_t 428 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_268; uint32_t 429 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_269; uint32_t 430 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_270; uint32_t 431 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_271; uint32_t 432 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_272; uint32_t 433 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_273; uint32_t 434 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_274; uint32_t 435 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_275; uint32_t 436 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_276; uint32_t 437 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_277; uint32_t 438 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_278; uint32_t 439 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_279; uint32_t 440 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_280; uint32_t 441 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_281; uint32_t 442 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_282; uint32_t 443 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_283; uint32_t 444 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_284; uint32_t 445 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_285; uint32_t 446 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_286; uint32_t 447 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_287; uint32_t 448 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_288; uint32_t 449 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_289; uint32_t 450 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_290; uint32_t 451 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_291; uint32_t 452 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_292; uint32_t 453 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_293; uint32_t 454 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_294; uint32_t 455 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_295; uint32_t 456 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_296; uint32_t 457 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_297; uint32_t 458 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_298; uint32_t 459 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_299; uint32_t 460 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_300; uint32_t 461 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_301; uint32_t 462 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_302; uint32_t 463 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_303; uint32_t 464 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_304; uint32_t 465 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_305; uint32_t 466 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_306; uint32_t 467 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_307; uint32_t 468 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_308; uint32_t 469 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_309; uint32_t 470 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_310; uint32_t 471 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_311; uint32_t 472 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_312; uint32_t 473 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_313; uint32_t 474 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_314; uint32_t 475 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_315; uint32_t 476 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_316; uint32_t 477 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_317; uint32_t 478 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_318; uint32_t 479 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_319; uint32_t 480 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_320; uint32_t 481 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_321; uint32_t 482 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_322; uint32_t 483 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_323; uint32_t 484 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_324; uint32_t 485 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_325; uint32_t 486 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_326; uint32_t 487 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_327; uint32_t 488 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_328; uint32_t 489 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_329; uint32_t 490 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_330; uint32_t 491 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_331; uint32_t 492 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_332; uint32_t 493 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_333; uint32_t 494 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_334; uint32_t 495 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_335; uint32_t 496 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_336; uint32_t 497 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_337; uint32_t 498 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_338; uint32_t 499 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_339; uint32_t 500 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_340; uint32_t 501 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_341; uint32_t 502 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_342; uint32_t 503 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_343; uint32_t 504 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_344; uint32_t 505 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_345; uint32_t 506 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_346; uint32_t 507 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_347; uint32_t 508 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_348; uint32_t 509 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_349; uint32_t 510 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_350; uint32_t 511 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_351; uint32_t 512 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_352; uint32_t 513 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_353; uint32_t 514 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_354; uint32_t 515 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_355; uint32_t 516 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_356; uint32_t 517 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_357; uint32_t 518 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_358; uint32_t 519 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_359; uint32_t 520 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_360; uint32_t 521 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_361; uint32_t 522 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_362; uint32_t 523 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_363; uint32_t 524 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_364; uint32_t 525 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_365; uint32_t 526 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_366; uint32_t 527 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_367; uint32_t 528 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_368; uint32_t 529 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_369; uint32_t 530 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_370; uint32_t 531 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_371; uint32_t 532 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_372; uint32_t 533 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_373; uint32_t 534 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_374; uint32_t 535 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_375; uint32_t 536 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_376; uint32_t 537 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_377; uint32_t 538 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_378; uint32_t 539 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_379; uint32_t 540 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_380; uint32_t 541 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_381; uint32_t 542 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_382; uint32_t 543 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_383; uint32_t 544 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_384; uint32_t 545 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_385; uint32_t 546 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_386; uint32_t 547 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_387; uint32_t 548 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_388; uint32_t 549 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_389; uint32_t 550 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_390; uint32_t 551 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_391; uint32_t 552 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_392; uint32_t 553 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_393; uint32_t 554 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_394; uint32_t 555 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_395; uint32_t 556 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_396; uint32_t 557 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_397; uint32_t 558 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_398; uint32_t 559 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_399; uint32_t 560 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_400; uint32_t 561 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_401; uint32_t 562 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_402; uint32_t 563 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_403; uint32_t 564 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_404; uint32_t 565 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_405; uint32_t 566 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_406; uint32_t 567 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_407; uint32_t 568 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_408; uint32_t 569 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_409; uint32_t 570 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_410; uint32_t 571 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_411; uint32_t 572 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_412; uint32_t 573 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_413; uint32_t 574 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_414; uint32_t 575 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_415; uint32_t 576 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_416; uint32_t 577 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_417; uint32_t 578 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_418; uint32_t 579 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_419; uint32_t 580 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_420; uint32_t 581 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_421; uint32_t 582 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_422; uint32_t 583 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_423; uint32_t 584 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_424; uint32_t 585 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_425; uint32_t 586 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_426; uint32_t 587 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_427; uint32_t 588 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_428; uint32_t 589 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_429; uint32_t 590 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_430; uint32_t 591 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_431; uint32_t 592 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_432; uint32_t 593 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_433; uint32_t 594 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_434; uint32_t 595 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_435; uint32_t 596 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_436; uint32_t 597 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_437; uint32_t 598 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_438; uint32_t 599 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_439; uint32_t 600 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_440; uint32_t 601 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_441; uint32_t 602 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_442; uint32_t 603 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_443; uint32_t 604 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_444; uint32_t 605 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_445; uint32_t 606 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_446; uint32_t 607 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_447; uint32_t 608 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_448; uint32_t 609 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_449; uint32_t 610 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_450; uint32_t 611 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_451; uint32_t 612 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_452; uint32_t 613 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_453; uint32_t 614 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_454; uint32_t 615 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_455; uint32_t 616 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_456; uint32_t 617 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_457; uint32_t 618 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_458; uint32_t 619 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_459; uint32_t 620 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_460; uint32_t 621 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_461; uint32_t 622 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_462; uint32_t 623 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_463; uint32_t 624 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_464; uint32_t 625 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_465; uint32_t 626 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_466; uint32_t 627 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_467; uint32_t 628 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_468; uint32_t 629 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_469; uint32_t 630 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_470; uint32_t 631 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_471; uint32_t 632 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_472; uint32_t 633 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_473; uint32_t 634 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_474; uint32_t 635 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_475; uint32_t 636 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_476; uint32_t 637 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_477; uint32_t 638 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_478; uint32_t 639 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_479; uint32_t 640 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_480; uint32_t 641 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_481; uint32_t 642 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_482; uint32_t 643 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_483; uint32_t 644 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_484; uint32_t 645 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_485; uint32_t 646 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_486; uint32_t 647 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_487; uint32_t 648 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_488; uint32_t 649 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_489; uint32_t 650 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_490; uint32_t 651 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_491; uint32_t 652 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_492; uint32_t 653 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_493; uint32_t 654 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_494; uint32_t 655 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_495; uint32_t 656 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_496; uint32_t 657 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_497; uint32_t 658 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_498; uint32_t 659 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_499; uint32_t 660 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_500; uint32_t 661 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_501; uint32_t 662 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_502; uint32_t 663 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_503; uint32_t 664 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_504; uint32_t 665 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_505; uint32_t 666 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_506; uint32_t 667 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_507; uint32_t 668 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_508; uint32_t 669 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_509; uint32_t 670 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_510; uint32_t 671 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved_511; uint32_t 676 drivers/gpu/drm/amd/include/v9_structs.h uint32_t wptr_poll_mem; uint32_t 677 drivers/gpu/drm/amd/include/v9_structs.h uint32_t rptr_report_mem; uint32_t 678 drivers/gpu/drm/amd/include/v9_structs.h uint32_t dynamic_cu_mask; uint32_t 679 drivers/gpu/drm/amd/include/v9_structs.h uint32_t dynamic_rb_mask; uint32_t 685 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_ib_completion_status; uint32_t 686 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_constegnine_count; uint32_t 687 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_ibOffset_ib1; uint32_t 688 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_ibOffset_ib2; uint32_t 691 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_chainib_addrlo_ib1; uint32_t 692 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_chainib_addrlo_ib2; uint32_t 693 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_chainib_addrhi_ib1; uint32_t 694 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_chainib_addrhi_ib2; uint32_t 695 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_chainib_size_ib1; uint32_t 696 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ce_chainib_size_ib2; uint32_t 701 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ib_completion_status; uint32_t 702 drivers/gpu/drm/amd/include/v9_structs.h uint32_t de_constEngine_count; uint32_t 703 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ib_offset_ib1; uint32_t 704 drivers/gpu/drm/amd/include/v9_structs.h uint32_t ib_offset_ib2; uint32_t 707 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_addrlo_ib1; uint32_t 708 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_addrlo_ib2; uint32_t 709 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_addrhi_ib1; uint32_t 710 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_addrhi_ib2; uint32_t 711 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_size_ib1; uint32_t 712 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_size_ib2; uint32_t 715 drivers/gpu/drm/amd/include/v9_structs.h uint32_t preamble_begin_ib1; uint32_t 716 drivers/gpu/drm/amd/include/v9_structs.h uint32_t preamble_begin_ib2; uint32_t 717 drivers/gpu/drm/amd/include/v9_structs.h uint32_t preamble_end_ib1; uint32_t 718 drivers/gpu/drm/amd/include/v9_structs.h uint32_t preamble_end_ib2; uint32_t 721 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_pream_addrlo_ib1; uint32_t 722 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_pream_addrlo_ib2; uint32_t 723 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_pream_addrhi_ib1; uint32_t 724 drivers/gpu/drm/amd/include/v9_structs.h uint32_t chain_ib_pream_addrhi_ib2; uint32_t 727 drivers/gpu/drm/amd/include/v9_structs.h uint32_t draw_indirect_baseLo; uint32_t 728 drivers/gpu/drm/amd/include/v9_structs.h uint32_t draw_indirect_baseHi; uint32_t 729 drivers/gpu/drm/amd/include/v9_structs.h uint32_t disp_indirect_baseLo; uint32_t 730 drivers/gpu/drm/amd/include/v9_structs.h uint32_t disp_indirect_baseHi; uint32_t 731 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_backup_addrlo; uint32_t 732 drivers/gpu/drm/amd/include/v9_structs.h uint32_t gds_backup_addrhi; uint32_t 733 drivers/gpu/drm/amd/include/v9_structs.h uint32_t index_base_addrlo; uint32_t 734 drivers/gpu/drm/amd/include/v9_structs.h uint32_t index_base_addrhi; uint32_t 735 drivers/gpu/drm/amd/include/v9_structs.h uint32_t sample_cntl; uint32_t 741 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved1[54]; uint32_t 745 drivers/gpu/drm/amd/include/v9_structs.h uint32_t DeIbBaseAddrLo; uint32_t 746 drivers/gpu/drm/amd/include/v9_structs.h uint32_t DeIbBaseAddrHi; uint32_t 747 drivers/gpu/drm/amd/include/v9_structs.h uint32_t reserved2[931]; uint32_t 28 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_cntl; uint32_t 29 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_base; uint32_t 30 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_base_hi; uint32_t 31 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_rptr; uint32_t 32 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_wptr; uint32_t 33 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_wptr_poll_cntl; uint32_t 34 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; uint32_t 35 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; uint32_t 36 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_rptr_addr_hi; uint32_t 37 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_rb_rptr_addr_lo; uint32_t 38 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_ib_cntl; uint32_t 39 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_ib_rptr; uint32_t 40 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_ib_offset; uint32_t 41 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_ib_base_lo; uint32_t 42 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_ib_base_hi; uint32_t 43 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_ib_size; uint32_t 44 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_skip_cntl; uint32_t 45 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_context_status; uint32_t 46 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_doorbell; uint32_t 47 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_virtual_addr; uint32_t 48 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_ape1_cntl; uint32_t 49 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdmax_rlcx_doorbell_log; uint32_t 50 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_22; uint32_t 51 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_23; uint32_t 52 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_24; uint32_t 53 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_25; uint32_t 54 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_26; uint32_t 55 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_27; uint32_t 56 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_28; uint32_t 57 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_29; uint32_t 58 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_30; uint32_t 59 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_31; uint32_t 60 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_32; uint32_t 61 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_33; uint32_t 62 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_34; uint32_t 63 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_35; uint32_t 64 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_36; uint32_t 65 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_37; uint32_t 66 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_38; uint32_t 67 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_39; uint32_t 68 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_40; uint32_t 69 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_41; uint32_t 70 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_42; uint32_t 71 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_43; uint32_t 72 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_44; uint32_t 73 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_45; uint32_t 74 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_46; uint32_t 75 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_47; uint32_t 76 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_48; uint32_t 77 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_49; uint32_t 78 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_50; uint32_t 79 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_51; uint32_t 80 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_52; uint32_t 81 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_53; uint32_t 82 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_54; uint32_t 83 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_55; uint32_t 84 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_56; uint32_t 85 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_57; uint32_t 86 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_58; uint32_t 87 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_59; uint32_t 88 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_60; uint32_t 89 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_61; uint32_t 90 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_62; uint32_t 91 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_63; uint32_t 92 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_64; uint32_t 93 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_65; uint32_t 94 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_66; uint32_t 95 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_67; uint32_t 96 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_68; uint32_t 97 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_69; uint32_t 98 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_70; uint32_t 99 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_71; uint32_t 100 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_72; uint32_t 101 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_73; uint32_t 102 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_74; uint32_t 103 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_75; uint32_t 104 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_76; uint32_t 105 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_77; uint32_t 106 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_78; uint32_t 107 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_79; uint32_t 108 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_80; uint32_t 109 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_81; uint32_t 110 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_82; uint32_t 111 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_83; uint32_t 112 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_84; uint32_t 113 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_85; uint32_t 114 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_86; uint32_t 115 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_87; uint32_t 116 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_88; uint32_t 117 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_89; uint32_t 118 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_90; uint32_t 119 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_91; uint32_t 120 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_92; uint32_t 121 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_93; uint32_t 122 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_94; uint32_t 123 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_95; uint32_t 124 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_96; uint32_t 125 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_97; uint32_t 126 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_98; uint32_t 127 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_99; uint32_t 128 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_100; uint32_t 129 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_101; uint32_t 130 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_102; uint32_t 131 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_103; uint32_t 132 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_104; uint32_t 133 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_105; uint32_t 134 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_106; uint32_t 135 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_107; uint32_t 136 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_108; uint32_t 137 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_109; uint32_t 138 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_110; uint32_t 139 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_111; uint32_t 140 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_112; uint32_t 141 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_113; uint32_t 142 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_114; uint32_t 143 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_115; uint32_t 144 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_116; uint32_t 145 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_117; uint32_t 146 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_118; uint32_t 147 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_119; uint32_t 148 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_120; uint32_t 149 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_121; uint32_t 150 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_122; uint32_t 151 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_123; uint32_t 152 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_124; uint32_t 153 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_125; uint32_t 155 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdma_engine_id; uint32_t 156 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sdma_queue_id; uint32_t 160 drivers/gpu/drm/amd/include/vi_structs.h uint32_t header; uint32_t 161 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_dispatch_initiator; uint32_t 162 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_dim_x; uint32_t 163 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_dim_y; uint32_t 164 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_dim_z; uint32_t 165 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_start_x; uint32_t 166 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_start_y; uint32_t 167 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_start_z; uint32_t 168 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_num_thread_x; uint32_t 169 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_num_thread_y; uint32_t 170 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_num_thread_z; uint32_t 171 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_pipelinestat_enable; uint32_t 172 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_perfcount_enable; uint32_t 173 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_pgm_lo; uint32_t 174 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_pgm_hi; uint32_t 175 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_tba_lo; uint32_t 176 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_tba_hi; uint32_t 177 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_tma_lo; uint32_t 178 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_tma_hi; uint32_t 179 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_pgm_rsrc1; uint32_t 180 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_pgm_rsrc2; uint32_t 181 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_vmid; uint32_t 182 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_resource_limits; uint32_t 183 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_static_thread_mgmt_se0; uint32_t 184 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_static_thread_mgmt_se1; uint32_t 185 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_tmpring_size; uint32_t 186 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_static_thread_mgmt_se2; uint32_t 187 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_static_thread_mgmt_se3; uint32_t 188 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_restart_x; uint32_t 189 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_restart_y; uint32_t 190 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_restart_z; uint32_t 191 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_thread_trace_enable; uint32_t 192 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_misc_reserved; uint32_t 193 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_dispatch_id; uint32_t 194 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_threadgroup_id; uint32_t 195 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_relaunch; uint32_t 196 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_wave_restore_addr_lo; uint32_t 197 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_wave_restore_addr_hi; uint32_t 198 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_wave_restore_control; uint32_t 199 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved9; uint32_t 200 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved10; uint32_t 201 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved11; uint32_t 202 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved12; uint32_t 203 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved13; uint32_t 204 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved14; uint32_t 205 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved15; uint32_t 206 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved16; uint32_t 207 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved17; uint32_t 208 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved18; uint32_t 209 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved19; uint32_t 210 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved20; uint32_t 211 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved21; uint32_t 212 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved22; uint32_t 213 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved23; uint32_t 214 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved24; uint32_t 215 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved25; uint32_t 216 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved26; uint32_t 217 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved27; uint32_t 218 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved28; uint32_t 219 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved29; uint32_t 220 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved30; uint32_t 221 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved31; uint32_t 222 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved32; uint32_t 223 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved33; uint32_t 224 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved34; uint32_t 225 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_0; uint32_t 226 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_1; uint32_t 227 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_2; uint32_t 228 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_3; uint32_t 229 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_4; uint32_t 230 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_5; uint32_t 231 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_6; uint32_t 232 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_7; uint32_t 233 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_8; uint32_t 234 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_9; uint32_t 235 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_10; uint32_t 236 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_11; uint32_t 237 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_12; uint32_t 238 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_13; uint32_t 239 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_14; uint32_t 240 drivers/gpu/drm/amd/include/vi_structs.h uint32_t compute_user_data_15; uint32_t 241 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_compute_csinvoc_count_lo; uint32_t 242 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_compute_csinvoc_count_hi; uint32_t 243 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved35; uint32_t 244 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved36; uint32_t 245 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved37; uint32_t 246 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_query_time_lo; uint32_t 247 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_query_time_hi; uint32_t 248 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_connect_start_time_lo; uint32_t 249 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_connect_start_time_hi; uint32_t 250 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_connect_end_time_lo; uint32_t 251 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_connect_end_time_hi; uint32_t 252 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_connect_end_wf_count; uint32_t 253 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_connect_end_pq_rptr; uint32_t 254 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr; uint32_t 255 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_connect_end_ib_rptr; uint32_t 256 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved38; uint32_t 257 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved39; uint32_t 258 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_save_start_time_lo; uint32_t 259 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_save_start_time_hi; uint32_t 260 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_save_end_time_lo; uint32_t 261 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_save_end_time_hi; uint32_t 262 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_restore_start_time_lo; uint32_t 263 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_restore_start_time_hi; uint32_t 264 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_restore_end_time_lo; uint32_t 265 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_restore_end_time_hi; uint32_t 266 drivers/gpu/drm/amd/include/vi_structs.h uint32_t disable_queue; uint32_t 267 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved41; uint32_t 268 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_cs_ctxsw_cnt0; uint32_t 269 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_cs_ctxsw_cnt1; uint32_t 270 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_cs_ctxsw_cnt2; uint32_t 271 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_cs_ctxsw_cnt3; uint32_t 272 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved42; uint32_t 273 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved43; uint32_t 274 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_pq_exe_status_lo; uint32_t 275 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_pq_exe_status_hi; uint32_t 276 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_packet_id_lo; uint32_t 277 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_packet_id_hi; uint32_t 278 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_packet_exe_status_lo; uint32_t 279 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_packet_exe_status_hi; uint32_t 280 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_save_base_addr_lo; uint32_t 281 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_save_base_addr_hi; uint32_t 282 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_save_mask_lo; uint32_t 283 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_save_mask_hi; uint32_t 284 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ctx_save_base_addr_lo; uint32_t 285 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ctx_save_base_addr_hi; uint32_t 286 drivers/gpu/drm/amd/include/vi_structs.h uint32_t dynamic_cu_mask_addr_lo; uint32_t 287 drivers/gpu/drm/amd/include/vi_structs.h uint32_t dynamic_cu_mask_addr_hi; uint32_t 288 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_base_addr_lo; uint32_t 289 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_base_addr_hi; uint32_t 290 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_active; uint32_t 291 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_vmid; uint32_t 292 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_persistent_state; uint32_t 293 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pipe_priority; uint32_t 294 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_queue_priority; uint32_t 295 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_quantum; uint32_t 296 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_base_lo; uint32_t 297 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_base_hi; uint32_t 298 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_rptr; uint32_t 299 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_rptr_report_addr_lo; uint32_t 300 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_rptr_report_addr_hi; uint32_t 301 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_wptr_poll_addr_lo; uint32_t 302 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_wptr_poll_addr_hi; uint32_t 303 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_doorbell_control; uint32_t 304 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_wptr; uint32_t 305 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_control; uint32_t 306 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_ib_base_addr_lo; uint32_t 307 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_ib_base_addr_hi; uint32_t 308 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_ib_rptr; uint32_t 309 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_ib_control; uint32_t 310 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_iq_timer; uint32_t 311 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_iq_rptr; uint32_t 312 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_dequeue_request; uint32_t 313 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_dma_offload; uint32_t 314 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_sema_cmd; uint32_t 315 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_msg_type; uint32_t 316 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_atomic0_preop_lo; uint32_t 317 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_atomic0_preop_hi; uint32_t 318 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_atomic1_preop_lo; uint32_t 319 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_atomic1_preop_hi; uint32_t 320 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_hq_status0; uint32_t 321 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_hq_control0; uint32_t 322 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_mqd_control; uint32_t 323 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_hq_status1; uint32_t 324 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_hq_control1; uint32_t 325 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_eop_base_addr_lo; uint32_t 326 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_eop_base_addr_hi; uint32_t 327 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_eop_control; uint32_t 328 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_eop_rptr; uint32_t 329 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_eop_wptr; uint32_t 330 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_eop_done_events; uint32_t 331 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_ctx_save_base_addr_lo; uint32_t 332 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_ctx_save_base_addr_hi; uint32_t 333 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_ctx_save_control; uint32_t 334 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_cntl_stack_offset; uint32_t 335 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_cntl_stack_size; uint32_t 336 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_wg_state_offset; uint32_t 337 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_ctx_save_size; uint32_t 338 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_gds_resource_state; uint32_t 339 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_error; uint32_t 340 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_eop_wptr_mem; uint32_t 341 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_eop_dones; uint32_t 342 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved46; uint32_t 343 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved47; uint32_t 344 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved48; uint32_t 345 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved49; uint32_t 346 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved50; uint32_t 347 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved51; uint32_t 348 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved52; uint32_t 349 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved53; uint32_t 350 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved54; uint32_t 351 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved55; uint32_t 352 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_header; uint32_t 353 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw0; uint32_t 354 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw1; uint32_t 355 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw2; uint32_t 356 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw3; uint32_t 357 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw4; uint32_t 358 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw5; uint32_t 359 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw6; uint32_t 360 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw7; uint32_t 361 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw8; uint32_t 362 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw9; uint32_t 363 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw10; uint32_t 364 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw11; uint32_t 365 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw12; uint32_t 366 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw13; uint32_t 367 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw14; uint32_t 368 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw15; uint32_t 369 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw16; uint32_t 370 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw17; uint32_t 371 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw18; uint32_t 372 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw19; uint32_t 373 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw20; uint32_t 374 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw21; uint32_t 375 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw22; uint32_t 376 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw23; uint32_t 377 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw24; uint32_t 378 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw25; uint32_t 379 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw26; uint32_t 380 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw27; uint32_t 381 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw28; uint32_t 382 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw29; uint32_t 383 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw30; uint32_t 384 drivers/gpu/drm/amd/include/vi_structs.h uint32_t iqtimer_pkt_dw31; uint32_t 385 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved56; uint32_t 386 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved57; uint32_t 387 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved58; uint32_t 388 drivers/gpu/drm/amd/include/vi_structs.h uint32_t set_resources_header; uint32_t 389 drivers/gpu/drm/amd/include/vi_structs.h uint32_t set_resources_dw1; uint32_t 390 drivers/gpu/drm/amd/include/vi_structs.h uint32_t set_resources_dw2; uint32_t 391 drivers/gpu/drm/amd/include/vi_structs.h uint32_t set_resources_dw3; uint32_t 392 drivers/gpu/drm/amd/include/vi_structs.h uint32_t set_resources_dw4; uint32_t 393 drivers/gpu/drm/amd/include/vi_structs.h uint32_t set_resources_dw5; uint32_t 394 drivers/gpu/drm/amd/include/vi_structs.h uint32_t set_resources_dw6; uint32_t 395 drivers/gpu/drm/amd/include/vi_structs.h uint32_t set_resources_dw7; uint32_t 396 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved59; uint32_t 397 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved60; uint32_t 398 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved61; uint32_t 399 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved62; uint32_t 400 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved63; uint32_t 401 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved64; uint32_t 402 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved65; uint32_t 403 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved66; uint32_t 404 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved67; uint32_t 405 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved68; uint32_t 406 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved69; uint32_t 407 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved70; uint32_t 408 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved71; uint32_t 409 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved72; uint32_t 410 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved73; uint32_t 411 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved74; uint32_t 412 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved75; uint32_t 413 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved76; uint32_t 414 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved77; uint32_t 415 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved78; uint32_t 416 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved_t[256]; uint32_t 421 drivers/gpu/drm/amd/include/vi_structs.h uint32_t wptr_poll_mem; uint32_t 422 drivers/gpu/drm/amd/include/vi_structs.h uint32_t rptr_report_mem; uint32_t 423 drivers/gpu/drm/amd/include/vi_structs.h uint32_t dynamic_cu_mask; uint32_t 424 drivers/gpu/drm/amd/include/vi_structs.h uint32_t dynamic_rb_mask; uint32_t 428 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_ib_completion_status; uint32_t 429 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_constegnine_count; uint32_t 430 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_ibOffset_ib1; uint32_t 431 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_ibOffset_ib2; uint32_t 435 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ib_completion_status; uint32_t 436 drivers/gpu/drm/amd/include/vi_structs.h uint32_t de_constEngine_count; uint32_t 437 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ib_offset_ib1; uint32_t 438 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ib_offset_ib2; uint32_t 439 drivers/gpu/drm/amd/include/vi_structs.h uint32_t preamble_begin_ib1; uint32_t 440 drivers/gpu/drm/amd/include/vi_structs.h uint32_t preamble_begin_ib2; uint32_t 441 drivers/gpu/drm/amd/include/vi_structs.h uint32_t preamble_end_ib1; uint32_t 442 drivers/gpu/drm/amd/include/vi_structs.h uint32_t preamble_end_ib2; uint32_t 443 drivers/gpu/drm/amd/include/vi_structs.h uint32_t draw_indirect_baseLo; uint32_t 444 drivers/gpu/drm/amd/include/vi_structs.h uint32_t draw_indirect_baseHi; uint32_t 445 drivers/gpu/drm/amd/include/vi_structs.h uint32_t disp_indirect_baseLo; uint32_t 446 drivers/gpu/drm/amd/include/vi_structs.h uint32_t disp_indirect_baseHi; uint32_t 447 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_backup_addrlo; uint32_t 448 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_backup_addrhi; uint32_t 449 drivers/gpu/drm/amd/include/vi_structs.h uint32_t index_base_addrlo; uint32_t 450 drivers/gpu/drm/amd/include/vi_structs.h uint32_t index_base_addrhi; uint32_t 451 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sample_cntl; uint32_t 456 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_ib_completion_status; uint32_t 457 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_constegnine_count; uint32_t 458 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_ibOffset_ib1; uint32_t 459 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_ibOffset_ib2; uint32_t 462 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_chainib_addrlo_ib1; uint32_t 463 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_chainib_addrlo_ib2; uint32_t 464 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_chainib_addrhi_ib1; uint32_t 465 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_chainib_addrhi_ib2; uint32_t 466 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_chainib_size_ib1; uint32_t 467 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ce_chainib_size_ib2; uint32_t 472 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ib_completion_status; uint32_t 473 drivers/gpu/drm/amd/include/vi_structs.h uint32_t de_constEngine_count; uint32_t 474 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ib_offset_ib1; uint32_t 475 drivers/gpu/drm/amd/include/vi_structs.h uint32_t ib_offset_ib2; uint32_t 478 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_addrlo_ib1; uint32_t 479 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_addrlo_ib2; uint32_t 480 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_addrhi_ib1; uint32_t 481 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_addrhi_ib2; uint32_t 482 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_size_ib1; uint32_t 483 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_size_ib2; uint32_t 486 drivers/gpu/drm/amd/include/vi_structs.h uint32_t preamble_begin_ib1; uint32_t 487 drivers/gpu/drm/amd/include/vi_structs.h uint32_t preamble_begin_ib2; uint32_t 488 drivers/gpu/drm/amd/include/vi_structs.h uint32_t preamble_end_ib1; uint32_t 489 drivers/gpu/drm/amd/include/vi_structs.h uint32_t preamble_end_ib2; uint32_t 492 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_pream_addrlo_ib1; uint32_t 493 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_pream_addrlo_ib2; uint32_t 494 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_pream_addrhi_ib1; uint32_t 495 drivers/gpu/drm/amd/include/vi_structs.h uint32_t chain_ib_pream_addrhi_ib2; uint32_t 498 drivers/gpu/drm/amd/include/vi_structs.h uint32_t draw_indirect_baseLo; uint32_t 499 drivers/gpu/drm/amd/include/vi_structs.h uint32_t draw_indirect_baseHi; uint32_t 500 drivers/gpu/drm/amd/include/vi_structs.h uint32_t disp_indirect_baseLo; uint32_t 501 drivers/gpu/drm/amd/include/vi_structs.h uint32_t disp_indirect_baseHi; uint32_t 502 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_backup_addrlo; uint32_t 503 drivers/gpu/drm/amd/include/vi_structs.h uint32_t gds_backup_addrhi; uint32_t 504 drivers/gpu/drm/amd/include/vi_structs.h uint32_t index_base_addrlo; uint32_t 505 drivers/gpu/drm/amd/include/vi_structs.h uint32_t index_base_addrhi; uint32_t 506 drivers/gpu/drm/amd/include/vi_structs.h uint32_t sample_cntl; uint32_t 512 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved1[60]; uint32_t 516 drivers/gpu/drm/amd/include/vi_structs.h uint32_t DeIbBaseAddrLo; uint32_t 517 drivers/gpu/drm/amd/include/vi_structs.h uint32_t DeIbBaseAddrHi; uint32_t 518 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved2[941]; uint32_t 524 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved1[54]; uint32_t 528 drivers/gpu/drm/amd/include/vi_structs.h uint32_t DeIbBaseAddrLo; uint32_t 529 drivers/gpu/drm/amd/include/vi_structs.h uint32_t DeIbBaseAddrHi; uint32_t 530 drivers/gpu/drm/amd/include/vi_structs.h uint32_t reserved2[931]; uint32_t 295 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) uint32_t 313 drivers/gpu/drm/amd/powerplay/amd_powerplay.c uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | uint32_t 381 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static uint32_t pp_dpm_get_sclk(void *handle, bool low) uint32_t 384 drivers/gpu/drm/amd/powerplay/amd_powerplay.c uint32_t clk = 0; uint32_t 399 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static uint32_t pp_dpm_get_mclk(void *handle, bool low) uint32_t 402 drivers/gpu/drm/amd/powerplay/amd_powerplay.c uint32_t clk = 0; uint32_t 500 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) uint32_t 516 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static uint32_t pp_dpm_get_fan_control_mode(void *handle) uint32_t 519 drivers/gpu/drm/amd/powerplay/amd_powerplay.c uint32_t mode = 0; uint32_t 534 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) uint32_t 552 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) uint32_t 571 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) uint32_t 588 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm) uint32_t 714 drivers/gpu/drm/amd/powerplay/amd_powerplay.c enum pp_clock_type type, uint32_t mask) uint32_t 775 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_dpm_set_sclk_od(void *handle, uint32_t value) uint32_t 812 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_dpm_set_mclk_od(void *handle, uint32_t value) uint32_t 841 drivers/gpu/drm/amd/powerplay/amd_powerplay.c *((uint32_t *)value) = hwmgr->pstate_sclk; uint32_t 844 drivers/gpu/drm/amd/powerplay/amd_powerplay.c *((uint32_t *)value) = hwmgr->pstate_mclk; uint32_t 847 drivers/gpu/drm/amd/powerplay/amd_powerplay.c *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM; uint32_t 850 drivers/gpu/drm/amd/powerplay/amd_powerplay.c *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM; uint32_t 888 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size) uint32_t 912 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size) uint32_t 945 drivers/gpu/drm/amd/powerplay/amd_powerplay.c uint32_t index; uint32_t 979 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_set_power_limit(void *handle, uint32_t limit) uint32_t 982 drivers/gpu/drm/amd/powerplay/amd_powerplay.c uint32_t max_power_limit; uint32_t 1011 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit) uint32_t 1281 drivers/gpu/drm/amd/powerplay/amd_powerplay.c uint32_t block_type, bool gate) uint32_t 1348 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock) uint32_t 1367 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock) uint32_t 1386 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock) uint32_t 1405 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_set_active_display_count(void *handle, uint32_t count) uint32_t 64 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t feature_mask[2] = { 0 }; uint32_t 66 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t count = 0; uint32_t 67 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t sort_feature[SMU_FEATURE_COUNT]; uint32_t 101 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t feature_mask[2] = { 0 }; uint32_t 129 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version) uint32_t 160 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t min, uint32_t max) uint32_t 163 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t param; uint32_t 176 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c param = (uint32_t)((clk_id << 16) | (max & 0xffff)); uint32_t 184 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c param = (uint32_t)((clk_id << 16) | (min & 0xffff)); uint32_t 196 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t min, uint32_t max) uint32_t 199 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t param; uint32_t 212 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c param = (uint32_t)((clk_id << 16) | (max & 0xffff)); uint32_t 220 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c param = (uint32_t)((clk_id << 16) | (min & 0xffff)); uint32_t 232 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t *min, uint32_t *max) uint32_t 234 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t clock_limit; uint32_t 275 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint16_t level, uint32_t *value) uint32_t 278 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t param; uint32_t 290 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); uint32_t 309 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t *value) uint32_t 342 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, uint32_t 388 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c void *data, uint32_t *size) uint32_t 399 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c *((uint32_t *)data) = smu->pstate_sclk; uint32_t 403 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c *((uint32_t *)data) = smu->pstate_mclk; uint32_t 407 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); uint32_t 411 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; uint32_t 415 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; uint32_t 419 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1; uint32_t 551 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; uint32_t 574 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t feature_low = 0, feature_high = 0; uint32_t 761 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, uint32_t 923 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t table_count = smu_table->table_count; uint32_t 924 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t i = 0; uint32_t 961 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t table_count = smu_table->table_count; uint32_t 962 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t i = 0; uint32_t 981 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg; uint32_t 1529 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | uint32_t 1572 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t sclk_mask, mclk_mask, soc_mask; uint32_t 1699 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c uint32_t index; uint32_t 1762 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_set_display_count(struct smu_context *smu, uint32_t count) uint32_t 190 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index) uint32_t 204 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index) uint32_t 220 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index) uint32_t 235 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index) uint32_t 251 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index) uint32_t 342 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *feature_mask, uint32_t num) uint32_t 348 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c memset(feature_mask, 0xFF, sizeof(uint32_t) * num); uint32_t 359 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t i, num_of_levels = 0, clk; uint32_t 695 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t feature_mask) uint32_t 700 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t freq; uint32_t 752 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c enum smu_clk_type type, uint32_t mask) uint32_t 756 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t soft_min_level, soft_max_level; uint32_t 934 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *value) uint32_t 961 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value) uint32_t 980 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *value) uint32_t 1015 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c void *data, uint32_t *size) uint32_t 1027 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c *(uint32_t *)data = pptable->FanMaximumRpm; uint32_t 1034 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c (uint32_t *)data); uint32_t 1038 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c ret = arcturus_get_gpu_power(smu, (uint32_t *)data); uint32_t 1045 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c (uint32_t *)data); uint32_t 1057 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *speed) uint32_t 1075 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *speed) uint32_t 1078 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t percent, current_rpm; uint32_t 1096 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *value) uint32_t 1145 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table) uint32_t 1147 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t i; uint32_t 1161 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table) uint32_t 1192 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t soft_level; uint32_t 1246 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t soft_min_level, soft_max_level; uint32_t 1291 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *sclk_mask, uint32_t 1292 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *mclk_mask, uint32_t 1293 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *soc_mask) uint32_t 1334 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t *limit, uint32_t 1338 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t asic_default_power_limit = 0; uint32_t 1396 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t i, size = 0; uint32_t 1423 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t size) uint32_t 1426 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t profile_mode = input[size]; uint32_t 1894 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c uint32_t feature_mask[2]; uint32_t 35 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h uint32_t value; uint32_t 36 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h uint32_t param1; uint32_t 40 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h uint32_t soft_min_level; uint32_t 41 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h uint32_t soft_max_level; uint32_t 42 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h uint32_t hard_min_level; uint32_t 43 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h uint32_t hard_max_level; uint32_t 47 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h uint32_t count; uint32_t 56 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h uint32_t lclk[MAX_PCIE_CONF]; uint32_t 38 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t hwip; uint32_t 39 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t inst; uint32_t 40 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t seg; uint32_t 41 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t reg_offset; uint32_t 42 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t mask; uint32_t 43 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t shift; uint32_t 44 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t timeout; uint32_t 45 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t val; uint32_t 346 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c PHM_PerformanceLevelDesignation designation, uint32_t index, uint32_t 491 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count) uint32_t 501 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) uint32_t 511 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) uint32_t 521 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) uint32_t 32 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t clk; uint32_t 44 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t sclk_offset; uint32_t 50 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t count; /* Number of entries. */ uint32_t 59 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t dclk; /* UVD D-clock */ uint32_t 60 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t vclk; /* UVD V-clock */ uint32_t 61 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t eclk; /* VCE clock */ uint32_t 62 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t aclk; /* ACP clock */ uint32_t 63 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t samclock; /* SAMU clock */ uint32_t 73 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t count; /* Number of entries. */ uint32_t 88 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t count; uint32_t 100 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t pcie_sclk; uint32_t 105 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t count; /* Number of entries. */ uint32_t 1269 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c uint32_t i; uint32_t 32 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h uint32_t VFT2_m1; uint32_t 33 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h uint32_t VFT2_m2; uint32_t 34 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h uint32_t VFT2_b; uint32_t 35 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h uint32_t VFT1_m1; uint32_t 36 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h uint32_t VFT1_m2; uint32_t 37 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h uint32_t VFT1_b; uint32_t 38 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h uint32_t VFT0_m1; uint32_t 39 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h uint32_t VFT0_m2; uint32_t 40 drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h uint32_t VFT0_b; uint32_t 262 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c uint32_t index; uint32_t 52 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t i, j; uint32_t 59 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK && uint32_t 61 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT); uint32_t 65 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK) >> uint32_t 72 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)*((uint32_t *)reg_data + j); uint32_t 87 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK), uint32_t 174 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t engine_clock, uint32_t 175 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t memory_clock) uint32_t 192 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&engine_clock_parameters); uint32_t 249 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock_value, uint32_t 262 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&mpll_parameters); uint32_t 270 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)mpll_parameters.ucPostDiv; uint32_t 272 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)(mpll_parameters.ucPllCntlFlag & uint32_t 275 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)((mpll_parameters.ucPllCntlFlag & uint32_t 278 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)((mpll_parameters.ucPllCntlFlag & uint32_t 281 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)((mpll_parameters.ucPllCntlFlag & uint32_t 284 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)(mpll_parameters.ucDllSpeed); uint32_t 286 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)(mpll_parameters.ucBWCntl); uint32_t 299 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param) uint32_t 309 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&mpll_parameters); uint32_t 313 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t)mpll_parameters.ulClock.ucPostDiv; uint32_t 319 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock_value, uint32_t 330 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&mpll_parameters); uint32_t 349 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock_value, uint32_t 360 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&pll_parameters); uint32_t 372 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock_value, uint32_t 384 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&pll_patameters); uint32_t 409 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock_value, uint32_t 421 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&pll_patameters); uint32_t 441 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock_value, uint32_t 454 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&pll_patameters); uint32_t 481 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr) uint32_t 486 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock; uint32_t 496 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c clock = (uint32_t)(le16_to_cpu(fw_info->usReferenceClock)); uint32_t 571 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c const uint32_t pinId, uint32_t 624 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c const uint32_t pinId, uint32_t 643 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t sclk, uint32_t 660 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t ul_RO_fused, ul_CACb_fused, ul_CACm_fused, ul_Kt_Beta_fused, ul_Kv_m_fused, ul_Kv_b_fused; uint32_t 669 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t ul_FT_Lkg_V0NORM; uint32_t 745 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&sOutput_FuseValues); uint32_t 766 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&sOutput_FuseValues); uint32_t 786 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&sOutput_FuseValues); uint32_t 807 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&sOutput_FuseValues); uint32_t 829 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&sOutput_FuseValues); uint32_t 850 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&sOutput_FuseValues); uint32_t 881 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&sOutput_FuseValues); uint32_t 1087 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t 1105 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&get_voltage_info_param_space); uint32_t 1150 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&get_voltage_info_param_space); uint32_t 1164 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr) uint32_t 1167 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t clock; uint32_t 1183 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c clock = (uint32_t)(le16_to_cpu(fwInfo_2_1->usMemoryReferenceClock)); uint32_t 1187 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c clock = (uint32_t)(le16_to_cpu(fwInfo_0_0->usReferenceClock)); uint32_t 1216 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c const uint32_t clockSpeed, uint32_t 1235 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c ((uint32_t)clockSpeed <= le32_to_cpu(ssInfo->ulTargetClockRange))) { uint32_t 1279 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c const uint32_t memory_clock, uint32_t 1290 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c const uint32_t engine_clock, uint32_t 1298 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint16_t end_index, uint32_t mask, uint32_t *efuse) uint32_t 1312 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&efuse_param); uint32_t 1318 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, uint32_t 1333 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&memory_clock_parameters); uint32_t 1339 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage) uint32_t 1352 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)&get_voltage_info_param_space); uint32_t 1465 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c (uint32_t *)voltage_parameters); uint32_t 1534 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc, uint32_t 1535 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t *min_vddc) uint32_t 48 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t pll_post_divider; uint32_t 49 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t pll_feedback_divider; uint32_t 50 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t pll_ref_divider; uint32_t 58 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ul_fb_div_frac : 14; uint32_t 59 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ul_fb_div : 12; uint32_t 60 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t un_used : 6; uint32_t 62 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ul_fb_divider; uint32_t 68 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t pll_post_divider; uint32_t 70 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t pll_ref_divider; uint32_t 73 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t vco_mode; uint32_t 79 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t pll_post_divider; uint32_t 80 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t real_clock; uint32_t 85 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t pll_post_divider; /* post divider value */ uint32_t 86 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t real_clock; uint32_t 95 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t pll_post_divider; /* post divider value */ uint32_t 96 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t real_clock; uint32_t 123 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t cl_kf : 12; uint32_t 124 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t clk_frac : 12; uint32_t 125 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t un_used : 8; uint32_t 127 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ul_fb_divider; uint32_t 139 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t mpll_post_divider; uint32_t 140 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t bw_ctrl; uint32_t 141 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t dll_speed; uint32_t 142 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t vco_mode; uint32_t 143 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t yclk_sel; uint32_t 144 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t qdr; uint32_t 145 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t half_rate; uint32_t 150 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulClock; uint32_t 151 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulPostDiv; uint32_t 158 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t speed_spectrum_percentage; /* in 1/100 percentage */ uint32_t 159 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t speed_spectrum_rate; /* in KHz */ uint32_t 173 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ul_bootup_uma_clock; /* in 10kHz unit */ uint32_t 180 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */ uint32_t 196 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t mclk[MAX_AC_TIMING_ENTRIES]; uint32_t 202 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t smio_low; uint32_t 208 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t count; uint32_t 209 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t mask_low; uint32_t 210 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t phase_delay; /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */ uint32_t 220 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t mclk_max; uint32_t 221 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; uint32_t 262 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulAVFS_meanNsigma_Acontant0; uint32_t 263 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulAVFS_meanNsigma_Acontant1; uint32_t 264 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulAVFS_meanNsigma_Acontant2; uint32_t 268 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0; uint32_t 269 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1; uint32_t 270 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2; uint32_t 271 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulGB_VDROOP_TABLE_CKSON_a0; uint32_t 272 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulGB_VDROOP_TABLE_CKSON_a1; uint32_t 273 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulGB_VDROOP_TABLE_CKSON_a2; uint32_t 274 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1; uint32_t 276 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b; uint32_t 277 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1; uint32_t 279 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b; uint32_t 290 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment); uint32_t 291 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); uint32_t 293 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr); uint32_t 294 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo); uint32_t 295 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo); uint32_t 297 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock); uint32_t 298 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr); uint32_t 299 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode); uint32_t 300 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); uint32_t 301 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); uint32_t 305 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param); uint32_t 307 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param); uint32_t 309 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t clock_value, uint32_t 312 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint16_t end_index, uint32_t mask, uint32_t *efuse); uint32_t 314 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug); uint32_t 315 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers); uint32_t 316 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, uint32_t 319 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage); uint32_t 334 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc, uint32_t 335 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t *min_vddc); uint32_t 180 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c const uint32_t pin_id, uint32_t 209 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c const uint32_t pin_id, uint32_t 247 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c uint32_t clock_type, uint32_t clock_value, uint32_t 253 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c uint32_t idx; uint32_t 255 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c pll_parameters.gpuclock_10khz = (uint32_t)clock_value; uint32_t 261 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c adev->mode_info.atom_context, idx, (uint32_t *)&pll_parameters)) uint32_t 493 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c uint32_t *frequency) uint32_t 498 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c uint32_t ix; uint32_t 508 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c adev->mode_info.atom_context, ix, (uint32_t *)¶meters)) uint32_t 521 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c uint32_t frequency = 0; uint32_t 557 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c uint32_t frequency = 0; uint32_t 40 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t smio_low; uint32_t 44 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t count; uint32_t 45 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t mask_low; uint32_t 46 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t phase_delay; uint32_t 61 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulClock; /* the actual clock */ uint32_t 62 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulDid; /* DFS divider */ uint32_t 63 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */ uint32_t 64 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */ uint32_t 68 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulReserve[2]; uint32_t 72 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulMaxVddc; uint32_t 73 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulMinVddc; uint32_t 75 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulMeanNsigmaAcontant0; uint32_t 76 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulMeanNsigmaAcontant1; uint32_t 77 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulMeanNsigmaAcontant2; uint32_t 81 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbVdroopTableCksoffA0; uint32_t 82 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbVdroopTableCksoffA1; uint32_t 83 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbVdroopTableCksoffA2; uint32_t 84 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbVdroopTableCksonA0; uint32_t 85 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbVdroopTableCksonA1; uint32_t 86 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbVdroopTableCksonA2; uint32_t 88 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbFuseTableCksoffM1; uint32_t 89 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbFuseTableCksoffM2; uint32_t 90 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbFuseTableCksoffB; uint32_t 92 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbFuseTableCksonM1; uint32_t 93 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbFuseTableCksonM2; uint32_t 94 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGbFuseTableCksonB; uint32_t 100 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulDispclk2GfxclkM1; uint32_t 101 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulDispclk2GfxclkM2; uint32_t 102 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulDispclk2GfxclkB; uint32_t 103 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulDcefclk2GfxclkM1; uint32_t 104 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulDcefclk2GfxclkM2; uint32_t 105 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulDcefclk2GfxclkB; uint32_t 106 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulPixelclk2GfxclkM1; uint32_t 107 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulPixelclk2GfxclkM2; uint32_t 108 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulPixelclk2GfxclkB; uint32_t 109 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulPhyclk2GfxclkM1; uint32_t 110 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulPhyclk2GfxclkM2; uint32_t 111 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulPhyclk2GfxclkB; uint32_t 112 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulAcgGbVdroopTableA0; uint32_t 113 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulAcgGbVdroopTableA1; uint32_t 114 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulAcgGbVdroopTableA2; uint32_t 115 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulAcgGbFuseTableM1; uint32_t 116 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulAcgGbFuseTableM2; uint32_t 117 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulAcgGbFuseTableB; uint32_t 118 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ucAcgEnableGbVdroopTable; uint32_t 119 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ucAcgEnableGbFuseTable; uint32_t 134 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulRevision; uint32_t 135 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulGfxClk; uint32_t 136 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulUClk; uint32_t 137 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulSocClk; uint32_t 138 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulDCEFClk; uint32_t 139 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulEClk; uint32_t 140 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulVClk; uint32_t 141 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulDClk; uint32_t 142 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t ulFClk; uint32_t 219 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t clock_type, uint32_t clock_value, uint32_t 222 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id, uint32_t 241 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h uint32_t *frequency); uint32_t 54 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static fInt Convert_ULONG_ToFraction(uint32_t); /* Use this to convert an uint32_t to a FINT */ uint32_t 79 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static fInt fDecodeLinearFuse(uint32_t fuse_value, fInt f_min, fInt f_range, uint32_t bitlength); uint32_t 80 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static fInt fDecodeLogisticFuse(uint32_t fuse_value, fInt f_average, fInt f_range, uint32_t bitlength); uint32_t 81 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static fInt fDecodeLeakageID (uint32_t leakageID_fuse, fInt ln_max_div_min, fInt f_min, uint32_t bitlength); uint32_t 110 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h uint32_t i; uint32_t 120 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static const uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78}; uint32_t 121 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static const uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078}; uint32_t 149 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h uint32_t i; uint32_t 155 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static const uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078}; uint32_t 156 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static const uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78}; uint32_t 172 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static fInt fDecodeLinearFuse(uint32_t fuse_value, fInt f_min, fInt f_range, uint32_t bitlength) uint32_t 187 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static fInt fDecodeLogisticFuse(uint32_t fuse_value, fInt f_average, fInt f_range, uint32_t bitlength) uint32_t 205 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static fInt fDecodeLeakageID (uint32_t leakageID_fuse, fInt ln_max_div_min, fInt f_min, uint32_t bitlength) uint32_t 236 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static fInt Convert_ULONG_ToFraction(uint32_t X) uint32_t 56 drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c uint8_t encode_pcie_lane_width(uint32_t num_lanes) uint32_t 61 drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c uint8_t decode_pcie_lane_width(uint32_t num_lanes) uint32_t 27 drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h extern uint8_t encode_pcie_lane_width(uint32_t num_lanes); uint32_t 28 drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h extern uint8_t decode_pcie_lane_width(uint32_t num_lanes); uint32_t 55 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) uint32_t 157 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t max_levels uint32_t 160 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t table_size, i; uint32_t 168 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table_size = sizeof(uint32_t) + uint32_t 254 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t disable_ppm = 0; uint32_t 255 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t disable_power_control = 0; uint32_t 321 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t table_size, i; uint32_t 328 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table_size = sizeof(uint32_t) + uint32_t 329 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c sizeof(uint32_t) * clk_volt_pp_table->count; uint32_t 336 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table->count = (uint32_t)clk_volt_pp_table->count; uint32_t 342 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table->values[i] = (uint32_t)dep_record->clk; uint32_t 373 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t table_size, i; uint32_t 381 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record) uint32_t 389 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; uint32_t 416 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t table_size, i; uint32_t 428 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record) uint32_t 436 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c sclk_table->count = (uint32_t)tonga_table->ucNumEntries; uint32_t 460 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record) uint32_t 468 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c sclk_table->count = (uint32_t)polaris_table->ucNumEntries; uint32_t 497 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t table_size, i, pcie_count; uint32_t 510 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table_size = sizeof(uint32_t) + uint32_t 523 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) uint32_t 524 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; uint32_t 549 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table_size = sizeof(uint32_t) + uint32_t 562 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) uint32_t 563 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; uint32_t 593 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t table_size; uint32_t 596 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table_size = sizeof(uint32_t) + sizeof(struct phm_cac_tdp_table); uint32_t 693 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t table_size, i; uint32_t 700 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c table_size = sizeof(uint32_t) + uint32_t 735 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t table_size; uint32_t 1175 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c return (uint32_t)(state_arrays->ucNumEntries); uint32_t 1181 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, uint32_t 1184 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t result = 0; uint32_t 1225 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i, uint32_t 1226 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c struct amd_vce_state *vce_state, void **clock_info, uint32_t *flag) uint32_t 1287 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t entry_index, struct pp_power_state *power_state, uint32_t 1289 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c struct pp_power_state *, void *, uint32_t)) uint32_t 1296 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c uint32_t flags = 0; uint32_t 30 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.h extern int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t entry_index, uint32_t 32 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.h struct pp_power_state *, void *, uint32_t)); uint32_t 852 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c uint32_t *vol_rep_time, uint32_t *bb_rep_time) uint32_t 859 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c *vol_rep_time = (uint32_t)le16_to_cpu(powerplay_tab->usVoltageTime); uint32_t 860 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c *bb_rep_time = (uint32_t)le16_to_cpu(powerplay_tab->usBackbiasTime); uint32_t 1610 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c vce_state->evclk = ((uint32_t)vce_clock_info->ucEVClkHigh << 16) | le16_to_cpu(vce_clock_info->usEVClkLow); uint32_t 1611 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c vce_state->ecclk = ((uint32_t)vce_clock_info->ucECClkHigh << 16) | le16_to_cpu(vce_clock_info->usECClkLow); uint32_t 48 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h uint32_t *vol_rep_time, uint32_t *bb_rep_time); uint32_t 61 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; uint32_t 208 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) uint32_t 222 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) uint32_t 236 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) uint32_t 250 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count) uint32_t 311 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t reg; uint32_t 411 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t num_entry, const DpmClock_t *pclk_dependency_table) uint32_t 413 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t table_size, i; uint32_t 416 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c table_size = sizeof(uint32_t) + sizeof(struct smu10_voltage_dependency_table) * num_entry; uint32_t 438 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t result; uint32_t 571 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; uint32_t 572 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; uint32_t 710 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 726 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 808 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, uint32_t 831 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c enum pp_clock_type type, uint32_t mask) uint32_t 836 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t low, high; uint32_t 887 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t i, now, size = 0; uint32_t 931 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c PHM_PerformanceLevelDesignation designation, uint32_t index, uint32_t 974 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t 975 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t clock) uint32_t 990 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t i; uint32_t 1047 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t i; uint32_t 1104 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); uint32_t 1120 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t sclk, mclk; uint32_t 1128 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c *((uint32_t *)value) = sclk * 100; uint32_t 1135 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c *((uint32_t *)value) = mclk * 100; uint32_t 1139 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr); uint32_t 1142 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1; uint32_t 1237 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t i, size = 0; uint32_t 1286 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) uint32_t 69 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t soft_min_clk; uint32_t 70 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t hard_min_clk; uint32_t 71 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t soft_max_clk; uint32_t 72 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t hard_max_clk; uint32_t 76 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t engine_clock; uint32_t 97 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t vclk; uint32_t 98 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t dclk; uint32_t 99 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t vclk_low_divider; uint32_t 100 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t vclk_high_divider; uint32_t 101 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t dclk_low_divider; uint32_t 102 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t dclk_high_divider; uint32_t 108 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t entry : 1; uint32_t 109 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t display : 1; uint32_t 110 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t driver: 1; uint32_t 111 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t vce : 1; uint32_t 112 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t uvd : 1; uint32_t 113 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t acp : 1; uint32_t 114 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t reserved: 26; uint32_t 116 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t u32All; uint32_t 129 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t level; uint32_t 131 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t evclk; uint32_t 132 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t ecclk; uint32_t 133 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t samclk; uint32_t 134 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t acpclk; uint32_t 137 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t nbps_flags; uint32_t 138 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t bapm_flags; uint32_t 178 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t frequency; uint32_t 179 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t latency; uint32_t 183 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t count; uint32_t 188 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t clk; uint32_t 189 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t vol; uint32_t 194 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t count; uint32_t 209 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t disable_driver_thermal_policy; uint32_t 210 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t thermal_auto_throttling_treshold; uint32_t 214 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t ddi_power_gating_disabled; uint32_t 217 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t dce_slow_sclk_threshold; uint32_t 221 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t bapm_enabled; uint32_t 226 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t is_nb_dpm_enabled; uint32_t 227 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t is_voltage_island_enabled; uint32_t 228 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t disable_smu_acp_s3_handshake; uint32_t 229 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t disable_notify_smu_vpu_recovery; uint32_t 235 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t power_containment_features; uint32_t 243 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t sram_end; uint32_t 244 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t dpm_table_start; uint32_t 245 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t soft_regs_start; uint32_t 254 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t fps_high_threshold; uint32_t 255 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t fps_low_threshold; uint32_t 257 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t dpm_flags; uint32_t 264 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t max_sclk_level; uint32_t 265 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t num_of_clk_entries; uint32_t 268 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t separation_time; uint32_t 273 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t ulTotalActiveCUs; uint32_t 277 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t isp_actual_hard_min_freq; uint32_t 278 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t soc_actual_hard_min_freq; uint32_t 279 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t dcf_actual_hard_min_freq; uint32_t 281 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t f_actual_hard_min_freq; uint32_t 282 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t fabric_actual_soft_min_freq; uint32_t 283 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t vclk_soft_min; uint32_t 284 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t dclk_soft_min; uint32_t 285 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t gfx_actual_soft_min_freq; uint32_t 286 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t gfx_min_freq_limit; uint32_t 287 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t gfx_max_freq_limit; uint32_t 298 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t active_process_mask; uint32_t 300 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t deep_sleep_dcefclk; uint32_t 301 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t num_active_display; uint32_t 165 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c const uint32_t *msg_id) uint32_t 168 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c uint32_t value; uint32_t 35 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h const uint32_t *msg_id); uint32_t 110 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c enum pp_clock_type type, uint32_t mask); uint32_t 149 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t speedCntl = 0; uint32_t 160 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t link_width; uint32_t 225 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 256 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t tmp; uint32_t 387 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t display_gap = uint32_t 448 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t arb_src, uint32_t arb_dest) uint32_t 450 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t mc_arb_dram_timing; uint32_t 451 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t mc_arb_dram_timing2; uint32_t 452 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t burst_time; uint32_t 453 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t mc_cg_config; uint32_t 513 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t tmp; uint32_t 534 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i, max_entry; uint32_t 535 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t tmp; uint32_t 677 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 759 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 825 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 870 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t min_vddc = 0; uint32_t 871 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t max_vddc = 0; uint32_t 898 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 1051 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t soft_register_value = 0; uint32_t 1052 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t handshake_disables_offset = data->soft_regs_start uint32_t 1067 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t soft_register_value = 0; uint32_t 1068 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t handshake_disables_offset = data->soft_regs_start uint32_t 1244 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) uint32_t 1700 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk = 0; uint32_t 1793 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t index; uint32_t 1821 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 1892 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 1996 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t table_size, i, j; uint32_t 2117 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 2118 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t hw_revision, sub_vendor_id, sub_sys_id; uint32_t 2151 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t temp_reg; uint32_t 2243 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t *voltage, struct smu7_leakage_voltage *leakage_table) uint32_t 2245 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t index; uint32_t 2364 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t vddc, vddci; uint32_t 2383 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 2384 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t vddc; uint32_t 2389 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c vddc = (uint32_t)(tab->entries[i].Vddc); uint32_t 2602 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t level, tmp; uint32_t 2692 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t level; uint32_t 2728 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) uint32_t 2730 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t percentage; uint32_t 2806 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk_mask = 0; uint32_t 2807 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t mclk_mask = 0; uint32_t 2808 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t pcie_mask = 0; uint32_t 2855 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t vblank_time_us) uint32_t 2858 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t switch_limit_us; uint32_t 2890 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk; uint32_t 2891 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t mclk; uint32_t 2896 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 3014 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 3036 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 3120 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c void *pp_table, uint32_t classification_flag) uint32_t 3260 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 3326 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t engine_clock, memory_clock; uint32_t 3408 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 3528 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk, mclk, activity_percent; uint32_t 3529 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t offset, val_vid; uint32_t 3540 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *((uint32_t *)value) = sclk; uint32_t 3546 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *((uint32_t *)value) = mclk; uint32_t 3560 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; uint32_t 3564 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr); uint32_t 3568 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; uint32_t 3572 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; uint32_t 3576 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c return smu7_get_gpu_power(hwmgr, (uint32_t *)value); uint32_t 3585 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid); uint32_t 3600 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk = smu7_ps->performance_levels uint32_t 3603 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t mclk = smu7_ps->performance_levels uint32_t 3606 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 3649 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 3650 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk, max_sclk = 0; uint32_t 3760 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t count; uint32_t 3804 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t low_limit, uint32_t high_limit) uint32_t 3806 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 3827 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t high_limit_count; uint32_t 4067 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); uint32_t 4068 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t display_gap2; uint32_t 4069 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t pre_vbi_time_in_us; uint32_t 4070 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t frame_time_in_us; uint32_t 4071 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t ref_clock, refresh_rate; uint32_t 4238 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t vbios_version; uint32_t 4239 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t tmp; uint32_t 4400 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c enum pp_clock_type type, uint32_t mask) uint32_t 4422 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; uint32_t 4452 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t clock, pcie_speed; uint32_t 4541 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) uint32_t 4561 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) uint32_t 4582 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) uint32_t 4624 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) uint32_t 4676 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk) uint32_t 4733 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t virtual_addr_low, uint32_t 4734 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t virtual_addr_hi, uint32_t 4735 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t mc_addr_low, uint32_t 4736 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t mc_addr_hi, uint32_t 4737 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t size) uint32_t 4813 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t clk, uint32_t 4814 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t voltage) uint32_t 4850 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c long *input, uint32_t size) uint32_t 4852 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 4857 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t input_clk; uint32_t 4858 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t input_vol; uint32_t 4859 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t input_level; uint32_t 4918 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i, size = 0; uint32_t 4919 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t len; uint32_t 4985 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t tmp, level; uint32_t 5001 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) uint32_t 5073 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PHM_PerformanceLevelDesignation designation, uint32_t index, uint32_t 5078 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t i; uint32_t 5167 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, uint32_t 5168 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t clock_insr) uint32_t 5171 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t temp; uint32_t 5172 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK); uint32_t 47 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t offset; uint32_t 48 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mask; uint32_t 49 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t shift; uint32_t 50 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t value; uint32_t 55 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t memory_clock; uint32_t 56 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t engine_clock; uint32_t 68 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vclk; uint32_t 69 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t dclk; uint32_t 73 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t evclk; uint32_t 74 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t ecclk; uint32_t 78 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t magic; uint32_t 81 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t sam_clk; uint32_t 84 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t sclk_threshold; uint32_t 90 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t value; uint32_t 91 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t param1; uint32_t 99 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t count; uint32_t 113 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vCG_SPLL_FUNC_CNTL; uint32_t 114 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vCG_SPLL_FUNC_CNTL_2; uint32_t 115 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vCG_SPLL_FUNC_CNTL_3; uint32_t 116 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vCG_SPLL_FUNC_CNTL_4; uint32_t 117 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vCG_SPLL_SPREAD_SPECTRUM; uint32_t 118 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 119 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vDLL_CNTL; uint32_t 120 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vMCLK_PWRMGT_CNTL; uint32_t 121 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vMPLL_AD_FUNC_CNTL; uint32_t 122 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vMPLL_DQ_FUNC_CNTL; uint32_t 123 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vMPLL_FUNC_CNTL; uint32_t 124 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vMPLL_FUNC_CNTL_1; uint32_t 125 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vMPLL_FUNC_CNTL_2; uint32_t 126 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vMPLL_SS1; uint32_t 127 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vMPLL_SS2; uint32_t 134 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vS0_VID_LOWER_SMIO_CNTL; uint32_t 150 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t sclk_bootup_value; uint32_t 151 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mclk_bootup_value; uint32_t 157 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t min_clock_in_sr; uint32_t 158 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t num_existing_displays; uint32_t 159 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vrefresh; uint32_t 163 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t uvd_dpm_enable_mask; uint32_t 164 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vce_dpm_enable_mask; uint32_t 165 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t acp_dpm_enable_mask; uint32_t 166 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t samu_dpm_enable_mask; uint32_t 167 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t sclk_dpm_enable_mask; uint32_t 168 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mclk_dpm_enable_mask; uint32_t 169 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t pcie_dpm_enable_mask; uint32_t 178 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t count; uint32_t 187 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t odn_mclk_min_limit; uint32_t 188 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t min_vddc; uint32_t 189 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t max_vddc; uint32_t 208 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t voting_rights_clients[8]; uint32_t 209 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t static_screen_threshold_unit; uint32_t 210 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t static_screen_threshold; uint32_t 211 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t voltage_control; uint32_t 212 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vdd_gfx_control; uint32_t 213 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vddc_vddgfx_delta; uint32_t 214 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t active_auto_throttle_sources; uint32_t 223 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t pcie_gen_cap; uint32_t 224 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t pcie_lane_cap; uint32_t 225 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t pcie_spc_cap; uint32_t 230 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mvdd_control; uint32_t 231 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vddc_mask_low; uint32_t 232 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mvdd_mask_low; uint32_t 247 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t soft_regs_start; uint32_t 249 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vddci_control; uint32_t 255 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mgcg_cgtt_local2; uint32_t 256 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mgcg_cgtt_local3; uint32_t 257 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t gpio_debug; uint32_t 258 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mc_micro_code_feature; uint32_t 259 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t highest_mclk; uint32_t 270 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t cac_table_start; uint32_t 276 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t power_containment_features; uint32_t 283 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t dte_tj_offset; uint32_t 284 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t fast_watermark_threshold; uint32_t 295 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t need_update_smu7_dpm_table; uint32_t 296 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t sclk_dpm_key_disabled; uint32_t 297 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mclk_dpm_key_disabled; uint32_t 298 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t pcie_dpm_key_disabled; uint32_t 299 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t min_engine_clocks; uint32_t 306 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mclk_dpm0_activity_target; uint32_t 307 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t low_sclk_interrupt_threshold; uint32_t 308 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t last_mclk_dpm_enable_mask; uint32_t 319 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t down_hyst; uint32_t 320 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t up_hyst; uint32_t 321 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t disable_dpm_mask; uint32_t 324 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t avfs_vdroop_override_setting; uint32_t 326 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t frame_time_x2; uint32_t 329 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vr_config; uint32_t 365 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, uint32_t 366 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t clock_insr); uint32_t 32 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c static uint32_t DIDTBlock_Info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; uint32_t 34 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c static uint32_t Polaris11_DIDTBlock_Info = SQ_PCC_MASK | TCP_IR_MASK | TD_PCC_MASK; uint32_t 855 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c uint32_t en = enable ? 1 : 0; uint32_t 856 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c uint32_t block_en = 0; uint32_t 858 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c uint32_t didt_block; uint32_t 899 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c uint32_t cache = 0; uint32_t 900 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c uint32_t data = 0; uint32_t 959 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c uint32_t num_se = 0; uint32_t 960 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c uint32_t count, value, value2; uint32_t 1091 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) uint32_t 1103 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c uint32_t target_tdp) uint32_t 1219 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp); uint32_t 57 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); uint32_t 55 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t *speed) uint32_t 57 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t duty100; uint32_t 58 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t duty; uint32_t 75 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c *speed = (uint32_t)tmp64; uint32_t 83 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) uint32_t 85 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t tach_period; uint32_t 86 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t crystal_clock_freq; uint32_t 111 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) uint32_t 196 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t speed) uint32_t 198 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t duty100; uint32_t 199 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t duty; uint32_t 219 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c duty = (uint32_t)tmp64; uint32_t 255 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) uint32_t 257 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t tach_period; uint32_t 258 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t crystal_clock_freq; uint32_t 366 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t alert; uint32_t 384 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c uint32_t alert; uint32_t 44 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed); uint32_t 46 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode); uint32_t 47 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed); uint32_t 50 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed); uint32_t 51 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed); uint32_t 68 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr, uint32_t 69 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t clock, uint32_t msg) uint32_t 99 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr, uint32_t 100 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t clock, uint32_t msg) uint32_t 129 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr, uint32_t 130 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t clock, uint32_t msg) uint32_t 160 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr) uint32_t 248 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_convert_8Bit_index_to_voltage( uint32_t 311 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t i; uint32_t 437 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t i; uint32_t 755 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; uint32_t 1291 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 1298 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 1415 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t data = 0; uint32_t 1445 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, uint32_t 1475 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t i; uint32_t 1494 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c enum pp_clock_type type, uint32_t mask) uint32_t 1552 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c PHM_PerformanceLevelDesignation designation, uint32_t index, uint32_t 1557 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t level_index; uint32_t 1558 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t i; uint32_t 1657 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t val = cgs_read_ind_register(hwmgr->device, uint32_t 1659 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP); uint32_t 1683 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX), uint32_t 1685 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), uint32_t 1687 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), uint32_t 1690 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; uint32_t 1703 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = sclk; uint32_t 1711 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = vddnb; uint32_t 1717 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = vddgfx; uint32_t 1725 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = vclk; uint32_t 1729 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = 0; uint32_t 1737 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = dclk; uint32_t 1741 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = 0; uint32_t 1749 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = ecclk; uint32_t 1753 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = 0; uint32_t 1763 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = activity_percent; uint32_t 1766 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; uint32_t 1769 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; uint32_t 1772 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr); uint32_t 1780 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t virtual_addr_low, uint32_t 1781 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t virtual_addr_hi, uint32_t 1782 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t mc_addr_low, uint32_t 1783 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t mc_addr_hi, uint32_t 1784 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t size) uint32_t 1822 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t dpm_features = 0; uint32_t 1873 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t dpm_features = 0; uint32_t 45 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t soft_min_clk; uint32_t 46 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t hard_min_clk; uint32_t 47 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t soft_max_clk; uint32_t 48 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t hard_max_clk; uint32_t 52 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t bootup_uma_clock; uint32_t 53 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t bootup_engine_clock; uint32_t 54 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dentist_vco_freq; uint32_t 55 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t nb_dpm_enable; uint32_t 56 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK]; uint32_t 57 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES]; uint32_t 59 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL]; uint32_t 63 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t system_config; uint32_t 64 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t uma_channel_number; uint32_t 79 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h (((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \ uint32_t 80 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h ((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \ uint32_t 100 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t engineClock; uint32_t 114 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t vclk; uint32_t 115 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dclk; uint32_t 116 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t vclk_low_divider; uint32_t 117 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t vclk_high_divider; uint32_t 118 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dclk_low_divider; uint32_t 119 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dclk_high_divider; uint32_t 131 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t entry : 1; uint32_t 132 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t display : 1; uint32_t 133 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t driver: 1; uint32_t 134 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t vce : 1; uint32_t 135 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t uvd : 1; uint32_t 136 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t acp : 1; uint32_t 137 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t reserved: 26; uint32_t 139 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t u32All; uint32_t 145 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t level; uint32_t 147 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t evclk; uint32_t 148 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t ecclk; uint32_t 149 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t samclk; uint32_t 150 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t acpclk; uint32_t 152 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t nbps_flags; uint32_t 153 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t bapm_flags; uint32_t 179 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t cpu_pstate_separation_time; uint32_t 183 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dpm_interval; uint32_t 185 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t voltage_drop_threshold; uint32_t 187 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t voting_rights_clients; uint32_t 189 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t disable_driver_thermal_policy; uint32_t 191 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t static_screen_threshold; uint32_t 193 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t gfx_power_gating_threshold; uint32_t 195 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t activity_hysteresis; uint32_t 196 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t bootup_sclk_divider; uint32_t 197 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t gfx_ramp_step; uint32_t 198 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t gfx_ramp_delay; /* in micro-seconds */ uint32_t 200 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t thermal_auto_throttling_treshold; uint32_t 208 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t mgcg_cgtt_local0; uint32_t 209 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t mgcg_cgtt_local1; uint32_t 211 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t tdr_clock; /* in 10khz unit */ uint32_t 213 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t ddi_power_gating_disabled; uint32_t 214 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t disable_gfx_power_gating_in_uvd; uint32_t 215 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t disable_nb_ps3_in_battery; uint32_t 217 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t lock_nb_ps_in_uvd_play_back; uint32_t 220 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t vce_slow_sclk_threshold; /* default 200mhz */ uint32_t 221 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dce_slow_sclk_threshold; /* default 300mhz */ uint32_t 222 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t min_sclk_did; /* minimum sclk divider */ uint32_t 226 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t bapm_enabled; uint32_t 227 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t clock_slow_down_freq; uint32_t 228 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t skip_clock_slow_down; uint32_t 229 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t enable_nb_ps_policy; uint32_t 230 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t voltage_drop_in_dce_power_gating; uint32_t 231 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t uvd_dpm_interval; uint32_t 232 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t override_dynamic_mgpg; uint32_t 233 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t lclk_deep_enabled; uint32_t 235 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t uvd_performance; uint32_t 239 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t lowest_valid; uint32_t 240 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t highest_valid; uint32_t 241 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t high_voltage_threshold; uint32_t 242 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t is_nb_dpm_enabled; uint32_t 244 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t is_voltage_island_enabled; uint32_t 251 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t power_containment_features; uint32_t 257 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t sram_end; uint32_t 258 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dpm_table_start; uint32_t 259 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t soft_regs_start; uint32_t 266 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t fps_high_threshold; uint32_t 267 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t fps_low_threshold; uint32_t 269 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dpm_flags; uint32_t 291 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t display_cac; uint32_t 292 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t low_sclk_interrupt_threshold; uint32_t 294 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dram_log_addr_h; uint32_t 295 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dram_log_addr_l; uint32_t 296 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dram_log_phy_addr_h; uint32_t 297 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dram_log_phy_addr_l; uint32_t 298 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t dram_log_buff_size; uint32_t 305 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t active_process_mask; uint32_t 307 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t max_sclk_level; uint32_t 308 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t num_of_clk_entries; uint32_t 34 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c uint32_t reg, data; uint32_t 56 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c uint32_t reg; uint32_t 47 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t **pptable_info_array, uint32_t 48 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c const uint32_t *pptable_array, uint32_t 49 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t power_saving_clock_count) uint32_t 51 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t array_size, i; uint32_t 52 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t *table; uint32_t 54 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c array_size = sizeof(uint32_t) * power_saving_clock_count; uint32_t 69 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t **pptable_info_array, uint32_t 70 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c const uint32_t *pptable_array, uint32_t 71 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t od_setting_count) uint32_t 73 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t array_size, i; uint32_t 74 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t *table; uint32_t 76 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c array_size = sizeof(uint32_t) * od_setting_count; uint32_t 89 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size) uint32_t 109 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, uint32_t 110 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t value, uint32_t mask) uint32_t 112 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t i; uint32_t 113 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t cur_value; uint32_t 140 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t indirect_port, uint32_t 141 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t index, uint32_t 142 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t value, uint32_t 143 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t mask) uint32_t 155 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t index, uint32_t 156 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t value, uint32_t mask) uint32_t 158 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t i; uint32_t 159 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t cur_value; uint32_t 179 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t indirect_port, uint32_t 180 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t index, uint32_t 181 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t value, uint32_t 182 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t mask) uint32_t 205 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t i, j; uint32_t 250 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t i; uint32_t 278 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t i; uint32_t 327 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, uint32_t 346 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t count, int max) uint32_t 362 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t index, uint32_t pcie_gen, uint32_t 363 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t pcie_lanes) uint32_t 409 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t voltage) uint32_t 431 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t i; uint32_t 443 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t value, uint32_t *boot_level) uint32_t 446 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t i; uint32_t 494 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t table_size; uint32_t 499 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record); uint32_t 523 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask) uint32_t 525 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t level = 0; uint32_t 541 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t req_vddc = 0, req_volt, i; uint32_t 558 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE); uint32_t 569 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t sclk, uint16_t id, uint16_t *voltage) uint32_t 571 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t vol; uint32_t 592 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t client_id = entry->client_id; uint32_t 593 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t src_id = entry->src_id; uint32_t 663 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size, uint32_t 707 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t i; uint32_t 47 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t padding[7]; uint32_t 52 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t **pptable_info_array, uint32_t 53 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h const uint32_t *pptable_array, uint32_t 54 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t power_saving_clock_count); uint32_t 58 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t **pptable_info_array, uint32_t 59 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h const uint32_t *pptable_array, uint32_t 60 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t od_setting_count); uint32_t 63 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t index, uint32_t 64 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t value, uint32_t mask); uint32_t 67 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t indirect_port, uint32_t index, uint32_t 68 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t value, uint32_t mask); uint32_t 79 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table); uint32_t 80 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max); uint32_t 81 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes); uint32_t 84 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t voltage); uint32_t 87 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level); uint32_t 91 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask); uint32_t 95 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t sclk, uint16_t id, uint16_t *voltage); uint32_t 97 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size); uint32_t 99 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, uint32_t 100 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t value, uint32_t mask); uint32_t 103 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t indirect_port, uint32_t 104 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t index, uint32_t 105 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t value, uint32_t 106 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t mask); uint32_t 114 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size, uint32_t 59 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; uint32_t 312 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 359 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t sub_vendor_id, hw_revision; uint32_t 360 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t top32, bottom32; uint32_t 555 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t vddc = 0; uint32_t 557 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t sclk = 0; uint32_t 611 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t index; uint32_t 639 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 714 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t table_size, i, j; uint32_t 823 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t config_telemetry = 0; uint32_t 957 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t mask = 0; uint32_t 958 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t tmp; uint32_t 968 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c mask |= (uint32_t)(i << (8 * j)); uint32_t 1008 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, j; uint32_t 1080 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 1131 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t max_vol_steps, uint32_t 1249 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 1296 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 1487 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t lclock, uint8_t *curr_lclk_did) uint32_t 1510 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, j; uint32_t 1550 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t gfx_clock, PllSetting_t *current_gfxclk_level, uint32_t 1551 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t *acg_freq) uint32_t 1558 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t gfx_max_clock = uint32_t 1560 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i = 0; uint32_t 1615 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t soc_clock, uint8_t *current_soc_did, uint32_t 1623 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 1668 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, j; uint32_t 1725 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, max_vddc_level; uint32_t 1751 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t mem_clock, uint8_t *current_mem_vid, uint32_t 1759 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t mem_max_clock = uint32_t 1761 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i = 0; uint32_t 1817 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, j; uint32_t 1861 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 1910 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 1922 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t eclock, uint8_t *current_eclk_did, uint32_t 1930 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 1954 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, j; uint32_t 1980 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t vclock, uint8_t *current_vclk_did) uint32_t 1996 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t dclock, uint8_t *current_dclk_did) uint32_t 2024 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, j; uint32_t 2090 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 2111 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 2295 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t agc_btc_response; uint32_t 2422 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t top32, bottom32; uint32_t 2463 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 2613 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c (uint32_t)(data->vbios_boot_state.dcef_clock / 100)); uint32_t 2826 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) uint32_t 2829 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, feature_mask = 0; uint32_t 2863 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) uint32_t 2866 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, feature_mask = 0; uint32_t 3003 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c void *pp_table, uint32_t classification_flag) uint32_t 3137 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t sclk; uint32_t 3138 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t mclk; uint32_t 3145 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 3150 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t stable_pstate_sclk_dpm_percentage; uint32_t 3151 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; uint32_t 3152 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t latency; uint32_t 3291 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t sclk = vega10_ps->performance_levels uint32_t 3294 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t mclk = vega10_ps->performance_levels uint32_t 3296 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 3375 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t low_limit, uint32_t high_limit) uint32_t 3377 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 3391 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t low_limit, uint32_t high_limit, uint32_t 3392 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t disable_dpm_mask) uint32_t 3394 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 3412 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t high_limit_count; uint32_t 3439 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static uint32_t vega10_find_lowest_dpm_level( uint32_t 3442 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 3452 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static uint32_t vega10_find_highest_dpm_level( uint32_t 3455 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i = 0; uint32_t 3490 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t socclk_idx; uint32_t 3644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t low_sclk_interrupt_threshold = 0; uint32_t 3657 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c (uint32_t)low_sclk_interrupt_threshold); uint32_t 3705 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 3727 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 3750 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t *query) uint32_t 3752 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t value; uint32_t 3770 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t sclk_mhz, mclk_idx, activity_percent = 0; uint32_t 3774 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t val_vid; uint32_t 3780 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *((uint32_t *)value) = sclk_mhz * 100; uint32_t 3786 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; uint32_t 3795 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; uint32_t 3799 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr); uint32_t 3804 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *((uint32_t *)value) = smum_get_argument(hwmgr) * uint32_t 3810 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *((uint32_t *)value) = smum_get_argument(hwmgr) * uint32_t 3815 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; uint32_t 3819 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; uint32_t 3823 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value); uint32_t 3829 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid); uint32_t 3857 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; uint32_t 3859 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t clk_request = 0; uint32_t 3892 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t frequency) uint32_t 3919 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t idx; uint32_t 3921 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 4032 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) uint32_t 4059 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) uint32_t 4079 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c enum pp_clock_type type, uint32_t mask) uint32_t 4141 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t sclk_mask = 0; uint32_t 4142 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t mclk_mask = 0; uint32_t 4143 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t soc_mask = 0; uint32_t 4184 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr) uint32_t 4215 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 4236 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t j = 0; uint32_t 4237 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 4261 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 4277 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 4317 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 4341 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table-> uint32_t 4764 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) uint32_t 4815 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) uint32_t 4852 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t virtual_addr_low, uint32_t 4853 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t virtual_addr_hi, uint32_t 4854 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t mc_addr_low, uint32_t 4855 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t mc_addr_hi, uint32_t 4856 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t size) uint32_t 4905 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i, size = 0; uint32_t 4945 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) uint32_t 4952 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t power_profile_mode = input[size]; uint32_t 4990 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t clk, uint32_t 4991 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t voltage) uint32_t 5157 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c long *input, uint32_t size) uint32_t 5163 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t input_clk; uint32_t 5164 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t input_vol; uint32_t 5165 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t input_level; uint32_t 5166 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 5246 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PHM_PerformanceLevelDesignation designation, uint32_t index, uint32_t 5251 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t i; uint32_t 80 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t smu_feature_id; uint32_t 81 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t smu_feature_bitmap; uint32_t 85 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t soc_clock; uint32_t 86 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t gfx_clock; uint32_t 87 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t mem_clock; uint32_t 91 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t baco_flags; uint32_t 96 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t vclk; uint32_t 97 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t dclk; uint32_t 101 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t evclk; uint32_t 102 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t ecclk; uint32_t 106 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t magic; uint32_t 111 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t sclk_threshold; uint32_t 117 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t value; uint32_t 118 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t param1; uint32_t 127 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t soft_min_level; uint32_t 128 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t soft_max_level; uint32_t 129 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t hard_min_level; uint32_t 130 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t hard_max_level; uint32_t 134 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t count; uint32_t 143 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t lclk[MAX_PCIE_CONF]; uint32_t 168 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t min_clock_in_sr; uint32_t 169 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t num_existing_displays; uint32_t 173 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t uvd_dpm_enable_mask; uint32_t 174 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t vce_dpm_enable_mask; uint32_t 175 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t acp_dpm_enable_mask; uint32_t 176 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t samu_dpm_enable_mask; uint32_t 177 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t sclk_dpm_enable_mask; uint32_t 178 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t mclk_dpm_enable_mask; uint32_t 187 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t gfx_clock; uint32_t 188 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t mem_clock; uint32_t 189 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t soc_clock; uint32_t 190 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t dcef_clock; uint32_t 194 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t soc_boot_level; uint32_t 195 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t gfx_boot_level; uint32_t 196 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t dcef_boot_level; uint32_t 197 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t mem_boot_level; uint32_t 198 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t uvd_boot_level; uint32_t 199 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t vce_boot_level; uint32_t 200 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t gfx_max_level; uint32_t 201 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t mem_max_level; uint32_t 202 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t soc_max_level; uint32_t 215 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t frequency; uint32_t 216 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t latency; uint32_t 220 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t count; uint32_t 236 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t fast_watermark_threshold; uint32_t 244 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t pcieClockOverride; uint32_t 261 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t stable_pstate_sclk_dpm_percentage; uint32_t 274 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t vddc_vddci_delta; uint32_t 285 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t count; uint32_t 290 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t count; uint32_t 299 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t max_vddc; uint32_t 300 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t min_vddc; uint32_t 304 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t target_fan_speed; uint32_t 305 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t target_temperature; uint32_t 306 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t min_performance_clock; uint32_t 307 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t min_fan_limit; uint32_t 319 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t vddc_control; uint32_t 321 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t mvdd_control; uint32_t 323 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t vddci_control; uint32_t 326 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t active_auto_throttle_sources; uint32_t 327 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t water_marks_bitmap; uint32_t 340 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t low_sclk_interrupt_threshold; uint32_t 342 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t total_active_cus; uint32_t 348 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t debug_settings; uint32_t 349 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t lowest_uclk_reserved_for_ulv; uint32_t 350 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t gfxclk_average_alpha; uint32_t 351 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t socclk_average_alpha; uint32_t 352 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t uclk_average_alpha; uint32_t 353 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t gfx_activity_average_alpha; uint32_t 354 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t display_voltage_mode; uint32_t 355 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t dcef_clk_quad_eqn_a; uint32_t 356 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t dcef_clk_quad_eqn_b; uint32_t 357 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t dcef_clk_quad_eqn_c; uint32_t 358 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t disp_clk_quad_eqn_a; uint32_t 359 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t disp_clk_quad_eqn_b; uint32_t 360 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t disp_clk_quad_eqn_c; uint32_t 361 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t pixel_clk_quad_eqn_a; uint32_t 362 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t pixel_clk_quad_eqn_b; uint32_t 363 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t pixel_clk_quad_eqn_c; uint32_t 364 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t phy_clk_quad_eqn_a; uint32_t 365 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t phy_clk_quad_eqn_b; uint32_t 366 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t phy_clk_quad_eqn_c; uint32_t 377 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t disable_dpm_mask; uint32_t 383 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t config_telemetry; uint32_t 384 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t acg_loop_state; uint32_t 385 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t mem_channels; uint32_t 801 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t data; uint32_t 837 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t data; uint32_t 852 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t data; uint32_t 853 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t en = (enable ? 1 : 0); uint32_t 854 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; uint32_t 936 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t num_se = 0, count, data; uint32_t 987 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t num_se = 0, count, data; uint32_t 1025 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t data; uint32_t 1048 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t num_se = 0, count, data; uint32_t 1095 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t num_se = 0; uint32_t 1096 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t count, data; uint32_t 1139 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t data; uint32_t 1324 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) uint32_t 1344 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit); uint32_t 1390 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c uint32_t adjust_percent) uint32_t 1406 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c (uint32_t)adjust_percent); uint32_t 46 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t offset; uint32_t 47 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t mask; uint32_t 48 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t shift; uint32_t 49 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t value; uint32_t 54 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t offset; uint32_t 55 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t mask; uint32_t 56 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t shift; uint32_t 57 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t value; uint32_t 74 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); uint32_t 89 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) uint32_t 347 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size, i; uint32_t 354 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + uint32_t 426 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size; uint32_t 434 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table); uint32_t 574 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size, i; uint32_t 580 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + uint32_t 589 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; uint32_t 608 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size, i; uint32_t 614 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + uint32_t 623 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; uint32_t 647 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size, i; uint32_t 655 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + uint32_t 714 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size, i; uint32_t 721 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + uint32_t 750 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size, i; uint32_t 754 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t dev_id; uint32_t 755 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t rev_id; uint32_t 778 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + uint32_t 787 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c clk_table->count = (uint32_t)num_entries; uint32_t 810 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size, i, pcie_count; uint32_t 821 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + uint32_t 878 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size, i; uint32_t 884 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + uint32_t 885 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c sizeof(uint32_t) * clk_volt_pp_table->count; uint32_t 892 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table->count = (uint32_t)clk_volt_pp_table->count; uint32_t 895 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk; uint32_t 1067 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t max_levels) uint32_t 1069 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t table_size, i; uint32_t 1075 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c table_size = sizeof(uint32_t) + uint32_t 1101 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t disable_power_control = 0; uint32_t 1297 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c return (uint32_t)(state_arrays->ucNumEntries); uint32_t 1300 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, uint32_t 1303 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t result = 0; uint32_t 1330 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c uint32_t entry_index, struct pp_power_state *power_state, uint32_t 1332 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c struct pp_power_state *, void *, uint32_t)) uint32_t 59 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h extern int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index, uint32_t 61 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h struct pp_power_state *, void *, uint32_t)); uint32_t 32 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) uint32_t 69 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t *speed) uint32_t 71 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t current_rpm; uint32_t 72 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t percent = 0; uint32_t 91 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) uint32_t 95 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t tach_period; uint32_t 96 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t crystal_clock_freq; uint32_t 128 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) uint32_t 252 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t speed) uint32_t 255 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t duty100; uint32_t 256 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t duty; uint32_t 276 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c duty = (uint32_t)tmp64; uint32_t 307 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) uint32_t 310 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t tach_period; uint32_t 311 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t crystal_clock_freq; uint32_t 372 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t val; uint32_t 429 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c uint32_t val = 0; uint32_t 523 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c (uint32_t)table->FanTargetTemperature); uint32_t 58 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h uint32_t *speed); uint32_t 61 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h uint32_t mode); uint32_t 63 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h uint32_t speed); uint32_t 68 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h uint32_t speed); uint32_t 70 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h uint32_t *speed); uint32_t 52 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c enum pp_clock_type type, uint32_t mask); uint32_t 54 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t *clock, uint32_t 293 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t top32, bottom32; uint32_t 480 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PPCLK_e clk_id, uint32_t *num_of_levels) uint32_t 500 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PPCLK_e clkID, uint32_t index, uint32_t *clock) uint32_t 522 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t i, num_of_levels, clk; uint32_t 697 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t min_level; uint32_t 754 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c (uint32_t)(data->vbios_boot_state.dcef_clock / 100)); uint32_t 769 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t result; uint32_t 788 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t allowed_features_low = 0, allowed_features_high = 0; uint32_t 881 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t adjust_percent) uint32_t 897 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c (uint32_t)adjust_percent); uint32_t 933 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t i; uint32_t 999 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_find_lowest_dpm_level( uint32_t 1002 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t i; uint32_t 1017 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_find_highest_dpm_level( uint32_t 1035 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c return (uint32_t)i; uint32_t 1041 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t min_freq; uint32_t 1124 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t max_freq; uint32_t 1204 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 1208 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t gfx_clk; uint32_t 1227 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 1231 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t mem_clk; uint32_t 1271 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) uint32_t 1285 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq) uint32_t 1287 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t gfx_clk = 0; uint32_t 1302 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq) uint32_t 1304 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t mem_clk = 0; uint32_t 1322 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t *activity_percent) uint32_t 1355 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value); uint32_t 1360 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value); uint32_t 1366 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); uint32_t 1371 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr); uint32_t 1379 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c *((uint32_t *)value) = metrics_table.TemperatureHotspot * uint32_t 1388 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c *((uint32_t *)value) = metrics_table.TemperatureHBM * uint32_t 1393 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; uint32_t 1397 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; uint32_t 1401 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value); uint32_t 1436 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; uint32_t 1438 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t clk_request = 0; uint32_t 1514 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t soft_level; uint32_t 1543 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t soft_level; uint32_t 1583 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) uint32_t 1615 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) uint32_t 1637 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t sclk_mask = 0; uint32_t 1638 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t mclk_mask = 0; uint32_t 1639 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t soc_mask = 0; uint32_t 1670 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr) uint32_t 1696 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t *clock, uint32_t 1714 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t ucount; uint32_t 1737 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t 1738 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t clock) uint32_t 1747 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t ucount; uint32_t 1774 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t ucount; uint32_t 1802 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t ucount; uint32_t 1881 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c enum pp_clock_type type, uint32_t mask) uint32_t 1884 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t soft_min_level, soft_max_level, hard_min_level; uint32_t 2177 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t i, latency; uint32_t 2476 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t *sclk_idx, uint32_t *mclk_idx, uint32_t 2477 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t min_sclk, uint32_t min_mclk) uint32_t 2481 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t i; uint32_t 2524 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) uint32_t 2545 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) uint32_t 2552 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t virtual_addr_low, uint32_t 2553 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t virtual_addr_hi, uint32_t 2554 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t mc_addr_low, uint32_t 2555 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t mc_addr_hi, uint32_t 2556 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c uint32_t size) uint32_t 2636 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PHM_PerformanceLevelDesignation designation, uint32_t index, uint32_t 85 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t smu_feature_id; uint32_t 91 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t value; uint32_t 92 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t param1; uint32_t 101 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t soft_min_level; uint32_t 102 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t soft_max_level; uint32_t 103 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t hard_min_level; uint32_t 104 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t hard_max_level; uint32_t 108 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t count; uint32_t 114 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t count; uint32_t 115 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t entries[MAX_REGULAR_DPM_NUMBER]; uint32_t 122 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t lclk[MAX_PCIE_CONF]; uint32_t 147 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t min_clock_in_sr; uint32_t 148 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t num_existing_displays; uint32_t 152 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t uvd_dpm_enable_mask; uint32_t 153 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t vce_dpm_enable_mask; uint32_t 154 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t samu_dpm_enable_mask; uint32_t 155 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t sclk_dpm_enable_mask; uint32_t 156 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t mclk_dpm_enable_mask; uint32_t 166 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t gfx_clock; uint32_t 167 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t mem_clock; uint32_t 168 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t soc_clock; uint32_t 169 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t dcef_clock; uint32_t 170 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t eclock; uint32_t 171 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t dclock; uint32_t 172 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t vclock; uint32_t 182 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t soc_boot_level; uint32_t 183 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t gfx_boot_level; uint32_t 184 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t dcef_boot_level; uint32_t 185 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t mem_boot_level; uint32_t 186 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t uvd_boot_level; uint32_t 187 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t vce_boot_level; uint32_t 188 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t gfx_max_level; uint32_t 189 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t mem_max_level; uint32_t 206 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t frequency; uint32_t 207 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t latency; uint32_t 211 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t count; uint32_t 230 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t pcie_clock_override; uint32_t 259 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t force_workload_policy_mask; uint32_t 263 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t perf_ui_tuning_profile_turbo; uint32_t 264 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t perf_ui_tuning_profile_powerSave; uint32_t 265 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t perf_ui_tuning_profile_xl; uint32_t 268 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t stable_pstate_sclk_dpm_percentage; uint32_t 273 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t auto_wattman_debug; uint32_t 274 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t auto_wattman_sample_period; uint32_t 283 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t count; uint32_t 296 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t odn_mclk_min_limit; uint32_t 300 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t target_fan_speed; uint32_t 301 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t target_temperature; uint32_t 302 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t min_performance_clock; uint32_t 303 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t min_fan_limit; uint32_t 308 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t ACMax; uint32_t 309 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t ACMin; uint32_t 310 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t DCMax; uint32_t 322 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t vddc_control; uint32_t 324 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t mvdd_control; uint32_t 326 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t vddci_control; uint32_t 329 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t active_auto_throttle_sources; uint32_t 330 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t water_marks_bitmap; uint32_t 343 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t low_sclk_interrupt_threshold; uint32_t 345 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t total_active_cus; uint32_t 351 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t debug_settings; uint32_t 352 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t lowest_uclk_reserved_for_ulv; uint32_t 353 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t gfxclk_average_alpha; uint32_t 354 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t socclk_average_alpha; uint32_t 355 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t uclk_average_alpha; uint32_t 356 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t gfx_activity_average_alpha; uint32_t 357 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t display_voltage_mode; uint32_t 358 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t dcef_clk_quad_eqn_a; uint32_t 359 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t dcef_clk_quad_eqn_b; uint32_t 360 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t dcef_clk_quad_eqn_c; uint32_t 361 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t disp_clk_quad_eqn_a; uint32_t 362 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t disp_clk_quad_eqn_b; uint32_t 363 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t disp_clk_quad_eqn_c; uint32_t 364 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t pixel_clk_quad_eqn_a; uint32_t 365 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t pixel_clk_quad_eqn_b; uint32_t 366 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t pixel_clk_quad_eqn_c; uint32_t 367 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t phy_clk_quad_eqn_a; uint32_t 368 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t phy_clk_quad_eqn_b; uint32_t 369 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t phy_clk_quad_eqn_c; uint32_t 382 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t disable_dpm_mask; uint32_t 385 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t apply_overdrive_next_settings_mask; uint32_t 388 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t workload_mask; uint32_t 391 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h uint32_t smu_version; uint32_t 77 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) uint32_t 197 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c uint32_t disable_power_control = 0; uint32_t 327 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, uint32_t 330 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c uint32_t result = 0; uint32_t 357 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c uint32_t entry_index, struct pp_power_state *power_state, uint32_t 359 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c struct pp_power_state *, void *, uint32_t)) uint32_t 32 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) uint32_t 55 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) uint32_t 178 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c uint32_t val; uint32_t 209 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c uint32_t val = 0; uint32_t 262 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c (uint32_t)table->FanTargetTemperature); uint32_t 58 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h uint32_t *speed); uint32_t 43 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c uint32_t reg; uint32_t 62 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c uint32_t reg; uint32_t 79 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c uint32_t data; uint32_t 328 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t top32, bottom32; uint32_t 520 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PPCLK_e clk_id, uint32_t *num_of_levels) uint32_t 540 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PPCLK_e clk_id, uint32_t index, uint32_t *clk) uint32_t 563 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t i, num_of_levels, clk; uint32_t 812 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c (uint32_t)(data->vbios_boot_state.dcef_clock / 100)); uint32_t 836 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg; uint32_t 883 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t allowed_features_low = 0, allowed_features_high = 0; uint32_t 1191 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t *voltage, uint32_t 1192 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t freq) uint32_t 1364 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t index, uint32_t 1365 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t value) uint32_t 1458 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct pp_hwmgr *hwmgr, uint32_t value) uint32_t 1463 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t od_sclk; uint32_t 1504 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct pp_hwmgr *hwmgr, uint32_t value) uint32_t 1509 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t od_mclk; uint32_t 1749 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_find_lowest_dpm_level( uint32_t 1752 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t i; uint32_t 1766 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_find_highest_dpm_level( uint32_t 1793 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) uint32_t 1797 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t min_freq; uint32_t 1886 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) uint32_t 1890 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t max_freq; uint32_t 1996 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t *clock, uint32_t 2021 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 2025 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t gfx_clk; uint32_t 2047 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) uint32_t 2051 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t mem_clk; uint32_t 2095 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t *query) uint32_t 2114 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PPCLK_e clk_id, uint32_t *clk_freq) uint32_t 2133 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t *activity_percent) uint32_t 2163 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t val_vid; uint32_t 2172 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100; uint32_t 2178 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c (uint32_t *)value); uint32_t 2184 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); uint32_t 2189 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr); uint32_t 2197 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c *((uint32_t *)value) = metrics_table.TemperatureEdge * uint32_t 2206 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c *((uint32_t *)value) = metrics_table.TemperatureHBM * uint32_t 2211 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; uint32_t 2215 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; uint32_t 2220 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value); uint32_t 2226 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c *((uint32_t *)value) = uint32_t 2227 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c (uint32_t)convert_to_vddc((uint8_t)val_vid); uint32_t 2247 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; uint32_t 2249 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t clk_request = 0; uint32_t 2283 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PHM_PerformanceLevelDesignation designation, uint32_t index, uint32_t 2335 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t soft_level; uint32_t 2377 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t soft_level; uint32_t 2420 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t soft_min_level, soft_max_level; uint32_t 2474 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) uint32_t 2507 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c enum pp_clock_type type, uint32_t mask) uint32_t 2510 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t soft_min_level, soft_max_level, hard_min_level; uint32_t 2673 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t sclk_mask, mclk_mask, soc_mask; uint32_t 2709 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr) uint32_t 2719 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) uint32_t 2776 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t 2777 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t clock) uint32_t 2907 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c long *input, uint32_t size) uint32_t 3267 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; uint32_t 3636 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t i, latency; uint32_t 3884 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t i, size = 0; uint32_t 3987 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) uint32_t 3991 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t power_profile_mode = input[size]; uint32_t 4089 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t virtual_addr_low, uint32_t 4090 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t virtual_addr_hi, uint32_t 4091 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t mc_addr_low, uint32_t 4092 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t mc_addr_hi, uint32_t 4093 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c uint32_t size) uint32_t 47 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h typedef uint32_t PP_Clock; uint32_t 97 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t smu_feature_id; uint32_t 102 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t soc_clock; uint32_t 103 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t gfx_clock; uint32_t 104 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t mem_clock; uint32_t 108 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t baco_flags; uint32_t 113 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t vclk; uint32_t 114 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t dclk; uint32_t 118 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t evclk; uint32_t 119 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t ecclk; uint32_t 123 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t magic; uint32_t 128 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t sclk_threshold; uint32_t 134 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t value; uint32_t 135 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t param1; uint32_t 153 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t soft_min_level; uint32_t 154 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t soft_max_level; uint32_t 155 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t hard_min_level; uint32_t 156 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t hard_max_level; uint32_t 160 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t count; uint32_t 166 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t count; uint32_t 167 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t entries[MAX_REGULAR_DPM_NUMBER]; uint32_t 174 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t lclk[MAX_PCIE_CONF]; uint32_t 200 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t min_clock_in_sr; uint32_t 201 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t num_existing_displays; uint32_t 205 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t uvd_dpm_enable_mask; uint32_t 206 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t vce_dpm_enable_mask; uint32_t 207 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t samu_dpm_enable_mask; uint32_t 208 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t sclk_dpm_enable_mask; uint32_t 209 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t mclk_dpm_enable_mask; uint32_t 218 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t gfx_clock; uint32_t 219 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t mem_clock; uint32_t 220 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t soc_clock; uint32_t 221 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t dcef_clock; uint32_t 222 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t eclock; uint32_t 223 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t dclock; uint32_t 224 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t vclock; uint32_t 225 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t fclock; uint32_t 242 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t soc_boot_level; uint32_t 243 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t gfx_boot_level; uint32_t 244 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t dcef_boot_level; uint32_t 245 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t mem_boot_level; uint32_t 246 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t uvd_boot_level; uint32_t 247 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t vce_boot_level; uint32_t 248 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t gfx_max_level; uint32_t 249 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t mem_max_level; uint32_t 266 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t frequency; uint32_t 267 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t latency; uint32_t 271 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t count; uint32_t 290 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t pcie_clock_override; uint32_t 319 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t force_workload_policy_mask; uint32_t 323 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t perf_ui_tuning_profile_turbo; uint32_t 324 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t perf_ui_tuning_profile_powerSave; uint32_t 325 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t perf_ui_tuning_profile_xl; uint32_t 328 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t stable_pstate_sclk_dpm_percentage; uint32_t 333 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t auto_wattman_debug; uint32_t 334 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t auto_wattman_sample_period; uint32_t 335 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t fclk_gfxclk_ratio; uint32_t 345 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t count; uint32_t 358 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t odn_mclk_min_limit; uint32_t 362 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t target_fan_speed; uint32_t 363 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t target_temperature; uint32_t 364 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t min_performance_clock; uint32_t 365 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t min_fan_limit; uint32_t 378 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t apply_overdrive_next_settings_mask; uint32_t 379 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t overdrive_next_state; uint32_t 380 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t overdrive_next_capabilities; uint32_t 381 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t odn_sclk_dpm_enable_mask; uint32_t 382 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t odn_mclk_dpm_enable_mask; uint32_t 424 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t feature_id; uint32_t 432 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t overdrive8_capabilities; uint32_t 447 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t vddc_control; uint32_t 449 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t mvdd_control; uint32_t 451 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t vddci_control; uint32_t 454 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t active_auto_throttle_sources; uint32_t 465 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t low_sclk_interrupt_threshold; uint32_t 467 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t total_active_cus; uint32_t 469 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t water_marks_bitmap; uint32_t 475 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t debug_settings; uint32_t 476 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t lowest_uclk_reserved_for_ulv; uint32_t 477 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t gfxclk_average_alpha; uint32_t 478 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t socclk_average_alpha; uint32_t 479 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t uclk_average_alpha; uint32_t 480 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t gfx_activity_average_alpha; uint32_t 481 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t display_voltage_mode; uint32_t 482 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t dcef_clk_quad_eqn_a; uint32_t 483 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t dcef_clk_quad_eqn_b; uint32_t 484 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t dcef_clk_quad_eqn_c; uint32_t 485 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t disp_clk_quad_eqn_a; uint32_t 486 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t disp_clk_quad_eqn_b; uint32_t 487 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t disp_clk_quad_eqn_c; uint32_t 488 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t pixel_clk_quad_eqn_a; uint32_t 489 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t pixel_clk_quad_eqn_b; uint32_t 490 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t pixel_clk_quad_eqn_c; uint32_t 491 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t phy_clk_quad_eqn_a; uint32_t 492 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t phy_clk_quad_eqn_b; uint32_t 493 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t phy_clk_quad_eqn_c; uint32_t 506 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t disable_dpm_mask; uint32_t 517 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t workload_mask; uint32_t 520 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t smu_version; uint32_t 526 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t counter_gfxoff; uint32_t 532 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t pcie_gen_level1; uint32_t 533 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t pcie_width_level1; uint32_t 32 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) uint32_t 45 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c uint32_t tdp_percentage_adjustment, uint32_t tdp_absolute_value_adjustment) uint32_t 51 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c uint32_t adjust_percent) uint32_t 67 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c (uint32_t)adjust_percent); uint32_t 26 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); uint32_t 29 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h uint32_t tdp_percentage_adjustment, uint32_t 30 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h uint32_t tdp_absolute_value_adjustment); uint32_t 661 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) uint32_t 692 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c uint32_t array_size, i; uint32_t 821 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c uint32_t disable_power_control = 0; uint32_t 822 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c uint32_t od_feature_count, od_setting_count, power_saving_clock_count; uint32_t 90 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c static int vega20_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) uint32_t 104 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) uint32_t 118 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t *speed) uint32_t 122 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t current_rpm, percent = 0; uint32_t 137 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t speed) uint32_t 140 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t duty100; uint32_t 141 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t duty; uint32_t 158 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c duty = (uint32_t)tmp64; uint32_t 179 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) uint32_t 186 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) uint32_t 189 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t tach_period, crystal_clock_freq; uint32_t 248 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t val; uint32_t 279 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c uint32_t val = 0; uint32_t 332 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c (uint32_t)table->FanTargetTemperature); uint32_t 56 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h uint32_t *speed); uint32_t 58 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h uint32_t speed); uint32_t 60 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h uint32_t *speed); uint32_t 62 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h uint32_t speed); uint32_t 131 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t vclk; uint32_t 132 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t dclk; uint32_t 139 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t id; uint32_t 179 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t align; uint32_t 192 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t core_clock; uint32_t 193 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t memory_clock; uint32_t 194 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t vddc; uint32_t 195 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t vddci; uint32_t 196 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t non_local_mem_freq; uint32_t 197 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t non_local_mem_width; uint32_t 201 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t min_mem_clk; uint32_t 202 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t max_mem_clk; uint32_t 203 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t min_eng_clk; uint32_t 204 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t max_eng_clk; uint32_t 205 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t min_bus_bandwidth; uint32_t 206 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t max_bus_bandwidth; uint32_t 211 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t revision; uint32_t 212 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t gfxclk; uint32_t 213 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t uclk; uint32_t 214 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t socclk; uint32_t 215 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t dcefclk; uint32_t 216 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t eclk; uint32_t 217 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t vclk; uint32_t 218 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t dclk; uint32_t 224 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t pp_table_id; uint32_t 225 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t format_revision; uint32_t 226 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t content_revision; uint32_t 227 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t fclk; uint32_t 252 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t power_play_table_size; uint32_t 262 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t table_count; uint32_t 271 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t dpm_context_size; uint32_t 291 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t power_context_size; uint32_t 299 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t feature_num; uint32_t 307 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t engine_clock; uint32_t 308 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t memory_clock; uint32_t 309 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t bus_bandwidth; uint32_t 310 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t engine_clock_in_sr; uint32_t 311 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t dcef_clock; uint32_t 312 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t dcef_clock_in_sr; uint32_t 317 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t frequency; uint32_t 318 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t latency; uint32_t 321 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t count; uint32_t 334 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t state; uint32_t 359 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t pstate_sclk; uint32_t 360 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t pstate_mclk; uint32_t 363 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t power_limit; uint32_t 364 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t default_power_limit; uint32_t 367 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t ppt_offset_bytes; uint32_t 368 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t ppt_size_bytes; uint32_t 376 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t watermarks_bitmap; uint32_t 377 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t hard_min_uclk_req_from_dal; uint32_t 380 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t workload_mask; uint32_t 381 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t workload_prority[WORKLOAD_POLICY_MAX]; uint32_t 382 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t workload_setting[WORKLOAD_POLICY_MAX]; uint32_t 383 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t power_profile_mode; uint32_t 384 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t default_power_profile_mode; uint32_t 387 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t smc_if_version; uint32_t 396 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index); uint32_t 397 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index); uint32_t 398 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index); uint32_t 399 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_smu_table_index)(struct smu_context *smu, uint32_t index); uint32_t 400 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_smu_power_index)(struct smu_context *smu, uint32_t index); uint32_t 403 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); uint32_t 409 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); uint32_t 414 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t value); uint32_t 417 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h long *input, uint32_t size); uint32_t 429 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); uint32_t 433 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h void *data, uint32_t *size); uint32_t 442 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t *sclk_mask, uint32_t 443 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t *mclk_mask, uint32_t 444 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t *soc_mask); uint32_t 449 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed); uint32_t 450 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); uint32_t 455 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t *value); uint32_t 457 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); uint32_t 462 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default); uint32_t 463 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock, bool max); uint32_t 493 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param); uint32_t 494 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg); uint32_t 495 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*init_display_count)(struct smu_context *smu, uint32_t count); uint32_t 497 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); uint32_t 499 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*set_power_limit)(struct smu_context *smu, uint32_t n); uint32_t 500 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value); uint32_t 504 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h void *data, uint32_t *size); uint32_t 505 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk); uint32_t 506 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*set_active_display_count)(struct smu_context *smu, uint32_t count); uint32_t 507 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time, uint32_t 529 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t (*get_fan_control_mode)(struct smu_context *smu); uint32_t 530 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); uint32_t 531 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed); uint32_t 532 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); uint32_t 533 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); uint32_t 542 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); uint32_t 771 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, uint32_t 798 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h void *data, uint32_t *size); uint32_t 810 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate); uint32_t 817 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version); uint32_t 819 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint16_t level, uint32_t *value); uint32_t 821 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t *value); uint32_t 823 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t *min, uint32_t *max); uint32_t 825 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t min, uint32_t max); uint32_t 827 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t min, uint32_t max); uint32_t 830 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_set_display_count(struct smu_context *smu, uint32_t count); uint32_t 116 drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h typedef uint32_t PPSMC_Result; uint32_t 117 drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h typedef uint32_t PPSMC_Msg; uint32_t 213 drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h #define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126) uint32_t 214 drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h #define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127) uint32_t 36 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t min_percent; uint32_t 37 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t max_percent; uint32_t 38 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t min_rpm; uint32_t 39 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t max_rpm; uint32_t 254 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h #define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8) uint32_t 261 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES]; uint32_t 272 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t coreClock; uint32_t 273 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t memory_clock; uint32_t 274 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t vddc; uint32_t 275 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t vddci; uint32_t 276 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t nonLocalMemoryFreq; uint32_t 277 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t nonLocalMemoryWidth; uint32_t 283 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h static inline void phm_cap_set(uint32_t *caps, uint32_t 290 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h static inline void phm_cap_unset(uint32_t *caps, uint32_t 296 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c) uint32_t 327 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t engineClock; uint32_t 328 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t memoryClock; uint32_t 329 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t BusBandwidth; uint32_t 330 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t engineClockInSR; uint32_t 331 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t dcefClock; uint32_t 332 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t dcefClockInSR; uint32_t 336 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t min_mem_clk; uint32_t 337 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t max_mem_clk; uint32_t 338 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t min_eng_clk; uint32_t 339 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t max_eng_clk; uint32_t 340 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t min_bus_bandwidth; uint32_t 341 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t max_bus_bandwidth; uint32_t 345 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES]; uint32_t 346 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t vbiosInterruptId; uint32_t 349 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t hardwareActivityPerformanceLevels; uint32_t 350 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t minimumClocksReductionPercentage; uint32_t 351 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t minOverdriveVDDC; uint32_t 352 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t maxOverdriveVDDC; uint32_t 353 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t overdriveVDDCStep; uint32_t 354 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t hardwarePerformanceLevels; uint32_t 356 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t TDPLimit; uint32_t 357 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t nearTDPLimit; uint32_t 358 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t nearTDPLimitAdjusted; uint32_t 359 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t SQRampingThreshold; uint32_t 360 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t CACLeakage; uint32_t 362 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t TDPAdjustment; uint32_t 365 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t VidMinLimit; uint32_t 366 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t VidMaxLimit; uint32_t 367 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t VidStep; uint32_t 368 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t VidAdjustment; uint32_t 373 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t num_of_entries; uint32_t 374 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t clock[MAX_NUM_CLOCKS]; uint32_t 385 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t clock; uint32_t 386 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t vddc; uint32_t 391 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t size; uint32_t 392 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t options; uint32_t 393 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t flags; uint32_t 394 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h uint32_t num_of_pl; uint32_t 441 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h PHM_PerformanceLevelDesignation designation, uint32_t index, uint32_t 466 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count); uint32_t 57 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t value; uint32_t 58 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t param1; uint32_t 62 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t count; uint32_t 93 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t count; uint32_t 94 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t values[1]; uint32_t 98 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t clk; uint32_t 99 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t v; uint32_t 103 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ecclk; uint32_t 104 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t evclk; uint32_t 105 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t v; uint32_t 109 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t vclk; uint32_t 110 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t dclk; uint32_t 111 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t v; uint32_t 115 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t samclk; uint32_t 116 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t v; uint32_t 120 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t acpclk; uint32_t 121 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t v; uint32_t 125 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t count; /* Number of entries. */ uint32_t 130 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t Voltage; uint32_t 131 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t Sclk; uint32_t 132 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t Mclk; uint32_t 136 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t vclk; uint32_t 137 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t dclk; uint32_t 138 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t v; uint32_t 147 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t acpclk; uint32_t 148 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t v; uint32_t 152 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t count; uint32_t 157 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ecclk; uint32_t 158 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t evclk; uint32_t 159 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t v; uint32_t 163 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t count; uint32_t 183 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t count; /* Number of entries. */ uint32_t 206 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t firmware); uint32_t 209 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t firmware); uint32_t 210 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t (*get_argument)(struct pp_hwmgr *hwmgr); uint32_t 213 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint16_t msg, uint32_t parameter); uint32_t 217 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); uint32_t 226 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t (*get_offsetof)(uint32_t type, uint32_t member); uint32_t 227 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t (*get_mac_definition)(uint32_t value); uint32_t 264 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); uint32_t 265 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); uint32_t 273 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h const uint32_t *msg_id); uint32_t 278 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); uint32_t 279 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); uint32_t 280 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent); uint32_t 281 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed); uint32_t 282 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent); uint32_t 283 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed); uint32_t 293 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time, uint32_t 299 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *); uint32_t 314 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); uint32_t 318 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); uint32_t 320 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); uint32_t 324 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count); uint32_t 325 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock); uint32_t 328 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t virtual_addr_low, uint32_t 329 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t virtual_addr_hi, uint32_t 330 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t mc_addr_low, uint32_t 331 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t mc_addr_hi, uint32_t 332 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t size); uint32_t 339 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size); uint32_t 342 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h long *input, uint32_t size); uint32_t 343 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n); uint32_t 348 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); uint32_t 349 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); uint32_t 375 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */ uint32_t 385 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t count; uint32_t 390 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t samclk; uint32_t 391 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t v; uint32_t 432 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t usBoostPowerLimit; uint32_t 473 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t usBoostPowerLimit; uint32_t 476 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulBoostClock; uint32_t 482 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t platform_tdp; uint32_t 483 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t small_ac_platform_tdp; uint32_t 484 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t platform_tdc; uint32_t 485 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t small_ac_platform_tdc; uint32_t 486 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t apu_tdp; uint32_t 487 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t dgpu_tdp; uint32_t 488 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t dgpu_ulv_power; uint32_t 489 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t tj_max; uint32_t 493 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulCUs; uint32_t 494 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulSustainableSOCPowerLimitLow; uint32_t 495 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulSustainableSOCPowerLimitHigh; uint32_t 496 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulMinSclkLow; uint32_t 497 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulMinSclkHigh; uint32_t 499 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulDClk; uint32_t 500 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulEClk; uint32_t 501 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulSustainableSclk; uint32_t 502 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulSustainableCUs; uint32_t 511 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t sclk; uint32_t 512 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t mclk; uint32_t 513 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t gfxclk; uint32_t 610 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t *power_saving_clock_max; uint32_t 611 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t *power_saving_clock_min; uint32_t 614 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t *od_settings_max; uint32_t 615 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t *od_settings_min; uint32_t 630 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t mclk_sclk_ratio; uint32_t 631 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t sclk_mclk_delta; uint32_t 632 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t vddc_vddci_delta; uint32_t 633 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t min_vddc_for_pcie_gen2; uint32_t 654 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulMinRPM; uint32_t 655 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulMaxRPM; uint32_t 666 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */ uint32_t 685 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ uint32_t 698 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */ uint32_t 699 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ulTargetGfxClk; uint32_t 715 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t SMC; uint32_t 716 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t DMCU; uint32_t 717 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t MC; uint32_t 718 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t NB; uint32_t 735 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t chip_family; uint32_t 736 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t chip_id; uint32_t 737 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t smu_version; uint32_t 742 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t pp_table_version; uint32_t 746 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t soft_pp_table_size; uint32_t 751 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t num_vce_state_tables; uint32_t 756 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t usec_timeout; uint32_t 771 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t num_ps; uint32_t 774 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t fan_ctrl_default_mode; uint32_t 776 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t tmin; uint32_t 778 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t ps_size; uint32_t 784 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t feature_mask; uint32_t 788 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t power_profile_mode; uint32_t 789 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t default_power_profile_mode; uint32_t 790 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t pstate_sclk; uint32_t 791 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t pstate_mclk; uint32_t 793 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t power_limit; uint32_t 794 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t default_power_limit; uint32_t 795 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t workload_mask; uint32_t 796 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t workload_prority[Workload_Policy_Max]; uint32_t 797 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t workload_setting[Workload_Policy_Max]; uint32_t 33 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h uint32_t data; uint32_t 34 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h uint32_t reg; uint32_t 40 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h uint32_t dfy_cntl; uint32_t 41 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h uint32_t dfy_addr_hi, dfy_addr_lo; uint32_t 42 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h uint32_t dfy_size; uint32_t 43 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h uint32_t dfy_data[]; uint32_t 143 drivers/gpu/drm/amd/powerplay/inc/power_state.h uint32_t VCLK; uint32_t 144 drivers/gpu/drm/amd/powerplay/inc/power_state.h uint32_t DCLK; uint32_t 151 drivers/gpu/drm/amd/powerplay/inc/power_state.h uint32_t id; uint32_t 36 drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h unsigned src_id, const uint32_t *iv_entry); uint32_t 42 drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h uint32_t src_id; /* Registered interrupt id */ uint32_t 43 drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h const uint32_t *iv_entry; uint32_t 150 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t CurrLevel_ACP : 4; uint32_t 151 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t CurrLevel_ISP : 4; uint32_t 152 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t CurrLevel_VCN : 4; uint32_t 153 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t CurrLevel_LCLK : 4; uint32_t 154 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t CurrLevel_MP0CLK : 4; uint32_t 155 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t CurrLevel_FCLK : 4; uint32_t 156 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t CurrLevel_SOCCLK : 4; uint32_t 157 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t CurrLevel_DCEFCLK : 4; uint32_t 159 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t TargLevel_ACP : 4; uint32_t 160 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t TargLevel_ISP : 4; uint32_t 161 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t TargLevel_VCN : 4; uint32_t 162 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t TargLevel_LCLK : 4; uint32_t 163 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t TargLevel_MP0CLK : 4; uint32_t 164 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t TargLevel_FCLK : 4; uint32_t 165 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t TargLevel_SOCCLK : 4; uint32_t 166 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t TargLevel_DCEFCLK : 4; uint32_t 168 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t CurrLevel_SHUBCLK : 4; uint32_t 169 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t TargLevel_SHUBCLK : 4; uint32_t 170 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t InUlv : 1; uint32_t 171 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t InS0i2 : 1; uint32_t 172 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t InWhisperMode : 1; uint32_t 173 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t Reserved : 21; uint32_t 175 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t Reserved2[2]; uint32_t 177 drivers/gpu/drm/amd/powerplay/inc/smu10.h uint32_t FeatureStatus[NUM_FEATURES / 32]; uint32_t 33 drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h uint32_t numFractionalBits; uint32_t 70 drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h uint32_t MmHubPadding[7]; uint32_t 105 drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h uint32_t Freq; /* In MHz */ uint32_t 106 drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h uint32_t Vol; /* Millivolts with 2 fractional bits */ uint32_t 289 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Enabled; uint32_t 290 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t SlaveAddress; uint32_t 291 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t ControllerPort; uint32_t 292 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t ControllerName; uint32_t 294 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t ThermalThrottler; uint32_t 295 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t I2cProtocol; uint32_t 296 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t I2cSpeed; uint32_t 300 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t a; uint32_t 301 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t b; uint32_t 302 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t c; uint32_t 306 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t m; uint32_t 307 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t b; uint32_t 311 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t a; uint32_t 312 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t b; uint32_t 313 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t c; uint32_t 362 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Version; uint32_t 365 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t FeaturesToRun[2]; uint32_t 391 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t FitLimit; uint32_t 518 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t DebugOverrides; uint32_t 535 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Reserved[11]; uint32_t 537 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Padding32[3]; uint32_t 606 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t BoardReserved[10]; uint32_t 609 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t MmHubPadding[8]; uint32_t 623 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t MmHubPadding[8]; uint32_t 668 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t ThrottlerStatus ; uint32_t 675 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t MmHubPadding[7]; uint32_t 700 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t MmHubPadding[7]; uint32_t 715 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t MmHubPadding[6]; uint32_t 750 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; uint32_t 751 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; uint32_t 752 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; uint32_t 754 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t VInversion[AVFS_VOLTAGE_COUNT]; uint32_t 761 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; uint32_t 763 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t EnabledAvfsModules; uint32_t 765 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t MmHubPadding[7]; uint32_t 779 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Gfx_PD_Data_limit_a; uint32_t 780 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Gfx_PD_Data_limit_b; uint32_t 781 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Gfx_PD_Data_limit_c; uint32_t 782 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Gfx_PD_Data_error_coeff; uint32_t 783 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Gfx_PD_Data_error_rate_coeff; uint32_t 794 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Soc_PD_Data_limit_a; uint32_t 795 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Soc_PD_Data_limit_b; uint32_t 796 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Soc_PD_Data_limit_c; uint32_t 797 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Soc_PD_Data_error_coeff; uint32_t 798 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Soc_PD_Data_error_rate_coeff; uint32_t 809 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Mem_PD_Data_limit_a; uint32_t 810 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Mem_PD_Data_limit_b; uint32_t 811 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Mem_PD_Data_limit_c; uint32_t 812 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Mem_PD_Data_error_coeff; uint32_t 813 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Mem_PD_Data_error_rate_coeff; uint32_t 824 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Fclk_PD_Data_limit_a; uint32_t 825 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Fclk_PD_Data_limit_b; uint32_t 826 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Fclk_PD_Data_limit_c; uint32_t 827 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Fclk_PD_Data_error_coeff; uint32_t 828 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint32_t Fclk_PD_Data_error_rate_coeff; uint32_t 263 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t SlaveAddress; uint32_t 313 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 339 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t a; // store in IEEE float format in this variable uint32_t 340 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t b; // store in IEEE float format in this variable uint32_t 341 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t c; // store in IEEE float format in this variable uint32_t 345 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t m; // store in IEEE float format in this variable uint32_t 346 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t b; // store in IEEE float format in this variable uint32_t 350 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t a; // store in IEEE float format in this variable uint32_t 351 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t b; // store in IEEE float format in this variable uint32_t 352 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t c; // store in IEEE float format in this variable uint32_t 453 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t Version; uint32_t 456 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t FeaturesToRun[2]; uint32_t 472 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) uint32_t 478 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t ThrottlerControlMask; // See Throtter masks defines uint32_t 506 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t Paddingclks[16]; uint32_t 594 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t DebugOverrides; uint32_t 611 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t PaddingAPCC[6]; //FIXME pending SPEC uint32_t 614 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t Reserved[11]; uint32_t 678 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. uint32_t 699 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t BoardReserved[9]; uint32_t 702 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 717 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 738 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t ThrottlerStatus ; uint32_t 743 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t Padding[4]; uint32_t 746 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 756 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 792 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; uint32_t 793 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; uint32_t 794 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; uint32_t 796 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits uint32_t 803 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units uint32_t 805 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t EnabledAvfsModules[2]; uint32_t 807 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 270 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t SlaveAddress; uint32_t 320 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 346 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t a; // store in IEEE float format in this variable uint32_t 347 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t b; // store in IEEE float format in this variable uint32_t 348 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t c; // store in IEEE float format in this variable uint32_t 352 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t m; // store in IEEE float format in this variable uint32_t 353 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t b; // store in IEEE float format in this variable uint32_t 357 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t a; // store in IEEE float format in this variable uint32_t 358 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t b; // store in IEEE float format in this variable uint32_t 359 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t c; // store in IEEE float format in this variable uint32_t 500 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t DieTemperatureRegisterOffset; uint32_t 502 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Reserved2; uint32_t 504 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Reserved3; uint32_t 506 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Status; uint32_t 515 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t BoardLevelEnergyAccumulator; uint32_t 519 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Version; uint32_t 522 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t FeaturesToRun[2]; uint32_t 545 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) uint32_t 551 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t ThrottlerControlMask; // See Throtter masks defines uint32_t 554 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t FwDStateMask; // See FW DState masks defines uint32_t 593 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Paddingclks[16]; uint32_t 690 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t DebugOverrides; uint32_t 704 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t PaddingAPCC[6]; //FIXME pending SPEC uint32_t 718 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t BtcConfig; uint32_t 724 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Reserved[8]; uint32_t 803 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) uint32_t 810 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t BoardReserved[8]; uint32_t 813 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 827 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 849 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 876 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t ThrottlerStatus ; uint32_t 883 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 895 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 910 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 919 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[32]; // SMU internal use uint32_t 928 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 965 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; uint32_t 966 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; uint32_t 967 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; uint32_t 969 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits uint32_t 976 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units uint32_t 978 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t EnabledAvfsModules[2]; //NV10 - 36 AVFS modules uint32_t 980 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 994 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Gfx_PD_Data_limit_a; // Q16 uint32_t 995 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Gfx_PD_Data_limit_b; // Q16 uint32_t 996 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Gfx_PD_Data_limit_c; // Q16 uint32_t 997 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Gfx_PD_Data_error_coeff; // Q16 uint32_t 998 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 uint32_t 1009 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Soc_PD_Data_limit_a; // Q16 uint32_t 1010 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Soc_PD_Data_limit_b; // Q16 uint32_t 1011 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Soc_PD_Data_limit_c; // Q16 uint32_t 1012 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Soc_PD_Data_error_coeff; // Q16 uint32_t 1013 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Soc_PD_Data_error_rate_coeff; // Q16 uint32_t 1024 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Mem_PD_Data_limit_a; // Q16 uint32_t 1025 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Mem_PD_Data_limit_b; // Q16 uint32_t 1026 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Mem_PD_Data_limit_c; // Q16 uint32_t 1027 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Mem_PD_Data_error_coeff; // Q16 uint32_t 1028 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Mem_PD_Data_error_rate_coeff; // Q16 uint32_t 1030 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t Mem_UpThreshold_Limit; // Q16 uint32_t 1035 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 1080 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint32_t MmHubPadding[8]; // SMU internal use uint32_t 34 drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h uint32_t numFractionalBits; uint32_t 75 drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h uint32_t MmHubPadding[7]; // SMU internal use uint32_t 112 drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h uint32_t Freq; // In MHz uint32_t 113 drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h uint32_t Vol; // Millivolts with 2 fractional bits uint32_t 106 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t Ki; uint32_t 109 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t StatePrecision; uint32_t 110 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t LfPrecision; uint32_t 111 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t LfOffset; uint32_t 112 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t MaxState; uint32_t 113 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t MaxLfFraction; uint32_t 114 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t StateShift; uint32_t 141 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t Digest[5]; uint32_t 142 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t Version; uint32_t 143 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t HeaderSize; uint32_t 144 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t Flags; uint32_t 145 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t EntryPoint; uint32_t 146 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t CodeSize; uint32_t 147 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t ImageSize; uint32_t 149 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t Rtos; uint32_t 150 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t SoftRegisters; uint32_t 151 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t DpmTable; uint32_t 152 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t FanTable; uint32_t 153 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t CacConfigTable; uint32_t 154 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t CacStatusTable; uint32_t 156 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t mcRegisterTable; uint32_t 158 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t mcArbDramTimingTable; uint32_t 160 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t PmFuseTable; uint32_t 161 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t Globals; uint32_t 162 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t Reserved[42]; uint32_t 163 drivers/gpu/drm/amd/powerplay/inc/smu7.h uint32_t Signature; uint32_t 44 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t high; uint32_t 45 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t low; uint32_t 123 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t Ki; uint32_t 126 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t StatePrecision; uint32_t 127 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t LfPrecision; uint32_t 128 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t LfOffset; uint32_t 129 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t MaxState; uint32_t 130 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t MaxLfFraction; uint32_t 131 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t StateShift; uint32_t 138 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t PercentageBusy; uint32_t 144 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t SigmaDeltaAccum; uint32_t 145 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t SigmaDeltaOutput; uint32_t 146 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t SigmaDeltaLevel; uint32_t 148 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t UtilizationSetpoint; uint32_t 170 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t MinimumPerfSclk; uint32_t 196 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t MaxAllowedFrequency; uint32_t 279 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t AvgGpuPower; uint32_t 296 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t RocPower; uint32_t 298 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t last_power; uint32_t 299 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t enableWinAvg; uint32_t 301 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t lkg_acc; uint32_t 305 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t uvd_cac_dclk; uint32_t 306 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t uvd_cac_vclk; uint32_t 307 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t vce_cac_eclk; uint32_t 308 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t samu_cac_samclk; uint32_t 309 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t display_cac_dispclk; uint32_t 310 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t acp_cac_aclk; uint32_t 311 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t unb_cac; uint32_t 313 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t WinTime; uint32_t 365 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t RefClockFrequency; uint32_t 366 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t PmTimerPeriod; uint32_t 367 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t FeatureEnables; uint32_t 369 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t PreVBlankGap; uint32_t 370 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t VBlankTimeout; uint32_t 371 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t TrainTimeGap; uint32_t 372 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t MvddSwitchTime; uint32_t 373 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t LongestAcpiTrainTime; uint32_t 374 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t AcpiDelay; uint32_t 375 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t G5TrainTime; uint32_t 376 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t DelayMpllPwron; uint32_t 377 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t VoltageChangeTimeout; uint32_t 379 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t HandshakeDisables; uint32_t 391 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t AverageGraphicsActivity; uint32_t 392 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t AverageMemoryActivity; uint32_t 393 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t AverageGioActivity; uint32_t 400 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t DRAM_LOG_ADDR_H; uint32_t 401 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t DRAM_LOG_ADDR_L; uint32_t 402 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 403 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 404 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 405 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t UlvEnterCount; uint32_t 406 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t UlvTime; uint32_t 407 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t UcodeLoadStatus; uint32_t 411 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t Reserved; uint32_t 418 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t Digest[5]; uint32_t 419 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t Version; uint32_t 420 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t HeaderSize; uint32_t 421 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t Flags; uint32_t 422 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t EntryPoint; uint32_t 423 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t CodeSize; uint32_t 424 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t ImageSize; uint32_t 426 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t Rtos; uint32_t 427 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t SoftRegisters; uint32_t 428 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t DpmTable; uint32_t 429 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t FanTable; uint32_t 430 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t CacConfigTable; uint32_t 431 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t CacStatusTable; uint32_t 433 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t mcRegisterTable; uint32_t 435 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t mcArbDramTimingTable; uint32_t 437 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t PmFuseTable; uint32_t 438 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t Globals; uint32_t 439 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t UvdDpmTable; uint32_t 440 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t AcpDpmTable; uint32_t 441 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t VceDpmTable; uint32_t 442 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t SamuDpmTable; uint32_t 443 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t UlvSettings; uint32_t 444 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t Reserved[37]; uint32_t 445 drivers/gpu/drm/amd/powerplay/inc/smu71.h uint32_t Signature; uint32_t 49 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MinVddc; uint32_t 50 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MinVddcPhases; uint32_t 52 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SclkFrequency; uint32_t 58 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 59 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 60 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 61 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 62 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CcPwrDynRm; uint32_t 63 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CcPwrDynRm1; uint32_t 78 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Flags; uint32_t 79 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MinVddc; uint32_t 80 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MinVddcPhases; uint32_t 81 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SclkFrequency; uint32_t 86 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CgSpllFuncCntl; uint32_t 87 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CgSpllFuncCntl2; uint32_t 88 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 89 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 90 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 91 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 92 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CcPwrDynRm; uint32_t 93 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CcPwrDynRm1; uint32_t 100 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CcPwrDynRm; uint32_t 101 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t CcPwrDynRm1; uint32_t 105 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Reserved; uint32_t 112 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MinVddc; uint32_t 113 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MinVddcPhases; uint32_t 114 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MinVddci; uint32_t 115 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MinMvdd; uint32_t 117 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MclkFrequency; uint32_t 138 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MpllFuncCntl; uint32_t 139 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MpllFuncCntl_1; uint32_t 140 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MpllFuncCntl_2; uint32_t 141 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MpllAdFuncCntl; uint32_t 142 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MpllDqFuncCntl; uint32_t 143 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MclkPwrmgtCntl; uint32_t 144 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t DllCntl; uint32_t 145 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MpllSs1; uint32_t 146 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MpllSs2; uint32_t 157 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t DownThreshold; uint32_t 158 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t UpThreshold; uint32_t 159 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Reserved; uint32_t 169 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t McArbDramTiming; uint32_t 170 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t McArbDramTiming2; uint32_t 188 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VclkFrequency; uint32_t 189 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t DclkFrequency; uint32_t 202 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Frequency; uint32_t 216 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SclkFrequency; uint32_t 217 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MclkFrequency; uint32_t 218 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VclkFrequency; uint32_t 219 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t DclkFrequency; uint32_t 220 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SamclkFrequency; uint32_t 221 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t AclkFrequency; uint32_t 222 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t EclkFrequency; uint32_t 246 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SystemFlags; uint32_t 249 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SmioMaskVddcVid; uint32_t 250 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SmioMaskVddcPhase; uint32_t 251 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SmioMaskVddciVid; uint32_t 252 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SmioMaskMvddVid; uint32_t 254 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcLevelCount; uint32_t 255 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddciLevelCount; uint32_t 256 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MvddLevelCount; uint32_t 267 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Reserved[5]; uint32_t 276 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SclkStepSize; uint32_t 277 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Smio [SMU71_MAX_ENTRIES_SMIO]; uint32_t 310 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t DisplayCac; uint32_t 332 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t BAPM_TEMP_GRADIENT; uint32_t 334 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t LowSclkInterruptThreshold; uint32_t 335 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddGfxReChkWait; uint32_t 360 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; uint32_t 393 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t RefreshPeriod; uint32_t 407 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t PercentageBusy; uint32_t 413 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SigmaDeltaAccum; uint32_t 414 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SigmaDeltaOutput; uint32_t 415 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SigmaDeltaLevel; uint32_t 417 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t UtilizationSetpoint; uint32_t 439 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t MinimumPerfMclk; uint32_t 477 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t UlvAbortedCount; uint32_t 478 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t UlvTimeStamp; uint32_t 489 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddGfxEnteredCount; uint32_t 490 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddGfxAbortedCount; uint32_t 496 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SavedInterruptMask[2]; uint32_t 559 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t version; uint32_t 560 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t asic_id; uint32_t 563 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t total_size; uint32_t 564 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t num_of_entries; uint32_t 568 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t filler_1[2]; uint32_t 577 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t BufferSize; uint32_t 578 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SamplesLogged; uint32_t 579 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t SampleSize; uint32_t 580 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t AddrL; uint32_t 581 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t AddrH; uint32_t 592 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t temperature; uint32_t 593 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; uint32_t 594 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t filler[4]; uint32_t 600 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcTotalPower; uint32_t 601 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcLeakagePower; uint32_t 602 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcConstantPower; uint32_t 603 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcGfxDynamicPower; uint32_t 604 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcUvdDynamicPower; uint32_t 605 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcVceDynamicPower; uint32_t 606 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcAcpDynamicPower; uint32_t 607 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcPcieDynamicPower; uint32_t 608 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcDceDynamicPower; uint32_t 609 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcCurrent; uint32_t 610 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddcVoltage; uint32_t 611 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddciTotalPower; uint32_t 612 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddciLeakagePower; uint32_t 613 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddciConstantPower; uint32_t 614 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t VddciDynamicPower; uint32_t 615 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Vddr1TotalPower; uint32_t 616 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Vddr1LeakagePower; uint32_t 617 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Vddr1ConstantPower; uint32_t 618 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t Vddr1DynamicPower; uint32_t 619 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t spare[8]; uint32_t 620 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint32_t temperature; uint32_t 73 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Cac; uint32_t 74 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t DynPower; uint32_t 75 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t TotalCurrent; uint32_t 76 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t TotalPower; uint32_t 83 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t value; uint32_t 90 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t high; uint32_t 91 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t low; uint32_t 208 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Ki; uint32_t 211 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t StatePrecision; uint32_t 212 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t LfPrecision; uint32_t 213 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t LfOffset; uint32_t 214 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t MaxState; uint32_t 215 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t MaxLfFraction; uint32_t 216 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t StateShift; uint32_t 222 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t PercentageBusy; uint32_t 228 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t SigmaDeltaAccum; uint32_t 229 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t SigmaDeltaOutput; uint32_t 230 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t SigmaDeltaLevel; uint32_t 232 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t UtilizationSetpoint; uint32_t 254 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t MinimumPerfSclk; uint32_t 280 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t MaxAllowedFrequency; uint32_t 282 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t FilteredSclkFrequency; uint32_t 283 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t LastSclkFrequency; uint32_t 284 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t FilteredSclkFrequencyCnt; uint32_t 379 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t TotalGpuPower; uint32_t 380 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t TdcCurrent; uint32_t 391 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t WinTime; uint32_t 398 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VddcCurrentTelemetry; uint32_t 399 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VddGfxCurrentTelemetry; uint32_t 400 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VddcPowerTelemetry; uint32_t 401 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VddGfxPowerTelemetry; uint32_t 402 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VddciPowerTelemetry; uint32_t 404 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VddcPower; uint32_t 405 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VddGfxPower; uint32_t 406 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VddciPower; uint32_t 408 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t TelemetryCurrent[2]; uint32_t 409 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t TelemetryVoltage[2]; uint32_t 410 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t TelemetryPower[2]; uint32_t 434 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Alpha; uint32_t 459 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t RefClockFrequency; uint32_t 460 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t PmTimerPeriod; uint32_t 461 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t FeatureEnables; uint32_t 463 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t PreVBlankGap; uint32_t 464 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VBlankTimeout; uint32_t 465 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t TrainTimeGap; uint32_t 467 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t MvddSwitchTime; uint32_t 468 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t LongestAcpiTrainTime; uint32_t 469 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t AcpiDelay; uint32_t 470 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t G5TrainTime; uint32_t 471 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t DelayMpllPwron; uint32_t 472 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t VoltageChangeTimeout; uint32_t 474 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t HandshakeDisables; uint32_t 486 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t AverageGraphicsActivity; uint32_t 487 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t AverageMemoryActivity; uint32_t 488 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t AverageGioActivity; uint32_t 500 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t DRAM_LOG_ADDR_H; uint32_t 501 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t DRAM_LOG_ADDR_L; uint32_t 502 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 503 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 504 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 505 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t UlvEnterCount; uint32_t 506 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t UlvTime; uint32_t 507 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t UcodeLoadStatus; uint32_t 508 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Reserved[2]; uint32_t 515 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Digest[5]; uint32_t 516 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Version; uint32_t 517 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t HeaderSize; uint32_t 518 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Flags; uint32_t 519 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t EntryPoint; uint32_t 520 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t CodeSize; uint32_t 521 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t ImageSize; uint32_t 523 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Rtos; uint32_t 524 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t SoftRegisters; uint32_t 525 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t DpmTable; uint32_t 526 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t FanTable; uint32_t 527 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t CacConfigTable; uint32_t 528 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t CacStatusTable; uint32_t 529 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t mcRegisterTable; uint32_t 530 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t mcArbDramTimingTable; uint32_t 531 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t PmFuseTable; uint32_t 532 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Globals; uint32_t 533 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t ClockStretcherTable; uint32_t 534 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Reserved[41]; uint32_t 535 drivers/gpu/drm/amd/powerplay/inc/smu72.h uint32_t Signature; uint32_t 50 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SclkFrequency; uint32_t 56 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 57 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 58 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 59 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 60 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CcPwrDynRm; uint32_t 61 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CcPwrDynRm1; uint32_t 75 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Flags; uint32_t 77 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SclkFrequency; uint32_t 82 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CgSpllFuncCntl; uint32_t 83 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CgSpllFuncCntl2; uint32_t 84 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 85 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 86 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 87 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 88 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CcPwrDynRm; uint32_t 89 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CcPwrDynRm1; uint32_t 95 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CcPwrDynRm; uint32_t 96 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CcPwrDynRm1; uint32_t 100 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Reserved; uint32_t 107 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MinMvdd; uint32_t 109 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MclkFrequency; uint32_t 130 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MpllFuncCntl; uint32_t 131 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MpllFuncCntl_1; uint32_t 132 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MpllFuncCntl_2; uint32_t 133 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MpllAdFuncCntl; uint32_t 134 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MpllDqFuncCntl; uint32_t 135 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MclkPwrmgtCntl; uint32_t 136 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t DllCntl; uint32_t 137 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MpllSs1; uint32_t 138 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MpllSs2; uint32_t 148 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t DownThreshold; uint32_t 149 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t UpThreshold; uint32_t 150 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Reserved; uint32_t 157 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t McArbDramTiming; uint32_t 158 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t McArbDramTiming2; uint32_t 173 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VclkFrequency; uint32_t 174 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t DclkFrequency; uint32_t 185 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Frequency; uint32_t 194 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SclkFrequency; uint32_t 195 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MclkFrequency; uint32_t 196 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VclkFrequency; uint32_t 197 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t DclkFrequency; uint32_t 198 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SamclkFrequency; uint32_t 199 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t AclkFrequency; uint32_t 200 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t EclkFrequency; uint32_t 222 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SystemFlags; uint32_t 225 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VRConfig; uint32_t 226 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SmioMask1; uint32_t 227 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SmioMask2; uint32_t 231 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcLevelCount; uint32_t 232 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddciLevelCount; uint32_t 233 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddGfxLevelCount; uint32_t 234 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MvddLevelCount; uint32_t 262 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Reserved[4]; uint32_t 276 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SclkStepSize; uint32_t 277 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Smio[SMU72_MAX_ENTRIES_SMIO]; uint32_t 333 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t BAPM_TEMP_GRADIENT; uint32_t 335 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t LowSclkInterruptThreshold; uint32_t 336 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddGfxReChkWait; uint32_t 364 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; uint32_t 396 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t RefreshPeriod; uint32_t 409 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t PercentageBusy; uint32_t 415 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SigmaDeltaAccum; uint32_t 416 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SigmaDeltaOutput; uint32_t 417 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SigmaDeltaLevel; uint32_t 419 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t UtilizationSetpoint; uint32_t 441 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MinimumPerfMclk; uint32_t 487 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t UlvAbortedCount; uint32_t 488 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t UlvTimeStamp; uint32_t 494 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t GPU_DBG[3]; uint32_t 495 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MEC_BaseAddress_Hi; uint32_t 496 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MEC_BaseAddress_Lo; uint32_t 497 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; uint32_t 498 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; uint32_t 499 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t CP_INT_CNTL; uint32_t 510 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddGfxEnteredCount; uint32_t 511 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddGfxAbortedCount; uint32_t 513 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddGfxVid; uint32_t 524 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t FilteredIddc; uint32_t 525 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t IddcLimit; uint32_t 526 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t IddcHyst; uint32_t 536 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t FilteredPkgPwr; uint32_t 537 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Limit; uint32_t 538 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Hyst; uint32_t 539 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t LimitFromDriver; uint32_t 546 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t source_powers[SMU72_DTE_SOURCES]; uint32_t 547 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t source_powers_last[SMU72_DTE_SOURCES]; uint32_t 566 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t measured_temperature; uint32_t 573 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SavedInterruptMask[2]; uint32_t 626 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t version; uint32_t 627 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t asic_id; uint32_t 630 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t total_size; uint32_t 631 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t num_of_entries; uint32_t 635 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t filler_1[2]; uint32_t 644 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t BufferSize; uint32_t 645 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SamplesLogged; uint32_t 646 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t SampleSize; uint32_t 647 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t AddrL; uint32_t 648 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t AddrH; uint32_t 656 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t temperature; uint32_t 657 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; uint32_t 663 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcTotalPower; uint32_t 664 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcLeakagePower; uint32_t 665 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcConstantPower; uint32_t 666 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcGfxDynamicPower; uint32_t 667 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcUvdDynamicPower; uint32_t 668 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcVceDynamicPower; uint32_t 669 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcAcpDynamicPower; uint32_t 670 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcPcieDynamicPower; uint32_t 671 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcDceDynamicPower; uint32_t 672 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcCurrent; uint32_t 673 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddcVoltage; uint32_t 674 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddciTotalPower; uint32_t 675 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddciLeakagePower; uint32_t 676 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddciConstantPower; uint32_t 677 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t VddciDynamicPower; uint32_t 678 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Vddr1TotalPower; uint32_t 679 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Vddr1LeakagePower; uint32_t 680 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Vddr1ConstantPower; uint32_t 681 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t Vddr1DynamicPower; uint32_t 682 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t spare[4]; uint32_t 683 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t temperature; uint32_t 694 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t P_scalar_acc; uint32_t 695 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t P_calc_max; uint32_t 696 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t P_calc_acc; uint32_t 699 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t I_calc_max; uint32_t 700 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t I_calc_acc; uint32_t 701 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t I_calc_acc_vddci; uint32_t 702 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t V_calc_noload_acc; uint32_t 703 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t V_calc_load_acc; uint32_t 704 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t V_calc_noload_acc_vddci; uint32_t 705 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t P_meas_acc; uint32_t 706 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t V_meas_noload_acc; uint32_t 707 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t V_meas_load_acc; uint32_t 708 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t I_meas_acc; uint32_t 709 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t P_meas_acc_vddci; uint32_t 710 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t V_meas_noload_acc_vddci; uint32_t 711 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t V_meas_load_acc_vddci; uint32_t 712 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t I_meas_acc_vddci; uint32_t 721 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t P_vddci_acc; uint32_t 722 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t P_vddr1_acc; uint32_t 723 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t P_nte1_acc; uint32_t 724 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t PkgPwr_max; uint32_t 725 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t PkgPwr_acc; uint32_t 726 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MclkSwitchingTime_max; uint32_t 727 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t MclkSwitchingTime_acc; uint32_t 728 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t FanPwm_acc; uint32_t 729 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t FanRpm_acc; uint32_t 731 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t AccCnt; uint32_t 66 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Cac; uint32_t 67 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t DynPower; uint32_t 68 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t TotalCurrent; uint32_t 69 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t TotalPower; uint32_t 77 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t value; uint32_t 84 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t high; uint32_t 85 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t low; uint32_t 204 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Ki; uint32_t 207 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t StatePrecision; uint32_t 209 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t LfPrecision; uint32_t 210 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t LfOffset; uint32_t 211 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t MaxState; uint32_t 212 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t MaxLfFraction; uint32_t 213 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t StateShift; uint32_t 220 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t PercentageBusy; uint32_t 226 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t SigmaDeltaAccum; uint32_t 227 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t SigmaDeltaOutput; uint32_t 228 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t SigmaDeltaLevel; uint32_t 230 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t UtilizationSetpoint; uint32_t 252 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t MinimumPerfSclk; uint32_t 278 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t MaxAllowedFrequency; uint32_t 280 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t FilteredSclkFrequency; uint32_t 281 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t LastSclkFrequency; uint32_t 282 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t FilteredSclkFrequencyCnt; uint32_t 288 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t LedAndMask; uint32_t 292 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t CurrentFps; uint32_t 293 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t FilteredFps; uint32_t 294 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t FrameCount; uint32_t 295 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t FrameCountLast; uint32_t 316 drivers/gpu/drm/amd/powerplay/inc/smu73.h typedef uint32_t SMU_VoltageLevel; uint32_t 401 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t GpuPower; uint32_t 403 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t VddcPower; uint32_t 404 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t VddcVoltage; uint32_t 405 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t VddcCurrent; uint32_t 407 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t MvddPower; uint32_t 408 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t MvddVoltage; uint32_t 409 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t MvddCurrent; uint32_t 411 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t RocPower; uint32_t 441 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t RefClockFrequency; uint32_t 442 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t PmTimerPeriod; uint32_t 443 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t FeatureEnables; uint32_t 445 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t PreVBlankGap; uint32_t 446 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t VBlankTimeout; uint32_t 447 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t TrainTimeGap; uint32_t 449 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t MvddSwitchTime; uint32_t 450 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t LongestAcpiTrainTime; uint32_t 451 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t AcpiDelay; uint32_t 452 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t G5TrainTime; uint32_t 453 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t DelayMpllPwron; uint32_t 454 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t VoltageChangeTimeout; uint32_t 456 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t HandshakeDisables; uint32_t 468 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t AverageGraphicsActivity; uint32_t 469 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t AverageMemoryActivity; uint32_t 470 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t AverageGioActivity; uint32_t 482 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t DRAM_LOG_ADDR_H; uint32_t 483 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t DRAM_LOG_ADDR_L; uint32_t 484 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 485 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 486 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 487 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t UlvEnterCount; uint32_t 488 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t UlvTime; uint32_t 489 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t UcodeLoadStatus; uint32_t 490 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Reserved[2]; uint32_t 498 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Digest[5]; uint32_t 499 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Version; uint32_t 500 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t HeaderSize; uint32_t 501 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Flags; uint32_t 502 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t EntryPoint; uint32_t 503 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t CodeSize; uint32_t 504 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t ImageSize; uint32_t 506 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Rtos; uint32_t 507 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t SoftRegisters; uint32_t 508 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t DpmTable; uint32_t 509 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t FanTable; uint32_t 510 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t CacConfigTable; uint32_t 511 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t CacStatusTable; uint32_t 514 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t mcRegisterTable; uint32_t 517 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t mcArbDramTimingTable; uint32_t 522 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t PmFuseTable; uint32_t 523 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Globals; uint32_t 524 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t ClockStretcherTable; uint32_t 525 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Reserved[41]; uint32_t 526 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint32_t Signature; uint32_t 47 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MinVoltage; uint32_t 49 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SclkFrequency; uint32_t 54 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 55 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 56 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 57 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 58 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CcPwrDynRm; uint32_t 59 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CcPwrDynRm1; uint32_t 73 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Flags; uint32_t 74 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MinVoltage; uint32_t 75 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SclkFrequency; uint32_t 80 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CgSpllFuncCntl; uint32_t 81 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CgSpllFuncCntl2; uint32_t 82 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 83 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 84 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 85 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 86 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CcPwrDynRm; uint32_t 87 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CcPwrDynRm1; uint32_t 93 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CcPwrDynRm; uint32_t 94 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CcPwrDynRm1; uint32_t 98 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Reserved; uint32_t 105 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MinVoltage; uint32_t 106 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MinMvdd; uint32_t 108 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MclkFrequency; uint32_t 133 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t DownThreshold; uint32_t 134 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t UpThreshold; uint32_t 135 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Reserved; uint32_t 144 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t McArbDramTiming; uint32_t 145 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t McArbDramTiming2; uint32_t 164 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VclkFrequency; uint32_t 165 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t DclkFrequency; uint32_t 166 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MinVoltage; uint32_t 177 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Frequency; uint32_t 178 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MinVoltage; uint32_t 187 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SclkFrequency; uint32_t 188 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MclkFrequency; uint32_t 189 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VclkFrequency; uint32_t 190 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t DclkFrequency; uint32_t 191 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SamclkFrequency; uint32_t 192 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t AclkFrequency; uint32_t 193 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t EclkFrequency; uint32_t 216 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SystemFlags; uint32_t 219 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VRConfig; uint32_t 220 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SmioMask1; uint32_t 221 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SmioMask2; uint32_t 225 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MvddLevelCount; uint32_t 246 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Reserved[4]; uint32_t 260 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SclkStepSize; uint32_t 261 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Smio [SMU73_MAX_ENTRIES_SMIO]; uint32_t 330 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t GeminiApertureHigh; uint32_t 331 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t GeminiApertureLow; uint32_t 341 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t spare123[2]; uint32_t 351 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t BAPM_TEMP_GRADIENT; uint32_t 353 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t LowSclkInterruptThreshold; uint32_t 354 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddGfxReChkWait; uint32_t 387 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t RefreshPeriod; uint32_t 403 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t PercentageBusy; uint32_t 409 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SigmaDeltaAccum; uint32_t 410 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SigmaDeltaOutput; uint32_t 411 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SigmaDeltaLevel; uint32_t 413 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t UtilizationSetpoint; uint32_t 435 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MinimumPerfMclk; uint32_t 482 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t UlvAbortedCount; uint32_t 483 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t UlvTimeStamp; uint32_t 490 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t GPU_DBG[3]; uint32_t 491 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MEC_BaseAddress_Hi; uint32_t 492 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MEC_BaseAddress_Lo; uint32_t 493 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; uint32_t 494 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; uint32_t 495 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t CP_INT_CNTL; uint32_t 507 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddGfxEnteredCount; uint32_t 508 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddGfxAbortedCount; uint32_t 510 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddGfxVid; uint32_t 521 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t FilteredIddc; uint32_t 522 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t IddcLimit; uint32_t 523 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t IddcHyst; uint32_t 533 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t FilteredPkgPwr; uint32_t 534 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Limit; uint32_t 535 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Hyst; uint32_t 536 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t LimitFromDriver; uint32_t 543 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t source_powers[SMU73_DTE_SOURCES]; uint32_t 544 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t source_powers_last[SMU73_DTE_SOURCES]; uint32_t 563 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t measured_temperature; uint32_t 570 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SavedInterruptMask[2]; uint32_t 582 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t b; uint32_t 650 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t PsmCharzFreq; uint32_t 655 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t EnabledAvfsModules; uint32_t 661 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t version; uint32_t 662 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t asic_id; uint32_t 665 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t total_size; uint32_t 666 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t num_of_entries; uint32_t 670 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t filler_1[2]; uint32_t 679 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t BufferSize; uint32_t 680 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SamplesLogged; uint32_t 681 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t SampleSize; uint32_t 682 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t AddrL; uint32_t 683 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t AddrH; uint32_t 691 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t temperature; uint32_t 692 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; uint32_t 698 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcTotalPower; uint32_t 699 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcLeakagePower; uint32_t 700 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcConstantPower; uint32_t 701 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcGfxDynamicPower; uint32_t 702 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcUvdDynamicPower; uint32_t 703 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcVceDynamicPower; uint32_t 704 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcAcpDynamicPower; uint32_t 705 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcPcieDynamicPower; uint32_t 706 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcDceDynamicPower; uint32_t 707 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcCurrent; uint32_t 708 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddcVoltage; uint32_t 709 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddciTotalPower; uint32_t 710 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddciLeakagePower; uint32_t 711 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddciConstantPower; uint32_t 712 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t VddciDynamicPower; uint32_t 713 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Vddr1TotalPower; uint32_t 714 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Vddr1LeakagePower; uint32_t 715 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Vddr1ConstantPower; uint32_t 716 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Vddr1DynamicPower; uint32_t 717 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t spare[4]; uint32_t 718 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t temperature; uint32_t 728 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t T_hbm_acc; uint32_t 731 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t I_calc_max; uint32_t 732 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t I_calc_acc; uint32_t 733 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t P_meas_acc; uint32_t 734 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t V_meas_load_acc; uint32_t 735 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t I_meas_acc; uint32_t 736 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t P_meas_acc_vddci; uint32_t 737 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t V_meas_load_acc_vddci; uint32_t 738 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t I_meas_acc_vddci; uint32_t 746 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t P_roc_acc; uint32_t 747 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t PkgPwr_max; uint32_t 748 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t PkgPwr_acc; uint32_t 749 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MclkSwitchingTime_max; uint32_t 750 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t MclkSwitchingTime_acc; uint32_t 751 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t FanPwm_acc; uint32_t 752 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t FanRpm_acc; uint32_t 753 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Gfx_busy_acc; uint32_t 754 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Mc_busy_acc; uint32_t 755 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t Fps_acc; uint32_t 757 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint32_t AccCnt; uint32_t 98 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Cac; uint32_t 99 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t DynPower; uint32_t 100 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t TotalCurrent; uint32_t 101 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t TotalPower; uint32_t 108 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t value; uint32_t 115 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t high; uint32_t 116 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t low; uint32_t 235 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Ki; uint32_t 238 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t StatePrecision; uint32_t 239 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t LfPrecision; uint32_t 240 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t LfOffset; uint32_t 241 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t MaxState; uint32_t 242 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t MaxLfFraction; uint32_t 243 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t StateShift; uint32_t 249 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t PercentageBusy; uint32_t 255 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t SigmaDeltaAccum; uint32_t 256 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t SigmaDeltaOutput; uint32_t 257 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t SigmaDeltaLevel; uint32_t 259 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t UtilizationSetpoint; uint32_t 281 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t MinimumPerfSclk; uint32_t 307 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t MaxAllowedFrequency; uint32_t 309 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t FilteredSclkFrequency; uint32_t 310 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t LastSclkFrequency; uint32_t 311 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t FilteredSclkFrequencyCnt; uint32_t 318 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t CurrentFps; uint32_t 319 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t FilteredFps; uint32_t 320 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t FrameCount; uint32_t 321 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t FrameCountLast; uint32_t 342 drivers/gpu/drm/amd/powerplay/inc/smu74.h typedef uint32_t SMU_VoltageLevel; uint32_t 424 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t TotalGpuPower; uint32_t 425 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t TdcCurrent; uint32_t 436 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t WinTime; uint32_t 443 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VddcCurrentTelemetry; uint32_t 444 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VddGfxCurrentTelemetry; uint32_t 445 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VddcPowerTelemetry; uint32_t 446 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VddGfxPowerTelemetry; uint32_t 447 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VddciPowerTelemetry; uint32_t 449 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VddcPower; uint32_t 450 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VddGfxPower; uint32_t 451 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VddciPower; uint32_t 453 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t TelemetryCurrent[2]; uint32_t 454 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t TelemetryVoltage[2]; uint32_t 455 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t TelemetryPower[2]; uint32_t 479 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Alpha; uint32_t 503 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t RefClockFrequency; uint32_t 504 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t PmTimerPeriod; uint32_t 505 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t FeatureEnables; uint32_t 507 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t PreVBlankGap; uint32_t 508 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VBlankTimeout; uint32_t 509 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t TrainTimeGap; uint32_t 511 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t MvddSwitchTime; uint32_t 512 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t LongestAcpiTrainTime; uint32_t 513 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t AcpiDelay; uint32_t 514 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t G5TrainTime; uint32_t 515 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t DelayMpllPwron; uint32_t 516 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VoltageChangeTimeout; uint32_t 518 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t HandshakeDisables; uint32_t 530 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t AverageGraphicsActivity; uint32_t 531 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t AverageMemoryActivity; uint32_t 532 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t AverageGioActivity; uint32_t 544 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t DRAM_LOG_ADDR_H; uint32_t 545 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t DRAM_LOG_ADDR_L; uint32_t 546 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 547 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 548 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 549 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t UlvEnterCount; uint32_t 550 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t UlvTime; uint32_t 551 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t UcodeLoadStatus; uint32_t 552 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t AllowMvddSwitch; uint32_t 560 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Digest[5]; uint32_t 561 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Version; uint32_t 562 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t HeaderSize; uint32_t 563 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Flags; uint32_t 564 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t EntryPoint; uint32_t 565 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t CodeSize; uint32_t 566 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t ImageSize; uint32_t 568 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Rtos; uint32_t 569 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t SoftRegisters; uint32_t 570 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t DpmTable; uint32_t 571 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t FanTable; uint32_t 572 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t CacConfigTable; uint32_t 573 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t CacStatusTable; uint32_t 575 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t mcRegisterTable; uint32_t 577 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t mcArbDramTimingTable; uint32_t 579 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t PmFuseTable; uint32_t 580 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Globals; uint32_t 581 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t ClockStretcherTable; uint32_t 582 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t VftTable; uint32_t 583 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Reserved1; uint32_t 584 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t AvfsTable; uint32_t 585 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t AvfsCksOffGbvTable; uint32_t 586 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t AvfsMeanNSigma; uint32_t 587 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t AvfsSclkOffsetTable; uint32_t 588 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Reserved[16]; uint32_t 589 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Signature; uint32_t 807 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t spare; uint32_t 817 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint32_t Aconstant[3]; uint32_t 68 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SclkFrequency; uint32_t 88 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 89 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 90 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CcPwrDynRm; uint32_t 91 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CcPwrDynRm1; uint32_t 106 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Flags; uint32_t 108 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SclkFrequency; uint32_t 113 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CcPwrDynRm; uint32_t 114 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CcPwrDynRm1; uint32_t 122 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CcPwrDynRm; uint32_t 123 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CcPwrDynRm1; uint32_t 135 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t MinMvdd; uint32_t 137 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t MclkFrequency; uint32_t 161 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t DownThreshold; uint32_t 162 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t UpThreshold; uint32_t 170 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t McArbDramTiming; uint32_t 171 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t McArbDramTiming2; uint32_t 185 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VclkFrequency; uint32_t 186 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t DclkFrequency; uint32_t 196 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Frequency; uint32_t 205 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SclkFrequency; uint32_t 206 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t MclkFrequency; uint32_t 207 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VclkFrequency; uint32_t 208 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t DclkFrequency; uint32_t 209 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SamclkFrequency; uint32_t 210 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t AclkFrequency; uint32_t 211 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t EclkFrequency; uint32_t 228 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t b; uint32_t 242 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SystemFlags; uint32_t 244 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VRConfig; uint32_t 245 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SmioMask1; uint32_t 246 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SmioMask2; uint32_t 250 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t MvddLevelCount; uint32_t 279 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Reserved[1]; uint32_t 294 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SclkStepSize; uint32_t 295 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Smio[SMU74_MAX_ENTRIES_SMIO]; uint32_t 353 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t LowSclkInterruptThreshold; uint32_t 354 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddGfxReChkWait; uint32_t 366 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CurrSclkPllRange; uint32_t 390 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t RefreshPeriod; uint32_t 403 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t PercentageBusy; uint32_t 409 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SigmaDeltaAccum; uint32_t 410 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SigmaDeltaOutput; uint32_t 411 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SigmaDeltaLevel; uint32_t 413 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t UtilizationSetpoint; uint32_t 435 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t MinimumPerfMclk; uint32_t 477 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t UlvAbortedCount; uint32_t 478 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t UlvTimeStamp; uint32_t 484 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t GPU_DBG[3]; uint32_t 485 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t MEC_BaseAddress_Hi; uint32_t 486 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t MEC_BaseAddress_Lo; uint32_t 487 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; uint32_t 488 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; uint32_t 489 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t CP_INT_CNTL; uint32_t 500 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddGfxEnteredCount; uint32_t 501 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddGfxAbortedCount; uint32_t 503 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddGfxVid; uint32_t 514 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t FilteredIddc; uint32_t 515 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t IddcLimit; uint32_t 516 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t IddcHyst; uint32_t 526 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t FilteredPkgPwr; uint32_t 527 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Limit; uint32_t 528 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Hyst; uint32_t 529 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t LimitFromDriver; uint32_t 536 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t source_powers[SMU74_DTE_SOURCES]; uint32_t 537 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t source_powers_last[SMU74_DTE_SOURCES]; uint32_t 556 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t measured_temperature; uint32_t 563 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SavedInterruptMask[2]; uint32_t 615 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t PsmCharzFreq; uint32_t 620 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t EnabledAvfsModules; uint32_t 626 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t version; uint32_t 627 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t asic_id; uint32_t 630 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t total_size; uint32_t 631 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t num_of_entries; uint32_t 635 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t filler_1[2]; uint32_t 644 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t BufferSize; uint32_t 645 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SamplesLogged; uint32_t 646 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t SampleSize; uint32_t 647 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t AddrL; uint32_t 648 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t AddrH; uint32_t 659 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t temperature; uint32_t 660 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; uint32_t 666 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcTotalPower; uint32_t 667 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcLeakagePower; uint32_t 668 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcConstantPower; uint32_t 669 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcGfxDynamicPower; uint32_t 670 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcUvdDynamicPower; uint32_t 671 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcVceDynamicPower; uint32_t 672 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcAcpDynamicPower; uint32_t 673 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcPcieDynamicPower; uint32_t 674 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcDceDynamicPower; uint32_t 675 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcCurrent; uint32_t 676 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddcVoltage; uint32_t 677 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddciTotalPower; uint32_t 678 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddciLeakagePower; uint32_t 679 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddciConstantPower; uint32_t 680 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t VddciDynamicPower; uint32_t 681 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Vddr1TotalPower; uint32_t 682 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Vddr1LeakagePower; uint32_t 683 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Vddr1ConstantPower; uint32_t 684 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t Vddr1DynamicPower; uint32_t 685 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t spare[4]; uint32_t 686 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t temperature; uint32_t 696 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t P_scalar_acc; uint32_t 697 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t P_calc_max; uint32_t 698 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t P_calc_acc; uint32_t 700 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t I_calc_max; uint32_t 701 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t I_calc_acc; uint32_t 702 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t I_calc_acc_vddci; uint32_t 703 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t V_calc_noload_acc; uint32_t 704 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t V_calc_load_acc; uint32_t 705 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t V_calc_noload_acc_vddci; uint32_t 706 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t P_meas_acc; uint32_t 707 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t V_meas_noload_acc; uint32_t 708 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t V_meas_load_acc; uint32_t 709 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t I_meas_acc; uint32_t 710 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t P_meas_acc_vddci; uint32_t 711 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t V_meas_noload_acc_vddci; uint32_t 712 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t V_meas_load_acc_vddci; uint32_t 713 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t I_meas_acc_vddci; uint32_t 720 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t P_vddci_acc; uint32_t 721 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t P_vddr1_acc; uint32_t 722 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t P_nte1_acc; uint32_t 723 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t PkgPwr_max; uint32_t 724 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t PkgPwr_acc; uint32_t 725 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t MclkSwitchingTime_max; uint32_t 726 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t MclkSwitchingTime_acc; uint32_t 727 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t FanPwm_acc; uint32_t 728 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t FanRpm_acc; uint32_t 730 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint32_t AccCnt; uint32_t 29 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t high; uint32_t 30 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t low; uint32_t 169 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Ki; uint32_t 172 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t StatePrecision; uint32_t 173 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t LfPrecision; uint32_t 174 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t LfOffset; uint32_t 175 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t MaxState; uint32_t 176 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t MaxLfFraction; uint32_t 177 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t StateShift; uint32_t 183 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t PercentageBusy; uint32_t 189 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t SigmaDeltaAccum; uint32_t 190 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t SigmaDeltaOutput; uint32_t 191 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t SigmaDeltaLevel; uint32_t 193 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t UtilizationSetpoint; uint32_t 215 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t MinimumPerfSclk; uint32_t 241 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t MaxAllowedFrequency; uint32_t 243 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t FilteredSclkFrequency; uint32_t 244 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t LastSclkFrequency; uint32_t 245 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t FilteredSclkFrequencyCnt; uint32_t 257 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t CurrentFps; uint32_t 258 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t FilteredFps; uint32_t 259 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t FrameCount; uint32_t 260 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t FrameCountLast; uint32_t 281 drivers/gpu/drm/amd/powerplay/inc/smu75.h typedef uint32_t SMU_VoltageLevel; uint32_t 356 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t GpuPower; uint32_t 358 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t VddcPower; uint32_t 359 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t VddcVoltage; uint32_t 360 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t VddcCurrent; uint32_t 362 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t VddciPower; uint32_t 363 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t VddciVoltage; uint32_t 364 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t VddciCurrent; uint32_t 366 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t RocPower; uint32_t 397 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t RefClockFrequency; uint32_t 398 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t PmTimerPeriod; uint32_t 399 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t FeatureEnables; uint32_t 401 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t PreVBlankGap; uint32_t 402 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t VBlankTimeout; uint32_t 403 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t TrainTimeGap; uint32_t 404 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t MvddSwitchTime; uint32_t 405 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t LongestAcpiTrainTime; uint32_t 406 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AcpiDelay; uint32_t 407 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t G5TrainTime; uint32_t 408 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t DelayMpllPwron; uint32_t 409 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t VoltageChangeTimeout; uint32_t 411 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t HandshakeDisables; uint32_t 423 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AverageGraphicsActivity; uint32_t 424 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AverageMemoryActivity; uint32_t 425 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AverageGioActivity; uint32_t 437 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t DRAM_LOG_ADDR_H; uint32_t 438 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t DRAM_LOG_ADDR_L; uint32_t 439 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 440 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 441 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 442 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t UlvEnterCount; uint32_t 443 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t UlvTime; uint32_t 444 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t UcodeLoadStatus; uint32_t 445 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AllowMvddSwitch; uint32_t 453 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Digest[5]; uint32_t 454 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Version; uint32_t 455 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t HeaderSize; uint32_t 456 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Flags; uint32_t 457 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t EntryPoint; uint32_t 458 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t CodeSize; uint32_t 459 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t ImageSize; uint32_t 461 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Rtos; uint32_t 462 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t SoftRegisters; uint32_t 463 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t DpmTable; uint32_t 464 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t FanTable; uint32_t 465 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t CacConfigTable; uint32_t 466 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t CacStatusTable; uint32_t 467 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t mcRegisterTable; uint32_t 468 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t mcArbDramTimingTable; uint32_t 469 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t PmFuseTable; uint32_t 470 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Globals; uint32_t 471 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t ClockStretcherTable; uint32_t 472 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t VftTable; uint32_t 473 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Reserved1; uint32_t 474 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AvfsCksOff_AvfsGbvTable; uint32_t 475 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AvfsCksOff_BtcGbvTable; uint32_t 476 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t MM_AvfsTable; uint32_t 477 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t PowerSharingTable; uint32_t 478 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AvfsTable; uint32_t 479 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AvfsCksOffGbvTable; uint32_t 480 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AvfsMeanNSigma; uint32_t 481 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t AvfsSclkOffsetTable; uint32_t 482 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Reserved[12]; uint32_t 483 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Signature; uint32_t 700 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t spare; uint32_t 735 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t Aconstant[3]; uint32_t 750 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t EnergyCounter; uint32_t 751 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint32_t EngeryThreshold; uint32_t 66 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SclkFrequency; uint32_t 88 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 89 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 90 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CcPwrDynRm; uint32_t 91 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CcPwrDynRm1; uint32_t 111 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Flags; uint32_t 113 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SclkFrequency; uint32_t 118 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CcPwrDynRm; uint32_t 119 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CcPwrDynRm1; uint32_t 127 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CcPwrDynRm; uint32_t 128 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CcPwrDynRm1; uint32_t 140 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t MinMvdd; uint32_t 142 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t MclkFrequency; uint32_t 171 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t DownThreshold; uint32_t 172 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t UpThreshold; uint32_t 182 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t McArbDramTiming; uint32_t 183 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t McArbDramTiming2; uint32_t 184 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t McArbBurstTime; uint32_t 185 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t McArbRfshRate; uint32_t 186 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t McArbMisc3; uint32_t 199 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VclkFrequency; uint32_t 200 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t DclkFrequency; uint32_t 211 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Frequency; uint32_t 220 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SclkFrequency; uint32_t 221 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t MclkFrequency; uint32_t 222 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VclkFrequency; uint32_t 223 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t DclkFrequency; uint32_t 224 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SamclkFrequency; uint32_t 225 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t AclkFrequency; uint32_t 226 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t EclkFrequency; uint32_t 246 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SystemFlags; uint32_t 248 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VRConfig; uint32_t 249 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SmioMask1; uint32_t 250 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SmioMask2; uint32_t 254 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t MvddLevelCount; uint32_t 285 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Reserved; uint32_t 300 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SclkStepSize; uint32_t 301 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Smio [SMU75_MAX_ENTRIES_SMIO]; uint32_t 359 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t LowSclkInterruptThreshold; uint32_t 360 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddGfxReChkWait; uint32_t 372 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CurrSclkPllRange; uint32_t 396 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t RefreshPeriod; uint32_t 410 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t PercentageBusy; uint32_t 416 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SigmaDeltaAccum; uint32_t 417 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SigmaDeltaOutput; uint32_t 418 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SigmaDeltaLevel; uint32_t 420 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t UtilizationSetpoint; uint32_t 442 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t MinimumPerfMclk; uint32_t 475 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t HbmTempRegBackup; uint32_t 489 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t UlvAbortedCount; uint32_t 490 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t UlvTimeStamp; uint32_t 496 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t GPU_DBG[3]; uint32_t 497 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t MEC_BaseAddress_Hi; uint32_t 498 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t MEC_BaseAddress_Lo; uint32_t 499 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; uint32_t 500 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; uint32_t 501 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t CP_INT_CNTL; uint32_t 512 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddGfxEnteredCount; uint32_t 513 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddGfxAbortedCount; uint32_t 515 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddGfxVid; uint32_t 526 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t FilteredIddc; uint32_t 527 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t IddcLimit; uint32_t 528 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t IddcHyst; uint32_t 538 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t FilteredPkgPwr; uint32_t 539 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Limit; uint32_t 540 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Hyst; uint32_t 541 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t LimitFromDriver; uint32_t 546 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t EnergyCount; uint32_t 547 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t PSACTCount; uint32_t 557 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t source_powers[SMU75_DTE_SOURCES]; uint32_t 558 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t source_powers_last[SMU75_DTE_SOURCES]; uint32_t 577 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t measured_temperature; uint32_t 584 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SavedInterruptMask[2]; uint32_t 642 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t PsmCharzFreq; uint32_t 647 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t EnabledAvfsModules; uint32_t 655 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t version; uint32_t 656 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t asic_id; uint32_t 659 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t total_size; uint32_t 660 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t num_of_entries; uint32_t 664 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t filler_1[2]; uint32_t 673 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t BufferSize; uint32_t 674 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SamplesLogged; uint32_t 675 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t SampleSize; uint32_t 676 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t AddrL; uint32_t 677 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t AddrH; uint32_t 688 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t temperature; uint32_t 689 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; uint32_t 695 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcTotalPower; uint32_t 696 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcLeakagePower; uint32_t 697 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcConstantPower; uint32_t 698 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcGfxDynamicPower; uint32_t 699 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcUvdDynamicPower; uint32_t 700 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcVceDynamicPower; uint32_t 701 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcAcpDynamicPower; uint32_t 702 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcPcieDynamicPower; uint32_t 703 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcDceDynamicPower; uint32_t 704 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcCurrent; uint32_t 705 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddcVoltage; uint32_t 706 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddciTotalPower; uint32_t 707 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddciLeakagePower; uint32_t 708 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddciConstantPower; uint32_t 709 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t VddciDynamicPower; uint32_t 710 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Vddr1TotalPower; uint32_t 711 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Vddr1LeakagePower; uint32_t 712 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Vddr1ConstantPower; uint32_t 713 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Vddr1DynamicPower; uint32_t 714 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t spare[4]; uint32_t 715 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t temperature; uint32_t 724 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t I_calc_max; uint32_t 725 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t I_calc_acc; uint32_t 726 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t P_meas_acc; uint32_t 727 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t V_meas_load_acc; uint32_t 728 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t I_meas_acc; uint32_t 729 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t P_meas_acc_vddci; uint32_t 730 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t V_meas_load_acc_vddci; uint32_t 731 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t I_meas_acc_vddci; uint32_t 738 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t P_roc_acc; uint32_t 739 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t PkgPwr_max; uint32_t 740 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t PkgPwr_acc; uint32_t 741 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t MclkSwitchingTime_max; uint32_t 742 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t MclkSwitchingTime_acc; uint32_t 743 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t FanPwm_acc; uint32_t 744 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t FanRpm_acc; uint32_t 745 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Gfx_busy_acc; uint32_t 746 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Mc_busy_acc; uint32_t 747 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Fps_acc; uint32_t 749 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t AccCnt; uint32_t 758 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t TgpPwr_acc; uint32_t 759 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Gfx_busy_acc; uint32_t 760 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t Mc_busy_acc; uint32_t 761 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint32_t AccCnt; uint32_t 40 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t RefClockFrequency; uint32_t 41 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t PmTimerP; uint32_t 42 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t FeatureEnables; uint32_t 43 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t PreVBlankGap; uint32_t 44 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t VBlankTimeout; uint32_t 45 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t TrainTimeGap; uint32_t 47 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MvddSwitchTime; uint32_t 48 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t LongestAcpiTrainTime; uint32_t 49 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t AcpiDelay; uint32_t 50 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t G5TrainTime; uint32_t 51 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DelayMpllPwron; uint32_t 52 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t VoltageChangeTimeout; uint32_t 53 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t HandshakeDisables; uint32_t 65 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t AverageGraphicsA; uint32_t 66 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t AverageMemoryA; uint32_t 67 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t AverageGioA; uint32_t 79 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DRAM_LOG_ADDR_H; uint32_t 80 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DRAM_LOG_ADDR_L; uint32_t 81 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 82 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 83 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 84 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t UlvEnterC; uint32_t 85 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t UlvTime; uint32_t 86 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t Reserved[3]; uint32_t 105 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t Flags; uint32_t 106 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MinVddc; uint32_t 107 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MinVddcPhases; uint32_t 109 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SclkFrequency; uint32_t 114 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 115 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 116 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 117 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 118 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CcPwrDynRm; uint32_t 119 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CcPwrDynRm1; uint32_t 136 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t Flags; uint32_t 137 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MinVddc; uint32_t 138 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MinVddcPhases; uint32_t 139 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SclkFrequency; uint32_t 144 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CgSpllFuncCntl; uint32_t 145 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CgSpllFuncCntl2; uint32_t 146 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 147 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 148 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 149 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 150 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CcPwrDynRm; uint32_t 151 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CcPwrDynRm1; uint32_t 158 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CcPwrDynRm; uint32_t 159 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t CcPwrDynRm1; uint32_t 163 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t Reserved; uint32_t 170 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MinVddc; uint32_t 171 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MinVddcPhases; uint32_t 172 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MinVddci; uint32_t 173 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MinMvdd; uint32_t 175 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MclkFrequency; uint32_t 196 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MpllFuncCntl; uint32_t 197 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MpllFuncCntl_1; uint32_t 198 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MpllFuncCntl_2; uint32_t 199 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MpllAdFuncCntl; uint32_t 200 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MpllDqFuncCntl; uint32_t 201 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MclkPwrmgtCntl; uint32_t 202 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DllCntl; uint32_t 203 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MpllSs1; uint32_t 204 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MpllSs2; uint32_t 215 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DownT; uint32_t 216 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t UpT; uint32_t 217 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t Reserved; uint32_t 225 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t McArbDramTiming; uint32_t 226 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t McArbDramTiming2; uint32_t 242 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t VclkFrequency; uint32_t 243 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DclkFrequency; uint32_t 255 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t Frequency; uint32_t 265 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SclkFrequency; uint32_t 266 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MclkFrequency; uint32_t 267 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t VclkFrequency; uint32_t 268 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t DclkFrequency; uint32_t 269 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SamclkFrequency; uint32_t 270 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t AclkFrequency; uint32_t 271 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t EclkFrequency; uint32_t 294 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SystemFlags; uint32_t 297 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SmioMaskVddcVid; uint32_t 298 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SmioMaskVddcPhase; uint32_t 299 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SmioMaskVddciVid; uint32_t 300 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SmioMaskMvddVid; uint32_t 302 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t VddcLevelCount; uint32_t 303 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t VddciLevelCount; uint32_t 304 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t MvddLevelCount; uint32_t 319 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t VRConfig; uint32_t 320 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t Reserved[4]; uint32_t 334 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t SclkStepSize; uint32_t 335 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t Smio [SMU7_MAX_ENTRIES_SMIO]; uint32_t 400 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t BAPM_TEMP_GRADIENT; uint32_t 402 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t LowSclkInterruptT; uint32_t 420 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; uint32_t 451 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint32_t RefreshPeriod; uint32_t 41 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t RefClockFrequency; uint32_t 42 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t PmTimerP; uint32_t 43 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t FeatureEnables; uint32_t 44 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t HandshakeDisables; uint32_t 56 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t AverageGraphicsA; uint32_t 57 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t AverageMemoryA; uint32_t 58 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t AverageGioA; uint32_t 70 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_ADDR_H; uint32_t 71 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_ADDR_L; uint32_t 72 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 73 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 74 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 75 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t UlvEnterC; uint32_t 76 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t UlvTime; uint32_t 77 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t Reserved[3]; uint32_t 85 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t MinVddNb; uint32_t 87 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t SclkFrequency; uint32_t 109 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t reserved; uint32_t 121 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t MinVddNb; uint32_t 127 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t LclkFrequency; uint32_t 142 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t VclkFrequency; uint32_t 143 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DclkFrequency; uint32_t 160 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t Frequency; uint32_t 165 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t Reserved; uint32_t 171 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t Flags; uint32_t 172 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t MinVddNb; uint32_t 173 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t SclkFrequency; uint32_t 202 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t SclkFrequency; uint32_t 203 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t LclkFrequency; uint32_t 204 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t VclkFrequency; uint32_t 205 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DclkFrequency; uint32_t 206 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t SamclkFrequency; uint32_t 207 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t AclkFrequency; uint32_t 208 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t EclkFrequency; uint32_t 219 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t SystemFlags; uint32_t 258 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DisplayCac; uint32_t 259 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t LowSclkInterruptT; uint32_t 261 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_ADDR_H; uint32_t 262 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_ADDR_L; uint32_t 263 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 264 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 265 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 276 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint32_t GIOLevelCount; uint32_t 210 drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h #define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126) uint32_t 211 drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h #define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127) uint32_t 32 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t Version; uint32_t 33 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t ImageSize; uint32_t 34 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t CodeSize; uint32_t 35 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t HeaderSize; uint32_t 36 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t EntryPoint; uint32_t 37 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t Rtos; uint32_t 38 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t UcodeLoadStatus; uint32_t 39 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t DpmTable; uint32_t 40 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t FanTable; uint32_t 41 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t PmFuseTable; uint32_t 42 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t Globals; uint32_t 43 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t Reserved[20]; uint32_t 44 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t Signature; uint32_t 48 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t avgTotalPower; uint32_t 49 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t avgGpuPower; uint32_t 50 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t avgUvdPower; uint32_t 51 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t avgVcePower; uint32_t 53 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t avgSclk; uint32_t 54 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t avgDclk; uint32_t 55 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t avgVclk; uint32_t 56 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t avgEclk; uint32_t 58 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t startTimeHi; uint32_t 59 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t startTimeLo; uint32_t 61 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t endTimeHi; uint32_t 62 drivers/gpu/drm/amd/powerplay/inc/smu8.h uint32_t endTimeLo; uint32_t 41 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t MmioAddress; uint32_t 42 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t MemoryBaseHi; uint32_t 43 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t MemoryBaseLo; uint32_t 71 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t DfsBypass; uint32_t 72 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t Frequency; uint32_t 79 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t SclkValidMask; uint32_t 80 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t MaxSclkIndex; uint32_t 87 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t LclkValidMask; uint32_t 88 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t MaxLclkIndex; uint32_t 95 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t EclkValidMask; uint32_t 96 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t MaxEclkIndex; uint32_t 103 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t VclkValidMask; uint32_t 104 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t MaxVclkIndex; uint32_t 111 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t DclkValidMask; uint32_t 112 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t MaxDclkIndex; uint32_t 119 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t AclkValidMask; uint32_t 120 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h uint32_t MaxAclkIndex; uint32_t 124 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t CurrLevel_GFXCLK : 4; uint32_t 125 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t CurrLevel_UVD : 4; uint32_t 126 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t CurrLevel_VCE : 4; uint32_t 127 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t CurrLevel_LCLK : 4; uint32_t 128 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t CurrLevel_MP0CLK : 4; uint32_t 129 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t CurrLevel_UCLK : 4; uint32_t 130 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t CurrLevel_SOCCLK : 4; uint32_t 131 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t CurrLevel_DCEFCLK : 4; uint32_t 133 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t TargLevel_GFXCLK : 4; uint32_t 134 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t TargLevel_UVD : 4; uint32_t 135 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t TargLevel_VCE : 4; uint32_t 136 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t TargLevel_LCLK : 4; uint32_t 137 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t TargLevel_MP0CLK : 4; uint32_t 138 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t TargLevel_UCLK : 4; uint32_t 139 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t TargLevel_SOCCLK : 4; uint32_t 140 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t TargLevel_DCEFCLK : 4; uint32_t 142 drivers/gpu/drm/amd/powerplay/inc/smu9.h uint32_t Reserved[6]; uint32_t 81 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */ uint32_t 82 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */ uint32_t 139 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t FitLimit; /* Failures in time (failures per million parts over the defined lifetime) */ uint32_t 149 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t GeminiApertureHigh; uint32_t 150 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t GeminiApertureLow; uint32_t 211 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t LowGfxclkInterruptThreshold; /* in units of 10KHz */ uint32_t 297 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t AConstant[3]; uint32_t 303 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t DpmLevelPowerDelta; uint32_t 320 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t AcgFreqTable[NUM_GFXCLK_DPM_LEVELS]; uint32_t 323 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t MmHubPadding[3]; /* SMU internal use */ uint32_t 349 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t MmHubPadding[7]; /* SMU internal use */ uint32_t 360 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t MmHubPadding[7]; /* SMU internal use */ uint32_t 364 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS]; uint32_t 365 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS]; uint32_t 366 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS]; uint32_t 367 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS]; uint32_t 368 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t DcBtcGb; uint32_t 370 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t MmHubPadding[7]; /* SMU internal use */ uint32_t 380 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t MmHubPadding[7]; /* SMU internal use */ uint32_t 408 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t AvfsTempCold; uint32_t 409 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t AvfsTempMid; uint32_t 410 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t AvfsTempHot; uint32_t 412 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t InversionVoltage; /* in mV with 2 fractional bits */ uint32_t 418 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t P2VCharzFreq; /* in 10KHz units */ uint32_t 420 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t EnabledAvfsModules; uint32_t 422 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint32_t MmHubPadding[7]; /* SMU internal use */ uint32_t 109 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t high; uint32_t 110 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t low; uint32_t 118 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t size_bytes; uint32_t 141 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_address; uint32_t 142 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_data; uint32_t 148 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_address; uint32_t 149 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_mask; uint32_t 150 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_data; uint32_t 155 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_address; uint32_t 156 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_mask; uint32_t 157 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t target_value; uint32_t 163 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_address; uint32_t 164 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_mask; uint32_t 165 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h uint32_t register_data; uint32_t 75 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t image_addr_high; uint32_t 76 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t image_addr_low; uint32_t 77 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t meta_data_addr_high; uint32_t 78 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t meta_data_addr_low; uint32_t 79 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t data_size_byte; uint32_t 85 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t image_addr_high; uint32_t 86 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t image_addr_low; uint32_t 87 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t meta_data_addr_high; uint32_t 88 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t meta_data_addr_low; uint32_t 89 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t data_size_byte; uint32_t 96 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t structure_version; uint32_t 97 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h uint32_t num_entries; uint32_t 78 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t display_clock; uint32_t 79 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t phy_clock; uint32_t 80 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t pixel_clock; uint32_t 81 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t uclock; uint32_t 82 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t dcef_clock; uint32_t 83 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t soc_clock; uint32_t 87 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t min; /* MHz */ uint32_t 88 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t max; /* MHz */ uint32_t 107 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t workload_policy_mask; uint32_t 108 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t dcef_min_ds_clk; uint32_t 120 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h uint32_t power_source; uint32_t 125 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h typedef uint32_t PPSMC_Result; uint32_t 126 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h typedef uint32_t PPSMC_Msg; uint32_t 89 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t feature_count; //Total number of supported features uint32_t 90 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t setting_count; //Total number of supported settings uint32_t 92 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t max[SMU_11_0_MAX_ODSETTING]; //default maximum settings uint32_t 93 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t min[SMU_11_0_MAX_ODSETTING]; //default minimum settings uint32_t 115 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT uint32_t 116 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t max[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz uint32_t 117 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t min[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz uint32_t 125 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t golden_pp_id; uint32_t 126 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t golden_revision; uint32_t 128 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps uint32_t 84 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern uint32_t smum_get_argument(struct pp_hwmgr *hwmgr); uint32_t 93 drivers/gpu/drm/amd/powerplay/inc/smumgr.h uint16_t msg, uint32_t parameter); uint32_t 97 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type); uint32_t 105 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t 106 drivers/gpu/drm/amd/powerplay/inc/smumgr.h uint32_t type, uint32_t member); uint32_t 107 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value); uint32_t 202 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t a; uint32_t 203 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t b; uint32_t 204 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t c; uint32_t 208 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t m; uint32_t 209 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t b; uint32_t 213 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t a; uint32_t 214 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t b; uint32_t 215 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t c; uint32_t 249 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Version; uint32_t 252 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t FeaturesToRun[2]; uint32_t 278 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t FitLimit; uint32_t 409 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t DebugOverrides; uint32_t 418 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Reserved[14]; uint32_t 505 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t BoardReserved[9]; uint32_t 508 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t MmHubPadding[7]; uint32_t 521 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t MmHubPadding[7]; uint32_t 562 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t ThrottlerStatus ; uint32_t 568 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t MmHubPadding[7]; uint32_t 593 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t MmHubPadding[7]; uint32_t 602 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t MmHubPadding[7]; uint32_t 636 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t AvfsTempCold; uint32_t 637 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t AvfsTempMid; uint32_t 638 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t AvfsTempHot; uint32_t 640 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t GfxVInversion; uint32_t 641 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t SocVInversion; uint32_t 647 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t P2VCharzFreq; uint32_t 649 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t EnabledAvfsModules; uint32_t 651 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t MmHubPadding[7]; uint32_t 665 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Gfx_PD_Data_limit_a; uint32_t 666 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Gfx_PD_Data_limit_b; uint32_t 667 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Gfx_PD_Data_limit_c; uint32_t 668 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Gfx_PD_Data_error_coeff; uint32_t 669 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Gfx_PD_Data_error_rate_coeff; uint32_t 680 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Soc_PD_Data_limit_a; uint32_t 681 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Soc_PD_Data_limit_b; uint32_t 682 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Soc_PD_Data_limit_c; uint32_t 683 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Soc_PD_Data_error_coeff; uint32_t 684 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Soc_PD_Data_error_rate_coeff; uint32_t 695 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Mem_PD_Data_limit_a; uint32_t 696 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Mem_PD_Data_limit_b; uint32_t 697 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Mem_PD_Data_limit_c; uint32_t 698 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Mem_PD_Data_error_coeff; uint32_t 699 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint32_t Mem_PD_Data_error_rate_coeff; uint32_t 125 drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h typedef uint32_t PPSMC_Result; uint32_t 126 drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h typedef uint32_t PPSMC_Msg; uint32_t 212 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index) uint32_t 227 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index) uint32_t 242 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index) uint32_t 257 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index) uint32_t 272 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index) uint32_t 307 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t mp0_fw_intf; uint32_t 320 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *feature_mask, uint32_t num) uint32_t 327 drivers/gpu/drm/amd/powerplay/navi10_ppt.c memset(feature_mask, 0, sizeof(uint32_t) * num); uint32_t 652 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *value) uint32_t 674 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t clk_index = 0; uint32_t 687 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t cur_value = 0, value = 0, count = 0; uint32_t 688 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t freq_values[3] = {0}; uint32_t 689 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t mark_index = 0; uint32_t 748 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, uint32_t mask) uint32_t 752 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; uint32_t 793 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t min_sclk_freq = 0, min_mclk_freq = 0; uint32_t 815 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t level_count = 0, freq = 0; uint32_t 825 drivers/gpu/drm/amd/powerplay/navi10_ppt.c level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); uint32_t 847 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t max_freq = 0; uint32_t 893 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t min_freq, max_freq, force_freq; uint32_t 920 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t min_freq, max_freq; uint32_t 943 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value) uint32_t 962 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *value) uint32_t 992 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t feature_mask[2]; uint32_t 1001 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *speed) uint32_t 1019 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *speed) uint32_t 1022 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t percent = 0; uint32_t 1023 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t current_rpm; uint32_t 1039 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t i, size = 0; uint32_t 1133 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) uint32_t 1214 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *sclk_mask, uint32_t 1215 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *mclk_mask, uint32_t 1216 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *soc_mask) uint32_t 1219 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t level_count = 0; uint32_t 1354 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *value) uint32_t 1389 drivers/gpu/drm/amd/powerplay/navi10_ppt.c void *data, uint32_t *size) uint32_t 1401 drivers/gpu/drm/amd/powerplay/navi10_ppt.c *(uint32_t *)data = pptable->FanMaximumRpm; uint32_t 1406 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data); uint32_t 1410 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = navi10_get_gpu_power(smu, (uint32_t *)data); uint32_t 1416 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data); uint32_t 1427 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) uint32_t 1429 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t num_discrete_levels = 0; uint32_t 1460 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t sclk_freq = 0, uclk_freq = 0; uint32_t 1461 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t uclk_level = 0; uint32_t 1536 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; uint32_t 1537 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t max_memory_clock = max_sustainable_clocks->uclock; uint32_t 1554 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t *limit, uint32_t 1558 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t asic_default_power_limit = 0; uint32_t 113 drivers/gpu/drm/amd/powerplay/renoir_ppt.c static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index) uint32_t 127 drivers/gpu/drm/amd/powerplay/renoir_ppt.c static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index) uint32_t 163 drivers/gpu/drm/amd/powerplay/renoir_ppt.c static int renoir_get_dpm_uclk_limited(struct smu_context *smu, uint32_t *clock, bool max) uint32_t 184 drivers/gpu/drm/amd/powerplay/renoir_ppt.c uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; uint32_t 64 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg) uint32_t 75 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t cur_value, i, timeout = adev->usec_timeout * 10; uint32_t 118 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t param) uint32_t 212 drivers/gpu/drm/amd/powerplay/smu_v11_0.c const uint32_t *src; uint32_t 214 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t addr_start = MP1_SRAM; uint32_t 215 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t i; uint32_t 216 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t mp1_fw_flags; uint32_t 219 drivers/gpu/drm/amd/powerplay/smu_v11_0.c src = (const uint32_t *)(adev->pm.fw->data + uint32_t 250 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t mp1_fw_flags; uint32_t 264 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t if_version = 0xff, smu_version = 0xff; uint32_t 315 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) uint32_t 318 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t ppt_offset_bytes; uint32_t 331 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t *size, uint32_t pptable_id) uint32_t 336 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t pptable_count = 0; uint32_t 362 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t size = 0; uint32_t 592 drivers/gpu/drm/amd/powerplay/smu_v11_0.c (uint32_t *)&input); uint32_t 606 drivers/gpu/drm/amd/powerplay/smu_v11_0.c (uint32_t *)&input); uint32_t 620 drivers/gpu/drm/amd/powerplay/smu_v11_0.c (uint32_t *)&input); uint32_t 634 drivers/gpu/drm/amd/powerplay/smu_v11_0.c (uint32_t *)&input); uint32_t 648 drivers/gpu/drm/amd/powerplay/smu_v11_0.c (uint32_t *)&input); uint32_t 665 drivers/gpu/drm/amd/powerplay/smu_v11_0.c (uint32_t *)&input); uint32_t 682 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t address_low, address_high; uint32_t 688 drivers/gpu/drm/amd/powerplay/smu_v11_0.c address_high = (uint32_t)upper_32_bits(address); uint32_t 689 drivers/gpu/drm/amd/powerplay/smu_v11_0.c address_low = (uint32_t)lower_32_bits(address); uint32_t 703 drivers/gpu/drm/amd/powerplay/smu_v11_0.c address_high = (uint32_t)upper_32_bits(address); uint32_t 704 drivers/gpu/drm/amd/powerplay/smu_v11_0.c address_low = (uint32_t)lower_32_bits(address); uint32_t 715 drivers/gpu/drm/amd/powerplay/smu_v11_0.c (uint32_t)memory_pool->size); uint32_t 791 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) uint32_t 834 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) uint32_t 850 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t feature_mask[2]; uint32_t 874 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t *feature_mask, uint32_t num) uint32_t 876 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t feature_mask_high = 0, feature_mask_low = 0; uint32_t 906 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t feature_mask[2]; uint32_t 942 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, uint32_t 1070 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) uint32_t 1100 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t *value) uint32_t 1103 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t freq = 0; uint32_t 1139 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t val; uint32_t 1166 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t val = 0; uint32_t 1224 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) uint32_t 1227 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t vdd = 0, val_vid = 0; uint32_t 1235 drivers/gpu/drm/amd/powerplay/smu_v11_0.c vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); uint32_t 1245 drivers/gpu/drm/amd/powerplay/smu_v11_0.c void *data, uint32_t *size) uint32_t 1254 drivers/gpu/drm/amd/powerplay/smu_v11_0.c ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data); uint32_t 1258 drivers/gpu/drm/amd/powerplay/smu_v11_0.c ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data); uint32_t 1262 drivers/gpu/drm/amd/powerplay/smu_v11_0.c ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); uint32_t 1266 drivers/gpu/drm/amd/powerplay/smu_v11_0.c *(uint32_t *)data = 0; uint32_t 1288 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; uint32_t 1382 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static uint32_t uint32_t 1408 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) uint32_t 1423 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) uint32_t 1426 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t duty100, duty; uint32_t 1442 drivers/gpu/drm/amd/powerplay/smu_v11_0.c duty = (uint32_t)tmp64; uint32_t 1453 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t mode) uint32_t 1480 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t speed) uint32_t 1484 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t tach_period, crystal_clock_freq; uint32_t 1512 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t pstate) uint32_t 1530 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t client_id = entry->client_id; uint32_t 1531 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t src_id = entry->src_id; uint32_t 1648 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t val; uint32_t 1726 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t *min, uint32_t *max) uint32_t 1729 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t param = 0; uint32_t 53 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg) uint32_t 64 drivers/gpu/drm/amd/powerplay/smu_v12_0.c uint32_t cur_value, i; uint32_t 107 drivers/gpu/drm/amd/powerplay/smu_v12_0.c uint32_t param) uint32_t 138 drivers/gpu/drm/amd/powerplay/smu_v12_0.c uint32_t mp1_fw_flags; uint32_t 152 drivers/gpu/drm/amd/powerplay/smu_v12_0.c uint32_t if_version = 0xff, smu_version = 0xff; uint32_t 227 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu) uint32_t 229 drivers/gpu/drm/amd/powerplay/smu_v12_0.c uint32_t reg; uint32_t 230 drivers/gpu/drm/amd/powerplay/smu_v12_0.c uint32_t gfxOff_Status = 0; uint32_t 323 drivers/gpu/drm/amd/powerplay/smu_v12_0.c uint32_t *min, uint32_t *max) uint32_t 95 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t smc_addr, uint32_t limit) uint32_t 108 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t 109 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c const uint8_t *src, uint32_t byte_count, uint32_t limit) uint32_t 112 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t data = 0; uint32_t 113 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t original_data; uint32_t 114 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t addr = 0; uint32_t 115 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t extra_shift; uint32_t 194 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t 195 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t *value, uint32_t limit) uint32_t 226 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint16_t msg, uint32_t parameter) uint32_t 236 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t dev_id; uint32_t 277 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t clock, uint32_t *vol) uint32_t 279 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i = 0; uint32_t 296 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk) uint32_t 300 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; uint32_t 301 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; uint32_t 302 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; uint32_t 303 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; uint32_t 304 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 305 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t ref_clock; uint32_t 306 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t ref_divider; uint32_t 307 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t fbdiv; uint32_t 341 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t vco_freq = clock * dividers.uc_pll_post_div; uint32_t 345 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t clk_s = ref_clock * 5 / uint32_t 347 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t clk_v = 4 * ss_info.speed_spectrum_percentage * uint32_t 371 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t sclk, uint32_t *p_shed) uint32_t 386 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock, uint32_t 387 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t clock_insr) uint32_t 390 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t temp; uint32_t 391 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t min = min_t(uint32_t, clock_insr, CISLAND_MINIMUM_ENGINE_CLOCK); uint32_t 407 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t clock, struct SMU7_Discrete_GraphicsLevel *level) uint32_t 418 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (uint32_t *)(&level->MinVddc)); uint32_t 476 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t array = smu_data->dpm_table_start + uint32_t 478 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) * uint32_t 482 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i; uint32_t 540 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) uint32_t 544 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t temp; uint32_t 549 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (uint32_t *)&temp, SMC_RAM_END)) uint32_t 559 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) uint32_t 590 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { uint32_t 674 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t pm_fuse_table_offset; uint32_t 780 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { uint32_t 783 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { uint32_t 796 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { uint32_t 799 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { uint32_t 872 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t count; uint32_t 900 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t count; uint32_t 948 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t voltage_response_time, ulv_voltage; uint32_t 1000 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i; uint32_t 1023 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t memory_clock, uint32_t 1030 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; uint32_t 1031 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; uint32_t 1032 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; uint32_t 1033 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; uint32_t 1034 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; uint32_t 1035 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; uint32_t 1036 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; uint32_t 1037 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; uint32_t 1038 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; uint32_t 1070 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t freq_nom; uint32_t 1071 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t tmp; uint32_t 1072 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); uint32_t 1085 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; uint32_t 1086 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t clkv = uint32_t 1087 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (uint32_t)((((131 * ss_info.speed_spectrum_percentage * uint32_t 1117 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock, uint32_t 1141 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static uint8_t ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) uint32_t 1156 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t memory_clock, uint32_t *p_shed) uint32_t 1174 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t memory_clock, uint32_t 1181 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mclk_edc_wr_enable_threshold = 40000; uint32_t 1182 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mclk_edc_enable_threshold = 40000; uint32_t 1183 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mclk_strobe_mode_threshold = 40000; uint32_t 1305 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t dev_id; uint32_t 1307 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel); uint32_t 1308 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * SMU7_MAX_LEVELS_MEMORY; uint32_t 1310 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i; uint32_t 1342 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, uint32_t 1348 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, uint32_t 1353 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i = 0; uint32_t 1383 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; uint32_t 1384 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; uint32_t 1385 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; uint32_t 1386 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; uint32_t 1621 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t engine_clock, uint32_t 1622 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t memory_clock, uint32_t 1626 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t dramTiming; uint32_t 1627 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t dramTiming2; uint32_t 1628 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t burstTime; uint32_t 1654 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i, j; uint32_t 1696 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel)); uint32_t 1706 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); uint32_t 1726 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i, j; uint32_t 1748 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t num_entries, uint32_t valid_flag) uint32_t 1750 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i, j; uint32_t 1762 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c const uint32_t memory_clock, uint32_t 1767 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i = 0; uint32_t 1792 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i; uint32_t 1812 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t address; uint32_t 1826 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]); uint32_t 2127 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t duty100; uint32_t 2128 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; uint32_t 2130 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t reference_clock; uint32_t 2193 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); uint32_t 2215 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t low_sclk_interrupt_threshold = 0; uint32_t 2231 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c sizeof(uint32_t), uint32_t 2247 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static uint32_t ci_get_offsetof(uint32_t type, uint32_t member) uint32_t 2287 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static uint32_t ci_get_mac_definition(uint32_t value) uint32_t 2312 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t byte_count, start_addr; uint32_t 2314 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t data; uint32_t 2370 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t tmp = 0; uint32_t 2540 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i; uint32_t 2584 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t temp_reg; uint32_t 2766 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t array = smu_data->dpm_table_start + uint32_t 2769 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t mclk_array = smu_data->dpm_table_start + uint32_t 2773 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t i; uint32_t 2774 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; uint32_t 2860 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | uint32_t 2864 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc : uint32_t 2896 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | uint32_t 2900 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc : uint32_t 2921 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) uint32_t 49 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h uint32_t mclk_max; uint32_t 50 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; uint32_t 62 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h uint32_t soft_regs_start; uint32_t 63 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h uint32_t dpm_table_start; uint32_t 64 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h uint32_t mc_reg_table_start; uint32_t 65 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h uint32_t fan_table_start; uint32_t 66 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h uint32_t arb_table_start; uint32_t 67 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h uint32_t ulv_setting_starts; uint32_t 69 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = { uint32_t 226 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t table_start; uint32_t 227 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t level_addr, vr_config_addr; uint32_t 228 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t level_size = sizeof(avfs_graphics_level); uint32_t 321 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t efuse = 0; uint32_t 322 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1; uint32_t 356 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t clock, uint32_t *voltage, uint32_t *mvdd) uint32_t 358 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t i; uint32_t 390 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c *mvdd = (uint32_t) dep_table->entries[i].mvdd * uint32_t 414 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; uint32_t 422 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t tmp; uint32_t 605 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) uint32_t 609 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t temp; uint32_t 614 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t *)&temp, SMC_RAM_END)) uint32_t 693 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t pm_fuse_table_offset; uint32_t 759 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t count; uint32_t 858 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk) uint32_t 862 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; uint32_t 863 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; uint32_t 864 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; uint32_t 865 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; uint32_t 866 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 867 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t ref_clock; uint32_t 868 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t ref_divider; uint32_t 869 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t fbdiv; uint32_t 904 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t vco_freq = clock * dividers.uc_pll_post_div; uint32_t 913 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t clk_s = ref_clock * 5 / uint32_t 916 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage * uint32_t 939 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level) uint32_t 943 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t threshold, mvdd; uint32_t 959 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t *)(&level->MinVoltage), &mvdd); uint32_t 1014 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t array = smu_data->smu7_data.dpm_table_start + uint32_t 1016 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) * uint32_t 1020 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t i, max_entry; uint32_t 1091 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t)array_size, SMC_RAM_END); uint32_t 1110 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock) uint32_t 1147 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk) uint32_t 1166 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level) uint32_t 1172 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t mclk_stutter_mode_threshold = 60000; uint32_t 1183 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd); uint32_t 1230 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t array = smu_data->smu7_data.dpm_table_start + uint32_t 1232 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) * uint32_t 1236 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t i; uint32_t 1270 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t)array_size, SMC_RAM_END); uint32_t 1276 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t mclk, SMIO_Pattern *smio_pat) uint32_t 1281 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t i = 0; uint32_t 1309 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t mvdd; uint32_t 1311 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; uint32_t 1312 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; uint32_t 1324 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd); uint32_t 1382 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t *)(&table->MemoryACPILevel.MinVoltage), &mvdd); uint32_t 1501 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t dram_timing; uint32_t 1502 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t dram_timing2; uint32_t 1503 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t burstTime; uint32_t 1534 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t i, j; uint32_t 1617 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t *)&(table->GraphicsBootLevel)); uint32_t 1621 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t *)&(table->MemoryBootLevel)); uint32_t 1668 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, uint32_t 1709 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c volt_without_cks = (uint32_t)((14041 * uint32_t 1712 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c volt_with_cks = (uint32_t)((13946 * uint32_t 1870 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t tmp; uint32_t 1888 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; uint32_t 2138 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t duty100; uint32_t 2139 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; uint32_t 2141 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t reference_clock; uint32_t 2218 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), uint32_t 2270 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t low_sclk_interrupt_threshold = 0; uint32_t 2286 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c sizeof(uint32_t), uint32_t 2296 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static uint32_t fiji_get_offsetof(uint32_t type, uint32_t member) uint32_t 2342 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static uint32_t fiji_get_mac_definition(uint32_t value) uint32_t 2371 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t mm_boot_level_offset, mm_boot_level_value; uint32_t 2396 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); uint32_t 2403 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t mm_boot_level_offset, mm_boot_level_value; uint32_t 2428 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); uint32_t 2432 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) uint32_t 2451 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t tmp; uint32_t 2558 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t array = smu_data->smu7_data.dpm_table_start + uint32_t 2561 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t mclk_array = smu_data->smu7_data.dpm_table_start + uint32_t 2565 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t i; uint32_t 2566 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; uint32_t 158 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t length, const uint8_t *src, uint32_t 159 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t limit, uint32_t start_addr) uint32_t 161 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t byte_count = length; uint32_t 162 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t data; uint32_t 186 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t val; uint32_t 229 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t firmwareType) uint32_t 284 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t dev_id; uint32_t 335 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) uint32_t 339 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t temp; uint32_t 344 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (uint32_t *)&temp, SMC_RAM_END)) uint32_t 404 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { uint32_t 438 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t pm_fuse_table_offset; uint32_t 508 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t clock, uint32_t *vol) uint32_t 510 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i = 0; uint32_t 554 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { uint32_t 557 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { uint32_t 574 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { uint32_t 577 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { uint32_t 647 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t count; uint32_t 672 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t count; uint32_t 717 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t voltage_response_time, ulv_voltage; uint32_t 769 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i; uint32_t 796 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) uint32_t 800 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; uint32_t 801 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; uint32_t 802 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; uint32_t 803 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; uint32_t 804 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 805 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t reference_clock; uint32_t 806 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t reference_divider; uint32_t 807 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t fbdiv; uint32_t 842 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; uint32_t 849 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); uint32_t 852 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); uint32_t 875 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t sclk, uint32_t *p_shed) uint32_t 892 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t engine_clock, uint32_t 964 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + uint32_t 967 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) * uint32_t 972 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i; uint32_t 1038 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (uint8_t *)levels, (uint32_t)level_array_size, uint32_t 1046 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t memory_clock, uint32_t 1054 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; uint32_t 1055 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; uint32_t 1056 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; uint32_t 1057 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; uint32_t 1058 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; uint32_t 1059 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; uint32_t 1060 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; uint32_t 1061 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; uint32_t 1062 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; uint32_t 1113 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t freq_nom; uint32_t 1114 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t tmp; uint32_t 1115 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); uint32_t 1132 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; uint32_t 1136 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t clkv = uint32_t 1137 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (uint32_t)((((131 * ss_info.speed_spectrum_percentage * uint32_t 1169 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, uint32_t 1195 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) uint32_t 1211 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t memory_clock, uint32_t *p_shed) uint32_t 1229 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t memory_clock, uint32_t 1236 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mclk_edc_wr_enable_threshold = 40000; uint32_t 1237 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mclk_edc_enable_threshold = 40000; uint32_t 1238 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mclk_strobe_mode_threshold = 40000; uint32_t 1354 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel); uint32_t 1355 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY; uint32_t 1357 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i; uint32_t 1389 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, uint32_t 1395 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, uint32_t 1400 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i = 0; uint32_t 1428 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t vddc_phase_shed_control = 0; uint32_t 1431 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; uint32_t 1432 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; uint32_t 1433 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; uint32_t 1434 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; uint32_t 1584 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t engine_clock, uint32_t 1585 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t memory_clock, uint32_t 1589 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t dramTiming; uint32_t 1590 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t dramTiming2; uint32_t 1591 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t burstTime; uint32_t 1617 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i, j; uint32_t 1659 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel)); uint32_t 1669 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); uint32_t 1693 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i, j; uint32_t 1716 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t num_entries, uint32_t valid_flag) uint32_t 1718 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i, j; uint32_t 1729 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c const uint32_t memory_clock, uint32_t 1734 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i = 0; uint32_t 1759 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i; uint32_t 1779 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t address; uint32_t 1794 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]); uint32_t 2089 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t duty100; uint32_t 2090 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; uint32_t 2092 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t reference_clock; uint32_t 2157 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); uint32_t 2180 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t low_sclk_interrupt_threshold = 0; uint32_t 2196 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c sizeof(uint32_t), uint32_t 2212 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static uint32_t iceland_get_offsetof(uint32_t type, uint32_t member) uint32_t 2254 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static uint32_t iceland_get_mac_definition(uint32_t value) uint32_t 2282 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t tmp; uint32_t 2469 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t i; uint32_t 2513 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t temp_reg; uint32_t 41 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h uint32_t display_cac; uint32_t 42 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h uint32_t bapm_temp_gradient; uint32_t 48 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h uint32_t mclk_max; uint32_t 49 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h uint32_t mc_data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; uint32_t 121 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t vr_config; uint32_t 122 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t dpm_table_start; uint32_t 125 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t graphics_level_address, vr_config_address, graphics_level_size; uint32_t 142 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), uint32_t 324 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t efuse; uint32_t 354 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) uint32_t 356 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t i; uint32_t 388 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c *mvdd = (uint32_t) dep_table->entries[i].mvdd * uint32_t 412 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; uint32_t 419 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t tmp; uint32_t 503 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) uint32_t 507 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t temp; uint32_t 512 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t *)&temp, SMC_RAM_END)) uint32_t 589 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t pm_fuse_table_offset; uint32_t 650 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t count, level; uint32_t 667 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); uint32_t 676 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t count, level; uint32_t 701 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t count; uint32_t 802 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t i, ref_clk; uint32_t 842 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t clock, SMU_SclkSetting *sclk_setting) uint32_t 847 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t ref_clock; uint32_t 848 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq; uint32_t 907 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level) uint32_t 911 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t mvdd; uint32_t 987 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t array = smu_data->smu7_data.dpm_table_start + uint32_t 989 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) * uint32_t 993 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t i, max_entry; uint32_t 1065 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t)array_size, SMC_RAM_END); uint32_t 1072 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level) uint32_t 1078 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t mclk_stutter_mode_threshold = 40000; uint32_t 1131 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t array = smu_data->smu7_data.dpm_table_start + uint32_t 1133 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) * uint32_t 1137 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t i; uint32_t 1169 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t)array_size, SMC_RAM_END); uint32_t 1175 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t mclk, SMIO_Pattern *smio_pat) uint32_t 1180 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t i = 0; uint32_t 1203 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t sclk_frequency; uint32_t 1208 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t mvdd; uint32_t 1297 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t vddci; uint32_t 1309 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table), uint32_t 1340 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t dram_timing; uint32_t 1341 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t dram_timing2; uint32_t 1342 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t burst_time; uint32_t 1367 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t i, j; uint32_t 1403 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t vddci; uint32_t 1416 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table), uint32_t 1461 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t *)&(table->GraphicsBootLevel)); uint32_t 1465 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t *)&(table->MemoryBootLevel)); uint32_t 1513 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; uint32_t 1560 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \ uint32_t 1562 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \ uint32_t 1565 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \ uint32_t 1567 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \ uint32_t 1651 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t tmp, i; uint32_t 1779 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t tmp; uint32_t 1797 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; uint32_t 2069 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t duty100; uint32_t 2070 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; uint32_t 2072 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t reference_clock; uint32_t 2153 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), uint32_t 2180 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t mm_boot_level_offset, mm_boot_level_value; uint32_t 2205 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); uint32_t 2212 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t mm_boot_level_offset, mm_boot_level_value; uint32_t 2237 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); uint32_t 2258 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) uint32_t 2281 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t low_sclk_interrupt_threshold = 0; uint32_t 2297 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sizeof(uint32_t), uint32_t 2311 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member) uint32_t 2357 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static uint32_t polaris10_get_mac_definition(uint32_t value) uint32_t 2388 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t tmp; uint32_t 2471 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t array = smu_data->smu7_data.dpm_table_start + uint32_t 2474 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t mclk_array = smu_data->smu7_data.dpm_table_start + uint32_t 2478 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t i; uint32_t 2479 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; uint32_t 43 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h uint32_t DisplayCac; uint32_t 44 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h uint32_t BAPM_TEMP_GRADIENT; uint32_t 50 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h uint32_t trans_lower_frequency; /* in 10khz */ uint32_t 51 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h uint32_t trans_upper_frequency; uint32_t 62 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK]; uint32_t 49 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr) uint32_t 52 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c uint32_t reg; uint32_t 72 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static uint32_t smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr) uint32_t 97 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c uint16_t msg, uint32_t parameter) uint32_t 179 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c uint32_t smc_driver_if_version; uint32_t 33 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.h uint32_t version; uint32_t 34 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.h uint32_t size; uint32_t 35 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.h uint32_t table_id; uint32_t 38 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit) uint32_t 49 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) uint32_t 51 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t data; uint32_t 52 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t addr; uint32_t 55 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t *pdata = (uint32_t *)&data_byte; uint32_t 85 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t 86 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c const uint8_t *src, uint32_t byte_count, uint32_t limit) uint32_t 89 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t data = 0; uint32_t 90 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t original_data; uint32_t 91 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t addr = 0; uint32_t 92 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t extra_shift; uint32_t 201 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) uint32_t 210 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) uint32_t 231 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type) uint32_t 280 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) uint32_t 291 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit) uint32_t 306 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t fw_type, uint32_t 343 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t fw_to_load; uint32_t 444 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type) uint32_t 447 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t ret; uint32_t 461 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit) uint32_t 463 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t byte_count = length; uint32_t 497 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE); uint32_t 505 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t reg, data; uint32_t 33 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t data_size; uint32_t 44 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t soft_regs_start; uint32_t 45 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t dpm_table_start; uint32_t 46 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t mc_reg_table_start; uint32_t 47 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t fan_table_start; uint32_t 48 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t arb_table_start; uint32_t 49 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t ulv_setting_starts; uint32_t 51 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t acpi_optimization; uint32_t 52 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t avfs_btc_param; uint32_t 56 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t 57 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t *dest, uint32_t byte_count, uint32_t limit); uint32_t 58 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t 59 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h const uint8_t *src, uint32_t byte_count, uint32_t limit); uint32_t 65 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t parameter); uint32_t 67 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint16_t msg, uint32_t parameter); uint32_t 70 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type); uint32_t 71 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t 72 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t *value, uint32_t limit); uint32_t 73 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t 74 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h uint32_t value, uint32_t limit); uint32_t 77 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type); uint32_t 56 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static uint32_t smu8_get_argument(struct pp_hwmgr *hwmgr) uint32_t 67 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint16_t msg, uint32_t parameter) uint32_t 80 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t val = cgs_read_register(hwmgr->device, uint32_t 110 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t smc_address, uint32_t limit) uint32_t 132 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t smc_address, uint32_t value, uint32_t limit) uint32_t 147 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t firmware) uint32_t 150 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t index = SMN_MP1_SRAM_START_ADDR + uint32_t 176 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t reg_data; uint32_t 177 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t tmp; uint32_t 292 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static enum cgs_ucode_id smu8_convert_fw_type_to_cgs(uint32_t fw_type) uint32_t 551 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t firmware_type; uint32_t 552 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t i; uint32_t 585 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t ulsize_byte, uint32_t 589 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t ulsize_aligned = SIZE_ALIGN_32(ulsize_byte); uint32_t 661 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t smc_address; uint32_t 662 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t fw_to_check = 0; uint32_t 727 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c uint32_t index = SMN_MP1_SRAM_START_ADDR + uint32_t 62 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.h uint32_t data_size; uint32_t 70 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.h uint32_t offset; uint32_t 71 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.h uint32_t value; uint32_t 75 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.h uint32_t command; uint32_t 41 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c uint32_t mp1_fw_flags; uint32_t 58 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr) uint32_t 61 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c uint32_t reg; uint32_t 62 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c uint32_t ret; uint32_t 100 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c uint32_t ret; uint32_t 123 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c uint16_t msg, uint32_t parameter) uint32_t 126 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c uint32_t ret; uint32_t 143 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr) uint32_t 29 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h uint16_t msg, uint32_t parameter); uint32_t 30 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr); uint32_t 82 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) uint32_t 91 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member) uint32_t 106 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c uint32_t smum_get_argument(struct pp_hwmgr *hwmgr) uint32_t 114 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value) uint32_t 147 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c uint16_t msg, uint32_t parameter) uint32_t 86 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static const uint32_t tonga_clock_stretcher_ddt_table[2][4][4] = { uint32_t 248 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) uint32_t 250 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i = 0; uint32_t 279 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd; uint32_t 297 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd; uint32_t 340 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t count; uint32_t 370 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t count; uint32_t 394 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t count; uint32_t 407 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount); uint32_t 408 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount); uint32_t 512 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i; uint32_t 539 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) uint32_t 543 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; uint32_t 544 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; uint32_t 545 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; uint32_t 546 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; uint32_t 547 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 548 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t reference_clock; uint32_t 549 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t reference_divider; uint32_t 550 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t fbdiv; uint32_t 585 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; uint32_t 592 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); uint32_t 595 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); uint32_t 617 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t engine_clock, uint32_t 621 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mvdd; uint32_t 694 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t level_array_address = smu_data->smu7_data.dpm_table_start + uint32_t 697 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) * uint32_t 702 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i, max_entry; uint32_t 781 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint8_t *)levels, (uint32_t)level_array_size, uint32_t 789 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t memory_clock, uint32_t 797 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; uint32_t 798 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; uint32_t 799 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; uint32_t 800 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; uint32_t 801 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; uint32_t 802 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; uint32_t 803 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; uint32_t 804 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; uint32_t 805 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; uint32_t 865 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t freq_nom; uint32_t 866 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t tmp; uint32_t 867 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); uint32_t 884 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; uint32_t 888 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t clkv = uint32_t 889 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t)((((131 * ss_info.speed_spectrum_percentage * uint32_t 920 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, uint32_t 944 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) uint32_t 961 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t memory_clock, uint32_t 968 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mclk_edc_wr_enable_threshold = 40000; uint32_t 969 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mclk_stutter_mode_threshold = 30000; uint32_t 970 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mclk_edc_enable_threshold = 40000; uint32_t 971 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mclk_strobe_mode_threshold = 40000; uint32_t 975 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mvdd = 0; uint32_t 1095 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t level_array_address = uint32_t 1098 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t level_array_size = uint32_t 1103 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i; uint32_t 1137 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, uint32_t 1144 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mclk, SMIO_Pattern *smio_pattern) uint32_t 1149 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i = 0; uint32_t 1183 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; uint32_t 1184 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; uint32_t 1185 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; uint32_t 1186 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; uint32_t 1459 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t engine_clock, uint32_t 1460 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t memory_clock, uint32_t 1464 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t dramTiming; uint32_t 1465 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t dramTiming2; uint32_t 1466 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t burstTime; uint32_t 1493 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i, j; uint32_t 1535 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel)); uint32_t 1547 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); uint32_t 1575 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, uint32_t 1586 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t hw_revision, dev_id; uint32_t 1624 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c volt_without_cks = (uint32_t)((7732 + 60 - ro - 20838 * uint32_t 1627 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c volt_with_cks = (uint32_t)((5250 + 51 - ro - 2404 * uint32_t 1631 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c volt_without_cks = (uint32_t)((14041 * uint32_t 1634 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c volt_with_cks = (uint32_t)((13946 * uint32_t 1800 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t tmp; uint32_t 1819 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; uint32_t 1909 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) uint32_t 1914 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t temp; uint32_t 1919 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t *)&temp, SMC_RAM_END)) uint32_t 1998 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t pm_fuse_table_offset; uint32_t 2068 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i, j; uint32_t 2094 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t num_entries, uint32_t valid_flag) uint32_t 2096 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i, j; uint32_t 2108 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c const uint32_t memory_clock, uint32_t 2113 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i = 0; uint32_t 2138 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i; uint32_t 2158 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t address; uint32_t 2174 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]); uint32_t 2465 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t duty100; uint32_t 2466 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; uint32_t 2468 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t reference_clock; uint32_t 2545 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t)sizeof(fan_table), uint32_t 2570 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t low_sclk_interrupt_threshold = 0; uint32_t 2586 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c sizeof(uint32_t), uint32_t 2604 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static uint32_t tonga_get_offsetof(uint32_t type, uint32_t member) uint32_t 2650 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static uint32_t tonga_get_mac_definition(uint32_t value) uint32_t 2679 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mm_boot_level_offset, mm_boot_level_value; uint32_t 2705 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); uint32_t 2713 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mm_boot_level_offset, mm_boot_level_value; uint32_t 2736 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); uint32_t 2740 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) uint32_t 2760 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t tmp; uint32_t 2930 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i; uint32_t 2976 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t temp_reg; uint32_t 3154 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t array = smu_data->smu7_data.dpm_table_start + uint32_t 3157 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t mclk_array = smu_data->smu7_data.dpm_table_start + uint32_t 3161 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t i; uint32_t 3162 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; uint32_t 43 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h uint32_t display_cac; uint32_t 44 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h uint32_t bapm_temp_gradient; uint32_t 50 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h uint32_t mclk_max; uint32_t 51 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h uint32_t mc_data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; uint32_t 98 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c bool enable, uint32_t feature_mask) uint32_t 148 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c uint32_t smc_driver_if_version; uint32_t 150 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c uint32_t dev_id; uint32_t 151 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c uint32_t rev_id; uint32_t 29 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h uint32_t version; uint32_t 30 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h uint32_t size; uint32_t 31 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h uint32_t table_id; uint32_t 46 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h bool enable, uint32_t feature_mask); uint32_t 120 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c uint32_t smu_features_low, smu_features_high; uint32_t 122 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); uint32_t 123 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); uint32_t 151 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c uint32_t smc_features_low, smc_features_high; uint32_t 31 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h uint32_t version; uint32_t 32 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h uint32_t size; uint32_t 50 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c uint32_t mp1_fw_flags; uint32_t 68 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static uint32_t vega20_wait_for_response(struct pp_hwmgr *hwmgr) uint32_t 71 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c uint32_t reg; uint32_t 129 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c uint16_t msg, uint32_t parameter) uint32_t 149 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static uint32_t vega20_get_argument(struct pp_hwmgr *hwmgr) uint32_t 304 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c uint32_t smu_features_low, smu_features_high; uint32_t 307 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); uint32_t 308 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); uint32_t 336 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c uint32_t smc_features_low, smc_features_high; uint32_t 30 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h uint32_t version; uint32_t 31 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h uint32_t size; uint32_t 229 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t tmp; uint32_t 303 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static uint32_t vegam_get_mac_definition(uint32_t value) uint32_t 334 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t mm_boot_level_offset, mm_boot_level_value; uint32_t 359 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); uint32_t 366 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t mm_boot_level_offset, mm_boot_level_value; uint32_t 391 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); uint32_t 412 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) uint32_t 451 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t count, level; uint32_t 468 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); uint32_t 477 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t count, level; uint32_t 502 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t count; uint32_t 601 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) uint32_t 603 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t i; uint32_t 635 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c *mvdd = (uint32_t) dep_table->entries[i].mvdd * uint32_t 661 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; uint32_t 670 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t i, ref_clk; uint32_t 717 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t clock, SMU_SclkSetting *sclk_setting) uint32_t 722 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t ref_clock; uint32_t 723 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq; uint32_t 787 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock, uint32_t 788 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t clock_insr) uint32_t 791 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t temp; uint32_t 792 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK); uint32_t 807 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level) uint32_t 811 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t mvdd; uint32_t 871 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t array = smu_data->smu7_data.dpm_table_start + uint32_t 873 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) * uint32_t 877 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t i, max_entry; uint32_t 955 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t)array_size, SMC_RAM_END); uint32_t 961 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) uint32_t 970 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock; uint32_t 979 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) uint32_t 985 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t mclk_stutter_mode_threshold = 60000; uint32_t 1038 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t array = smu_data->smu7_data.dpm_table_start + uint32_t 1040 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) * uint32_t 1044 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t i; uint32_t 1077 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t)array_size, SMC_RAM_END); uint32_t 1083 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t mclk, SMIO_Pattern *smio_pat) uint32_t 1088 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t i = 0; uint32_t 1111 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t sclk_frequency; uint32_t 1116 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t mvdd; uint32_t 1214 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t vddci; uint32_t 1226 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table), uint32_t 1257 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t dram_timing; uint32_t 1258 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t dram_timing2; uint32_t 1259 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t burst_time; uint32_t 1260 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t rfsh_rate; uint32_t 1261 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t misc3; uint32_t 1291 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t i, j; uint32_t 1327 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t vddci; uint32_t 1340 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table), uint32_t 1385 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t *)&(table->GraphicsBootLevel)); uint32_t 1389 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t *)&(table->MemoryBootLevel)); uint32_t 1437 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t tmp; uint32_t 1492 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; uint32_t 1501 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t mask = (1 << ((STRAP_ASIC_RO_MSB - STRAP_ASIC_RO_LSB) + 1)) - 1; uint32_t 1517 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * uint32_t 1520 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * uint32_t 1556 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t efuse; uint32_t 1578 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t tmp, i; uint32_t 1768 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) uint32_t 1772 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t temp; uint32_t 1777 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t *)&temp, SMC_RAM_END)) uint32_t 1854 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t pm_fuse_table_offset; uint32_t 2159 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member) uint32_t 2224 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t low_sclk_interrupt_threshold = 0; uint32_t 2240 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sizeof(uint32_t), uint32_t 52 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.h uint32_t DisplayCac; uint32_t 53 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.h uint32_t BAPM_TEMP_GRADIENT; uint32_t 59 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.h uint32_t trans_lower_frequency; /* in 10khz */ uint32_t 60 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.h uint32_t trans_upper_frequency; uint32_t 71 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.h uint32_t bif_sclk_table[SMU75_MAX_LEVELS_LINK]; uint32_t 226 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index) uint32_t 241 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index) uint32_t 256 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index) uint32_t 271 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index) uint32_t 286 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index) uint32_t 383 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t od_feature_count, od_feature_array_size, uint32_t 419 drivers/gpu/drm/amd/powerplay/vega20_ppt.c od_setting_array_size = sizeof(uint32_t) * od_setting_count; uint32_t 591 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t *feature_mask, uint32_t num) uint32_t 596 drivers/gpu/drm/amd/powerplay/vega20_ppt.c memset(feature_mask, 0, sizeof(uint32_t) * num); uint32_t 666 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t i, num_of_levels = 0, clk; uint32_t 945 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t gen_speed, lane_width; uint32_t 1184 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t feature_mask) uint32_t 1188 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t freq; uint32_t 1272 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type, uint32_t mask) uint32_t 1276 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t soft_min_level, soft_max_level, hard_min_level; uint32_t 1482 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t *voltage, uint32_t 1483 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t freq) uint32_t 1788 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t i, size = 0; uint32_t 1896 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) uint32_t 1988 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t *sclk_mask, uint32_t 1989 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t *mclk_mask, uint32_t 1990 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t *soc_mask) uint32_t 2110 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t i, latency; uint32_t 2295 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table) uint32_t 2297 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t i; uint32_t 2311 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table) uint32_t 2342 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t soft_level; uint32_t 2393 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t soft_min_level, soft_max_level; uint32_t 2435 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t index, uint32_t 2436 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t value) uint32_t 2512 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t index, uint32_t 2513 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t value) uint32_t 2541 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t value) uint32_t 2548 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t od_clk, index; uint32_t 2614 drivers/gpu/drm/amd/powerplay/vega20_ppt.c long *input, uint32_t size) uint32_t 2867 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t feature_mask[2]; uint32_t 2882 drivers/gpu/drm/amd/powerplay/vega20_ppt.c (uint32_t)pptable->FanTargetTemperature); uint32_t 2888 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t *speed) uint32_t 2905 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t *speed) uint32_t 2908 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t current_rpm = 0, percent = 0; uint32_t 2921 drivers/gpu/drm/amd/powerplay/vega20_ppt.c static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value) uint32_t 2923 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t smu_version; uint32_t 2949 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t *value) uint32_t 2978 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t *value) uint32_t 2982 drivers/gpu/drm/amd/powerplay/vega20_ppt.c uint32_t temp = 0; uint32_t 3020 drivers/gpu/drm/amd/powerplay/vega20_ppt.c void *data, uint32_t *size) uint32_t 3032 drivers/gpu/drm/amd/powerplay/vega20_ppt.c *(uint32_t *)data = pptable->FanMaximumRpm; uint32_t 3039 drivers/gpu/drm/amd/powerplay/vega20_ppt.c (uint32_t *)data); uint32_t 3043 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_gpu_power(smu, (uint32_t *)data); uint32_t 3049 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data); uint32_t 85 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t value; uint32_t 86 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t param1; uint32_t 90 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t soft_min_level; uint32_t 91 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t soft_max_level; uint32_t 92 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t hard_min_level; uint32_t 93 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t hard_max_level; uint32_t 97 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t count; uint32_t 106 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t lclk[MAX_PCIE_CONF]; uint32_t 160 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t feature_id; uint32_t 170 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t *od_settings_max; uint32_t 171 drivers/gpu/drm/amd/powerplay/vega20_ppt.h uint32_t *od_settings_min; uint32_t 32 drivers/gpu/drm/arc/arcpgu_crtc.c uint32_t pixel_format = fb->format->format; uint32_t 118 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c uint32_t maxX, uint32_t maxY) uint32_t 87 drivers/gpu/drm/arm/hdlcd_crtc.c uint32_t pixel_format; uint32_t 101 drivers/gpu/drm/armada/armada_510.c const struct drm_display_mode *mode, uint32_t *sclk) uint32_t 86 drivers/gpu/drm/armada/armada_crtc.c uint32_t val; uint32_t 98 drivers/gpu/drm/armada/armada_crtc.c uint32_t dumb_ctrl; uint32_t 262 drivers/gpu/drm/armada/armada_crtc.c uint32_t val; uint32_t 335 drivers/gpu/drm/armada/armada_crtc.c uint32_t lm, rm, tm, bm, val, sclk; uint32_t 541 drivers/gpu/drm/armada/armada_crtc.c static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix, uint32_t 544 drivers/gpu/drm/armada/armada_crtc.c uint32_t addr; uint32_t 549 drivers/gpu/drm/armada/armada_crtc.c uint32_t *p = &pix[y * stride]; uint32_t 553 drivers/gpu/drm/armada/armada_crtc.c uint32_t val = *p; uint32_t 594 drivers/gpu/drm/armada/armada_crtc.c uint32_t xoff, xscr, w = dcrtc->cursor_w, s; uint32_t 595 drivers/gpu/drm/armada/armada_crtc.c uint32_t yoff, yscr, h = dcrtc->cursor_h; uint32_t 596 drivers/gpu/drm/armada/armada_crtc.c uint32_t para1; uint32_t 668 drivers/gpu/drm/armada/armada_crtc.c uint32_t *pix; uint32_t 692 drivers/gpu/drm/armada/armada_crtc.c struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h) uint32_t 13 drivers/gpu/drm/armada/armada_crtc.h uint32_t offset; uint32_t 14 drivers/gpu/drm/armada/armada_crtc.h uint32_t mask; uint32_t 15 drivers/gpu/drm/armada/armada_crtc.h uint32_t val; uint32_t 44 drivers/gpu/drm/armada/armada_crtc.h uint32_t spu_v_h_total; uint32_t 45 drivers/gpu/drm/armada/armada_crtc.h uint32_t spu_v_porch; uint32_t 46 drivers/gpu/drm/armada/armada_crtc.h uint32_t spu_adv_reg; uint32_t 54 drivers/gpu/drm/armada/armada_crtc.h uint32_t cursor_hw_pos; uint32_t 55 drivers/gpu/drm/armada/armada_crtc.h uint32_t cursor_hw_sz; uint32_t 56 drivers/gpu/drm/armada/armada_crtc.h uint32_t cursor_w; uint32_t 57 drivers/gpu/drm/armada/armada_crtc.h uint32_t cursor_h; uint32_t 59 drivers/gpu/drm/armada/armada_crtc.h uint32_t cfg_dumb_ctrl; uint32_t 60 drivers/gpu/drm/armada/armada_crtc.h uint32_t spu_iopad_ctrl; uint32_t 63 drivers/gpu/drm/armada/armada_crtc.h uint32_t irq_ena; uint32_t 22 drivers/gpu/drm/armada/armada_drm.h armada_updatel(uint32_t val, uint32_t mask, void __iomem *ptr) uint32_t 24 drivers/gpu/drm/armada/armada_drm.h uint32_t ov, v; uint32_t 32 drivers/gpu/drm/armada/armada_drm.h static inline uint32_t armada_pitch(uint32_t width, uint32_t bpp) uint32_t 34 drivers/gpu/drm/armada/armada_drm.h uint32_t pitch = bpp != 4 ? width * ((bpp + 7) / 8) : width / 2; uint32_t 48 drivers/gpu/drm/armada/armada_drm.h uint32_t *); uint32_t 254 drivers/gpu/drm/armada/armada_overlay.c uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, uint32_t 474 drivers/gpu/drm/armada/armada_overlay.c static const uint32_t armada_ovl_formats[] = { uint32_t 20 drivers/gpu/drm/armada/armada_plane.c static const uint32_t armada_primary_formats[] = { uint32_t 34 drivers/gpu/drm/armada/armada_trace.h uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h), uint32_t 227 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c static const uint32_t aspeed_gfx_formats[] = { uint32_t 93 drivers/gpu/drm/ast/ast_drv.h uint32_t dram_bus_width; uint32_t 94 drivers/gpu/drm/ast/ast_drv.h uint32_t dram_type; uint32_t 95 drivers/gpu/drm/ast/ast_drv.h uint32_t mclk; uint32_t 96 drivers/gpu/drm/ast/ast_drv.h uint32_t vram_size; uint32_t 175 drivers/gpu/drm/ast/ast_drv.h uint32_t base, uint8_t index, uint32_t 182 drivers/gpu/drm/ast/ast_drv.h uint32_t base, uint8_t index, uint32_t 185 drivers/gpu/drm/ast/ast_drv.h uint32_t base, uint8_t index); uint32_t 187 drivers/gpu/drm/ast/ast_drv.h uint32_t base, uint8_t index, uint8_t mask); uint32_t 41 drivers/gpu/drm/ast/ast_main.c uint32_t base, uint8_t index, uint32_t 51 drivers/gpu/drm/ast/ast_main.c uint32_t base, uint8_t index) uint32_t 60 drivers/gpu/drm/ast/ast_main.c uint32_t base, uint8_t index, uint8_t mask) uint32_t 72 drivers/gpu/drm/ast/ast_main.c uint32_t data, jregd0, jregd1; uint32_t 122 drivers/gpu/drm/ast/ast_main.c uint32_t jreg, scu_rev; uint32_t 275 drivers/gpu/drm/ast/ast_main.c uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; uint32_t 276 drivers/gpu/drm/ast/ast_main.c uint32_t denum, num, div, ref_pll, dsel; uint32_t 48 drivers/gpu/drm/ast/ast_mode.c uint32_t handle, uint32_t 49 drivers/gpu/drm/ast/ast_mode.c uint32_t width, uint32_t 50 drivers/gpu/drm/ast/ast_mode.c uint32_t height); uint32_t 646 drivers/gpu/drm/ast/ast_mode.c u16 *blue, uint32_t size, uint32_t 786 drivers/gpu/drm/ast/ast_mode.c uint32_t jtemp; uint32_t 962 drivers/gpu/drm/ast/ast_mode.c uint32_t val, val2, count, pass; uint32_t 984 drivers/gpu/drm/ast/ast_mode.c uint32_t val, val2, count, pass; uint32_t 1154 drivers/gpu/drm/ast/ast_mode.c uint32_t handle, uint32_t 1155 drivers/gpu/drm/ast/ast_mode.c uint32_t width, uint32_t 1156 drivers/gpu/drm/ast/ast_mode.c uint32_t height) uint32_t 118 drivers/gpu/drm/ast/ast_post.c uint32_t data; uint32_t 131 drivers/gpu/drm/ast/ast_post.c uint32_t data; uint32_t 50 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c uint32_t src_x; uint32_t 51 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c uint32_t src_y; uint32_t 52 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c uint32_t src_w; uint32_t 53 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c uint32_t src_h; uint32_t 81 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c static uint32_t rgb_formats[] = { uint32_t 99 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c static uint32_t rgb_and_yuv_formats[] = { uint32_t 24 drivers/gpu/drm/bochs/bochs_kms.c static const uint32_t bochs_formats[] = { uint32_t 453 drivers/gpu/drm/cirrus/cirrus.c static const uint32_t cirrus_formats[] = { uint32_t 173 drivers/gpu/drm/cirrus/cirrus_drv.h uint32_t flags); uint32_t 178 drivers/gpu/drm/cirrus/cirrus_drv.h uint32_t handle, uint32_t 221 drivers/gpu/drm/cirrus/cirrus_drv.h uint32_t flags, struct cirrus_bo **pcirrusbo); uint32_t 546 drivers/gpu/drm/drm_atomic.c uint32_t num_clips; uint32_t 2430 drivers/gpu/drm/drm_atomic_helper.c uint32_t flags) uint32_t 2833 drivers/gpu/drm/drm_atomic_helper.c uint32_t src_x, uint32_t src_y, uint32_t 2834 drivers/gpu/drm/drm_atomic_helper.c uint32_t src_w, uint32_t src_h, uint32_t 3299 drivers/gpu/drm/drm_atomic_helper.c uint32_t flags) uint32_t 3353 drivers/gpu/drm/drm_atomic_helper.c uint32_t flags, uint32_t 3396 drivers/gpu/drm/drm_atomic_helper.c uint32_t flags, uint32_t 3397 drivers/gpu/drm/drm_atomic_helper.c uint32_t target, uint32_t 3445 drivers/gpu/drm/drm_atomic_helper.c uint32_t size, uint32_t 1280 drivers/gpu/drm/drm_atomic_uapi.c uint32_t __user *objs_ptr = (uint32_t __user *)(unsigned long)(arg->objs_ptr); uint32_t 1281 drivers/gpu/drm/drm_atomic_uapi.c uint32_t __user *count_props_ptr = (uint32_t __user *)(unsigned long)(arg->count_props_ptr); uint32_t 1282 drivers/gpu/drm/drm_atomic_uapi.c uint32_t __user *props_ptr = (uint32_t __user *)(unsigned long)(arg->props_ptr); uint32_t 1331 drivers/gpu/drm/drm_atomic_uapi.c uint32_t obj_id, count_props; uint32_t 1360 drivers/gpu/drm/drm_atomic_uapi.c uint32_t prop_id; uint32_t 120 drivers/gpu/drm/drm_color_mgmt.c uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision) uint32_t 122 drivers/gpu/drm/drm_color_mgmt.c uint32_t val = user_input; uint32_t 123 drivers/gpu/drm/drm_color_mgmt.c uint32_t max = 0xffff >> (16 - bit_precision); uint32_t 2127 drivers/gpu/drm/drm_connector.c uint32_t __user *encoder_ptr; uint32_t 2144 drivers/gpu/drm/drm_connector.c encoder_ptr = (uint32_t __user *)(unsigned long)(out_resp->encoders_ptr); uint32_t 2222 drivers/gpu/drm/drm_connector.c (uint32_t __user *)(unsigned long)(out_resp->props_ptr), uint32_t 536 drivers/gpu/drm/drm_crtc.c uint32_t __user *set_connectors_ptr; uint32_t 679 drivers/gpu/drm/drm_crtc.c set_connectors_ptr = (uint32_t __user *)(unsigned long)crtc_req->set_connectors_ptr; uint32_t 140 drivers/gpu/drm/drm_crtc_internal.h uint32_t obj_type, bool register_obj, uint32_t 143 drivers/gpu/drm/drm_crtc_internal.h uint32_t obj_type); uint32_t 148 drivers/gpu/drm/drm_crtc_internal.h uint32_t id, uint32_t type); uint32_t 152 drivers/gpu/drm/drm_crtc_internal.h uint32_t __user *prop_ptr, uint32_t 154 drivers/gpu/drm/drm_crtc_internal.h uint32_t *arg_count_props); uint32_t 156 drivers/gpu/drm/drm_crtc_internal.h uint32_t prop_id); uint32_t 197 drivers/gpu/drm/drm_crtc_internal.h int drm_framebuffer_check_src_coords(uint32_t src_x, uint32_t src_y, uint32_t 198 drivers/gpu/drm/drm_crtc_internal.h uint32_t src_w, uint32_t src_h, uint32_t 77 drivers/gpu/drm/drm_damage_helper.c uint32_t num_clips, uint32_t src_inc) uint32_t 187 drivers/gpu/drm/drm_damage_helper.c uint32_t inc = 1; uint32_t 389 drivers/gpu/drm/drm_debugfs_crc.c uint32_t frame, uint32_t *crcs) uint32_t 1050 drivers/gpu/drm/drm_dp_helper.c uint32_t crcs[3]; uint32_t 1658 drivers/gpu/drm/drm_fb_helper.c static void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch, uint32_t 1659 drivers/gpu/drm/drm_fb_helper.c uint32_t depth) uint32_t 1677 drivers/gpu/drm/drm_fb_helper.c uint32_t fb_width, uint32_t fb_height) uint32_t 46 drivers/gpu/drm/drm_fourcc.c uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth) uint32_t 48 drivers/gpu/drm/drm_fourcc.c uint32_t fmt = DRM_FORMAT_INVALID; uint32_t 109 drivers/gpu/drm/drm_fourcc.c uint32_t drm_driver_legacy_fb_format(struct drm_device *dev, uint32_t 110 drivers/gpu/drm/drm_fourcc.c uint32_t bpp, uint32_t depth) uint32_t 112 drivers/gpu/drm/drm_fourcc.c uint32_t fmt = drm_mode_legacy_fb_format(bpp, depth); uint32_t 138 drivers/gpu/drm/drm_fourcc.c const char *drm_get_format_name(uint32_t format, struct drm_format_name_buf *buf) uint32_t 75 drivers/gpu/drm/drm_framebuffer.c int drm_framebuffer_check_src_coords(uint32_t src_x, uint32_t src_y, uint32_t 76 drivers/gpu/drm/drm_framebuffer.c uint32_t src_w, uint32_t src_h, uint32_t 487 drivers/gpu/drm/drm_framebuffer.c uint32_t *fb_id = data; uint32_t 764 drivers/gpu/drm/drm_framebuffer.c uint32_t id) uint32_t 352 drivers/gpu/drm/drm_gem.c uint32_t handle) uint32_t 141 drivers/gpu/drm/drm_gem_cma_helper.c uint32_t *handle) uint32_t 343 drivers/gpu/drm/drm_gem_shmem_helper.c uint32_t *handle) uint32_t 528 drivers/gpu/drm/drm_gem_vram_helper.c uint32_t handle, uint64_t *offset) uint32_t 150 drivers/gpu/drm/drm_lease.c uint32_t drm_lease_filter_crtcs(struct drm_file *file_priv, uint32_t crtcs_in) uint32_t 156 drivers/gpu/drm/drm_lease.c uint32_t crtcs_out = 0; uint32_t 168 drivers/gpu/drm/drm_lease.c uint32_t mask_in = 1ul << count_in; uint32_t 170 drivers/gpu/drm/drm_lease.c uint32_t mask_out = 1ul << count_out; uint32_t 495 drivers/gpu/drm/drm_lease.c uint32_t *object_ids; uint32_t 468 drivers/gpu/drm/drm_mipi_dbi.c static const uint32_t mipi_dbi_formats[] = { uint32_t 498 drivers/gpu/drm/drm_mipi_dbi.c const uint32_t *formats, unsigned int format_count, uint32_t 97 drivers/gpu/drm/drm_mode_config.c uint32_t __user *fb_id; uint32_t 98 drivers/gpu/drm/drm_mode_config.c uint32_t __user *crtc_id; uint32_t 99 drivers/gpu/drm/drm_mode_config.c uint32_t __user *connector_id; uint32_t 100 drivers/gpu/drm/drm_mode_config.c uint32_t __user *encoder_id; uint32_t 40 drivers/gpu/drm/drm_mode_object.c uint32_t obj_type, bool register_obj, uint32_t 80 drivers/gpu/drm/drm_mode_object.c struct drm_mode_object *obj, uint32_t obj_type) uint32_t 124 drivers/gpu/drm/drm_mode_object.c bool drm_mode_object_lease_required(uint32_t type) uint32_t 138 drivers/gpu/drm/drm_mode_object.c uint32_t id, uint32_t type) uint32_t 175 drivers/gpu/drm/drm_mode_object.c uint32_t id, uint32_t type) uint32_t 339 drivers/gpu/drm/drm_mode_object.c uint32_t __user *prop_ptr, uint32_t 341 drivers/gpu/drm/drm_mode_object.c uint32_t *arg_count_props) uint32_t 409 drivers/gpu/drm/drm_mode_object.c (uint32_t __user *)(unsigned long)(arg->props_ptr), uint32_t 421 drivers/gpu/drm/drm_mode_object.c uint32_t prop_id) uint32_t 105 drivers/gpu/drm/drm_modeset_helper.c static const uint32_t safe_modeset_formats[] = { uint32_t 199 drivers/gpu/drm/drm_modeset_lock.c uint32_t flags) uint32_t 34 drivers/gpu/drm/drm_of.c uint32_t drm_of_crtc_port_mask(struct drm_device *dev, uint32_t 62 drivers/gpu/drm/drm_of.c uint32_t drm_of_find_possible_crtcs(struct drm_device *dev, uint32_t 66 drivers/gpu/drm/drm_of.c uint32_t possible_crtcs = 0; uint32_t 174 drivers/gpu/drm/drm_plane.c uint32_t possible_crtcs, uint32_t 176 drivers/gpu/drm/drm_plane.c const uint32_t *formats, unsigned int format_count, uint32_t 202 drivers/gpu/drm/drm_plane.c plane->format_types = kmalloc_array(format_count, sizeof(uint32_t), uint32_t 255 drivers/gpu/drm/drm_plane.c memcpy(plane->format_types, formats, format_count * sizeof(uint32_t)); uint32_t 333 drivers/gpu/drm/drm_plane.c uint32_t possible_crtcs, uint32_t 335 drivers/gpu/drm/drm_plane.c const uint32_t *formats, unsigned int format_count, uint32_t 479 drivers/gpu/drm/drm_plane.c uint32_t __user *plane_ptr; uint32_t 517 drivers/gpu/drm/drm_plane.c uint32_t __user *format_ptr; uint32_t 554 drivers/gpu/drm/drm_plane.c format_ptr = (uint32_t __user *)(unsigned long)plane_resp->format_type_ptr; uint32_t 557 drivers/gpu/drm/drm_plane.c sizeof(uint32_t) * plane->format_count)) { uint32_t 600 drivers/gpu/drm/drm_plane.c uint32_t crtc_w, uint32_t crtc_h, uint32_t 601 drivers/gpu/drm/drm_plane.c uint32_t src_x, uint32_t src_y, uint32_t 602 drivers/gpu/drm/drm_plane.c uint32_t src_w, uint32_t src_h) uint32_t 677 drivers/gpu/drm/drm_plane.c uint32_t crtc_w, uint32_t crtc_h, uint32_t 679 drivers/gpu/drm/drm_plane.c uint32_t src_x, uint32_t src_y, uint32_t 680 drivers/gpu/drm/drm_plane.c uint32_t src_w, uint32_t src_h, uint32_t 730 drivers/gpu/drm/drm_plane.c uint32_t crtc_w, uint32_t crtc_h, uint32_t 731 drivers/gpu/drm/drm_plane.c uint32_t src_x, uint32_t src_y, uint32_t 732 drivers/gpu/drm/drm_plane.c uint32_t src_w, uint32_t src_h, uint32_t 765 drivers/gpu/drm/drm_plane.c uint32_t crtc_w, uint32_t crtc_h, uint32_t 767 drivers/gpu/drm/drm_plane.c uint32_t src_x, uint32_t src_y, uint32_t 768 drivers/gpu/drm/drm_plane.c uint32_t src_w, uint32_t src_h) uint32_t 858 drivers/gpu/drm/drm_plane.c uint32_t crtc_w = 0, crtc_h = 0; uint32_t 859 drivers/gpu/drm/drm_plane.c uint32_t src_w = 0, src_h = 0; uint32_t 153 drivers/gpu/drm/drm_plane_helper.c uint32_t src_x, uint32_t src_y, uint32_t 154 drivers/gpu/drm/drm_plane_helper.c uint32_t src_w, uint32_t src_h, uint32_t 92 drivers/gpu/drm/drm_prime.c uint32_t handle; uint32_t 99 drivers/gpu/drm/drm_prime.c struct dma_buf *dma_buf, uint32_t handle) uint32_t 146 drivers/gpu/drm/drm_prime.c uint32_t handle) uint32_t 168 drivers/gpu/drm/drm_prime.c uint32_t *handle) uint32_t 293 drivers/gpu/drm/drm_prime.c uint32_t *handle) uint32_t 375 drivers/gpu/drm/drm_prime.c uint32_t flags) uint32_t 423 drivers/gpu/drm/drm_prime.c struct drm_file *file_priv, uint32_t handle, uint32_t 424 drivers/gpu/drm/drm_prime.c uint32_t flags, uint32_t 389 drivers/gpu/drm/drm_probe_helper.c uint32_t maxX, uint32_t maxY) uint32_t 334 drivers/gpu/drm/drm_property.c uint32_t type) uint32_t 654 drivers/gpu/drm/drm_property.c uint32_t id) uint32_t 191 drivers/gpu/drm/drm_simple_kms_helper.c uint32_t format, uint32_t 262 drivers/gpu/drm/drm_simple_kms_helper.c const uint32_t *formats, unsigned int format_count, uint32_t 405 drivers/gpu/drm/drm_syncobj.c int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags, uint32_t 466 drivers/gpu/drm/drm_syncobj.c u32 *handle, uint32_t flags) uint32_t 871 drivers/gpu/drm/drm_syncobj.c uint32_t count, uint32_t 872 drivers/gpu/drm/drm_syncobj.c uint32_t flags, uint32_t 874 drivers/gpu/drm/drm_syncobj.c uint32_t *idx) uint32_t 879 drivers/gpu/drm/drm_syncobj.c uint32_t signaled_count, i; uint32_t 1052 drivers/gpu/drm/drm_syncobj.c uint32_t first = ~0; uint32_t 1080 drivers/gpu/drm/drm_syncobj.c uint32_t count_handles, uint32_t 1083 drivers/gpu/drm/drm_syncobj.c uint32_t i, *handles; uint32_t 1092 drivers/gpu/drm/drm_syncobj.c sizeof(uint32_t) * count_handles)) { uint32_t 1126 drivers/gpu/drm/drm_syncobj.c uint32_t count) uint32_t 1128 drivers/gpu/drm/drm_syncobj.c uint32_t i; uint32_t 1208 drivers/gpu/drm/drm_syncobj.c uint32_t i; uint32_t 1241 drivers/gpu/drm/drm_syncobj.c uint32_t i; uint32_t 1276 drivers/gpu/drm/drm_syncobj.c uint32_t i, j; uint32_t 1347 drivers/gpu/drm/drm_syncobj.c uint32_t i; uint32_t 95 drivers/gpu/drm/drm_vm.c static pgprot_t drm_dma_prot(uint32_t map_type, struct vm_area_struct *vma) uint32_t 37 drivers/gpu/drm/drm_vram_mm_helper.c uint32_t page_flags) uint32_t 59 drivers/gpu/drm/drm_vram_mm_helper.c static int bo_driver_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, uint32_t 75 drivers/gpu/drm/exynos/exynos5433_drm_decon.c static const uint32_t decon_formats[] = { uint32_t 67 drivers/gpu/drm/exynos/exynos7_drm_decon.c static const uint32_t decon_formats[] = { uint32_t 113 drivers/gpu/drm/exynos/exynos_drm_drv.h const uint32_t *pixel_formats; uint32_t 221 drivers/gpu/drm/exynos/exynos_drm_fimd.c static const uint32_t fimd_formats[] = { uint32_t 643 drivers/gpu/drm/exynos/exynos_drm_fimd.c uint32_t pixel_format = fb->format->format; uint32_t 108 drivers/gpu/drm/exynos/exynos_drm_ipp.c uint32_t __user *ipp_ptr = (uint32_t __user *) uint32_t 128 drivers/gpu/drm/exynos/exynos_drm_ipp.c static inline struct exynos_drm_ipp *__ipp_get(uint32_t id) uint32_t 189 drivers/gpu/drm/exynos/exynos_drm_ipp.c struct exynos_drm_ipp *ipp, uint32_t fourcc, uint32_t 318 drivers/gpu/drm/exynos/exynos_drm_ipp.c uint32_t id; uint32_t 322 drivers/gpu/drm/exynos/exynos_drm_ipp.c if (get_user(id, (uint32_t __user *)params)) uint32_t 104 drivers/gpu/drm/exynos/exynos_drm_ipp.h uint32_t fourcc; uint32_t 105 drivers/gpu/drm/exynos/exynos_drm_ipp.h uint32_t type; uint32_t 80 drivers/gpu/drm/exynos/exynos_drm_vidi.c static const uint32_t formats[] = { uint32_t 78 drivers/gpu/drm/exynos/exynos_mixer.c static const uint32_t mixer_formats[] = { uint32_t 88 drivers/gpu/drm/exynos/exynos_mixer.c static const uint32_t vp_formats[] = { uint32_t 73 drivers/gpu/drm/gma500/accel_2d.c uint32_t avail = PSB_RSGX32(PSB_CR_2D_SOCIF); uint32_t 95 drivers/gpu/drm/gma500/accel_2d.c static int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf, uint32_t 160 drivers/gpu/drm/gma500/accel_2d.c uint32_t src_offset, uint32_t src_stride, uint32_t 161 drivers/gpu/drm/gma500/accel_2d.c uint32_t src_format, uint32_t dst_offset, uint32_t 162 drivers/gpu/drm/gma500/accel_2d.c uint32_t dst_stride, uint32_t dst_format, uint32_t 167 drivers/gpu/drm/gma500/accel_2d.c uint32_t blit_cmd; uint32_t 168 drivers/gpu/drm/gma500/accel_2d.c uint32_t buffer[10]; uint32_t 169 drivers/gpu/drm/gma500/accel_2d.c uint32_t *buf; uint32_t 170 drivers/gpu/drm/gma500/accel_2d.c uint32_t direction; uint32_t 234 drivers/gpu/drm/gma500/accel_2d.c uint32_t offset; uint32_t 235 drivers/gpu/drm/gma500/accel_2d.c uint32_t stride; uint32_t 236 drivers/gpu/drm/gma500/accel_2d.c uint32_t src_format; uint32_t 237 drivers/gpu/drm/gma500/accel_2d.c uint32_t dst_format; uint32_t 180 drivers/gpu/drm/gma500/cdv_device.c uint32_t ret_val = 0; uint32_t 258 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t output_reg; uint32_t 259 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t DP; uint32_t 263 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t color_range; uint32_t 282 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t PreEmph1; uint32_t 283 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t PreEmph2; uint32_t 284 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t VSwing1; uint32_t 285 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t VSwing2; uint32_t 286 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t VSwing3; uint32_t 287 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t VSwing4; uint32_t 288 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t VSwing5; uint32_t 300 drivers/gpu/drm/gma500/cdv_intel_dp.c static uint32_t dp_vswing_premph_table[] = { uint32_t 545 drivers/gpu/drm/gma500/cdv_intel_dp.c static uint32_t uint32_t 549 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t v = 0; uint32_t 554 drivers/gpu/drm/gma500/cdv_intel_dp.c v |= ((uint32_t) src[i]) << ((3-i) * 8); uint32_t 559 drivers/gpu/drm/gma500/cdv_intel_dp.c unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) uint32_t 574 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t output_reg = intel_dp->output_reg; uint32_t 576 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t ch_ctl = output_reg + 0x10; uint32_t 577 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t ch_data = ch_ctl + 4; uint32_t 580 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t status; uint32_t 581 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t aux_clock_divider; uint32_t 946 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t tu; uint32_t 947 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t gmch_m; uint32_t 948 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t gmch_n; uint32_t 949 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t link_m; uint32_t 950 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t link_n; uint32_t 954 drivers/gpu/drm/gma500/cdv_intel_dp.c cdv_intel_reduce_ratio(uint32_t *num, uint32_t *den) uint32_t 1092 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t pfit_control; uint32_t 1175 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t dp_reg = REG_READ(intel_dp->output_reg); uint32_t 1386 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t dp_reg_value, uint32_t 1508 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t DP = intel_dp->DP; uint32_t 1600 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t DP = intel_dp->DP; uint32_t 1683 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t DP = intel_dp->DP; uint32_t 43 drivers/gpu/drm/gma500/cdv_intel_lvds.c uint32_t savePP_ON; uint32_t 44 drivers/gpu/drm/gma500/cdv_intel_lvds.c uint32_t savePP_OFF; uint32_t 45 drivers/gpu/drm/gma500/cdv_intel_lvds.c uint32_t saveLVDS; uint32_t 46 drivers/gpu/drm/gma500/cdv_intel_lvds.c uint32_t savePP_CONTROL; uint32_t 47 drivers/gpu/drm/gma500/cdv_intel_lvds.c uint32_t savePP_CYCLE; uint32_t 48 drivers/gpu/drm/gma500/cdv_intel_lvds.c uint32_t savePFIT_CONTROL; uint32_t 49 drivers/gpu/drm/gma500/cdv_intel_lvds.c uint32_t savePFIT_PGM_RATIOS; uint32_t 50 drivers/gpu/drm/gma500/cdv_intel_lvds.c uint32_t saveBLC_PWM_CTL; uint32_t 45 drivers/gpu/drm/gma500/framebuffer.c uint32_t v; uint32_t 66 drivers/gpu/drm/gma500/framebuffer.c ((uint32_t *) info->pseudo_palette)[regno] = v; uint32_t 70 drivers/gpu/drm/gma500/framebuffer.c ((uint32_t *) info->pseudo_palette)[regno] = v; uint32_t 12 drivers/gpu/drm/gma500/gma_device.c uint32_t clock; uint32_t 321 drivers/gpu/drm/gma500/gma_display.c uint32_t handle, uint32_t 322 drivers/gpu/drm/gma500/gma_display.c uint32_t width, uint32_t height) uint32_t 328 drivers/gpu/drm/gma500/gma_display.c uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; uint32_t 329 drivers/gpu/drm/gma500/gma_display.c uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; uint32_t 330 drivers/gpu/drm/gma500/gma_display.c uint32_t temp; uint32_t 445 drivers/gpu/drm/gma500/gma_display.c uint32_t temp = 0; uint32_t 446 drivers/gpu/drm/gma500/gma_display.c uint32_t addr; uint32_t 531 drivers/gpu/drm/gma500/gma_display.c uint32_t palette_reg; uint32_t 574 drivers/gpu/drm/gma500/gma_display.c uint32_t palette_reg; uint32_t 62 drivers/gpu/drm/gma500/gma_display.h uint32_t handle, uint32_t 63 drivers/gpu/drm/gma500/gma_display.h uint32_t width, uint32_t height); uint32_t 29 drivers/gpu/drm/gma500/gtt.c static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type) uint32_t 31 drivers/gpu/drm/gma500/gtt.c uint32_t mask = PSB_PTE_VALID; uint32_t 416 drivers/gpu/drm/gma500/gtt.c uint32_t pte; uint32_t 15 drivers/gpu/drm/gma500/gtt.h uint32_t gatt_start; uint32_t 16 drivers/gpu/drm/gma500/gtt.h uint32_t mmu_gatt_start; uint32_t 17 drivers/gpu/drm/gma500/gtt.h uint32_t gtt_start; uint32_t 18 drivers/gpu/drm/gma500/gtt.h uint32_t gtt_phys_start; uint32_t 25 drivers/gpu/drm/gma500/mid_bios.c uint32_t fuse_value = 0; uint32_t 26 drivers/gpu/drm/gma500/mid_bios.c uint32_t fuse_value_tmp = 0; uint32_t 95 drivers/gpu/drm/gma500/mid_bios.c uint32_t platform_rev_id = 0; uint32_t 41 drivers/gpu/drm/gma500/mmu.c static inline uint32_t psb_mmu_pt_index(uint32_t offset) uint32_t 46 drivers/gpu/drm/gma500/mmu.c static inline uint32_t psb_mmu_pd_index(uint32_t offset) uint32_t 80 drivers/gpu/drm/gma500/mmu.c uint32_t val = PSB_RSGX32(PSB_CR_BIF_CTRL); uint32_t 106 drivers/gpu/drm/gma500/mmu.c uint32_t val; uint32_t 132 drivers/gpu/drm/gma500/mmu.c uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 : uint32_t 151 drivers/gpu/drm/gma500/mmu.c static inline uint32_t psb_mmu_mask_pte(uint32_t pfn, int type) uint32_t 153 drivers/gpu/drm/gma500/mmu.c uint32_t mask = PSB_PTE_VALID; uint32_t 169 drivers/gpu/drm/gma500/mmu.c uint32_t *v; uint32_t 196 drivers/gpu/drm/gma500/mmu.c for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i) uint32_t 202 drivers/gpu/drm/gma500/mmu.c for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i) uint32_t 272 drivers/gpu/drm/gma500/mmu.c uint32_t clflush_add = pd->driver->clflush_add >> PAGE_SHIFT; uint32_t 273 drivers/gpu/drm/gma500/mmu.c uint32_t clflush_count = PAGE_SIZE / clflush_add; uint32_t 276 drivers/gpu/drm/gma500/mmu.c uint32_t *ptes; uint32_t 292 drivers/gpu/drm/gma500/mmu.c ptes = (uint32_t *) v; uint32_t 293 drivers/gpu/drm/gma500/mmu.c for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i) uint32_t 319 drivers/gpu/drm/gma500/mmu.c uint32_t index = psb_mmu_pd_index(addr); uint32_t 321 drivers/gpu/drm/gma500/mmu.c uint32_t *v; uint32_t 359 drivers/gpu/drm/gma500/mmu.c uint32_t index = psb_mmu_pd_index(addr); uint32_t 376 drivers/gpu/drm/gma500/mmu.c uint32_t *v; uint32_t 397 drivers/gpu/drm/gma500/mmu.c uint32_t pte) uint32_t 420 drivers/gpu/drm/gma500/mmu.c uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver) uint32_t 473 drivers/gpu/drm/gma500/mmu.c uint32_t tfms, misc, cap0, cap4, clflush_size; uint32_t 484 drivers/gpu/drm/gma500/mmu.c PAGE_SIZE * clflush_size / sizeof(uint32_t); uint32_t 500 drivers/gpu/drm/gma500/mmu.c uint32_t num_pages, uint32_t desired_tile_stride, uint32_t 501 drivers/gpu/drm/gma500/mmu.c uint32_t hw_tile_stride) uint32_t 504 drivers/gpu/drm/gma500/mmu.c uint32_t rows = 1; uint32_t 505 drivers/gpu/drm/gma500/mmu.c uint32_t i; uint32_t 548 drivers/gpu/drm/gma500/mmu.c uint32_t num_pages, uint32_t desired_tile_stride, uint32_t 549 drivers/gpu/drm/gma500/mmu.c uint32_t hw_tile_stride) uint32_t 556 drivers/gpu/drm/gma500/mmu.c unsigned long address, uint32_t num_pages) uint32_t 595 drivers/gpu/drm/gma500/mmu.c uint32_t num_pages, uint32_t desired_tile_stride, uint32_t 596 drivers/gpu/drm/gma500/mmu.c uint32_t hw_tile_stride) uint32_t 599 drivers/gpu/drm/gma500/mmu.c uint32_t rows = 1; uint32_t 600 drivers/gpu/drm/gma500/mmu.c uint32_t i; uint32_t 650 drivers/gpu/drm/gma500/mmu.c int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn, uint32_t 651 drivers/gpu/drm/gma500/mmu.c unsigned long address, uint32_t num_pages, uint32_t 655 drivers/gpu/drm/gma500/mmu.c uint32_t pte; uint32_t 697 drivers/gpu/drm/gma500/mmu.c unsigned long address, uint32_t num_pages, uint32_t 698 drivers/gpu/drm/gma500/mmu.c uint32_t desired_tile_stride, uint32_t hw_tile_stride, uint32_t 702 drivers/gpu/drm/gma500/mmu.c uint32_t rows = 1; uint32_t 703 drivers/gpu/drm/gma500/mmu.c uint32_t i; uint32_t 704 drivers/gpu/drm/gma500/mmu.c uint32_t pte; uint32_t 763 drivers/gpu/drm/gma500/mmu.c int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual, uint32_t 768 drivers/gpu/drm/gma500/mmu.c uint32_t tmp; uint32_t 774 drivers/gpu/drm/gma500/mmu.c uint32_t *v; uint32_t 25 drivers/gpu/drm/gma500/mmu.h uint32_t bif_ctrl; uint32_t 37 drivers/gpu/drm/gma500/mmu.h uint32_t index; uint32_t 38 drivers/gpu/drm/gma500/mmu.h uint32_t count; uint32_t 40 drivers/gpu/drm/gma500/mmu.h uint32_t *v; uint32_t 50 drivers/gpu/drm/gma500/mmu.h uint32_t pd_mask; uint32_t 51 drivers/gpu/drm/gma500/mmu.h uint32_t invalid_pde; uint32_t 52 drivers/gpu/drm/gma500/mmu.h uint32_t invalid_pte; uint32_t 69 drivers/gpu/drm/gma500/mmu.h uint32_t num_pages); uint32_t 71 drivers/gpu/drm/gma500/mmu.h uint32_t start_pfn, uint32_t 73 drivers/gpu/drm/gma500/mmu.h uint32_t num_pages, int type); uint32_t 74 drivers/gpu/drm/gma500/mmu.h extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual, uint32_t 78 drivers/gpu/drm/gma500/mmu.h unsigned long address, uint32_t num_pages, uint32_t 79 drivers/gpu/drm/gma500/mmu.h uint32_t desired_tile_stride, uint32_t 80 drivers/gpu/drm/gma500/mmu.h uint32_t hw_tile_stride, int type); uint32_t 82 drivers/gpu/drm/gma500/mmu.h unsigned long address, uint32_t num_pages, uint32_t 83 drivers/gpu/drm/gma500/mmu.h uint32_t desired_tile_stride, uint32_t 84 drivers/gpu/drm/gma500/mmu.h uint32_t hw_tile_stride); uint32_t 105 drivers/gpu/drm/gma500/oaktrail_device.c uint32_t value; uint32_t 106 drivers/gpu/drm/gma500/oaktrail_device.c uint32_t blc_pwm_precision_factor; uint32_t 63 drivers/gpu/drm/gma500/psb_device.c uint32_t value; uint32_t 64 drivers/gpu/drm/gma500/psb_device.c uint32_t blc_pwm_precision_factor; uint32_t 112 drivers/gpu/drm/gma500/psb_drv.c uint32_t stolen_gtt; uint32_t 325 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveVCLK_DIVISOR_VGA0; uint32_t 326 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveVCLK_DIVISOR_VGA1; uint32_t 327 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveVCLK_POST_DIV; uint32_t 328 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveVGACNTRL; uint32_t 329 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveADPA; uint32_t 330 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveLVDS; uint32_t 331 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDVOA; uint32_t 332 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDVOB; uint32_t 333 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDVOC; uint32_t 334 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_ON; uint32_t 335 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_OFF; uint32_t 336 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_CONTROL; uint32_t 337 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_CYCLE; uint32_t 338 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePFIT_CONTROL; uint32_t 339 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveCLOCKGATING; uint32_t 340 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPARB; uint32_t 341 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePFIT_AUTO_RATIOS; uint32_t 342 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePFIT_PGM_RATIOS; uint32_t 343 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_ON_DELAYS; uint32_t 344 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_OFF_DELAYS; uint32_t 345 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_DIVISOR; uint32_t 346 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveBCLRPAT_A; uint32_t 347 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveBCLRPAT_B; uint32_t 348 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePERF_MODE; uint32_t 349 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPFW1; uint32_t 350 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPFW2; uint32_t 351 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPFW3; uint32_t 352 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPFW4; uint32_t 353 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPFW5; uint32_t 354 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPFW6; uint32_t 355 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveCHICKENBIT; uint32_t 356 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPACURSOR_CTRL; uint32_t 357 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPBCURSOR_CTRL; uint32_t 358 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPACURSOR_BASE; uint32_t 359 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPBCURSOR_BASE; uint32_t 360 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPACURSOR_POS; uint32_t 361 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPBCURSOR_POS; uint32_t 362 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOV_OVADD; uint32_t 363 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOV_OGAMC0; uint32_t 364 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOV_OGAMC1; uint32_t 365 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOV_OGAMC2; uint32_t 366 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOV_OGAMC3; uint32_t 367 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOV_OGAMC4; uint32_t 368 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOV_OGAMC5; uint32_t 369 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOVC_OVADD; uint32_t 370 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOVC_OGAMC0; uint32_t 371 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOVC_OGAMC1; uint32_t 372 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOVC_OGAMC2; uint32_t 373 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOVC_OGAMC3; uint32_t 374 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOVC_OGAMC4; uint32_t 375 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveOVC_OGAMC5; uint32_t 378 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveHISTOGRAM_INT_CONTROL_REG; uint32_t 379 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; uint32_t 380 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePWM_CONTROL_LOGIC; uint32_t 384 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveMIPI; uint32_t 385 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveMIPI_C; uint32_t 387 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePFIT_CONTROL; uint32_t 388 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePFIT_PGM_RATIOS; uint32_t 389 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveHDMIPHYMISCCTL; uint32_t 390 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveHDMIB_CONTROL; uint32_t 394 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPCLK_GATE_D; uint32_t 395 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveRAMCLK_GATE_D; uint32_t 396 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPARB; uint32_t 397 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveDSPFW[6]; uint32_t 398 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveADPA; uint32_t 399 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_CONTROL; uint32_t 400 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePFIT_PGM_RATIOS; uint32_t 401 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveLVDS; uint32_t 402 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePFIT_CONTROL; uint32_t 403 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_ON_DELAYS; uint32_t 404 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_OFF_DELAYS; uint32_t 405 drivers/gpu/drm/gma500/psb_drv.h uint32_t savePP_CYCLE; uint32_t 406 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveVGACNTRL; uint32_t 407 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveIER; uint32_t 408 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveIMR; uint32_t 414 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveBSM; uint32_t 415 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveVBT; uint32_t 421 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveBLC_PWM_CTL2; uint32_t 422 drivers/gpu/drm/gma500/psb_drv.h uint32_t saveBLC_PWM_CTL; uint32_t 445 drivers/gpu/drm/gma500/psb_drv.h uint32_t stolen_base; uint32_t 465 drivers/gpu/drm/gma500/psb_drv.h uint32_t gatt_free_offset; uint32_t 468 drivers/gpu/drm/gma500/psb_drv.h uint32_t vdc_irq_mask; uint32_t 469 drivers/gpu/drm/gma500/psb_drv.h uint32_t pipestat[PSB_NUM_PIPE]; uint32_t 484 drivers/gpu/drm/gma500/psb_drv.h uint32_t num_pipe; uint32_t 487 drivers/gpu/drm/gma500/psb_drv.h uint32_t ospm_base; uint32_t 532 drivers/gpu/drm/gma500/psb_drv.h uint32_t iLVDS_enable; uint32_t 548 drivers/gpu/drm/gma500/psb_drv.h uint32_t msi_addr; uint32_t 549 drivers/gpu/drm/gma500/psb_drv.h uint32_t msi_data; uint32_t 561 drivers/gpu/drm/gma500/psb_drv.h uint32_t apm_reg; uint32_t 572 drivers/gpu/drm/gma500/psb_drv.h uint32_t blc_adj1; uint32_t 573 drivers/gpu/drm/gma500/psb_drv.h uint32_t blc_adj2; uint32_t 775 drivers/gpu/drm/gma500/psb_drv.h uint32_t ret_val = 0; uint32_t 794 drivers/gpu/drm/gma500/psb_drv.h uint32_t ret_val = 0; uint32_t 811 drivers/gpu/drm/gma500/psb_drv.h static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) uint32_t 817 drivers/gpu/drm/gma500/psb_drv.h static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg) uint32_t 827 drivers/gpu/drm/gma500/psb_drv.h static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev, uint32_t 828 drivers/gpu/drm/gma500/psb_drv.h uint32_t reg, int aux) uint32_t 830 drivers/gpu/drm/gma500/psb_drv.h uint32_t val; uint32_t 842 drivers/gpu/drm/gma500/psb_drv.h static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, uint32_t 843 drivers/gpu/drm/gma500/psb_drv.h uint32_t val) uint32_t 849 drivers/gpu/drm/gma500/psb_drv.h static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg, uint32_t 850 drivers/gpu/drm/gma500/psb_drv.h uint32_t val) uint32_t 859 drivers/gpu/drm/gma500/psb_drv.h static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg, uint32_t 860 drivers/gpu/drm/gma500/psb_drv.h uint32_t val, int aux) uint32_t 871 drivers/gpu/drm/gma500/psb_drv.h uint32_t reg, uint32_t val) uint32_t 880 drivers/gpu/drm/gma500/psb_drv.h uint32_t reg, uint32_t val) uint32_t 97 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveBLC_PWM_CTL; uint32_t 138 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveDSPCNTR; uint32_t 139 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t savePIPECONF; uint32_t 140 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t savePIPESRC; uint32_t 141 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveDPLL; uint32_t 142 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveFP0; uint32_t 143 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveFP1; uint32_t 144 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveHTOTAL; uint32_t 145 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveHBLANK; uint32_t 146 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveHSYNC; uint32_t 147 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveVTOTAL; uint32_t 148 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveVBLANK; uint32_t 149 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveVSYNC; uint32_t 150 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveDSPSTRIDE; uint32_t 151 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveDSPSIZE; uint32_t 152 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveDSPPOS; uint32_t 153 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t saveDSPBASE; uint32_t 154 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t savePalette[256]; uint32_t 161 drivers/gpu/drm/gma500/psb_intel_drv.h uint32_t cursor_addr; uint32_t 41 drivers/gpu/drm/gma500/psb_intel_lvds.c uint32_t savePP_ON; uint32_t 42 drivers/gpu/drm/gma500/psb_intel_lvds.c uint32_t savePP_OFF; uint32_t 43 drivers/gpu/drm/gma500/psb_intel_lvds.c uint32_t saveLVDS; uint32_t 44 drivers/gpu/drm/gma500/psb_intel_lvds.c uint32_t savePP_CONTROL; uint32_t 45 drivers/gpu/drm/gma500/psb_intel_lvds.c uint32_t savePP_CYCLE; uint32_t 46 drivers/gpu/drm/gma500/psb_intel_lvds.c uint32_t savePFIT_CONTROL; uint32_t 47 drivers/gpu/drm/gma500/psb_intel_lvds.c uint32_t savePFIT_PGM_RATIOS; uint32_t 48 drivers/gpu/drm/gma500/psb_intel_lvds.c uint32_t saveBLC_PWM_CTL; uint32_t 555 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t data; uint32_t 557 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t bin_reg_index:7; uint32_t 558 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t reserved:4; uint32_t 559 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t bin_reg_func_select:1; uint32_t 560 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t sync_to_phase_in:1; uint32_t 561 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t alt_enhancement_mode:2; uint32_t 562 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t reserved1:1; uint32_t 563 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t sync_to_phase_in_count:8; uint32_t 564 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t histogram_mode_select:1; uint32_t 565 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t reserved2:4; uint32_t 566 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t ie_pipe_assignment:1; uint32_t 567 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t ie_mode_table_enabled:1; uint32_t 568 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t ie_histogram_enable:1; uint32_t 575 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t data; uint32_t 577 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t guardband:22; uint32_t 578 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t guardband_interrupt_delay:8; uint32_t 579 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t interrupt_status:1; uint32_t 580 drivers/gpu/drm/gma500/psb_intel_reg.h uint32_t interrupt_enable:1; uint32_t 100 drivers/gpu/drm/gma500/psb_intel_sdvo.c uint32_t color_range; uint32_t 139 drivers/gpu/drm/gma500/psb_intel_sdvo.c uint32_t saveSDVO; /* Can be SDVOB or SDVOC depending on sdvo_reg */ uint32_t 902 drivers/gpu/drm/gma500/psb_intel_sdvo.c uint32_t format_map; uint32_t 1553 drivers/gpu/drm/gma500/psb_intel_sdvo.c uint32_t reply = 0, format_map = 0; uint32_t 2262 drivers/gpu/drm/gma500/psb_intel_sdvo.c uint32_t format_map, i; uint32_t 138 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipe_stat_val = 0; uint32_t 139 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipe_stat_reg = psb_pipestat(pipe); uint32_t 140 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipe_enable = dev_priv->pipestat[pipe]; uint32_t 141 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16; uint32_t 142 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipe_clear; uint32_t 143 drivers/gpu/drm/gma500/psb_irq.c uint32_t i = 0; uint32_t 178 drivers/gpu/drm/gma500/psb_irq.c static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat) uint32_t 246 drivers/gpu/drm/gma500/psb_irq.c uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0; uint32_t 504 drivers/gpu/drm/gma500/psb_irq.c uint32_t reg_val = 0; uint32_t 505 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipeconf_reg = mid_pipeconf(pipe); uint32_t 568 drivers/gpu/drm/gma500/psb_irq.c uint32_t reg_val = 0; uint32_t 569 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipeconf_reg = mid_pipeconf(pipe); uint32_t 614 drivers/gpu/drm/gma500/psb_irq.c uint32_t high_frame = PIPEAFRAMEHIGH; uint32_t 615 drivers/gpu/drm/gma500/psb_irq.c uint32_t low_frame = PIPEAFRAMEPIXEL; uint32_t 616 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipeconf_reg = PIPEACONF; uint32_t 617 drivers/gpu/drm/gma500/psb_irq.c uint32_t reg_val = 0; uint32_t 618 drivers/gpu/drm/gma500/psb_irq.c uint32_t high1 = 0, high2 = 0, low = 0, count = 0; uint32_t 238 drivers/gpu/drm/i2c/ch7006_mode.c uint32_t subc_inc; uint32_t 58 drivers/gpu/drm/i2c/ch7006_priv.h uint32_t dispmode; uint32_t 69 drivers/gpu/drm/i2c/ch7006_priv.h uint32_t dispmode; uint32_t 71 drivers/gpu/drm/i2c/ch7006_priv.h uint32_t valid_scales; uint32_t 72 drivers/gpu/drm/i2c/ch7006_priv.h uint32_t valid_norms; uint32_t 129 drivers/gpu/drm/imx/imx-drm-core.c uint32_t crtc_mask = drm_of_find_possible_crtcs(drm, np); uint32_t 37 drivers/gpu/drm/imx/ipuv3-plane.c static const uint32_t ipu_plane_formats[] = { uint32_t 321 drivers/gpu/drm/imx/ipuv3-plane.c uint32_t format, uint64_t modifier) uint32_t 41 drivers/gpu/drm/imx/ipuv3-plane.h uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t 42 drivers/gpu/drm/imx/ipuv3-plane.h uint32_t src_h, bool interlaced); uint32_t 50 drivers/gpu/drm/meson/meson_drv.h uint32_t osd1_ctrl_stat; uint32_t 51 drivers/gpu/drm/meson/meson_drv.h uint32_t osd1_blk0_cfg[5]; uint32_t 52 drivers/gpu/drm/meson/meson_drv.h uint32_t osd1_addr; uint32_t 53 drivers/gpu/drm/meson/meson_drv.h uint32_t osd1_stride; uint32_t 54 drivers/gpu/drm/meson/meson_drv.h uint32_t osd1_height; uint32_t 55 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_ctrl0; uint32_t 56 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_i_wh_m1; uint32_t 57 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_o_h_start_end; uint32_t 58 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_o_v_start_end; uint32_t 59 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_v_ini_phase; uint32_t 60 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_v_phase_step; uint32_t 61 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_h_ini_phase; uint32_t 62 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_h_phase_step; uint32_t 63 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_h_ctrl0; uint32_t 64 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_sc_v_ctrl0; uint32_t 65 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_blend_din0_scope_h; uint32_t 66 drivers/gpu/drm/meson/meson_drv.h uint32_t osd_blend_din0_scope_v; uint32_t 67 drivers/gpu/drm/meson/meson_drv.h uint32_t osb_blend0_size; uint32_t 68 drivers/gpu/drm/meson/meson_drv.h uint32_t osb_blend1_size; uint32_t 73 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_gen_reg; uint32_t 74 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_luma_x0; uint32_t 75 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_luma_y0; uint32_t 76 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_chroma_x0; uint32_t 77 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_chroma_y0; uint32_t 78 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_repeat_loop; uint32_t 79 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_luma0_rpt_pat; uint32_t 80 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_chroma0_rpt_pat; uint32_t 81 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_range_map_y; uint32_t 82 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_range_map_cb; uint32_t 83 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_range_map_cr; uint32_t 84 drivers/gpu/drm/meson/meson_drv.h uint32_t viu_vd1_fmt_w; uint32_t 85 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_canvas0; uint32_t 86 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_if0_gen_reg2; uint32_t 87 drivers/gpu/drm/meson/meson_drv.h uint32_t viu_vd1_fmt_ctrl; uint32_t 88 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_addr0; uint32_t 89 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_addr1; uint32_t 90 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_addr2; uint32_t 91 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_stride0; uint32_t 92 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_stride1; uint32_t 93 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_stride2; uint32_t 94 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_height0; uint32_t 95 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_height1; uint32_t 96 drivers/gpu/drm/meson/meson_drv.h uint32_t vd1_height2; uint32_t 97 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_pic_in_height; uint32_t 98 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_postblend_vd1_h_start_end; uint32_t 99 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_postblend_vd1_v_start_end; uint32_t 100 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_hsc_region12_startp; uint32_t 101 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_hsc_region34_startp; uint32_t 102 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_hsc_region4_endp; uint32_t 103 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_hsc_start_phase_step; uint32_t 104 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_hsc_region1_phase_slope; uint32_t 105 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_hsc_region3_phase_slope; uint32_t 106 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_line_in_length; uint32_t 107 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_preblend_h_size; uint32_t 108 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_vsc_region12_startp; uint32_t 109 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_vsc_region34_startp; uint32_t 110 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_vsc_region4_endp; uint32_t 111 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_vsc_start_phase_step; uint32_t 112 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_vsc_ini_phase; uint32_t 113 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_vsc_phase_ctrl; uint32_t 114 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_hsc_phase_ctrl; uint32_t 115 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_blend_vd2_h_start_end; uint32_t 116 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_blend_vd2_v_start_end; uint32_t 543 drivers/gpu/drm/meson/meson_overlay.c static const uint32_t supported_drm_formats[] = { uint32_t 357 drivers/gpu/drm/meson/meson_plane.c static const uint32_t supported_drm_formats[] = { uint32_t 314 drivers/gpu/drm/meson/meson_viu.c uint32_t osd1_fifo_ctrl_stat, osd1_ctrl_stat2; uint32_t 338 drivers/gpu/drm/meson/meson_viu.c static inline uint32_t meson_viu_osd_burst_length_reg(uint32_t length) uint32_t 340 drivers/gpu/drm/meson/meson_viu.c uint32_t val = (((length & 0x80) % 24) / 12); uint32_t 347 drivers/gpu/drm/meson/meson_viu.c uint32_t reg; uint32_t 66 drivers/gpu/drm/meson/meson_vpp.c static const uint32_t vpp_filter_coefs_bicubic[] = { uint32_t 30 drivers/gpu/drm/mgag200/mgag200_cursor.c uint32_t handle, uint32_t 31 drivers/gpu/drm/mgag200/mgag200_cursor.c uint32_t width, uint32_t 32 drivers/gpu/drm/mgag200/mgag200_cursor.c uint32_t height) uint32_t 45 drivers/gpu/drm/mgag200/mgag200_cursor.c uint32_t colour_set[16]; uint32_t 46 drivers/gpu/drm/mgag200/mgag200_cursor.c uint32_t *next_space = &colour_set[0]; uint32_t 47 drivers/gpu/drm/mgag200/mgag200_cursor.c uint32_t *palette_iter; uint32_t 48 drivers/gpu/drm/mgag200/mgag200_cursor.c uint32_t this_colour; uint32_t 124 drivers/gpu/drm/mgag200/mgag200_cursor.c memset(&colour_set[0], 0, sizeof(uint32_t)*16); uint32_t 226 drivers/gpu/drm/mgag200/mgag200_drv.h uint32_t handle, uint32_t width, uint32_t height); uint32_t 92 drivers/gpu/drm/mgag200/mgag200_main.c uint32_t flags) uint32_t 1384 drivers/gpu/drm/mgag200/mgag200_mode.c u16 *blue, uint32_t size, uint32_t 1537 drivers/gpu/drm/mgag200/mgag200_mode.c static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode, uint32_t 1540 drivers/gpu/drm/mgag200/mgag200_mode.c uint32_t total_area, divisor; uint32_t 1558 drivers/gpu/drm/mgag200/mgag200_mode.c return (uint32_t)(bandwidth); uint32_t 316 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 322 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 328 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 334 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 340 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 346 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 352 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 358 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 364 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 370 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 376 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) uint32_t 384 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) uint32_t 390 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) uint32_t 491 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) uint32_t 518 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) uint32_t 528 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) uint32_t 537 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) uint32_t 563 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) uint32_t 569 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) uint32_t 574 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } uint32_t 576 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } uint32_t 578 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } uint32_t 580 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } uint32_t 599 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) uint32_t 608 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) uint32_t 614 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) uint32_t 624 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) uint32_t 630 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) uint32_t 692 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) uint32_t 703 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) uint32_t 713 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) uint32_t 720 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) uint32_t 726 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) uint32_t 743 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) uint32_t 749 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) uint32_t 757 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) uint32_t 763 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) uint32_t 770 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) uint32_t 776 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) uint32_t 782 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) uint32_t 790 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) uint32_t 796 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) uint32_t 809 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) uint32_t 815 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) uint32_t 824 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) uint32_t 830 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) uint32_t 838 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) uint32_t 844 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) uint32_t 854 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) uint32_t 860 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) uint32_t 869 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) uint32_t 875 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) uint32_t 907 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) uint32_t 913 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) uint32_t 919 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) uint32_t 927 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) uint32_t 933 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) uint32_t 939 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) uint32_t 947 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) uint32_t 953 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) uint32_t 959 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) uint32_t 969 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) uint32_t 977 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) uint32_t 985 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) uint32_t 993 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) uint32_t 1001 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) uint32_t 1009 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) uint32_t 1017 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) uint32_t 1023 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) uint32_t 1033 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) uint32_t 1039 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) uint32_t 1045 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) uint32_t 1056 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) uint32_t 1062 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) uint32_t 1073 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) uint32_t 1079 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) uint32_t 1087 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) uint32_t 1093 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) uint32_t 1099 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) uint32_t 1105 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) uint32_t 1111 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) uint32_t 1117 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) uint32_t 1123 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) uint32_t 1129 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) uint32_t 1137 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) uint32_t 1143 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) uint32_t 1149 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) uint32_t 1155 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) uint32_t 1161 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) uint32_t 1167 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) uint32_t 1173 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) uint32_t 1179 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) uint32_t 1187 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) uint32_t 1193 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) uint32_t 1201 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) uint32_t 1207 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) uint32_t 1217 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) uint32_t 1223 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) uint32_t 1229 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) uint32_t 1235 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) uint32_t 1244 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) uint32_t 1258 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) uint32_t 1265 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) uint32_t 1271 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) uint32_t 1277 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) uint32_t 1283 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) uint32_t 1289 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) uint32_t 1295 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) uint32_t 1301 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) uint32_t 1307 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) uint32_t 1315 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) uint32_t 1321 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) uint32_t 1327 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) uint32_t 1333 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) uint32_t 1339 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) uint32_t 1345 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) uint32_t 1355 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) uint32_t 1366 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) uint32_t 1372 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) uint32_t 1378 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) uint32_t 1385 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) uint32_t 1391 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) uint32_t 1397 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) uint32_t 1403 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) uint32_t 1411 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) uint32_t 1417 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) uint32_t 1423 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) uint32_t 1433 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) uint32_t 1449 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) uint32_t 1455 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) uint32_t 1461 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) uint32_t 1497 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) uint32_t 1503 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) uint32_t 1509 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) uint32_t 1517 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) uint32_t 1529 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) uint32_t 1535 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) uint32_t 1541 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) uint32_t 1547 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) uint32_t 1557 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) uint32_t 1559 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; uint32_t 1563 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) uint32_t 1565 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; uint32_t 1571 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) uint32_t 1573 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; uint32_t 1577 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) uint32_t 1579 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; uint32_t 1585 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) uint32_t 1587 drivers/gpu/drm/msm/adreno/a2xx.xml.h return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; uint32_t 1593 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) uint32_t 1599 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) uint32_t 1605 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) uint32_t 1611 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) uint32_t 1620 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) uint32_t 1631 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) uint32_t 1642 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) uint32_t 1648 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) uint32_t 1656 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) uint32_t 1662 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) uint32_t 1668 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) uint32_t 1676 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) uint32_t 1684 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) uint32_t 1692 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) uint32_t 1700 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) uint32_t 1708 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) uint32_t 1714 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) uint32_t 1722 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) uint32_t 1728 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) uint32_t 1742 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) uint32_t 1750 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) uint32_t 1758 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) uint32_t 1765 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) uint32_t 1775 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) uint32_t 1783 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) uint32_t 1790 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) uint32_t 1796 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) uint32_t 1802 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) uint32_t 1808 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) uint32_t 1820 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) uint32_t 1826 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) uint32_t 1864 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) uint32_t 1870 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) uint32_t 1876 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) uint32_t 1882 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) uint32_t 1888 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) uint32_t 1894 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) uint32_t 1900 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) uint32_t 1906 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) uint32_t 1912 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) uint32_t 1921 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) uint32_t 1927 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) uint32_t 1933 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) uint32_t 1940 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) uint32_t 1946 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) uint32_t 1954 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) uint32_t 1960 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) uint32_t 1966 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) uint32_t 1974 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) uint32_t 1980 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) uint32_t 1986 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) uint32_t 1992 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) uint32_t 1998 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) uint32_t 2004 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val) uint32_t 2010 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) uint32_t 2016 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) uint32_t 2022 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) uint32_t 2028 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) uint32_t 2034 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) uint32_t 2042 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) uint32_t 2048 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) uint32_t 2054 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) uint32_t 2060 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) uint32_t 2068 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) uint32_t 2074 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) uint32_t 2080 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) uint32_t 2088 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) uint32_t 2095 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) uint32_t 2101 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) uint32_t 2107 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) uint32_t 2114 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) uint32_t 64 drivers/gpu/drm/msm/adreno/a2xx_gpu.c uint32_t *ptr, len; uint32_t 174 drivers/gpu/drm/msm/adreno/a2xx_gpu.c ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data); uint32_t 185 drivers/gpu/drm/msm/adreno/a2xx_gpu.c ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PFP]->data); uint32_t 254 drivers/gpu/drm/msm/adreno/a2xx_gpu.c uint32_t mstatus, status; uint32_t 917 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } uint32_t 919 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } uint32_t 946 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) uint32_t 954 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) uint32_t 960 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) uint32_t 968 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) uint32_t 976 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) uint32_t 984 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) uint32_t 992 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) uint32_t 1000 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) uint32_t 1008 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) uint32_t 1016 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) uint32_t 1018 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; uint32_t 1022 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) uint32_t 1024 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; uint32_t 1030 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) uint32_t 1038 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) uint32_t 1046 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) uint32_t 1057 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) uint32_t 1066 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) uint32_t 1072 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) uint32_t 1078 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) uint32_t 1087 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) uint32_t 1093 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) uint32_t 1102 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) uint32_t 1108 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) uint32_t 1117 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) uint32_t 1123 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) uint32_t 1132 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) uint32_t 1138 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) uint32_t 1147 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) uint32_t 1153 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) uint32_t 1167 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) uint32_t 1182 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) uint32_t 1193 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 1199 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) uint32_t 1207 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) uint32_t 1213 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) uint32_t 1218 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } uint32_t 1220 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } uint32_t 1226 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) uint32_t 1232 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) uint32_t 1238 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) uint32_t 1243 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } uint32_t 1246 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) uint32_t 1252 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) uint32_t 1258 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 1265 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) uint32_t 1270 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } uint32_t 1273 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) uint32_t 1278 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } uint32_t 1281 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) uint32_t 1287 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) uint32_t 1293 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) uint32_t 1299 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) uint32_t 1305 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) uint32_t 1311 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) uint32_t 1320 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) uint32_t 1326 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) uint32_t 1334 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) uint32_t 1340 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) uint32_t 1348 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) uint32_t 1354 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) uint32_t 1362 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) uint32_t 1368 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) uint32_t 1384 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) uint32_t 1391 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) uint32_t 1398 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) uint32_t 1405 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) uint32_t 1413 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) uint32_t 1421 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) uint32_t 1429 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) uint32_t 1435 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) uint32_t 1441 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) uint32_t 1447 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) uint32_t 1453 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) uint32_t 1459 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) uint32_t 1471 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) uint32_t 1483 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) uint32_t 1489 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) uint32_t 1497 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) uint32_t 1508 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) uint32_t 1514 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) uint32_t 1520 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) uint32_t 1526 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) uint32_t 1532 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) uint32_t 1538 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) uint32_t 1544 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) uint32_t 1550 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) uint32_t 1560 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) uint32_t 1568 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) uint32_t 1576 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) uint32_t 1582 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) uint32_t 1588 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) uint32_t 1596 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) uint32_t 1602 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) uint32_t 1608 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) uint32_t 1619 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) uint32_t 1625 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) uint32_t 1647 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) uint32_t 1653 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) uint32_t 1663 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) uint32_t 1669 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) uint32_t 1675 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) uint32_t 1689 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) uint32_t 1699 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) uint32_t 1707 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) uint32_t 1719 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) uint32_t 1726 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) uint32_t 1732 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) uint32_t 1740 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) uint32_t 1746 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) uint32_t 1752 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) uint32_t 1760 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) uint32_t 1768 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) uint32_t 1774 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) uint32_t 1780 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) uint32_t 1788 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) uint32_t 1794 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) uint32_t 1800 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) uint32_t 1808 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) uint32_t 1814 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) uint32_t 1822 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) uint32_t 1828 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) uint32_t 1836 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) uint32_t 1842 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) uint32_t 1848 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) uint32_t 1854 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) uint32_t 1859 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } uint32_t 1861 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } uint32_t 1863 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } uint32_t 1871 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } uint32_t 1873 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } uint32_t 1884 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) uint32_t 1890 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) uint32_t 1896 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) uint32_t 1902 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) uint32_t 1910 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) uint32_t 1916 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) uint32_t 1922 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) uint32_t 1928 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) uint32_t 1934 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) uint32_t 1949 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } uint32_t 1951 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } uint32_t 1954 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) uint32_t 1960 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) uint32_t 1968 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) uint32_t 1974 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) uint32_t 1979 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } uint32_t 1981 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } uint32_t 1983 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } uint32_t 1986 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) uint32_t 1993 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) uint32_t 1999 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) uint32_t 2006 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) uint32_t 2012 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) uint32_t 2022 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) uint32_t 2028 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) uint32_t 2036 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) uint32_t 2043 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) uint32_t 2049 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) uint32_t 2057 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) uint32_t 2063 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) uint32_t 2068 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } uint32_t 2070 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } uint32_t 2073 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) uint32_t 2079 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) uint32_t 2085 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) uint32_t 2091 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) uint32_t 2097 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) uint32_t 2103 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) uint32_t 2109 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) uint32_t 2115 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) uint32_t 2121 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) uint32_t 2127 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) uint32_t 2133 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) uint32_t 2139 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) uint32_t 2145 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) uint32_t 2151 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) uint32_t 2157 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) uint32_t 2163 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) uint32_t 2168 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } uint32_t 2170 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } uint32_t 2173 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) uint32_t 2179 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) uint32_t 2185 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) uint32_t 2191 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) uint32_t 2197 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) uint32_t 2203 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) uint32_t 2209 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) uint32_t 2215 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) uint32_t 2221 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) uint32_t 2227 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) uint32_t 2233 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) uint32_t 2239 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) uint32_t 2245 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) uint32_t 2251 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) uint32_t 2257 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) uint32_t 2263 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) uint32_t 2276 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) uint32_t 2283 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) uint32_t 2289 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) uint32_t 2297 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) uint32_t 2303 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) uint32_t 2311 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 2317 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 2323 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 2330 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) uint32_t 2338 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) uint32_t 2344 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) uint32_t 2350 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) uint32_t 2358 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) uint32_t 2364 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) uint32_t 2371 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) uint32_t 2376 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } uint32_t 2378 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } uint32_t 2381 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) uint32_t 2388 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) uint32_t 2394 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) uint32_t 2401 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) uint32_t 2406 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } uint32_t 2408 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } uint32_t 2411 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) uint32_t 2417 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) uint32_t 2423 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) uint32_t 2429 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) uint32_t 2437 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) uint32_t 2443 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 2449 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 2459 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) uint32_t 2465 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) uint32_t 2471 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) uint32_t 2479 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) uint32_t 2485 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) uint32_t 2495 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) uint32_t 2503 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) uint32_t 2509 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) uint32_t 2517 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 2523 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 2532 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 2541 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) uint32_t 2549 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) uint32_t 2555 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) uint32_t 2561 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) uint32_t 2567 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) uint32_t 2575 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) uint32_t 2581 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 2587 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 2597 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) uint32_t 2603 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) uint32_t 2609 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) uint32_t 2617 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) uint32_t 2623 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) uint32_t 2637 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) uint32_t 2644 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) uint32_t 2649 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } uint32_t 2651 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } uint32_t 2654 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) uint32_t 2662 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } uint32_t 2664 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } uint32_t 2667 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) uint32_t 2675 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) uint32_t 2685 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) uint32_t 2691 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) uint32_t 2697 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) uint32_t 2707 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) uint32_t 2713 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) uint32_t 2719 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) uint32_t 2803 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) uint32_t 2809 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) uint32_t 2816 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } uint32_t 2818 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } uint32_t 2821 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) uint32_t 2827 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) uint32_t 2833 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) uint32_t 2839 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) uint32_t 2844 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } uint32_t 2846 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } uint32_t 2871 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } uint32_t 2873 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } uint32_t 2875 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } uint32_t 2877 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } uint32_t 2879 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } uint32_t 2892 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) uint32_t 2898 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) uint32_t 2946 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) uint32_t 2954 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) uint32_t 2960 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) uint32_t 3007 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) uint32_t 3013 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) uint32_t 3019 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) uint32_t 3025 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) uint32_t 3034 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) uint32_t 3046 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) uint32_t 3052 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) uint32_t 3058 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) uint32_t 3064 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) uint32_t 3070 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) uint32_t 3076 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) uint32_t 3082 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) uint32_t 3092 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) uint32_t 3098 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) uint32_t 3100 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; uint32_t 3104 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) uint32_t 3106 drivers/gpu/drm/msm/adreno/a3xx.xml.h return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; uint32_t 3114 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) uint32_t 3120 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) uint32_t 3126 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) uint32_t 3132 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) uint32_t 3138 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) uint32_t 3144 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) uint32_t 3150 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) uint32_t 3157 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) uint32_t 3165 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) uint32_t 3171 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) uint32_t 3177 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) uint32_t 3185 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) uint32_t 3191 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) uint32_t 3197 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) uint32_t 3205 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) uint32_t 3211 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) uint32_t 3217 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) uint32_t 66 drivers/gpu/drm/msm/adreno/a3xx_gpu.c uint32_t *ptr, len; uint32_t 249 drivers/gpu/drm/msm/adreno/a3xx_gpu.c ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data); uint32_t 261 drivers/gpu/drm/msm/adreno/a3xx_gpu.c ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PFP]->data); uint32_t 349 drivers/gpu/drm/msm/adreno/a3xx_gpu.c uint32_t status; uint32_t 22 drivers/gpu/drm/msm/adreno/a3xx_gpu.h uint32_t ocmem_base; uint32_t 847 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) uint32_t 904 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) uint32_t 910 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) uint32_t 926 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) uint32_t 932 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) uint32_t 946 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) uint32_t 961 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) uint32_t 968 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } uint32_t 970 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } uint32_t 977 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) uint32_t 983 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) uint32_t 988 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } uint32_t 991 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) uint32_t 997 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) uint32_t 1003 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) uint32_t 1009 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 1016 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) uint32_t 1021 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } uint32_t 1023 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } uint32_t 1026 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) uint32_t 1031 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } uint32_t 1034 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) uint32_t 1040 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) uint32_t 1046 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) uint32_t 1052 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) uint32_t 1058 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) uint32_t 1064 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) uint32_t 1072 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) uint32_t 1078 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) uint32_t 1084 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) uint32_t 1092 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) uint32_t 1100 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) uint32_t 1106 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) uint32_t 1112 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) uint32_t 1120 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) uint32_t 1128 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) uint32_t 1134 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) uint32_t 1140 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) uint32_t 1148 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) uint32_t 1156 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) uint32_t 1162 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) uint32_t 1168 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) uint32_t 1176 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) uint32_t 1184 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) uint32_t 1191 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) uint32_t 1199 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) uint32_t 1206 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) uint32_t 1215 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) uint32_t 1223 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) uint32_t 1229 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) uint32_t 1235 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) uint32_t 1241 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) uint32_t 1247 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) uint32_t 1253 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) uint32_t 1259 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) uint32_t 1265 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) uint32_t 1273 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) uint32_t 1279 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) uint32_t 1285 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) uint32_t 1291 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) uint32_t 1299 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) uint32_t 1307 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) uint32_t 1315 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) uint32_t 1321 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) uint32_t 1327 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) uint32_t 1333 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) uint32_t 1339 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) uint32_t 1345 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) uint32_t 1353 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) uint32_t 1365 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) uint32_t 1379 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) uint32_t 1385 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) uint32_t 1393 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) uint32_t 1401 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) uint32_t 1412 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) uint32_t 1418 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) uint32_t 1424 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) uint32_t 1430 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) uint32_t 1436 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) uint32_t 1442 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) uint32_t 1448 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) uint32_t 1454 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) uint32_t 1466 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) uint32_t 1474 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) uint32_t 1482 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) uint32_t 1488 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) uint32_t 1494 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) uint32_t 1502 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) uint32_t 1508 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) uint32_t 1514 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) uint32_t 1523 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) uint32_t 1529 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) uint32_t 1534 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } uint32_t 1536 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } uint32_t 1538 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } uint32_t 1544 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } uint32_t 1546 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } uint32_t 1548 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } uint32_t 1550 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } uint32_t 1552 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } uint32_t 1554 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } uint32_t 1556 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } uint32_t 1558 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } uint32_t 2012 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } uint32_t 2014 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } uint32_t 2016 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } uint32_t 2018 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } uint32_t 2020 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } uint32_t 2022 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } uint32_t 2024 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } uint32_t 2026 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } uint32_t 2028 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } uint32_t 2030 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } uint32_t 2032 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } uint32_t 2034 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } uint32_t 2036 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } uint32_t 2038 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } uint32_t 2040 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } uint32_t 2042 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } uint32_t 2056 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } uint32_t 2058 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } uint32_t 2198 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } uint32_t 2200 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } uint32_t 2203 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) uint32_t 2209 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) uint32_t 2250 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } uint32_t 2252 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } uint32_t 2293 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) uint32_t 2301 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 2307 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 2313 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) uint32_t 2319 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 2329 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) uint32_t 2335 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) uint32_t 2343 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) uint32_t 2349 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) uint32_t 2355 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) uint32_t 2360 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } uint32_t 2362 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } uint32_t 2365 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) uint32_t 2371 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) uint32_t 2377 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) uint32_t 2383 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) uint32_t 2388 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } uint32_t 2390 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } uint32_t 2393 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) uint32_t 2399 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) uint32_t 2405 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) uint32_t 2411 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) uint32_t 2419 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 2425 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 2441 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) uint32_t 2449 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 2455 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 2461 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) uint32_t 2467 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 2477 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) uint32_t 2488 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 2494 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 2510 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) uint32_t 2517 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) uint32_t 2523 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) uint32_t 2528 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } uint32_t 2530 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } uint32_t 2533 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) uint32_t 2540 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) uint32_t 2563 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 2569 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 2585 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) uint32_t 2591 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) uint32_t 2596 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } uint32_t 2598 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } uint32_t 2601 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) uint32_t 2607 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) uint32_t 2613 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) uint32_t 2619 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) uint32_t 2624 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } uint32_t 2626 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } uint32_t 2629 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) uint32_t 2635 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) uint32_t 2641 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) uint32_t 2647 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) uint32_t 2655 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 2661 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 2677 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) uint32_t 2683 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) uint32_t 2689 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) uint32_t 2694 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } uint32_t 2696 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } uint32_t 2699 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) uint32_t 2705 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) uint32_t 2711 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) uint32_t 2717 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) uint32_t 2722 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } uint32_t 2724 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } uint32_t 2727 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) uint32_t 2733 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) uint32_t 2739 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) uint32_t 2745 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) uint32_t 2753 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 2759 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 2789 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) uint32_t 2796 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) uint32_t 2805 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) uint32_t 2811 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) uint32_t 2817 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) uint32_t 2822 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } uint32_t 2824 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } uint32_t 2826 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } uint32_t 2828 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } uint32_t 2835 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) uint32_t 2841 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) uint32_t 2852 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } uint32_t 2854 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } uint32_t 2857 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) uint32_t 2863 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) uint32_t 2869 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) uint32_t 2875 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) uint32_t 2880 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } uint32_t 2882 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } uint32_t 2884 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } uint32_t 2886 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } uint32_t 2919 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) uint32_t 2925 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) uint32_t 2931 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) uint32_t 2937 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) uint32_t 2945 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) uint32_t 2951 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) uint32_t 2957 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) uint32_t 2967 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) uint32_t 2973 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) uint32_t 2979 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) uint32_t 2988 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } uint32_t 2990 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } uint32_t 2993 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) uint32_t 2999 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) uint32_t 3006 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } uint32_t 3008 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } uint32_t 3011 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) uint32_t 3016 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } uint32_t 3019 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) uint32_t 3024 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } uint32_t 3026 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } uint32_t 3029 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) uint32_t 3036 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) uint32_t 3042 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) uint32_t 3049 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) uint32_t 3055 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) uint32_t 3087 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) uint32_t 3093 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) uint32_t 3099 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) uint32_t 3105 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) uint32_t 3160 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) uint32_t 3166 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) uint32_t 3174 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) uint32_t 3182 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) uint32_t 3190 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) uint32_t 3198 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) uint32_t 3206 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) uint32_t 3214 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) uint32_t 3222 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) uint32_t 3224 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; uint32_t 3228 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) uint32_t 3230 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; uint32_t 3236 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) uint32_t 3248 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) uint32_t 3256 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) uint32_t 3264 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) uint32_t 3272 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) uint32_t 3283 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) uint32_t 3294 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) uint32_t 3300 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) uint32_t 3307 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) uint32_t 3316 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) uint32_t 3322 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) uint32_t 3331 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) uint32_t 3337 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) uint32_t 3346 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) uint32_t 3352 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) uint32_t 3361 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) uint32_t 3367 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) uint32_t 3376 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) uint32_t 3382 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) uint32_t 3391 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) uint32_t 3397 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) uint32_t 3459 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) uint32_t 3469 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) uint32_t 3481 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) uint32_t 3489 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) uint32_t 3495 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) uint32_t 3503 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) uint32_t 3509 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) uint32_t 3515 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) uint32_t 3521 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) uint32_t 3529 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) uint32_t 3539 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) uint32_t 3545 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3553 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 3559 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) uint32_t 3567 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) uint32_t 3573 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3581 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 3587 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) uint32_t 3595 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) uint32_t 3601 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3609 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 3615 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) uint32_t 3623 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) uint32_t 3629 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3637 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 3643 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) uint32_t 3651 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) uint32_t 3657 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3665 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 3671 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) uint32_t 3679 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val) uint32_t 3685 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3693 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) uint32_t 3699 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val) uint32_t 3707 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val) uint32_t 3713 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val) uint32_t 3719 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val) uint32_t 3725 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val) uint32_t 3733 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val) uint32_t 3743 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val) uint32_t 3753 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val) uint32_t 3763 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val) uint32_t 3769 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val) uint32_t 3816 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) uint32_t 3822 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) uint32_t 3830 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) uint32_t 3841 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) uint32_t 3847 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) uint32_t 3858 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) uint32_t 3864 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) uint32_t 3870 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) uint32_t 3879 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) uint32_t 3885 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) uint32_t 3993 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) uint32_t 3999 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) uint32_t 4005 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) uint32_t 4011 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) uint32_t 4017 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) uint32_t 4023 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) uint32_t 4029 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) uint32_t 4037 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) uint32_t 4046 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) uint32_t 4048 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; uint32_t 4052 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) uint32_t 4054 drivers/gpu/drm/msm/adreno/a4xx.xml.h return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; uint32_t 4062 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) uint32_t 4068 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) uint32_t 4074 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) uint32_t 4080 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) uint32_t 4086 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) uint32_t 4092 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) uint32_t 4098 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) uint32_t 4106 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) uint32_t 4112 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) uint32_t 4120 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) uint32_t 4126 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) uint32_t 4132 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) uint32_t 4140 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) uint32_t 4146 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) uint32_t 4154 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) uint32_t 4160 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) uint32_t 4174 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val) uint32_t 4182 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val) uint32_t 4190 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) uint32_t 4198 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val) uint32_t 4206 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val) uint32_t 4212 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val) uint32_t 4218 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val) uint32_t 4226 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val) uint32_t 4232 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val) uint32_t 140 drivers/gpu/drm/msm/adreno/a4xx_gpu.c uint32_t *ptr, len; uint32_t 269 drivers/gpu/drm/msm/adreno/a4xx_gpu.c ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data); uint32_t 277 drivers/gpu/drm/msm/adreno/a4xx_gpu.c ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PFP]->data); uint32_t 348 drivers/gpu/drm/msm/adreno/a4xx_gpu.c uint32_t status; uint32_t 354 drivers/gpu/drm/msm/adreno/a4xx_gpu.c uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); uint32_t 19 drivers/gpu/drm/msm/adreno/a4xx_gpu.h uint32_t ocmem_base; uint32_t 1036 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } uint32_t 1038 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } uint32_t 1040 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } uint32_t 1042 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } uint32_t 1045 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) uint32_t 1051 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) uint32_t 1958 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) uint32_t 1964 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) uint32_t 1977 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } uint32_t 1979 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } uint32_t 1982 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) uint32_t 1988 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) uint32_t 1994 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) uint32_t 2000 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) uint32_t 2005 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } uint32_t 2007 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; } uint32_t 2009 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; } uint32_t 2011 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } uint32_t 2013 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; } uint32_t 2023 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val) uint32_t 2029 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) uint32_t 2672 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) uint32_t 2678 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) uint32_t 2686 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) uint32_t 2694 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) uint32_t 2702 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) uint32_t 2710 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) uint32_t 2718 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) uint32_t 2726 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) uint32_t 2737 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) uint32_t 2747 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) uint32_t 2749 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK; uint32_t 2753 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) uint32_t 2755 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK; uint32_t 2761 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) uint32_t 2775 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) uint32_t 2783 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) uint32_t 2791 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) uint32_t 2799 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) uint32_t 2815 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 2823 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 2835 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) uint32_t 2841 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) uint32_t 2850 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) uint32_t 2856 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) uint32_t 2865 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) uint32_t 2871 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) uint32_t 2880 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) uint32_t 2886 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) uint32_t 2895 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) uint32_t 2901 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) uint32_t 2910 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) uint32_t 2916 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) uint32_t 2933 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) uint32_t 2945 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) uint32_t 2951 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) uint32_t 2965 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) uint32_t 2971 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) uint32_t 2979 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 2987 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 3009 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) uint32_t 3018 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) uint32_t 3024 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) uint32_t 3030 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) uint32_t 3036 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) uint32_t 3042 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) uint32_t 3048 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) uint32_t 3054 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) uint32_t 3060 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) uint32_t 3065 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } uint32_t 3067 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } uint32_t 3073 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) uint32_t 3079 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) uint32_t 3084 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; } uint32_t 3087 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) uint32_t 3093 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) uint32_t 3099 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) uint32_t 3105 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) uint32_t 3111 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) uint32_t 3117 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) uint32_t 3122 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; } uint32_t 3125 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) uint32_t 3131 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) uint32_t 3137 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) uint32_t 3143 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 3149 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; } uint32_t 3152 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) uint32_t 3157 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } uint32_t 3160 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) uint32_t 3165 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } uint32_t 3167 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; } uint32_t 3172 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) uint32_t 3178 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) uint32_t 3184 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) uint32_t 3192 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) uint32_t 3200 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) uint32_t 3206 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) uint32_t 3212 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) uint32_t 3220 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) uint32_t 3228 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) uint32_t 3234 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) uint32_t 3240 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) uint32_t 3248 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) uint32_t 3256 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) uint32_t 3262 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) uint32_t 3268 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) uint32_t 3276 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) uint32_t 3284 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) uint32_t 3291 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) uint32_t 3299 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) uint32_t 3307 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) uint32_t 3321 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) uint32_t 3330 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) uint32_t 3342 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) uint32_t 3350 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) uint32_t 3361 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) uint32_t 3367 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) uint32_t 3373 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) uint32_t 3379 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) uint32_t 3385 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) uint32_t 3391 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) uint32_t 3397 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) uint32_t 3403 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) uint32_t 3418 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) uint32_t 3426 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) uint32_t 3434 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) uint32_t 3440 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) uint32_t 3446 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) uint32_t 3454 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) uint32_t 3460 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) uint32_t 3466 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) uint32_t 3475 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) uint32_t 3481 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) uint32_t 3492 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) uint32_t 3501 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) uint32_t 3507 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) uint32_t 3516 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) uint32_t 3522 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) uint32_t 3537 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) uint32_t 3545 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) uint32_t 3563 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) uint32_t 3574 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; } uint32_t 3576 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; } uint32_t 3578 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; } uint32_t 3580 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; } uint32_t 3583 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) uint32_t 3588 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; } uint32_t 3591 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) uint32_t 3603 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) uint32_t 3611 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) uint32_t 3623 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) uint32_t 3629 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } uint32_t 3631 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } uint32_t 3633 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } uint32_t 3635 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } uint32_t 3641 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } uint32_t 3643 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } uint32_t 3652 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) uint32_t 3658 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val) uint32_t 3681 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val) uint32_t 3687 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val) uint32_t 3694 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val) uint32_t 3700 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val) uint32_t 3706 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } uint32_t 3708 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } uint32_t 3710 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; } uint32_t 3712 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; } uint32_t 3714 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; } uint32_t 3716 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; } uint32_t 3718 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; } uint32_t 3720 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; } uint32_t 3725 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) uint32_t 3739 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) uint32_t 3745 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) uint32_t 3760 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) uint32_t 3766 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) uint32_t 3772 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) uint32_t 3780 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) uint32_t 3786 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) uint32_t 3798 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) uint32_t 3806 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) uint32_t 3812 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) uint32_t 3818 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) uint32_t 3826 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) uint32_t 3834 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) uint32_t 3840 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) uint32_t 3846 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) uint32_t 3859 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } uint32_t 3861 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } uint32_t 3863 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; } uint32_t 3865 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; } uint32_t 3867 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } uint32_t 3869 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } uint32_t 3871 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } uint32_t 3874 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) uint32_t 3881 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) uint32_t 3887 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) uint32_t 3894 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } uint32_t 3896 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } uint32_t 3898 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } uint32_t 3901 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) uint32_t 3907 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) uint32_t 3920 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3926 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 3935 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3941 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 3950 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3956 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 3965 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3971 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 3980 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 3986 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 3995 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 4001 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 4013 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4019 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4025 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4033 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4041 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) uint32_t 4046 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } uint32_t 4048 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } uint32_t 4051 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) uint32_t 4057 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) uint32_t 4063 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) uint32_t 4069 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) uint32_t 4074 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } uint32_t 4076 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } uint32_t 4079 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) uint32_t 4085 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) uint32_t 4091 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) uint32_t 4097 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) uint32_t 4111 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4117 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4123 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4131 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4150 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) uint32_t 4156 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) uint32_t 4162 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) uint32_t 4167 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } uint32_t 4169 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } uint32_t 4172 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) uint32_t 4178 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } uint32_t 4180 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } uint32_t 4183 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) uint32_t 4196 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4202 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4208 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4216 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4230 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4236 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4242 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4250 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4264 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4270 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4276 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4284 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4298 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4304 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4310 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4318 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4332 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 4340 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 4415 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) uint32_t 4421 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val) uint32_t 4429 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) uint32_t 4437 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) uint32_t 4443 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) uint32_t 4449 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) uint32_t 4457 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) uint32_t 4465 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) uint32_t 4471 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) uint32_t 4482 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 4488 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 4497 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 4503 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 4512 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 4518 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 4527 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 4533 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 4542 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 4548 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 4557 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) uint32_t 4563 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) uint32_t 4572 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) uint32_t 4581 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) uint32_t 4590 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) uint32_t 4599 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) uint32_t 4608 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) uint32_t 4617 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) uint32_t 4631 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) uint32_t 4637 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) uint32_t 4643 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) uint32_t 4649 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) uint32_t 4657 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) uint32_t 4665 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) uint32_t 4673 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) uint32_t 4681 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) uint32_t 4689 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) uint32_t 4697 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) uint32_t 4705 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) uint32_t 4711 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) uint32_t 4717 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) uint32_t 4723 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) uint32_t 4779 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) uint32_t 4785 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) uint32_t 4791 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 4804 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) uint32_t 4810 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) uint32_t 4818 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) uint32_t 4824 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) uint32_t 4830 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 4843 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) uint32_t 4849 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) uint32_t 4867 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) uint32_t 4873 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) uint32_t 4879 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 4888 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) uint32_t 4894 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) uint32_t 4900 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 4916 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) uint32_t 4922 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) uint32_t 4928 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) uint32_t 4934 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) uint32_t 4940 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) uint32_t 4946 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) uint32_t 4952 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) uint32_t 4960 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) uint32_t 4969 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) uint32_t 4971 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK; uint32_t 4975 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) uint32_t 4977 drivers/gpu/drm/msm/adreno/a5xx.xml.h return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK; uint32_t 4983 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) uint32_t 4993 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) uint32_t 5000 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) uint32_t 5006 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) uint32_t 5012 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) uint32_t 5018 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) uint32_t 5024 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val) uint32_t 5030 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) uint32_t 5036 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) uint32_t 5042 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) uint32_t 5050 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) uint32_t 5056 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) uint32_t 5064 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val) uint32_t 5070 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) uint32_t 5076 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) uint32_t 5084 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) uint32_t 5093 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) uint32_t 5101 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val) uint32_t 5107 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) uint32_t 5127 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val) uint32_t 5135 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val) uint32_t 5143 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) uint32_t 5151 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val) uint32_t 5159 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val) uint32_t 5165 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val) uint32_t 5173 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val) uint32_t 5179 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val) uint32_t 5187 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val) uint32_t 5195 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val) uint32_t 67 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c uint32_t val[4]; uint32_t 25 drivers/gpu/drm/msm/adreno/a5xx_gpu.c uint32_t wptr; uint32_t 52 drivers/gpu/drm/msm/adreno/a5xx_gpu.c uint32_t *ptr, dwords; uint32_t 26 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t gpmu_dwords; uint32_t 28 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t lm_leakage; uint32_t 99 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t magic; uint32_t 100 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t info; uint32_t 101 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t data; uint32_t 102 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t cntl; uint32_t 103 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t rptr; uint32_t 104 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t wptr; uint32_t 130 drivers/gpu/drm/msm/adreno/a5xx_gpu.h static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, uint32_t 131 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t reg, uint32_t mask, uint32_t value) uint32_t 39 drivers/gpu/drm/msm/adreno/a5xx_power.c uint32_t reg; uint32_t 40 drivers/gpu/drm/msm/adreno/a5xx_power.c uint32_t value; uint32_t 103 drivers/gpu/drm/msm/adreno/a5xx_power.c static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) uint32_t 167 drivers/gpu/drm/msm/adreno/a5xx_power.c gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, 4 * sizeof(uint32_t)); uint32_t 325 drivers/gpu/drm/msm/adreno/a5xx_power.c uint32_t dwords = 0, offset = 0, bosize; uint32_t 368 drivers/gpu/drm/msm/adreno/a5xx_power.c uint32_t _size = cmds_size > TYPE4_MAX_PAYLOAD ? uint32_t 43 drivers/gpu/drm/msm/adreno/a5xx_preempt.c uint32_t wptr; uint32_t 161 drivers/gpu/drm/msm/adreno/a5xx_preempt.c uint32_t status; uint32_t 1064 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } uint32_t 1066 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } uint32_t 1068 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } uint32_t 1070 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } uint32_t 1073 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) uint32_t 1079 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) uint32_t 2004 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) uint32_t 2010 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) uint32_t 2018 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) uint32_t 2024 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) uint32_t 2030 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) uint32_t 2038 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) uint32_t 2062 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) uint32_t 2068 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) uint32_t 2074 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) uint32_t 2080 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) uint32_t 2086 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) uint32_t 2092 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) uint32_t 2098 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) uint32_t 2104 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) uint32_t 2112 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) uint32_t 2118 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) uint32_t 2124 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) uint32_t 2130 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) uint32_t 2136 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) uint32_t 2142 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) uint32_t 2148 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) uint32_t 2154 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) uint32_t 2336 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) uint32_t 2463 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) uint32_t 2473 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) uint32_t 2526 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) uint32_t 2532 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) uint32_t 2541 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) uint32_t 2547 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) uint32_t 2556 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) uint32_t 2562 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) uint32_t 2570 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) uint32_t 2576 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) uint32_t 2586 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) uint32_t 2592 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) uint32_t 2600 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) uint32_t 2606 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) uint32_t 2618 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) uint32_t 2624 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) uint32_t 2629 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } uint32_t 2631 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } uint32_t 2634 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) uint32_t 2640 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) uint32_t 2646 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) uint32_t 2652 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) uint32_t 2666 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val) uint32_t 2680 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val) uint32_t 2685 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } uint32_t 2687 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } uint32_t 2708 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) uint32_t 2714 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) uint32_t 2722 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val) uint32_t 2730 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val) uint32_t 2738 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val) uint32_t 2746 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val) uint32_t 2754 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val) uint32_t 2762 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val) uint32_t 2773 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) uint32_t 2783 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) uint32_t 2785 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; uint32_t 2789 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) uint32_t 2791 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; uint32_t 2797 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) uint32_t 2808 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) uint32_t 2816 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) uint32_t 2824 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) uint32_t 2832 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) uint32_t 2846 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 2854 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 2872 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) uint32_t 2878 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) uint32_t 2887 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) uint32_t 2893 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) uint32_t 2902 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) uint32_t 2908 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) uint32_t 2917 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) uint32_t 2923 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) uint32_t 2932 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) uint32_t 2938 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) uint32_t 2947 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) uint32_t 2953 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) uint32_t 2970 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) uint32_t 2982 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) uint32_t 2988 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) uint32_t 3004 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) uint32_t 3013 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val) uint32_t 3021 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val) uint32_t 3029 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val) uint32_t 3037 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val) uint32_t 3046 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) uint32_t 3052 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) uint32_t 3061 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) uint32_t 3067 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) uint32_t 3076 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val) uint32_t 3082 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val) uint32_t 3091 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val) uint32_t 3097 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val) uint32_t 3107 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) uint32_t 3113 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) uint32_t 3126 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) uint32_t 3134 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 3142 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 3174 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) uint32_t 3182 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) uint32_t 3188 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) uint32_t 3194 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) uint32_t 3200 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) uint32_t 3206 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) uint32_t 3212 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) uint32_t 3218 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) uint32_t 3224 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) uint32_t 3232 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) uint32_t 3238 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) uint32_t 3244 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) uint32_t 3250 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) uint32_t 3256 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) uint32_t 3262 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) uint32_t 3268 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) uint32_t 3274 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) uint32_t 3307 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } uint32_t 3309 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } uint32_t 3315 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) uint32_t 3321 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) uint32_t 3326 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } uint32_t 3329 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) uint32_t 3335 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) uint32_t 3341 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) uint32_t 3347 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) uint32_t 3353 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) uint32_t 3359 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) uint32_t 3364 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } uint32_t 3367 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) uint32_t 3373 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) uint32_t 3379 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 3384 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } uint32_t 3387 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) uint32_t 3392 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } uint32_t 3395 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) uint32_t 3400 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; } uint32_t 3402 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; } uint32_t 3404 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } uint32_t 3409 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) uint32_t 3417 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) uint32_t 3425 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) uint32_t 3433 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) uint32_t 3441 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) uint32_t 3448 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) uint32_t 3456 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) uint32_t 3464 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) uint32_t 3477 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) uint32_t 3486 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) uint32_t 3494 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) uint32_t 3502 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) uint32_t 3523 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) uint32_t 3529 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) uint32_t 3535 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) uint32_t 3541 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) uint32_t 3547 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) uint32_t 3553 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) uint32_t 3559 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) uint32_t 3565 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) uint32_t 3576 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) uint32_t 3584 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) uint32_t 3598 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) uint32_t 3604 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) uint32_t 3612 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) uint32_t 3618 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) uint32_t 3626 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) uint32_t 3632 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) uint32_t 3641 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) uint32_t 3647 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) uint32_t 3664 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) uint32_t 3670 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) uint32_t 3679 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) uint32_t 3685 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) uint32_t 3693 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 3703 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) uint32_t 3710 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) uint32_t 3716 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) uint32_t 3722 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 3734 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) uint32_t 3742 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) uint32_t 3766 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) uint32_t 3779 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } uint32_t 3781 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; } uint32_t 3783 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; } uint32_t 3785 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } uint32_t 3788 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) uint32_t 3794 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) uint32_t 3806 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) uint32_t 3817 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) uint32_t 3823 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) uint32_t 3829 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 3842 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val) uint32_t 3873 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } uint32_t 3875 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } uint32_t 3877 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } uint32_t 3879 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } uint32_t 3885 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } uint32_t 3887 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } uint32_t 3895 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) uint32_t 3901 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) uint32_t 3908 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) uint32_t 3914 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) uint32_t 3920 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } uint32_t 3922 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; } uint32_t 3924 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; } uint32_t 3926 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } uint32_t 3928 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } uint32_t 3930 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } uint32_t 3932 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; } uint32_t 3934 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; } uint32_t 3943 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val) uint32_t 3949 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) uint32_t 3955 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val) uint32_t 3963 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) uint32_t 4006 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val) uint32_t 4025 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val) uint32_t 4033 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) uint32_t 4039 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) uint32_t 4045 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) uint32_t 4053 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) uint32_t 4061 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) uint32_t 4067 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) uint32_t 4073 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) uint32_t 4095 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } uint32_t 4097 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; } uint32_t 4099 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; } uint32_t 4101 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } uint32_t 4103 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } uint32_t 4105 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } uint32_t 4107 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } uint32_t 4110 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) uint32_t 4117 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val) uint32_t 4123 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) uint32_t 4130 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } uint32_t 4132 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } uint32_t 4134 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } uint32_t 4137 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) uint32_t 4143 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) uint32_t 4153 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) uint32_t 4158 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } uint32_t 4160 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } uint32_t 4163 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) uint32_t 4169 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) uint32_t 4175 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) uint32_t 4181 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) uint32_t 4186 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } uint32_t 4188 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } uint32_t 4191 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) uint32_t 4197 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) uint32_t 4203 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) uint32_t 4209 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) uint32_t 4217 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4223 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4229 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4235 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4255 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) uint32_t 4261 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) uint32_t 4271 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4277 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4283 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4289 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4309 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) uint32_t 4315 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) uint32_t 4325 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4331 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4337 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4343 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4361 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) uint32_t 4367 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) uint32_t 4377 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4383 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4389 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4395 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4415 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) uint32_t 4421 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) uint32_t 4463 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4469 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4475 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4481 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4513 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) uint32_t 4519 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) uint32_t 4525 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) uint32_t 4531 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) uint32_t 4537 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) uint32_t 4543 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) uint32_t 4549 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) uint32_t 4555 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) uint32_t 4563 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) uint32_t 4571 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) uint32_t 4576 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } uint32_t 4578 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } uint32_t 4581 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val) uint32_t 4610 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } uint32_t 4612 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } uint32_t 4615 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) uint32_t 4624 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) uint32_t 4630 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) uint32_t 4636 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) uint32_t 4642 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) uint32_t 4662 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) uint32_t 4668 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) uint32_t 4694 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 4702 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) uint32_t 4719 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) uint32_t 4725 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) uint32_t 4731 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) uint32_t 4741 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) uint32_t 4747 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) uint32_t 4759 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) uint32_t 4775 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) uint32_t 4783 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) uint32_t 4791 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) uint32_t 4799 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) uint32_t 4811 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) uint32_t 4817 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) uint32_t 4823 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) uint32_t 4831 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) uint32_t 4839 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) uint32_t 4845 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) uint32_t 4855 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) uint32_t 4861 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) uint32_t 4867 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) uint32_t 4873 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) uint32_t 4881 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) uint32_t 4889 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) uint32_t 4897 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) uint32_t 4905 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) uint32_t 4913 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) uint32_t 4921 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) uint32_t 4929 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) uint32_t 4935 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) uint32_t 4941 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) uint32_t 4947 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) uint32_t 4963 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) uint32_t 4980 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) uint32_t 4986 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) uint32_t 4992 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) uint32_t 4998 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) uint32_t 5004 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) uint32_t 5010 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) uint32_t 5016 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) uint32_t 5024 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) uint32_t 5033 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) uint32_t 5035 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; uint32_t 5039 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) uint32_t 5041 drivers/gpu/drm/msm/adreno/a6xx.xml.h return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; uint32_t 5047 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) uint32_t 5057 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) uint32_t 5064 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) uint32_t 5070 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) uint32_t 5076 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) uint32_t 5082 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) uint32_t 5088 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) uint32_t 5094 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) uint32_t 5100 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val) uint32_t 5106 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) uint32_t 5114 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) uint32_t 5120 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) uint32_t 5128 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val) uint32_t 5134 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) uint32_t 5140 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) uint32_t 5148 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) uint32_t 5157 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) uint32_t 5165 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) uint32_t 5171 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) uint32_t 5181 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) uint32_t 5189 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) uint32_t 5265 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) uint32_t 5271 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) uint32_t 5285 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) uint32_t 5291 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) uint32_t 5297 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) uint32_t 5305 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) uint32_t 5329 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) uint32_t 5335 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) uint32_t 5341 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) uint32_t 5347 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) uint32_t 5353 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) uint32_t 5359 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) uint32_t 5365 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) uint32_t 5371 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) uint32_t 5379 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) uint32_t 5385 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) uint32_t 5391 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) uint32_t 5397 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) uint32_t 5403 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) uint32_t 5409 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) uint32_t 5415 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) uint32_t 5421 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) uint32_t 69 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val) uint32_t 75 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val) uint32_t 152 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val) uint32_t 158 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val) uint32_t 181 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) uint32_t 54 drivers/gpu/drm/msm/adreno/a6xx_gpu.c uint32_t wptr; uint32_t 205 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) uint32_t 211 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) uint32_t 217 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) uint32_t 228 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) uint32_t 234 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) uint32_t 252 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) uint32_t 258 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) uint32_t 264 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) uint32_t 272 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) uint32_t 278 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) uint32_t 286 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) uint32_t 292 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) uint32_t 298 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) uint32_t 306 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) uint32_t 314 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) uint32_t 322 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) uint32_t 328 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) uint32_t 381 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) uint32_t 387 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) uint32_t 395 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) uint32_t 401 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) uint32_t 409 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) uint32_t 415 drivers/gpu/drm/msm/adreno/adreno_common.xml.h static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) uint32_t 159 drivers/gpu/drm/msm/adreno/adreno_gpu.c int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) uint32_t 381 drivers/gpu/drm/msm/adreno/adreno_gpu.c static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, uint32_t 489 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t wptr; uint32_t 510 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t wptr = get_wptr(ring); uint32_t 791 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t start = adreno_gpu->registers[i]; uint32_t 792 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t end = adreno_gpu->registers[i+1]; uint32_t 793 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t addr; uint32_t 796 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t val = gpu_read(gpu, addr); uint32_t 802 drivers/gpu/drm/msm/adreno/adreno_gpu.c static uint32_t ring_freewords(struct msm_ringbuffer *ring) uint32_t 805 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; uint32_t 807 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t wptr = ring->next - ring->start; uint32_t 808 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t rptr = get_rptr(adreno_gpu, ring); uint32_t 812 drivers/gpu/drm/msm/adreno/adreno_gpu.c void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) uint32_t 73 drivers/gpu/drm/msm/adreno/adreno_gpu.h uint32_t revn; uint32_t 76 drivers/gpu/drm/msm/adreno/adreno_gpu.h uint32_t gmem; uint32_t 89 drivers/gpu/drm/msm/adreno/adreno_gpu.h uint32_t gmem; /* actual gmem size */ uint32_t 90 drivers/gpu/drm/msm/adreno/adreno_gpu.h uint32_t revn; /* numeric revision name */ uint32_t 219 drivers/gpu/drm/msm/adreno/adreno_gpu.h int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); uint32_t 236 drivers/gpu/drm/msm/adreno/adreno_gpu.h void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); uint32_t 366 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline uint32_t get_wptr(struct msm_ringbuffer *ring) uint32_t 380 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) uint32_t 386 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) uint32_t 392 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) uint32_t 398 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) uint32_t 406 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) uint32_t 412 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) uint32_t 420 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) uint32_t 426 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) uint32_t 432 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) uint32_t 438 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) uint32_t 446 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) uint32_t 452 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) uint32_t 460 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) uint32_t 468 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val) uint32_t 474 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) uint32_t 480 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) uint32_t 486 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) uint32_t 492 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) uint32_t 500 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) uint32_t 508 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) uint32_t 516 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) uint32_t 524 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) uint32_t 530 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) uint32_t 536 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) uint32_t 542 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) uint32_t 551 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) uint32_t 559 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) uint32_t 567 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) uint32_t 575 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) uint32_t 583 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) uint32_t 591 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) uint32_t 597 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) uint32_t 603 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) uint32_t 609 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) uint32_t 618 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) uint32_t 626 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) uint32_t 634 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) uint32_t 640 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) uint32_t 646 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) uint32_t 652 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) uint32_t 658 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val) uint32_t 666 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) uint32_t 674 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) uint32_t 684 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) uint32_t 692 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) uint32_t 700 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) uint32_t 706 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) uint32_t 712 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) uint32_t 718 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) uint32_t 724 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val) uint32_t 732 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) uint32_t 741 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) uint32_t 749 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) uint32_t 755 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) uint32_t 761 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) uint32_t 767 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) uint32_t 773 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val) uint32_t 782 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) uint32_t 790 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) uint32_t 798 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) uint32_t 807 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) uint32_t 815 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) uint32_t 823 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) uint32_t 831 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) uint32_t 839 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) uint32_t 844 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } uint32_t 846 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } uint32_t 849 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) uint32_t 859 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val) uint32_t 865 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) uint32_t 870 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } uint32_t 873 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) uint32_t 878 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } uint32_t 881 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) uint32_t 891 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) uint32_t 897 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) uint32_t 905 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) uint32_t 911 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) uint32_t 919 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) uint32_t 927 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) uint32_t 935 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) uint32_t 941 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) uint32_t 949 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) uint32_t 957 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) uint32_t 965 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) uint32_t 973 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) uint32_t 981 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val) uint32_t 989 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val) uint32_t 997 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) uint32_t 1003 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) uint32_t 1013 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) uint32_t 1021 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val) uint32_t 1029 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val) uint32_t 1035 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val) uint32_t 1045 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val) uint32_t 1053 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val) uint32_t 1067 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) uint32_t 1077 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val) uint32_t 1085 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val) uint32_t 1093 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val) uint32_t 1101 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) uint32_t 1109 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val) uint32_t 1117 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) uint32_t 1127 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) uint32_t 1135 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) uint32_t 1143 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val) uint32_t 1151 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val) uint32_t 1159 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) uint32_t 1167 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) uint32_t 1175 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) uint32_t 1185 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) uint32_t 1193 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) uint32_t 1201 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) uint32_t 1209 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) uint32_t 1217 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) uint32_t 1225 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) uint32_t 1239 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) uint32_t 1247 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) uint32_t 1255 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) uint32_t 1263 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) uint32_t 1271 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) uint32_t 1281 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) uint32_t 1291 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) uint32_t 1299 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) uint32_t 1311 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) uint32_t 1319 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) uint32_t 1327 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) uint32_t 1336 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) uint32_t 1344 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) uint32_t 1354 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) uint32_t 1362 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) uint32_t 1368 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) uint32_t 1376 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) uint32_t 1382 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) uint32_t 1390 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) uint32_t 1396 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) uint32_t 1404 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) uint32_t 1410 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) uint32_t 1420 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val) uint32_t 1428 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) uint32_t 1436 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) uint32_t 1447 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) uint32_t 1455 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) uint32_t 1461 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) uint32_t 1467 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) uint32_t 1476 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) uint32_t 1484 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) uint32_t 1492 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) uint32_t 1498 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) uint32_t 1504 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) uint32_t 1512 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val) uint32_t 1518 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val) uint32_t 1524 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } uint32_t 1526 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } uint32_t 1529 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) uint32_t 1534 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } uint32_t 1537 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) uint32_t 1542 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } uint32_t 1545 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) uint32_t 1553 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val) uint32_t 1559 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val) uint32_t 43 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h uint32_t instance_idx); uint32_t 58 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h uint32_t irq_count); uint32_t 73 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h uint32_t irq_count); uint32_t 67 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c uint32_t blend_op; uint32_t 128 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c uint32_t stage_idx, lm_idx; uint32_t 67 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h uint32_t state; uint32_t 68 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h uint32_t transition_type; uint32_t 69 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h uint32_t transition_error; uint32_t 173 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c uint32_t bus_scaling_client; uint32_t 1426 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) uint32_t 1557 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c uint32_t i, pending_flush; uint32_t 191 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t format; uint32_t 192 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t color; uint32_t 523 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t *v_sample, uint32_t 524 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t *h_sample) uint32_t 582 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t width, uint32_t 583 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t height, uint32_t 604 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t y_sclines, uv_sclines; uint32_t 605 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t y_meta_scanlines = 0; uint32_t 606 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t uv_meta_scanlines = 0; uint32_t 634 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t rgb_scanlines, rgb_meta_scanlines; uint32_t 661 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t width, uint32_t 662 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t height, uint32_t 664 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t *pitches) uint32_t 680 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t v_subsample, h_subsample; uint32_t 681 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t chroma_samp; uint32_t 682 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t bpp = 1; uint32_t 733 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t w, uint32_t 734 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t h, uint32_t 736 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t *pitches) uint32_t 759 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t base_addr = 0; uint32_t 880 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t plane_addr[DPU_MAX_PLANES]; uint32_t 928 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t bos_total_size = 0; uint32_t 965 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t format, uint32_t 968 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c uint32_t i = 0; uint32_t 1016 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c const uint32_t format, uint32_t 18 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h const uint32_t format, uint32_t 32 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h const uint32_t format, uint32_t 7 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h static const uint32_t qcom_compressed_supported_formats[] = { uint32_t 13 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h static const uint32_t plane_formats[] = { uint32_t 44 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h static const uint32_t plane_formats_yuv[] = { uint32_t 115 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx, uint32_t 118 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c uint32_t flushbits = 0; uint32_t 170 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx, uint32_t 173 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c uint32_t flushbits = 0; uint32_t 127 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx, uint32_t 130 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx, uint32_t 848 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c uint32_t cache_irq_mask; uint32_t 894 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c uint32_t cache_irq_mask; uint32_t 137 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c uint32_t mixer_op_mode) uint32_t 42 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage, uint32_t 43 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op); uint32_t 48 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op); uint32_t 383 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t num_planes; uint32_t 384 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t width; uint32_t 385 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t height; uint32_t 386 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t total_size; uint32_t 387 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t plane_addr[DPU_MAX_PLANES]; uint32_t 388 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t plane_size[DPU_MAX_PLANES]; uint32_t 389 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t plane_pitch[DPU_MAX_PLANES]; uint32_t 394 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; uint32_t 395 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; uint32_t 396 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; uint32_t 397 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; uint32_t 398 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; uint32_t 136 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h uint32_t roi_w[DPU_MAX_PLANES]; uint32_t 137 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h uint32_t roi_h[DPU_MAX_PLANES]; uint32_t 50 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps))) uint32_t 92 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c static const uint32_t off_tbl[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = { uint32_t 199 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t enable; uint32_t 247 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t enable; uint32_t 248 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t dir_en; uint32_t 258 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t horz_decimate; uint32_t 259 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t vert_decimate; uint32_t 269 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t preload_x[DPU_MAX_PLANES]; uint32_t 270 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t preload_y[DPU_MAX_PLANES]; uint32_t 271 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t src_width[DPU_MAX_PLANES]; uint32_t 272 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t src_height[DPU_MAX_PLANES]; uint32_t 274 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t dst_width; uint32_t 275 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t dst_height; uint32_t 277 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t y_rgb_filter_cfg; uint32_t 278 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t uv_filter_cfg; uint32_t 279 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t alpha_filter_cfg; uint32_t 280 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t blend_cfg; uint32_t 282 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t lut_flag; uint32_t 283 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t dir_lut_idx; uint32_t 286 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t y_rgb_cir_lut_idx; uint32_t 287 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t uv_cir_lut_idx; uint32_t 288 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t y_rgb_sep_lut_idx; uint32_t 289 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h uint32_t uv_sep_lut_idx; uint32_t 150 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c uint32_t i, addr; uint32_t 201 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) uint32_t 163 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h uint32_t offset; uint32_t 164 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h uint32_t blk_len; uint32_t 178 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms); uint32_t 89 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t features; /* capabilities from catalog */ uint32_t 94 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t color_fill; uint32_t 442 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, uint32_t 445 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) uint32_t 447 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t i; uint32_t 573 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t color, uint32_t alpha) uint32_t 825 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t min_src_size) uint32_t 850 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t min_src_size, max_linewidth; uint32_t 970 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t src_flags; uint32_t 1408 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t format, uint64_t modifier) uint32_t 1455 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t pipe, enum drm_plane_type type, uint32_t 1459 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c const uint32_t *format_list; uint32_t 1464 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c uint32_t num_formats; uint32_t 33 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h uint32_t multirect_index; uint32_t 34 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h uint32_t multirect_mode; uint32_t 111 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h uint32_t pipe, enum drm_plane_type type, uint32_t 135 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h uint32_t color, uint32_t alpha); uint32_t 38 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c uint32_t id; uint32_t 39 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c uint32_t enc_id; uint32_t 45 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c uint32_t enc_id, uint32_t 147 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c uint32_t id, uint32_t 307 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c uint32_t enc_id, uint32_t 361 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id, uint32_t 431 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c uint32_t enc_id, uint32_t 482 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c uint32_t enc_id, uint32_t 483 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c uint32_t id, uint32_t 516 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c uint32_t enc_id, uint32_t 580 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c static void _dpu_rm_release_reservation(struct dpu_rm *rm, uint32_t enc_id) uint32_t 23 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h uint32_t lm_max_width; uint32_t 43 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h uint32_t enc_id; uint32_t 104 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h uint32_t enc_id, uint32_t 171 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, uint32_t 175 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 191 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, uint32_t 196 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, uint32_t 202 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, uint32_t 206 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 227 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 230 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 238 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 242 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 246 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 250 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 254 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 258 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 262 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 266 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 270 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 274 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 278 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 282 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 286 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id), uint32_t 291 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay), uint32_t 294 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 308 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, int val), uint32_t 311 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 321 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, int count), uint32_t 325 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, int ctl_idx), uint32_t 330 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, unsigned int flags, int private_flags), uint32_t 333 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 347 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool enable), uint32_t 350 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 361 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool enable), uint32_t 365 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool enable), uint32_t 369 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool enable), uint32_t 373 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool enable), uint32_t 378 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported, uint32_t 382 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 402 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, u32 event, enum dpu_intf intf_idx), uint32_t 405 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 419 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, unsigned int idx, uint32_t 423 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 437 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, uint32_t 443 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 466 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, ktime_t time), uint32_t 469 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 480 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, ktime_t time), uint32_t 484 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, ktime_t time), uint32_t 489 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, u32 event), uint32_t 492 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 502 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, u32 event), uint32_t 506 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, u32 event), uint32_t 510 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, u32 event), uint32_t 514 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, u32 event), uint32_t 519 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time, uint32_t 523 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 544 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable, uint32_t 548 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 565 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count, uint32_t 569 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 585 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count, uint32_t 589 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 608 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx), uint32_t 611 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 622 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable, uint32_t 626 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 643 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t crtc_id, uint32_t plane_id, uint32_t 645 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format, uint32_t 650 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, crtc_id ) uint32_t 651 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, plane_id ) uint32_t 652 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, fb_id ) uint32_t 655 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, stage_idx ) uint32_t 658 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, multirect_idx ) uint32_t 659 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, multirect_mode ) uint32_t 660 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, pixel_format ) uint32_t 690 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds), uint32_t 693 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 707 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable, uint32_t 711 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 712 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, enc_id ) uint32_t 729 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), uint32_t 732 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 746 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), uint32_t 750 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), uint32_t 754 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), uint32_t 759 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, int frame_pending), uint32_t 762 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 800 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode), uint32_t 803 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, drm_id ) uint32_t 805 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, multirect_mode ) uint32_t 818 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t id, uint32_t enc_id), uint32_t 821 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, id ) uint32_t 822 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, enc_id ) uint32_t 831 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t id, uint32_t enc_id), uint32_t 835 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t id, uint32_t enc_id), uint32_t 840 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id), uint32_t 843 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, id ) uint32_t 844 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, enc_id ) uint32_t 845 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( uint32_t, pp_id ) uint32_t 113 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) uint32_t 119 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) uint32_t 141 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) uint32_t 147 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) uint32_t 153 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) uint32_t 183 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) uint32_t 190 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) uint32_t 197 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) uint32_t 204 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) uint32_t 211 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) uint32_t 218 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) uint32_t 225 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) uint32_t 232 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) uint32_t 243 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) uint32_t 250 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) uint32_t 257 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) uint32_t 264 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) uint32_t 271 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) uint32_t 278 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) uint32_t 285 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) uint32_t 292 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) uint32_t 310 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t __offset_OVLP(uint32_t idx) uint32_t 319 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } uint32_t 321 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } uint32_t 323 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } uint32_t 326 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val) uint32_t 332 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val) uint32_t 337 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } uint32_t 339 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } uint32_t 341 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } uint32_t 343 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t __offset_STAGE(uint32_t idx) uint32_t 353 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } uint32_t 355 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } uint32_t 358 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) uint32_t 366 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) uint32_t 375 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } uint32_t 377 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } uint32_t 379 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } uint32_t 381 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } uint32_t 383 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } uint32_t 385 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } uint32_t 387 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t __offset_STAGE_CO3(uint32_t idx) uint32_t 397 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } uint32_t 399 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } uint32_t 402 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); } uint32_t 404 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); } uint32_t 406 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); } uint32_t 408 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); } uint32_t 410 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); } uint32_t 412 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } uint32_t 415 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 417 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 419 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 421 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 423 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 425 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 427 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 429 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 431 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 433 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } uint32_t 437 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } uint32_t 439 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } uint32_t 441 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } uint32_t 445 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } uint32_t 447 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t __offset_DMA(enum mdp4_dma idx) uint32_t 456 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } uint32_t 458 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } uint32_t 461 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) uint32_t 467 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) uint32_t 473 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) uint32_t 480 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val) uint32_t 487 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); } uint32_t 490 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) uint32_t 496 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) uint32_t 501 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); } uint32_t 503 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); } uint32_t 505 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); } uint32_t 508 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) uint32_t 514 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) uint32_t 519 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); } uint32_t 522 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) uint32_t 528 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) uint32_t 533 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); } uint32_t 535 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); } uint32_t 538 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val) uint32_t 544 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val) uint32_t 549 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); } uint32_t 553 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) uint32_t 559 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); } uint32_t 561 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); } uint32_t 563 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); } uint32_t 565 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); } uint32_t 567 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } uint32_t 570 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } uint32_t 572 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } uint32_t 574 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } uint32_t 576 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } uint32_t 578 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } uint32_t 580 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } uint32_t 582 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } uint32_t 584 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } uint32_t 586 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } uint32_t 588 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } uint32_t 590 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } uint32_t 592 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } uint32_t 595 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) uint32_t 601 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) uint32_t 606 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } uint32_t 609 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) uint32_t 615 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val) uint32_t 620 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } uint32_t 623 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) uint32_t 629 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) uint32_t 634 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } uint32_t 637 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) uint32_t 643 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val) uint32_t 648 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; } uint32_t 650 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; } uint32_t 652 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; } uint32_t 654 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; } uint32_t 656 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } uint32_t 659 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) uint32_t 665 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) uint32_t 670 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } uint32_t 673 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) uint32_t 679 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) uint32_t 684 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } uint32_t 687 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) uint32_t 693 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) uint32_t 698 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } uint32_t 701 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) uint32_t 707 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) uint32_t 713 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) uint32_t 719 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) uint32_t 726 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) uint32_t 733 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) uint32_t 741 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) uint32_t 748 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) uint32_t 754 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) uint32_t 759 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; } uint32_t 762 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) uint32_t 768 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) uint32_t 774 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) uint32_t 780 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) uint32_t 785 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } uint32_t 790 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) uint32_t 796 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) uint32_t 810 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } uint32_t 812 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } uint32_t 814 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } uint32_t 816 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } uint32_t 818 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } uint32_t 821 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } uint32_t 823 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } uint32_t 825 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } uint32_t 827 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } uint32_t 829 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } uint32_t 831 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } uint32_t 833 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } uint32_t 835 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } uint32_t 837 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } uint32_t 839 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } uint32_t 848 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) uint32_t 854 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) uint32_t 866 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) uint32_t 872 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) uint32_t 884 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) uint32_t 890 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) uint32_t 905 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) uint32_t 938 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } uint32_t 940 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; } uint32_t 943 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) uint32_t 949 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) uint32_t 955 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) uint32_t 961 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) uint32_t 966 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; } uint32_t 969 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) uint32_t 975 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) uint32_t 981 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) uint32_t 1022 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) uint32_t 1028 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) uint32_t 1040 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) uint32_t 1046 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) uint32_t 1058 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) uint32_t 1064 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) uint32_t 1079 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) uint32_t 1101 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) uint32_t 1107 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) uint32_t 1119 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) uint32_t 1125 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) uint32_t 1137 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) uint32_t 1143 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) uint32_t 1158 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) uint32_t 29 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c uint32_t width, height; uint32_t 30 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c uint32_t x, y; uint32_t 33 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c uint32_t next_iova; uint32_t 67 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c static void request_pending(struct drm_crtc *crtc, uint32_t pending) uint32_t 80 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c uint32_t flush = 0; uint32_t 156 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c uint32_t mixer_cfg = 0; uint32_t 200 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c uint32_t op; uint32_t 403 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct drm_file *file_priv, uint32_t handle, uint32_t 404 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c uint32_t width, uint32_t height) uint32_t 495 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus) uint32_t 516 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) uint32_t 547 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc) uint32_t 554 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config) uint32_t 567 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c uint32_t intf_sel; uint32_t 44 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c uint32_t dsi_hsync_skew, vsync_period, vsync_len, ctrl_pol; uint32_t 45 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c uint32_t display_v_start, display_v_end; uint32_t 46 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c uint32_t hsync_start_x, hsync_end_x; uint32_t 18 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c uint32_t bsc; uint32_t 90 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol; uint32_t 91 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c uint32_t display_v_start, display_v_end; uint32_t 92 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c uint32_t hsync_start_x, hsync_end_x; uint32_t 13 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, uint32_t 14 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c uint32_t old_irqmask) uint32_t 21 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c static void mdp4_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) uint32_t 74 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c uint32_t status, enable; uint32_t 22 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c uint32_t version, major, minor, dmap_cfg, vg_cfg; uint32_t 48 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h uint32_t max_clk; uint32_t 61 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline uint32_t pipe2flush(enum mdp4_pipe pipe) uint32_t 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline uint32_t ovlp2flush(int ovlp) uint32_t 81 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline uint32_t dma2irq(enum mdp4_dma dma) uint32_t 91 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline uint32_t dma2err(enum mdp4_dma dma) uint32_t 101 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer, uint32_t 158 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, uint32_t 159 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h uint32_t old_irqmask); uint32_t 167 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe) uint32_t 189 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc); uint32_t 190 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config); uint32_t 23 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c uint32_t bsc; uint32_t 104 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c uint32_t lvds_intf = 0, lvds_phy_cfg0 = 0; uint32_t 261 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c uint32_t lcdc_hsync_skew, vsync_period, vsync_len, ctrl_pol; uint32_t 262 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c uint32_t display_v_start, display_v_end; uint32_t 263 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c uint32_t hsync_start_x, hsync_end_x; uint32_t 364 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c uint32_t config; uint32_t 28 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c uint32_t val; uint32_t 29 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c uint32_t reg; uint32_t 21 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t caps; uint32_t 22 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t nformats; uint32_t 23 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t formats[32]; uint32_t 50 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t src_x, uint32_t src_y, uint32_t 51 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t src_w, uint32_t src_h); uint32_t 196 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t src_x, uint32_t src_y, uint32_t 197 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t src_w, uint32_t src_h) uint32_t 204 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t op_mode = 0; uint32_t 205 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT; uint32_t 206 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT; uint32_t 249 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t sel_unit = SCALE_FIR; uint32_t 265 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c uint32_t sel_unit = SCALE_FIR; uint32_t 180 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) uint32_t 186 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) uint32_t 192 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) uint32_t 207 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) uint32_t 213 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) uint32_t 219 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) uint32_t 227 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) uint32_t 233 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) uint32_t 239 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) uint32_t 245 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) uint32_t 265 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } uint32_t 267 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } uint32_t 270 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val) uint32_t 276 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val) uint32_t 282 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val) uint32_t 287 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } uint32_t 289 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } uint32_t 292 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val) uint32_t 298 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val) uint32_t 304 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val) uint32_t 309 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_IGC(enum mdp5_igc_type idx) uint32_t 319 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } uint32_t 321 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } uint32_t 323 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } uint32_t 326 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val) uint32_t 349 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_CTL(uint32_t idx) uint32_t 360 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } uint32_t 362 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_LAYER(uint32_t idx) uint32_t 374 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } uint32_t 376 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } uint32_t 379 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val) uint32_t 385 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val) uint32_t 391 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val) uint32_t 397 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val) uint32_t 403 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val) uint32_t 409 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val) uint32_t 415 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val) uint32_t 421 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val) uint32_t 429 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val) uint32_t 435 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val) uint32_t 440 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); } uint32_t 443 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val) uint32_t 449 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val) uint32_t 457 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val) uint32_t 462 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); } uint32_t 493 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); } uint32_t 495 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); } uint32_t 497 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_LAYER_EXT(uint32_t idx) uint32_t 509 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } uint32_t 511 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } uint32_t 524 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val) uint32_t 530 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val) uint32_t 535 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_PIPE(enum mdp5_pipe idx) uint32_t 554 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } uint32_t 556 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); } uint32_t 559 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val) uint32_t 565 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val) uint32_t 571 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); } uint32_t 573 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); } uint32_t 575 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); } uint32_t 577 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); } uint32_t 580 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val) uint32_t 586 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val) uint32_t 591 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); } uint32_t 594 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val) uint32_t 600 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val) uint32_t 605 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); } uint32_t 608 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val) uint32_t 614 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val) uint32_t 619 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); } uint32_t 622 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val) uint32_t 628 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val) uint32_t 633 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); } uint32_t 636 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val) uint32_t 641 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } uint32_t 643 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } uint32_t 646 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val) uint32_t 652 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val) uint32_t 657 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } uint32_t 659 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } uint32_t 662 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val) uint32_t 668 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val) uint32_t 673 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } uint32_t 675 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } uint32_t 678 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val) uint32_t 683 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } uint32_t 685 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } uint32_t 688 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val) uint32_t 693 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } uint32_t 696 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val) uint32_t 702 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val) uint32_t 707 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); } uint32_t 710 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val) uint32_t 716 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val) uint32_t 721 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); } uint32_t 724 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val) uint32_t 730 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val) uint32_t 735 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); } uint32_t 738 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val) uint32_t 744 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val) uint32_t 749 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); } uint32_t 752 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val) uint32_t 758 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val) uint32_t 763 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); } uint32_t 765 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); } uint32_t 767 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); } uint32_t 769 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); } uint32_t 771 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); } uint32_t 774 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val) uint32_t 780 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val) uint32_t 785 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); } uint32_t 788 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val) uint32_t 794 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val) uint32_t 799 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); } uint32_t 801 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); } uint32_t 804 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) uint32_t 810 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) uint32_t 816 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) uint32_t 822 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) uint32_t 829 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val) uint32_t 836 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) uint32_t 844 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val) uint32_t 850 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) uint32_t 855 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); } uint32_t 858 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val) uint32_t 864 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val) uint32_t 870 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val) uint32_t 876 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val) uint32_t 881 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); } uint32_t 885 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val) uint32_t 898 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); } uint32_t 900 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); } uint32_t 902 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); } uint32_t 904 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); } uint32_t 906 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); } uint32_t 908 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); } uint32_t 910 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); } uint32_t 912 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); } uint32_t 914 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); } uint32_t 916 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); } uint32_t 918 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); } uint32_t 920 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); } uint32_t 923 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val) uint32_t 929 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val) uint32_t 934 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx) uint32_t 943 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } uint32_t 945 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } uint32_t 948 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val) uint32_t 954 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val) uint32_t 960 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val) uint32_t 966 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val) uint32_t 971 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } uint32_t 974 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val) uint32_t 980 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val) uint32_t 986 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val) uint32_t 992 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val) uint32_t 997 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } uint32_t 1000 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val) uint32_t 1006 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val) uint32_t 1011 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); } uint32_t 1016 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val) uint32_t 1022 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val) uint32_t 1028 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val) uint32_t 1034 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val) uint32_t 1040 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val) uint32_t 1046 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val) uint32_t 1051 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); } uint32_t 1053 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); } uint32_t 1055 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); } uint32_t 1057 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); } uint32_t 1059 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); } uint32_t 1061 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); } uint32_t 1063 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_LM(uint32_t idx) uint32_t 1075 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } uint32_t 1077 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } uint32_t 1087 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); } uint32_t 1090 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val) uint32_t 1096 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val) uint32_t 1101 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); } uint32_t 1103 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); } uint32_t 1105 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_BLEND(uint32_t idx) uint32_t 1118 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1120 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1123 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val) uint32_t 1133 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val) uint32_t 1142 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1144 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1146 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1148 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1150 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1152 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1154 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1156 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1158 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1160 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); } uint32_t 1162 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); } uint32_t 1165 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val) uint32_t 1171 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val) uint32_t 1176 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); } uint32_t 1179 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val) uint32_t 1185 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val) uint32_t 1190 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); } uint32_t 1193 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val) uint32_t 1199 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val) uint32_t 1204 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); } uint32_t 1207 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val) uint32_t 1212 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); } uint32_t 1215 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val) uint32_t 1220 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); } uint32_t 1222 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); } uint32_t 1225 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val) uint32_t 1231 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val) uint32_t 1236 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); } uint32_t 1240 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val) uint32_t 1246 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); } uint32_t 1248 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); } uint32_t 1250 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); } uint32_t 1252 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); } uint32_t 1254 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); } uint32_t 1256 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); } uint32_t 1258 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_DSPP(uint32_t idx) uint32_t 1268 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } uint32_t 1270 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } uint32_t 1274 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val) uint32_t 1287 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); } uint32_t 1289 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); } uint32_t 1291 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); } uint32_t 1293 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); } uint32_t 1295 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); } uint32_t 1297 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); } uint32_t 1299 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); } uint32_t 1301 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); } uint32_t 1303 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_PP(uint32_t idx) uint32_t 1313 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } uint32_t 1315 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } uint32_t 1317 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); } uint32_t 1320 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val) uint32_t 1327 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); } uint32_t 1329 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); } uint32_t 1332 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val) uint32_t 1338 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val) uint32_t 1343 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); } uint32_t 1345 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); } uint32_t 1348 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val) uint32_t 1354 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val) uint32_t 1359 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); } uint32_t 1362 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val) uint32_t 1368 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val) uint32_t 1373 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); } uint32_t 1375 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); } uint32_t 1377 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); } uint32_t 1379 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); } uint32_t 1381 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); } uint32_t 1383 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); } uint32_t 1385 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); } uint32_t 1387 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); } uint32_t 1389 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); } uint32_t 1391 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_WB(uint32_t idx) uint32_t 1404 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } uint32_t 1406 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } uint32_t 1409 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val) uint32_t 1415 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val) uint32_t 1421 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val) uint32_t 1427 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val) uint32_t 1434 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val) uint32_t 1440 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val) uint32_t 1449 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val) uint32_t 1456 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val) uint32_t 1462 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val) uint32_t 1468 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val) uint32_t 1473 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); } uint32_t 1477 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val) uint32_t 1483 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val) uint32_t 1489 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val) uint32_t 1497 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val) uint32_t 1503 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val) uint32_t 1510 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val) uint32_t 1516 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val) uint32_t 1522 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val) uint32_t 1527 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); } uint32_t 1530 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val) uint32_t 1536 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val) uint32_t 1542 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val) uint32_t 1548 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val) uint32_t 1553 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); } uint32_t 1555 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); } uint32_t 1557 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); } uint32_t 1559 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); } uint32_t 1561 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); } uint32_t 1564 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val) uint32_t 1570 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val) uint32_t 1575 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); } uint32_t 1578 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val) uint32_t 1584 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val) uint32_t 1589 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); } uint32_t 1591 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); } uint32_t 1593 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); } uint32_t 1595 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); } uint32_t 1597 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); } uint32_t 1599 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); } uint32_t 1601 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); } uint32_t 1603 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); } uint32_t 1605 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); } uint32_t 1607 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); } uint32_t 1609 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); } uint32_t 1611 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); } uint32_t 1614 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val) uint32_t 1620 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val) uint32_t 1625 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); } uint32_t 1627 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); } uint32_t 1630 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val) uint32_t 1636 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val) uint32_t 1641 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); } uint32_t 1644 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val) uint32_t 1650 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val) uint32_t 1655 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); } uint32_t 1658 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val) uint32_t 1664 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val) uint32_t 1669 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); } uint32_t 1672 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val) uint32_t 1678 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val) uint32_t 1683 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); } uint32_t 1686 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val) uint32_t 1691 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } uint32_t 1693 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } uint32_t 1696 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val) uint32_t 1702 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val) uint32_t 1707 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } uint32_t 1709 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } uint32_t 1712 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val) uint32_t 1718 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val) uint32_t 1723 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } uint32_t 1725 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } uint32_t 1728 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val) uint32_t 1733 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } uint32_t 1735 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } uint32_t 1738 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val) uint32_t 1743 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_INTF(uint32_t idx) uint32_t 1754 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } uint32_t 1756 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } uint32_t 1758 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } uint32_t 1760 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); } uint32_t 1763 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val) uint32_t 1769 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val) uint32_t 1774 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); } uint32_t 1776 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); } uint32_t 1778 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); } uint32_t 1780 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); } uint32_t 1782 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); } uint32_t 1784 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); } uint32_t 1786 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); } uint32_t 1788 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); } uint32_t 1790 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); } uint32_t 1793 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val) uint32_t 1799 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); } uint32_t 1802 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val) uint32_t 1807 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); } uint32_t 1809 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); } uint32_t 1811 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); } uint32_t 1814 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val) uint32_t 1820 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val) uint32_t 1825 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); } uint32_t 1828 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val) uint32_t 1834 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val) uint32_t 1840 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); } uint32_t 1842 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); } uint32_t 1844 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); } uint32_t 1846 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); } uint32_t 1851 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); } uint32_t 1853 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); } uint32_t 1855 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); } uint32_t 1857 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); } uint32_t 1859 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); } uint32_t 1861 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); } uint32_t 1863 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); } uint32_t 1865 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); } uint32_t 1867 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); } uint32_t 1869 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); } uint32_t 1871 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); } uint32_t 1873 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); } uint32_t 1875 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); } uint32_t 1877 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); } uint32_t 1879 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); } uint32_t 1881 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); } uint32_t 1883 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); } uint32_t 1885 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); } uint32_t 1887 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); } uint32_t 1889 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t __offset_AD(uint32_t idx) uint32_t 1897 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } uint32_t 1899 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } uint32_t 1901 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); } uint32_t 1903 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); } uint32_t 1905 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); } uint32_t 1907 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); } uint32_t 1909 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); } uint32_t 1911 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); } uint32_t 1913 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); } uint32_t 1915 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); } uint32_t 1917 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); } uint32_t 1919 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); } uint32_t 1921 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); } uint32_t 1923 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); } uint32_t 1925 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); } uint32_t 1927 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); } uint32_t 1929 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); } uint32_t 1931 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); } uint32_t 1933 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); } uint32_t 1935 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); } uint32_t 1937 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); } uint32_t 1939 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); } uint32_t 1941 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); } uint32_t 1943 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); } uint32_t 1945 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); } uint32_t 1947 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); } uint32_t 1949 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); } uint32_t 1951 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); } uint32_t 1953 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); } uint32_t 1955 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); } uint32_t 1957 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); } uint32_t 1959 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); } uint32_t 1961 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); } uint32_t 1963 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); } uint32_t 1965 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); } uint32_t 778 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c uint32_t major, uint32_t minor) uint32_t 28 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t base[MAX_BASES] uint32_t 38 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t caps; uint32_t 44 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t nb_stages; /* number of stages per blender */ uint32_t 45 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t max_width; /* Maximum output resolution */ uint32_t 46 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t max_height; uint32_t 51 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t caps; /* pipe capabilities */ uint32_t 56 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t flush_hw_mask; /* FLUSH register's hardware mask */ uint32_t 62 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t clients[MAX_CLIENTS]; /* SMP port allocation /pipe */ uint32_t 69 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t caps; /* MDP capabilities: MDP_CAP_xxx bits */ uint32_t 75 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t base[MAX_BASES]; uint32_t 97 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t max_clk; uint32_t 122 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t major, uint32_t minor); uint32_t 59 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t width, height; uint32_t 73 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c static void request_pending(struct drm_crtc *crtc, uint32_t pending) uint32_t 111 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t flush_mask = 0; uint32_t 221 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t lm = mixer->lm; uint32_t 223 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t r_lm = r_mixer ? r_mixer->lm : 0; uint32_t 225 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0; uint32_t 369 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t lm = mixer->lm; uint32_t 750 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h) uint32_t 753 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t xres = crtc->mode.hdisplay; uint32_t 754 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t yres = crtc->mode.vdisplay; uint32_t 794 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t blendcfg, stride; uint32_t 795 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t x, y, src_x, src_y, width, height; uint32_t 796 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t roi_w, roi_h; uint32_t 856 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct drm_file *file, uint32_t handle, uint32_t 857 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t width, uint32_t height) uint32_t 869 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); uint32_t 947 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); uint32_t 949 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t roi_w; uint32_t 950 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t roi_h; uint32_t 1071 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus) uint32_t 1090 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) uint32_t 1097 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus) uint32_t 1147 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc) uint32_t 102 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol; uint32_t 103 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c uint32_t display_v_start, display_v_end; uint32_t 104 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c uint32_t hsync_start_x, hsync_end_x; uint32_t 105 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c uint32_t format = 0x2100; uint32_t 15 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, uint32_t 16 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c uint32_t old_irqmask) uint32_t 23 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) uint32_t 87 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c uint32_t status, enable; uint32_t 802 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c const enum mdp5_pipe *pipes, const uint32_t *offsets, uint32_t 803 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c uint32_t caps) uint32_t 37 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */ uint32_t 163 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h uint32_t bsc; uint32_t 221 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h static inline uint32_t intf2err(int intf_num) uint32_t 232 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h static inline uint32_t intf2vblank(struct mdp5_hw_mixer *mixer, uint32_t 257 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer) uint32_t 262 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, uint32_t 263 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h uint32_t old_irqmask); uint32_t 273 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h uint32_t mdp5_plane_get_flush(struct drm_plane *plane); uint32_t 280 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc); uint32_t 39 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c uint32_t caps, struct mdp5_hw_mixer **mixer, uint32_t 16 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h uint32_t caps; uint32_t 20 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h uint32_t flush_mask; /* used to commit LM registers */ uint32_t 31 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h uint32_t caps, struct mdp5_hw_mixer **mixer, uint32_t 10 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c uint32_t caps, uint32_t blkcfg, uint32_t 152 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c uint32_t reg_offset, uint32_t caps) uint32_t 20 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h uint32_t reg_offset; uint32_t 21 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h uint32_t caps; uint32_t 23 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h uint32_t flush_mask; /* used to commit pipe registers */ uint32_t 28 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h uint32_t blkcfg; uint32_t 37 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h uint32_t caps, uint32_t blkcfg, uint32_t 43 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h uint32_t reg_offset, uint32_t caps); uint32_t 17 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t nformats; uint32_t 18 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t formats[32]; uint32_t 262 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t max_width, max_height; uint32_t 264 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t caps = 0; uint32_t 311 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t blkcfg = 0; uint32_t 561 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & uint32_t 571 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t i, mode = 0; /* RGB, no CSC */ uint32_t 572 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t *matrix; uint32_t 601 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t *pre_clamp = csc->pre_clamp; uint32_t 602 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t *post_clamp = csc->post_clamp; uint32_t 623 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) uint32_t 625 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t unit; uint32_t 646 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t pixel_format, uint32_t src, uint32_t dest, uint32_t 647 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t phasex_steps[COMP_MAX]) uint32_t 652 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t phasex_step; uint32_t 669 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t pixel_format, uint32_t src, uint32_t dest, uint32_t 670 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t phasey_steps[COMP_MAX]) uint32_t 675 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t phasey_step; uint32_t 691 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static uint32_t get_scale_config(const struct mdp_format *format, uint32_t 692 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t src, uint32_t dst, bool horz) uint32_t 696 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t sub; uint32_t 697 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t ya_filter, uv_filter; uint32_t 723 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t src, uint32_t dst, uint32_t phase_step[2], uint32_t 746 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], uint32_t 747 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) uint32_t 750 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t lr, tb, req; uint32_t 754 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t roi_w = src_w; uint32_t 755 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t roi_h = src_h; uint32_t 923 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t nplanes, config = 0; uint32_t 926 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t hdecm = 0, vdecm = 0; uint32_t 927 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t pix_format; uint32_t 932 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t src_x, src_y; uint32_t 933 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t src_w, src_h; uint32_t 934 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t src_img_w, src_img_h; uint32_t 1049 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t mdp5_plane_get_flush(struct drm_plane *plane) uint32_t 116 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c uint32_t mdp5_smp_calculate(struct mdp5_smp *smp, uint32_t 125 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c uint32_t blkcfg = 0; uint32_t 167 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c enum mdp5_pipe pipe, uint32_t blkcfg) uint32_t 75 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h uint32_t mdp5_smp_calculate(struct mdp5_smp *smp, uint32_t 80 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h enum mdp5_pipe pipe, uint32_t blkcfg); uint32_t 144 drivers/gpu/drm/msm/disp/mdp_format.c uint32_t mdp_get_formats(uint32_t *pixel_formats, uint32_t max_formats, uint32_t 147 drivers/gpu/drm/msm/disp/mdp_format.c uint32_t i; uint32_t 163 drivers/gpu/drm/msm/disp/mdp_format.c const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint32_t 24 drivers/gpu/drm/msm/disp/mdp_kms.c uint32_t irqmask = mdp_kms->vblank_mask; uint32_t 46 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status) uint32_t 66 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable) uint32_t 79 drivers/gpu/drm/msm/disp/mdp_kms.c static void wait_irq(struct mdp_irq *irq, uint32_t irqstatus) uint32_t 87 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask) uint32_t 22 drivers/gpu/drm/msm/disp/mdp_kms.h void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask, uint32_t 23 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t old_irqmask); uint32_t 34 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t vblank_mask; /* irq bits set for userspace vblank */ uint32_t 35 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t cur_irq_mask; /* current irq mask */ uint32_t 59 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t irqmask; uint32_t 61 drivers/gpu/drm/msm/disp/mdp_kms.h void (*irq)(struct mdp_irq *irq, uint32_t irqstatus); uint32_t 64 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status); uint32_t 65 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable); uint32_t 66 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask); uint32_t 89 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only); uint32_t 90 drivers/gpu/drm/msm/disp/mdp_kms.h const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); uint32_t 112 drivers/gpu/drm/msm/disp/mdp_kms.h static inline bool pipe_supports_yuv(uint32_t pipe_caps) uint32_t 128 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t matrix[9]; uint32_t 129 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t pre_bias[3]; uint32_t 130 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t post_bias[3]; uint32_t 131 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t pre_clamp[6]; uint32_t 132 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t post_clamp[6]; uint32_t 113 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) uint32_t 119 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) uint32_t 125 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) uint32_t 156 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) uint32_t 162 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) uint32_t 168 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) uint32_t 185 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) uint32_t 193 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) uint32_t 199 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) uint32_t 207 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) uint32_t 213 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) uint32_t 221 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) uint32_t 227 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) uint32_t 235 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) uint32_t 241 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) uint32_t 249 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) uint32_t 255 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) uint32_t 263 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) uint32_t 269 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) uint32_t 282 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) uint32_t 291 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) uint32_t 297 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) uint32_t 305 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) uint32_t 311 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) uint32_t 324 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) uint32_t 330 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) uint32_t 336 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) uint32_t 344 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) uint32_t 350 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) uint32_t 357 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } uint32_t 359 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } uint32_t 364 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) uint32_t 370 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) uint32_t 376 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) uint32_t 397 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) uint32_t 403 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) uint32_t 418 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) uint32_t 450 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) uint32_t 459 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) uint32_t 571 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } uint32_t 573 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } uint32_t 575 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } uint32_t 577 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } uint32_t 579 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } uint32_t 581 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } uint32_t 583 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } uint32_t 600 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) uint32_t 608 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) uint32_t 616 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) uint32_t 626 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) uint32_t 634 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) uint32_t 642 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) uint32_t 650 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) uint32_t 658 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) uint32_t 666 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) uint32_t 672 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) uint32_t 680 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) uint32_t 688 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) uint32_t 800 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } uint32_t 802 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } uint32_t 804 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } uint32_t 806 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } uint32_t 808 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } uint32_t 810 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } uint32_t 812 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } uint32_t 814 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } uint32_t 816 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } uint32_t 818 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } uint32_t 841 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) uint32_t 849 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) uint32_t 857 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) uint32_t 868 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) uint32_t 876 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) uint32_t 884 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) uint32_t 892 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) uint32_t 900 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) uint32_t 908 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) uint32_t 914 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) uint32_t 922 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) uint32_t 930 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) uint32_t 1017 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) uint32_t 1026 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) uint32_t 1032 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) uint32_t 1040 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) uint32_t 1048 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) uint32_t 1127 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } uint32_t 1129 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } uint32_t 1131 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } uint32_t 1133 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } uint32_t 1135 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } uint32_t 1137 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } uint32_t 1139 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } uint32_t 1141 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } uint32_t 1143 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } uint32_t 1145 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } uint32_t 1168 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) uint32_t 1176 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) uint32_t 1184 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) uint32_t 1195 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) uint32_t 1203 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) uint32_t 1211 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) uint32_t 1219 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) uint32_t 1227 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) uint32_t 1235 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) uint32_t 1241 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) uint32_t 1249 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) uint32_t 1257 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) uint32_t 1318 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val) uint32_t 1324 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val) uint32_t 1363 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val) uint32_t 1368 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } uint32_t 1370 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } uint32_t 1373 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val) uint32_t 1378 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } uint32_t 1381 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } uint32_t 1383 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } uint32_t 1385 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } uint32_t 1387 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } uint32_t 1389 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; } uint32_t 1392 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val) uint32_t 1397 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; } uint32_t 1400 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val) uint32_t 1405 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; } uint32_t 1408 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val) uint32_t 1413 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; } uint32_t 1416 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val) uint32_t 1421 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; } uint32_t 1424 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val) uint32_t 1429 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; } uint32_t 1432 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val) uint32_t 1438 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val) uint32_t 1443 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; } uint32_t 1446 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val) uint32_t 1451 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; } uint32_t 1454 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) uint32_t 1459 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; } uint32_t 1461 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; } uint32_t 1463 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; } uint32_t 1629 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } uint32_t 1631 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } uint32_t 1633 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } uint32_t 1635 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } uint32_t 1637 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } uint32_t 1639 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } uint32_t 1641 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } uint32_t 1643 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } uint32_t 1645 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; } uint32_t 1647 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; } uint32_t 1649 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; } uint32_t 1651 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } uint32_t 1653 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } uint32_t 56 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t __offset_CLK(enum mmss_cc_clk idx) uint32_t 64 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } uint32_t 66 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } uint32_t 72 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val) uint32_t 78 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val) uint32_t 83 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } uint32_t 86 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val) uint32_t 92 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val) uint32_t 97 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } uint32_t 100 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val) uint32_t 106 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val) uint32_t 112 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val) uint32_t 57 drivers/gpu/drm/msm/dsi/sfpb.xml.h static inline uint32_t SFPB_GPREG_MASTER_PORT_EN(enum sfpb_ahb_arb_master_port_en val) uint32_t 83 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_CONFIGURATION_CTRL_LANES(uint32_t val) uint32_t 90 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_CONFIGURATION_CTRL_COLOR(enum edp_color_depth val) uint32_t 102 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_TOTAL_HOR_VER_HORIZ(uint32_t val) uint32_t 108 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_TOTAL_HOR_VER_VERT(uint32_t val) uint32_t 116 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_HORIZ(uint32_t val) uint32_t 122 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_VERT(uint32_t val) uint32_t 130 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ(uint32_t val) uint32_t 137 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT(uint32_t val) uint32_t 146 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_ACTIVE_HOR_VER_HORIZ(uint32_t val) uint32_t 152 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_ACTIVE_HOR_VER_VERT(uint32_t val) uint32_t 160 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_MISC0(uint32_t val) uint32_t 167 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_COMPONENT_FORMAT(enum edp_component_format val) uint32_t 175 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_COLOR(enum edp_color_depth val) uint32_t 181 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_MISC1(uint32_t val) uint32_t 188 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_MISC1_MISC0_STEREO(uint32_t val) uint32_t 258 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_AUX_DATA_DATA(uint32_t val) uint32_t 264 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t EDP_AUX_DATA_INDEX(uint32_t val) uint32_t 276 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; } uint32_t 278 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; } uint32_t 16 drivers/gpu/drm/msm/hdmi/hdmi.c uint32_t ctrl = 0; uint32_t 219 drivers/gpu/drm/msm/hdmi/hdmi.h uint32_t num_of_channels, uint32_t channel_allocation, uint32_t 220 drivers/gpu/drm/msm/hdmi/hdmi.h uint32_t level_shift, bool down_mix); uint32_t 85 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) uint32_t 92 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) uint32_t 117 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val) uint32_t 123 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val) uint32_t 129 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val) uint32_t 135 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val) uint32_t 145 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) uint32_t 153 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) uint32_t 159 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) uint32_t 171 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } uint32_t 175 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } uint32_t 179 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } uint32_t 181 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } uint32_t 183 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } uint32_t 186 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) uint32_t 191 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } uint32_t 194 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACR_1_N(uint32_t val) uint32_t 202 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val) uint32_t 208 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val) uint32_t 216 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val) uint32_t 222 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) uint32_t 257 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val) uint32_t 330 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val) uint32_t 344 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val) uint32_t 369 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val) uint32_t 375 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val) uint32_t 383 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val) uint32_t 388 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } uint32_t 390 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } uint32_t 393 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val) uint32_t 402 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) uint32_t 410 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val) uint32_t 416 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val) uint32_t 422 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) uint32_t 452 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val) uint32_t 462 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) uint32_t 494 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) uint32_t 500 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) uint32_t 508 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) uint32_t 514 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) uint32_t 522 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) uint32_t 528 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) uint32_t 536 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) uint32_t 542 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) uint32_t 550 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) uint32_t 592 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val) uint32_t 600 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val) uint32_t 606 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) uint32_t 25 drivers/gpu/drm/msm/hdmi/hdmi_audio.c uint32_t n; /* N parameter for clock regeneration */ uint32_t 26 drivers/gpu/drm/msm/hdmi/hdmi_audio.c uint32_t cts; /* CTS parameter for clock regeneration */ uint32_t 80 drivers/gpu/drm/msm/hdmi/hdmi_audio.c uint32_t acr_pkt_ctrl, vbi_pkt_ctrl, aud_pkt_ctrl; uint32_t 81 drivers/gpu/drm/msm/hdmi/hdmi_audio.c uint32_t infofrm_ctrl, audio_config; uint32_t 114 drivers/gpu/drm/msm/hdmi/hdmi_audio.c uint32_t n, cts, multiplier; uint32_t 218 drivers/gpu/drm/msm/hdmi/hdmi_audio.c uint32_t num_of_channels, uint32_t channel_allocation, uint32_t 219 drivers/gpu/drm/msm/hdmi/hdmi_audio.c uint32_t level_shift, bool down_mix) uint32_t 208 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c uint32_t frame_ctrl; uint32_t 148 drivers/gpu/drm/msm/hdmi/hdmi_connector.c uint32_t hpd_ctrl; uint32_t 249 drivers/gpu/drm/msm/hdmi/hdmi_connector.c uint32_t hpd_int_status, hpd_int_ctrl; uint32_t 277 drivers/gpu/drm/msm/hdmi/hdmi_connector.c uint32_t hpd_int_status; uint32_t 357 drivers/gpu/drm/msm/hdmi/hdmi_connector.c uint32_t hdmi_ctrl; uint32_t 43 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c uint32_t retry = 0xffff; uint32_t 44 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c uint32_t ddc_int_ctrl; uint32_t 74 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c uint32_t ddc_int_ctrl; uint32_t 95 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c static const uint32_t nack[] = { uint32_t 101 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c uint32_t ddc_status, ddc_data, i2c_trans; uint32_t 118 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c uint32_t raw_addr = p->addr << 1; uint32_t 376 drivers/gpu/drm/msm/msm_drv.c (uint32_t)priv->vram.paddr, uint32_t 377 drivers/gpu/drm/msm/msm_drv.c (uint32_t)(priv->vram.paddr + size)); uint32_t 122 drivers/gpu/drm/msm/msm_drv.h uint32_t capabilities; uint32_t 123 drivers/gpu/drm/msm/msm_drv.h uint32_t num_of_h_tiles; uint32_t 124 drivers/gpu/drm/msm/msm_drv.h uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; uint32_t 221 drivers/gpu/drm/msm/msm_drv.h uint32_t pixel_format; uint32_t 287 drivers/gpu/drm/msm/msm_drv.h uint32_t handle, uint64_t *offset); uint32_t 305 drivers/gpu/drm/msm/msm_drv.h int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); uint32_t 309 drivers/gpu/drm/msm/msm_drv.h uint32_t size, uint32_t flags, uint32_t *handle, char *name); uint32_t 311 drivers/gpu/drm/msm/msm_drv.h uint32_t size, uint32_t flags); uint32_t 313 drivers/gpu/drm/msm/msm_drv.h uint32_t size, uint32_t flags); uint32_t 314 drivers/gpu/drm/msm/msm_drv.h void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, uint32_t 315 drivers/gpu/drm/msm/msm_drv.h uint32_t flags, struct msm_gem_address_space *aspace, uint32_t 317 drivers/gpu/drm/msm/msm_drv.h void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, uint32_t 318 drivers/gpu/drm/msm/msm_drv.h uint32_t flags, struct msm_gem_address_space *aspace, uint32_t 333 drivers/gpu/drm/msm/msm_drv.h uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, uint32_t 340 drivers/gpu/drm/msm/msm_drv.h int w, int h, int p, uint32_t format); uint32_t 80 drivers/gpu/drm/msm/msm_fb.c uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, uint32_t 207 drivers/gpu/drm/msm/msm_fb.c msm_alloc_stolen_fb(struct drm_device *dev, int w, int h, int p, uint32_t format) uint32_t 70 drivers/gpu/drm/msm/msm_fbdev.c uint32_t format; uint32_t 36 drivers/gpu/drm/msm/msm_fence.c static inline bool fence_completed(struct msm_fence_context *fctx, uint32_t fence) uint32_t 42 drivers/gpu/drm/msm/msm_fence.c int msm_wait_fence(struct msm_fence_context *fctx, uint32_t fence, uint32_t 81 drivers/gpu/drm/msm/msm_fence.c void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence) uint32_t 17 drivers/gpu/drm/msm/msm_fence.h uint32_t last_fence; /* last assigned fence */ uint32_t 18 drivers/gpu/drm/msm/msm_fence.h uint32_t completed_fence; /* last completed fence */ uint32_t 27 drivers/gpu/drm/msm/msm_fence.h int msm_wait_fence(struct msm_fence_context *fctx, uint32_t fence, uint32_t 29 drivers/gpu/drm/msm/msm_fence.h void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence); uint32_t 532 drivers/gpu/drm/msm/msm_gem.c uint32_t handle, uint64_t *offset) uint32_t 763 drivers/gpu/drm/msm/msm_gem.c int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout) uint32_t 956 drivers/gpu/drm/msm/msm_gem.c uint32_t size, uint32_t flags, uint32_t *handle, uint32_t 979 drivers/gpu/drm/msm/msm_gem.c uint32_t size, uint32_t flags, uint32_t 1024 drivers/gpu/drm/msm/msm_gem.c uint32_t size, uint32_t flags, bool struct_mutex_locked) uint32_t 1097 drivers/gpu/drm/msm/msm_gem.c uint32_t size, uint32_t flags) uint32_t 1103 drivers/gpu/drm/msm/msm_gem.c uint32_t size, uint32_t flags) uint32_t 1113 drivers/gpu/drm/msm/msm_gem.c uint32_t size; uint32_t 1156 drivers/gpu/drm/msm/msm_gem.c static void *_msm_gem_kernel_new(struct drm_device *dev, uint32_t size, uint32_t 1157 drivers/gpu/drm/msm/msm_gem.c uint32_t flags, struct msm_gem_address_space *aspace, uint32_t 1194 drivers/gpu/drm/msm/msm_gem.c void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, uint32_t 1195 drivers/gpu/drm/msm/msm_gem.c uint32_t flags, struct msm_gem_address_space *aspace, uint32_t 1201 drivers/gpu/drm/msm/msm_gem.c void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, uint32_t 1202 drivers/gpu/drm/msm/msm_gem.c uint32_t flags, struct msm_gem_address_space *aspace, uint32_t 40 drivers/gpu/drm/msm/msm_gem.h uint32_t flags; uint32_t 137 drivers/gpu/drm/msm/msm_gem.h uint32_t seqno; /* Sequence number of the submit on the ring */ uint32_t 148 drivers/gpu/drm/msm/msm_gem.h uint32_t type; uint32_t 149 drivers/gpu/drm/msm/msm_gem.h uint32_t size; /* in dwords */ uint32_t 151 drivers/gpu/drm/msm/msm_gem.h uint32_t idx; /* cmdstream buffer idx in bos[] */ uint32_t 154 drivers/gpu/drm/msm/msm_gem.h uint32_t flags; uint32_t 157 drivers/gpu/drm/msm/msm_gem.h uint32_t handle; uint32_t 29 drivers/gpu/drm/msm/msm_gem_submit.c struct msm_gpu_submitqueue *queue, uint32_t nr_bos, uint32_t 30 drivers/gpu/drm/msm/msm_gem_submit.c uint32_t nr_cmds) uint32_t 282 drivers/gpu/drm/msm/msm_gem_submit.c static int submit_bo(struct msm_gem_submit *submit, uint32_t idx, uint32_t 303 drivers/gpu/drm/msm/msm_gem_submit.c uint32_t offset, uint32_t nr_relocs, uint64_t relocs) uint32_t 305 drivers/gpu/drm/msm/msm_gem_submit.c uint32_t i, last_offset = 0; uint32_t 306 drivers/gpu/drm/msm/msm_gem_submit.c uint32_t *ptr; uint32_t 332 drivers/gpu/drm/msm/msm_gem_submit.c uint32_t off; uint32_t 390 drivers/gpu/drm/msm/msm_gpu.c uint32_t fence) uint32_t 404 drivers/gpu/drm/msm/msm_gpu.c find_submit(struct msm_ringbuffer *ring, uint32_t fence) uint32_t 474 drivers/gpu/drm/msm/msm_gpu.c uint32_t fence = ring->memptrs->fence; uint32_t 524 drivers/gpu/drm/msm/msm_gpu.c uint32_t fence = ring->memptrs->fence; uint32_t 555 drivers/gpu/drm/msm/msm_gpu.c static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) uint32_t 557 drivers/gpu/drm/msm/msm_gpu.c uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; uint32_t 578 drivers/gpu/drm/msm/msm_gpu.c uint32_t elapsed; uint32_t 622 drivers/gpu/drm/msm/msm_gpu.c int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, uint32_t 623 drivers/gpu/drm/msm/msm_gpu.c uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) uint32_t 44 drivers/gpu/drm/msm/msm_gpu.h int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); uint32_t 82 drivers/gpu/drm/msm/msm_gpu.h uint32_t totaltime, activetime; /* sw counters */ uint32_t 83 drivers/gpu/drm/msm/msm_gpu.h uint32_t last_cntrs[5]; /* hw counters */ uint32_t 85 drivers/gpu/drm/msm/msm_gpu.h uint32_t num_perfcntrs; uint32_t 112 drivers/gpu/drm/msm/msm_gpu.h uint32_t fast_rate; uint32_t 165 drivers/gpu/drm/msm/msm_gpu.h uint32_t select_reg; uint32_t 166 drivers/gpu/drm/msm/msm_gpu.h uint32_t sample_reg; uint32_t 167 drivers/gpu/drm/msm/msm_gpu.h uint32_t select_val; uint32_t 226 drivers/gpu/drm/msm/msm_gpu.h uint32_t val = gpu_read(gpu, reg); uint32_t 271 drivers/gpu/drm/msm/msm_gpu.h int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, uint32_t 272 drivers/gpu/drm/msm/msm_gpu.h uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); uint32_t 15 drivers/gpu/drm/msm/msm_gpummu.c uint32_t *table; uint32_t 22 drivers/gpu/drm/msm/msm_gpummu.c #define TABLE_SIZE (sizeof(uint32_t) * GPUMMU_VA_RANGE / GPUMMU_PAGE_SIZE) uint32_t 105 drivers/gpu/drm/msm/msm_kms.h const uint32_t format, uint32_t 80 drivers/gpu/drm/msm/msm_perf.c uint32_t activetime = 0, totaltime = 0; uint32_t 81 drivers/gpu/drm/msm/msm_perf.c uint32_t cntrs[5]; uint32_t 82 drivers/gpu/drm/msm/msm_perf.c uint32_t val; uint32_t 181 drivers/gpu/drm/msm/msm_rd.c uint32_t gpu_id; uint32_t 301 drivers/gpu/drm/msm/msm_rd.c uint64_t iova, uint32_t size) uint32_t 319 drivers/gpu/drm/msm/msm_rd.c (uint32_t[3]){ iova, size, iova >> 32 }, 12); uint32_t 389 drivers/gpu/drm/msm/msm_rd.c uint32_t szd = submit->cmd[i].size; /* in dwords */ uint32_t 407 drivers/gpu/drm/msm/msm_rd.c (uint32_t[3]){ iova, szd, iova >> 32 }, 12); uint32_t 30 drivers/gpu/drm/msm/msm_ringbuffer.h volatile uint32_t rptr; uint32_t 31 drivers/gpu/drm/msm/msm_ringbuffer.h volatile uint32_t fence; uint32_t 40 drivers/gpu/drm/msm/msm_ringbuffer.h uint32_t *start, *end, *cur, *next; uint32_t 43 drivers/gpu/drm/msm/msm_ringbuffer.h uint32_t seqno; uint32_t 44 drivers/gpu/drm/msm/msm_ringbuffer.h uint32_t hangcheck_fence; uint32_t 58 drivers/gpu/drm/msm/msm_ringbuffer.h OUT_RING(struct msm_ringbuffer *ring, uint32_t data) uint32_t 107 drivers/gpu/drm/msm/msm_submitqueue.c clamp_t(uint32_t, 2, 0, priv->gpu->nr_rings - 1) : 0; uint32_t 67 drivers/gpu/drm/mxsfb/mxsfb_drv.c static const uint32_t mxsfb_formats[] = { uint32_t 204 drivers/gpu/drm/nouveau/dispnv04/arb.c uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); uint32_t 213 drivers/gpu/drm/nouveau/dispnv04/arb.c uint32_t type; uint32_t 714 drivers/gpu/drm/nouveau/dispnv04/crtc.c uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); uint32_t 796 drivers/gpu/drm/nouveau/dispnv04/crtc.c uint32_t size, uint32_t 926 drivers/gpu/drm/nouveau/dispnv04/crtc.c uint32_t pixel; uint32_t 944 drivers/gpu/drm/nouveau/dispnv04/crtc.c uint32_t pixel; uint32_t 984 drivers/gpu/drm/nouveau/dispnv04/crtc.c uint32_t buffer_handle, uint32_t width, uint32_t height) uint32_t 1263 drivers/gpu/drm/nouveau/dispnv04/crtc.c static const uint32_t modeset_formats[] = { uint32_t 38 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) uint32_t 139 drivers/gpu/drm/nouveau/dispnv04/dac.c uint32_t saved_rtest_ctrl, saved_rgen_ctrl; uint32_t 234 drivers/gpu/drm/nouveau/dispnv04/dac.c uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) uint32_t 241 drivers/gpu/drm/nouveau/dispnv04/dac.c uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); uint32_t 242 drivers/gpu/drm/nouveau/dispnv04/dac.c uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, uint32_t 384 drivers/gpu/drm/nouveau/dispnv04/dac.c uint32_t dac_offset = nv04_dac_output_offset(encoder); uint32_t 385 drivers/gpu/drm/nouveau/dispnv04/dac.c uint32_t otherdac; uint32_t 431 drivers/gpu/drm/nouveau/dispnv04/dac.c uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1]; uint32_t 433 drivers/gpu/drm/nouveau/dispnv04/dac.c uint32_t dacclk = NVReadRAMDAC(dev, 0, dacclk_off); uint32_t 49 drivers/gpu/drm/nouveau/dispnv04/dfp.c static inline bool is_fpc_off(uint32_t fpc) uint32_t 118 drivers/gpu/drm/nouveau/dispnv04/dfp.c uint32_t *fpc; uint32_t 207 drivers/gpu/drm/nouveau/dispnv04/dfp.c uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000; uint32_t 294 drivers/gpu/drm/nouveau/dispnv04/dfp.c uint32_t mode_ratio, panel_ratio; uint32_t 380 drivers/gpu/drm/nouveau/dispnv04/dfp.c uint32_t diff, scale; uint32_t 29 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t fb_start; uint32_t 30 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t crtc_cfg; uint32_t 31 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t cursor_cfg; uint32_t 32 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t gpio_ext; uint32_t 33 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t crtc_830; uint32_t 34 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t crtc_834; uint32_t 35 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t crtc_850; uint32_t 36 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t crtc_eng_ctrl; uint32_t 39 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t nv10_cursync; uint32_t 41 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t ramdac_gen_ctrl; uint32_t 42 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t ramdac_630; uint32_t 43 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t ramdac_634; uint32_t 44 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t tv_setup; uint32_t 45 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t tv_vtotal; uint32_t 46 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t tv_vskew; uint32_t 47 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t tv_vsync_delay; uint32_t 48 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t tv_htotal; uint32_t 49 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t tv_hskew; uint32_t 50 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t tv_hsync_delay; uint32_t 51 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t tv_hsync_delay2; uint32_t 52 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t fp_horiz_regs[7]; uint32_t 53 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t fp_vert_regs[7]; uint32_t 54 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t dither; uint32_t 55 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t fp_control; uint32_t 56 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t dither_regs[6]; uint32_t 57 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t fp_debug_0; uint32_t 58 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t fp_debug_1; uint32_t 59 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t fp_debug_2; uint32_t 60 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t fp_margin_color; uint32_t 61 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t ramdac_8c0; uint32_t 62 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t ramdac_a20; uint32_t 63 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t ramdac_a24; uint32_t 64 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t ramdac_a34; uint32_t 65 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t ctv_regs[38]; uint32_t 69 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t output; uint32_t 75 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t pllsel; uint32_t 76 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t sel_clk; uint32_t 82 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t saved_vga_font[4][16384]; uint32_t 83 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t dac_users[4]; uint32_t 102 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); uint32_t 131 drivers/gpu/drm/nouveau/dispnv04/hw.c nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, uint32_t 132 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t pll2, struct nvkm_pll_vals *pllvals) uint32_t 169 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t reg1, pll1, pll2 = 0; uint32_t 181 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); uint32_t 187 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); uint32_t 224 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t mpllP; uint32_t 235 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t clock; uint32_t 425 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); uint32_t 472 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; uint32_t 502 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); uint32_t 669 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t reg900; uint32_t 59 drivers/gpu/drm/nouveau/dispnv04/hw.h static inline uint32_t NVReadCRTC(struct drm_device *dev, uint32_t 60 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg) uint32_t 63 drivers/gpu/drm/nouveau/dispnv04/hw.h uint32_t val; uint32_t 71 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg, uint32_t val) uint32_t 79 drivers/gpu/drm/nouveau/dispnv04/hw.h static inline uint32_t NVReadRAMDAC(struct drm_device *dev, uint32_t 80 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg) uint32_t 83 drivers/gpu/drm/nouveau/dispnv04/hw.h uint32_t val; uint32_t 91 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg, uint32_t val) uint32_t 165 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg) uint32_t 181 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg, uint8_t value) uint32_t 348 drivers/gpu/drm/nouveau/dispnv04/hw.h uint32_t curpos = NVReadRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS); uint32_t 353 drivers/gpu/drm/nouveau/dispnv04/hw.h nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset) uint32_t 388 drivers/gpu/drm/nouveau/dispnv04/hw.h static inline uint32_t uint32_t 389 drivers/gpu/drm/nouveau/dispnv04/hw.h nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp) uint32_t 60 drivers/gpu/drm/nouveau/dispnv04/overlay.c static uint32_t formats[] = { uint32_t 93 drivers/gpu/drm/nouveau/dispnv04/overlay.c uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, uint32_t 94 drivers/gpu/drm/nouveau/dispnv04/overlay.c uint32_t crtc_w, uint32_t crtc_h) uint32_t 115 drivers/gpu/drm/nouveau/dispnv04/overlay.c uint32_t src_x, uint32_t src_y, uint32_t 116 drivers/gpu/drm/nouveau/dispnv04/overlay.c uint32_t src_w, uint32_t src_h, uint32_t 364 drivers/gpu/drm/nouveau/dispnv04/overlay.c uint32_t src_x, uint32_t src_y, uint32_t 365 drivers/gpu/drm/nouveau/dispnv04/overlay.c uint32_t src_w, uint32_t src_h, uint32_t 373 drivers/gpu/drm/nouveau/dispnv04/overlay.c uint32_t overlay = 1; uint32_t 407 drivers/gpu/drm/nouveau/dispnv04/overlay.c (uint32_t)(((src_h - 1) << 11) / (crtc_h - 1)) << 16 | (uint32_t)(((src_w - 1) << 11) / (crtc_w - 1))); uint32_t 320 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c uint32_t (*filters[])[4][7] = {&tv_enc->state.hfilter, uint32_t 356 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c static void tv_save_filter(struct drm_device *dev, uint32_t base, uint32_t 357 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c uint32_t regs[4][7]) uint32_t 360 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c uint32_t offsets[] = { base, base + 0x1c, base + 0x40, base + 0x5c }; uint32_t 368 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c static void tv_load_filter(struct drm_device *dev, uint32_t base, uint32_t 369 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c uint32_t regs[4][7]) uint32_t 372 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c uint32_t offsets[] = { base, base + 0x1c, base + 0x40, base + 0x5c }; uint32_t 45 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) uint32_t 50 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c uint32_t testval, regoffset = nv04_dac_output_offset(encoder); uint32_t 51 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, uint32_t 53 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c uint32_t sample = 0; uint32_t 130 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) uint32_t 405 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c uint32_t dacclk_off = NV_PRAMDAC_DACCLK + uint32_t 407 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c uint32_t dacclk; uint32_t 33 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t hfilter[4][7]; uint32_t 34 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t hfilter2[4][7]; uint32_t 35 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t vfilter[4][7]; uint32_t 37 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_200; uint32_t 38 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_204; uint32_t 39 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_208; uint32_t 40 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_20c; uint32_t 41 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_304; uint32_t 42 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_500; uint32_t 43 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_504; uint32_t 44 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_508; uint32_t 45 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_600; uint32_t 46 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_604; uint32_t 47 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_608; uint32_t 48 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_60c; uint32_t 49 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_610; uint32_t 50 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ptv_614; uint32_t 83 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t pin_mask; uint32_t 108 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t ctv_regs[38]; uint32_t 130 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg, uint32_t 131 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t val) uint32_t 137 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg) uint32_t 46 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t fb_ctxdma_handle; uint32_t 47 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t tt_ctxdma_handle; uint32_t 50 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t pushbuf_domains; uint32_t 53 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t notifier_handle; uint32_t 57 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t handle; uint32_t 58 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t grclass; uint32_t 60 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t nr_subchan; uint32_t 69 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t handle; uint32_t 74 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t channel; uint32_t 75 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t handle; uint32_t 76 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t size; uint32_t 77 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t offset; uint32_t 82 drivers/gpu/drm/nouveau/nouveau_abi16.h uint32_t handle; uint32_t 72 drivers/gpu/drm/nouveau/nouveau_acpi.c static int nouveau_optimus_dsm(acpi_handle handle, int func, int arg, uint32_t *result) uint32_t 276 drivers/gpu/drm/nouveau/nouveau_acpi.c uint32_t result; uint32_t 219 drivers/gpu/drm/nouveau/nouveau_bios.c uint32_t sel_clk_binding, sel_clk; uint32_t 640 drivers/gpu/drm/nouveau/nouveau_bios.c uint32_t sel_clk_binding, sel_clk; uint32_t 1396 drivers/gpu/drm/nouveau/nouveau_bios.c uint32_t conn, uint32_t conf, struct dcb_output *entry) uint32_t 1421 drivers/gpu/drm/nouveau/nouveau_bios.c uint32_t mask; uint32_t 1543 drivers/gpu/drm/nouveau/nouveau_bios.c uint32_t conn, uint32_t conf, struct dcb_output *entry) uint32_t 83 drivers/gpu/drm/nouveau/nouveau_bios.h uint32_t length; uint32_t 88 drivers/gpu/drm/nouveau/nouveau_bios.h uint32_t dactestval; uint32_t 89 drivers/gpu/drm/nouveau/nouveau_bios.h uint32_t tvdactestval; uint32_t 101 drivers/gpu/drm/nouveau/nouveau_bios.h uint32_t fmaxvco, fminvco; uint32_t 321 drivers/gpu/drm/nouveau/nouveau_bo.c uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, uint32_t 342 drivers/gpu/drm/nouveau/nouveau_bo.c set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) uint32_t 355 drivers/gpu/drm/nouveau/nouveau_bo.c set_placement_range(struct nouveau_bo *nvbo, uint32_t type) uint32_t 389 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) uint32_t 392 drivers/gpu/drm/nouveau/nouveau_bo.c uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : uint32_t 408 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) uint32_t 636 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) uint32_t 650 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) uint32_t 657 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, uint32_t 1036 drivers/gpu/drm/nouveau/nouveau_bo.c static inline uint32_t uint32_t 40 drivers/gpu/drm/nouveau/nouveau_crtc.h uint32_t dpms_saved_fp_control; uint32_t 41 drivers/gpu/drm/nouveau/nouveau_crtc.h uint32_t fp_users; uint32_t 51 drivers/gpu/drm/nouveau/nouveau_crtc.h uint32_t offset; uint32_t 52 drivers/gpu/drm/nouveau/nouveau_crtc.h uint32_t handle; uint32_t 57 drivers/gpu/drm/nouveau/nouveau_crtc.h uint32_t offset; uint32_t 58 drivers/gpu/drm/nouveau/nouveau_crtc.h void (*set_offset)(struct nouveau_crtc *, uint32_t offset); uint32_t 648 drivers/gpu/drm/nouveau/nouveau_display.c uint32_t domain; uint32_t 673 drivers/gpu/drm/nouveau/nouveau_display.c uint32_t handle, uint64_t *poffset) uint32_t 111 drivers/gpu/drm/nouveau/nouveau_dma.c uint32_t cnt = 0, prev_get = 0; uint32_t 114 drivers/gpu/drm/nouveau/nouveau_dma.c uint32_t get = nvif_rd32(&chan->user, 0x88); uint32_t 168 drivers/gpu/drm/nouveau/nouveau_gem.c nouveau_gem_new(struct nouveau_cli *cli, u64 size, int align, uint32_t domain, uint32_t 169 drivers/gpu/drm/nouveau/nouveau_gem.c uint32_t tile_mode, uint32_t tile_flags, uint32_t 287 drivers/gpu/drm/nouveau/nouveau_gem.c nouveau_gem_set_domain(struct drm_gem_object *gem, uint32_t read_domains, uint32_t 288 drivers/gpu/drm/nouveau/nouveau_gem.c uint32_t write_domains, uint32_t valid_domains) uint32_t 292 drivers/gpu/drm/nouveau/nouveau_gem.c uint32_t domains = valid_domains & nvbo->valid_domains & uint32_t 294 drivers/gpu/drm/nouveau/nouveau_gem.c uint32_t pref_flags = 0, valid_flags = 0; uint32_t 622 drivers/gpu/drm/nouveau/nouveau_gem.c uint32_t data; uint32_t 814 drivers/gpu/drm/nouveau/nouveau_gem.c uint32_t cmd; uint32_t 16 drivers/gpu/drm/nouveau/nouveau_gem.h uint32_t domain, uint32_t tile_mode, uint32_t 17 drivers/gpu/drm/nouveau/nouveau_gem.h uint32_t tile_flags, struct nouveau_bo **); uint32_t 85 drivers/gpu/drm/nouveau/nouveau_sgdma.c nouveau_sgdma_create_ttm(struct ttm_buffer_object *bo, uint32_t page_flags) uint32_t 66 drivers/gpu/drm/nouveau/nv04_fbcon.c OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); uint32_t 82 drivers/gpu/drm/nouveau/nv04_fbcon.c uint32_t fg; uint32_t 83 drivers/gpu/drm/nouveau/nv04_fbcon.c uint32_t bg; uint32_t 84 drivers/gpu/drm/nouveau/nv04_fbcon.c uint32_t dsize; uint32_t 85 drivers/gpu/drm/nouveau/nv04_fbcon.c uint32_t *data = (uint32_t *)image->data; uint32_t 97 drivers/gpu/drm/nouveau/nv04_fbcon.c fg = ((uint32_t *) info->pseudo_palette)[image->fg_color]; uint32_t 98 drivers/gpu/drm/nouveau/nv04_fbcon.c bg = ((uint32_t *) info->pseudo_palette)[image->bg_color]; uint32_t 49 drivers/gpu/drm/nouveau/nv50_fbcon.c OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); uint32_t 99 drivers/gpu/drm/nouveau/nv50_fbcon.c uint32_t dwords, *data = (uint32_t *)image->data; uint32_t 100 drivers/gpu/drm/nouveau/nv50_fbcon.c uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); uint32_t 101 drivers/gpu/drm/nouveau/nv50_fbcon.c uint32_t *palette = info->pseudo_palette; uint32_t 49 drivers/gpu/drm/nouveau/nvc0_fbcon.c OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); uint32_t 99 drivers/gpu/drm/nouveau/nvc0_fbcon.c uint32_t dwords, *data = (uint32_t *)image->data; uint32_t 100 drivers/gpu/drm/nouveau/nvc0_fbcon.c uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); uint32_t 101 drivers/gpu/drm/nouveau/nvc0_fbcon.c uint32_t *palette = info->pseudo_palette; uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h static uint32_t gf100_ce_data[] = { uint32_t 175 drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h static uint32_t gf100_ce_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h static uint32_t gt215_ce_data[] = { uint32_t 187 drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h static uint32_t gt215_ce_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h static uint32_t gf100_grgpc_data[] = { uint32_t 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h static uint32_t gf100_grgpc_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h static uint32_t gf117_grgpc_data[] = { uint32_t 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h static uint32_t gf117_grgpc_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h static uint32_t gk104_grgpc_data[] = { uint32_t 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h static uint32_t gk104_grgpc_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h static uint32_t gk110_grgpc_data[] = { uint32_t 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h static uint32_t gk110_grgpc_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h static uint32_t gk208_grgpc_data[] = { uint32_t 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h static uint32_t gk208_grgpc_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h static uint32_t gm107_grgpc_data[] = { uint32_t 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h static uint32_t gm107_grgpc_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h static uint32_t gf100_grhub_data[] = { uint32_t 209 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h static uint32_t gf100_grhub_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h static uint32_t gf117_grhub_data[] = { uint32_t 209 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h static uint32_t gf117_grhub_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h static uint32_t gk104_grhub_data[] = { uint32_t 209 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h static uint32_t gk104_grhub_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h static uint32_t gk110_grhub_data[] = { uint32_t 209 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h static uint32_t gk110_grhub_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h static uint32_t gk208_grhub_data[] = { uint32_t 209 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h static uint32_t gk208_grhub_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h static uint32_t gm107_grhub_data[] = { uint32_t 209 drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h static uint32_t gm107_grhub_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h static uint32_t g98_sec_data[] = { uint32_t 154 drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h static uint32_t g98_sec_code[] = { uint32_t 148 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldpll = nvkm_rd32(device, reg); uint32_t 150 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; uint32_t 151 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t saved_powerctrl_1 = 0; uint32_t 184 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c static uint32_t uint32_t 185 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) uint32_t 204 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); uint32_t 205 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldpll1 = nvkm_rd32(device, reg1); uint32_t 206 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0; uint32_t 207 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; uint32_t 208 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; uint32_t 209 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldramdac580 = 0, ramdac580 = 0; uint32_t 211 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t saved_powerctrl_1 = 0, savedc040 = 0; uint32_t 287 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t Preg = NMNMreg - 4; uint32_t 289 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldPval = nvkm_rd32(device, Preg); uint32_t 290 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t NMNM = pv->NM2 << 16 | pv->NM1; uint32_t 291 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | uint32_t 293 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t saved4600 = 0; uint32_t 295 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t maskc040 = ~(3 << 14), savedc040; uint32_t 39 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c uint32_t patt = 0xdeadbeef; uint32_t 37 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900); uint32_t 38 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c uint32_t amount, off; uint32_t 2 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h static uint32_t gf100_pmu_data[] = { uint32_t 920 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h static uint32_t gf100_pmu_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h static uint32_t gf119_pmu_data[] = { uint32_t 919 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h static uint32_t gf119_pmu_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h static uint32_t gk208_pmu_data[] = { uint32_t 919 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h static uint32_t gk208_pmu_code[] = { uint32_t 2 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h static uint32_t gt215_pmu_data[] = { uint32_t 920 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h static uint32_t gt215_pmu_code[] = { uint32_t 96 drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c uint32_t thrs_reg, u8 status_bit, uint32_t 145 drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c uint32_t intr; uint32_t 172 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c uint32_t stat = nvkm_rd32(device, 0x1100); uint32_t 327 drivers/gpu/drm/omapdrm/omap_crtc.c void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus) uint32_t 33 drivers/gpu/drm/omapdrm/omap_crtc.h void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus); uint32_t 240 drivers/gpu/drm/panfrost/panfrost_gem.c uint32_t *handle) uint32_t 75 drivers/gpu/drm/panfrost/panfrost_gem.h uint32_t *handle); uint32_t 187 drivers/gpu/drm/qxl/qxl_cmd.c uint32_t type, bool interruptible) uint32_t 199 drivers/gpu/drm/qxl/qxl_cmd.c uint32_t type, bool interruptible) uint32_t 336 drivers/gpu/drm/qxl/qxl_cmd.c uint32_t surface_width, surface_height; uint32_t 429 drivers/gpu/drm/qxl/qxl_cmd.c uint32_t handle; uint32_t 459 drivers/gpu/drm/qxl/qxl_cmd.c uint32_t surface_id) uint32_t 149 drivers/gpu/drm/qxl/qxl_dev.h #define QXL_ROM_MAGIC (*(uint32_t *)"QXRO") uint32_t 150 drivers/gpu/drm/qxl/qxl_dev.h #define QXL_RAM_MAGIC (*(uint32_t *)"QXRA") uint32_t 221 drivers/gpu/drm/qxl/qxl_dev.h uint32_t top; uint32_t 222 drivers/gpu/drm/qxl/qxl_dev.h uint32_t left; uint32_t 223 drivers/gpu/drm/qxl/qxl_dev.h uint32_t bottom; uint32_t 224 drivers/gpu/drm/qxl/qxl_dev.h uint32_t right; uint32_t 229 drivers/gpu/drm/qxl/qxl_dev.h uint32_t magic; uint32_t 230 drivers/gpu/drm/qxl/qxl_dev.h uint32_t id; uint32_t 231 drivers/gpu/drm/qxl/qxl_dev.h uint32_t update_id; uint32_t 232 drivers/gpu/drm/qxl/qxl_dev.h uint32_t compression_level; uint32_t 233 drivers/gpu/drm/qxl/qxl_dev.h uint32_t log_level; uint32_t 234 drivers/gpu/drm/qxl/qxl_dev.h uint32_t mode; /* qxl-1 */ uint32_t 235 drivers/gpu/drm/qxl/qxl_dev.h uint32_t modes_offset; uint32_t 236 drivers/gpu/drm/qxl/qxl_dev.h uint32_t num_io_pages; uint32_t 237 drivers/gpu/drm/qxl/qxl_dev.h uint32_t pages_offset; /* qxl-1 */ uint32_t 238 drivers/gpu/drm/qxl/qxl_dev.h uint32_t draw_area_offset; /* qxl-1 */ uint32_t 239 drivers/gpu/drm/qxl/qxl_dev.h uint32_t surface0_area_size; /* qxl-1 name: draw_area_size */ uint32_t 240 drivers/gpu/drm/qxl/qxl_dev.h uint32_t ram_header_offset; uint32_t 241 drivers/gpu/drm/qxl/qxl_dev.h uint32_t mm_clock; uint32_t 243 drivers/gpu/drm/qxl/qxl_dev.h uint32_t n_surfaces; uint32_t 253 drivers/gpu/drm/qxl/qxl_dev.h uint32_t client_monitors_config_crc; uint32_t 263 drivers/gpu/drm/qxl/qxl_dev.h uint32_t id; uint32_t 264 drivers/gpu/drm/qxl/qxl_dev.h uint32_t x_res; uint32_t 265 drivers/gpu/drm/qxl/qxl_dev.h uint32_t y_res; uint32_t 266 drivers/gpu/drm/qxl/qxl_dev.h uint32_t bits; uint32_t 267 drivers/gpu/drm/qxl/qxl_dev.h uint32_t stride; uint32_t 268 drivers/gpu/drm/qxl/qxl_dev.h uint32_t x_mili; uint32_t 269 drivers/gpu/drm/qxl/qxl_dev.h uint32_t y_mili; uint32_t 270 drivers/gpu/drm/qxl/qxl_dev.h uint32_t orientation; uint32_t 275 drivers/gpu/drm/qxl/qxl_dev.h uint32_t n_modes; uint32_t 292 drivers/gpu/drm/qxl/qxl_dev.h uint32_t type; uint32_t 293 drivers/gpu/drm/qxl/qxl_dev.h uint32_t padding; uint32_t 301 drivers/gpu/drm/qxl/qxl_dev.h uint32_t group_id; uint32_t 302 drivers/gpu/drm/qxl/qxl_dev.h uint32_t flags; uint32_t 315 drivers/gpu/drm/qxl/qxl_dev.h uint32_t width; uint32_t 316 drivers/gpu/drm/qxl/qxl_dev.h uint32_t height; uint32_t 318 drivers/gpu/drm/qxl/qxl_dev.h uint32_t format; uint32_t 319 drivers/gpu/drm/qxl/qxl_dev.h uint32_t position; uint32_t 320 drivers/gpu/drm/qxl/qxl_dev.h uint32_t mouse_mode; uint32_t 321 drivers/gpu/drm/qxl/qxl_dev.h uint32_t flags; uint32_t 322 drivers/gpu/drm/qxl/qxl_dev.h uint32_t type; uint32_t 340 drivers/gpu/drm/qxl/qxl_dev.h uint32_t num_items; uint32_t 341 drivers/gpu/drm/qxl/qxl_dev.h uint32_t prod; uint32_t 342 drivers/gpu/drm/qxl/qxl_dev.h uint32_t notify_on_prod; uint32_t 343 drivers/gpu/drm/qxl/qxl_dev.h uint32_t cons; uint32_t 344 drivers/gpu/drm/qxl/qxl_dev.h uint32_t notify_on_cons; uint32_t 349 drivers/gpu/drm/qxl/qxl_dev.h uint32_t magic; uint32_t 350 drivers/gpu/drm/qxl/qxl_dev.h uint32_t int_pending; uint32_t 351 drivers/gpu/drm/qxl/qxl_dev.h uint32_t int_mask; uint32_t 361 drivers/gpu/drm/qxl/qxl_dev.h uint32_t update_surface; uint32_t 380 drivers/gpu/drm/qxl/qxl_dev.h uint32_t group_id; uint32_t 384 drivers/gpu/drm/qxl/qxl_dev.h uint32_t data_size; uint32_t 398 drivers/gpu/drm/qxl/qxl_dev.h uint32_t update_id; uint32_t 404 drivers/gpu/drm/qxl/qxl_dev.h uint32_t update_id; uint32_t 405 drivers/gpu/drm/qxl/qxl_dev.h uint32_t surface_id; uint32_t 419 drivers/gpu/drm/qxl/qxl_dev.h uint32_t data_size; uint32_t 478 drivers/gpu/drm/qxl/qxl_dev.h uint32_t data_size; uint32_t 505 drivers/gpu/drm/qxl/qxl_dev.h uint32_t type; uint32_t 507 drivers/gpu/drm/qxl/qxl_dev.h uint32_t color; uint32_t 544 drivers/gpu/drm/qxl/qxl_dev.h uint32_t src_color; uint32_t 545 drivers/gpu/drm/qxl/qxl_dev.h uint32_t true_color; uint32_t 602 drivers/gpu/drm/qxl/qxl_dev.h uint32_t type; uint32_t 640 drivers/gpu/drm/qxl/qxl_dev.h uint32_t t00; uint32_t 641 drivers/gpu/drm/qxl/qxl_dev.h uint32_t t01; uint32_t 642 drivers/gpu/drm/qxl/qxl_dev.h uint32_t t02; uint32_t 643 drivers/gpu/drm/qxl/qxl_dev.h uint32_t t10; uint32_t 644 drivers/gpu/drm/qxl/qxl_dev.h uint32_t t11; uint32_t 645 drivers/gpu/drm/qxl/qxl_dev.h uint32_t t12; uint32_t 669 drivers/gpu/drm/qxl/qxl_dev.h uint32_t flags; uint32_t 687 drivers/gpu/drm/qxl/qxl_dev.h uint32_t mm_time; uint32_t 707 drivers/gpu/drm/qxl/qxl_dev.h uint32_t surface_id; uint32_t 714 drivers/gpu/drm/qxl/qxl_dev.h uint32_t mm_time; uint32_t 741 drivers/gpu/drm/qxl/qxl_dev.h uint32_t format; uint32_t 742 drivers/gpu/drm/qxl/qxl_dev.h uint32_t width; uint32_t 743 drivers/gpu/drm/qxl/qxl_dev.h uint32_t height; uint32_t 750 drivers/gpu/drm/qxl/qxl_dev.h uint32_t surface_id; uint32_t 752 drivers/gpu/drm/qxl/qxl_dev.h uint32_t flags; uint32_t 759 drivers/gpu/drm/qxl/qxl_dev.h uint32_t num_rects; uint32_t 771 drivers/gpu/drm/qxl/qxl_dev.h uint32_t flags; uint32_t 772 drivers/gpu/drm/qxl/qxl_dev.h uint32_t count; uint32_t 777 drivers/gpu/drm/qxl/qxl_dev.h uint32_t data_size; uint32_t 789 drivers/gpu/drm/qxl/qxl_dev.h uint32_t group; uint32_t 790 drivers/gpu/drm/qxl/qxl_dev.h uint32_t unique; uint32_t 817 drivers/gpu/drm/qxl/qxl_dev.h uint32_t width; uint32_t 818 drivers/gpu/drm/qxl/qxl_dev.h uint32_t height; uint32_t 824 drivers/gpu/drm/qxl/qxl_dev.h uint32_t ents[0]; uint32_t 830 drivers/gpu/drm/qxl/qxl_dev.h uint32_t x; uint32_t 831 drivers/gpu/drm/qxl/qxl_dev.h uint32_t y; uint32_t 832 drivers/gpu/drm/qxl/qxl_dev.h uint32_t stride; uint32_t 838 drivers/gpu/drm/qxl/qxl_dev.h uint32_t surface_id; uint32_t 842 drivers/gpu/drm/qxl/qxl_dev.h uint32_t data_size; uint32_t 860 drivers/gpu/drm/qxl/qxl_dev.h uint32_t id; uint32_t 861 drivers/gpu/drm/qxl/qxl_dev.h uint32_t surface_id; uint32_t 862 drivers/gpu/drm/qxl/qxl_dev.h uint32_t width; uint32_t 863 drivers/gpu/drm/qxl/qxl_dev.h uint32_t height; uint32_t 864 drivers/gpu/drm/qxl/qxl_dev.h uint32_t x; uint32_t 865 drivers/gpu/drm/qxl/qxl_dev.h uint32_t y; uint32_t 866 drivers/gpu/drm/qxl/qxl_dev.h uint32_t flags; uint32_t 74 drivers/gpu/drm/qxl/qxl_display.c uint32_t crc; uint32_t 548 drivers/gpu/drm/qxl/qxl_display.c uint32_t dumb_shadow_offset = 0; uint32_t 723 drivers/gpu/drm/qxl/qxl_display.c uint32_t width, height; uint32_t 849 drivers/gpu/drm/qxl/qxl_display.c static const uint32_t qxl_cursor_plane_formats[] = { uint32_t 869 drivers/gpu/drm/qxl/qxl_display.c static const uint32_t qxl_primary_plane_formats[] = { uint32_t 898 drivers/gpu/drm/qxl/qxl_display.c const uint32_t *formats; uint32_t 127 drivers/gpu/drm/qxl/qxl_draw.c uint32_t dumb_shadow_offset) uint32_t 93 drivers/gpu/drm/qxl/qxl_drv.h uint32_t surface_id; uint32_t 154 drivers/gpu/drm/qxl/qxl_drv.h uint32_t release_offset; uint32_t 155 drivers/gpu/drm/qxl/qxl_drv.h uint32_t surface_release_id; uint32_t 172 drivers/gpu/drm/qxl/qxl_drv.h uint32_t pseudo_palette[16]; uint32_t 174 drivers/gpu/drm/qxl/qxl_drv.h uint32_t visual; uint32_t 180 drivers/gpu/drm/qxl/qxl_drv.h uint32_t color; uint32_t 236 drivers/gpu/drm/qxl/qxl_drv.h uint32_t release_seqno; uint32_t 338 drivers/gpu/drm/qxl/qxl_drv.h uint32_t *handle); uint32_t 352 drivers/gpu/drm/qxl/qxl_drv.h uint32_t handle, uint64_t *offset_p); uint32_t 413 drivers/gpu/drm/qxl/qxl_drv.h uint32_t type, bool interruptible); uint32_t 416 drivers/gpu/drm/qxl/qxl_drv.h uint32_t type, bool interruptible); uint32_t 429 drivers/gpu/drm/qxl/qxl_drv.h uint32_t dumb_shadow_offset); uint32_t 469 drivers/gpu/drm/qxl/qxl_drv.h uint32_t surface_id); uint32_t 37 drivers/gpu/drm/qxl/qxl_dumb.c uint32_t handle; uint32_t 40 drivers/gpu/drm/qxl/qxl_dumb.c uint32_t pitch, format; uint32_t 75 drivers/gpu/drm/qxl/qxl_dumb.c uint32_t handle, uint64_t *offset_p) uint32_t 81 drivers/gpu/drm/qxl/qxl_gem.c uint32_t *handle) uint32_t 43 drivers/gpu/drm/qxl/qxl_ioctl.c uint32_t handle; uint32_t 77 drivers/gpu/drm/qxl/qxl_ioctl.c uint32_t dst_offset; uint32_t 102 drivers/gpu/drm/qxl/qxl_ioctl.c uint32_t id = 0; uint32_t 109 drivers/gpu/drm/qxl/qxl_ioctl.c *(uint32_t *)(reloc_page + (info->dst_offset & ~PAGE_MASK)) = id; uint32_t 36 drivers/gpu/drm/qxl/qxl_irq.c uint32_t pending; uint32_t 92 drivers/gpu/drm/qxl/qxl_ttm.c static int qxl_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) uint32_t 97 drivers/gpu/drm/qxl/qxl_ttm.c static int qxl_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, uint32_t 244 drivers/gpu/drm/qxl/qxl_ttm.c uint32_t page_flags) uint32_t 40 drivers/gpu/drm/radeon/atom-bits.h static inline uint32_t get_u32(void *bios, int ptr) uint32_t 42 drivers/gpu/drm/radeon/atom-bits.h return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16); uint32_t 31 drivers/gpu/drm/radeon/atom-types.h typedef uint32_t ULONG; uint32_t 61 drivers/gpu/drm/radeon/atom.c uint32_t *ps, *ws; uint32_t 70 drivers/gpu/drm/radeon/atom.c static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); uint32_t 71 drivers/gpu/drm/radeon/atom.c int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); uint32_t 73 drivers/gpu/drm/radeon/atom.c static uint32_t atom_arg_mask[8] = { uint32_t 107 drivers/gpu/drm/radeon/atom.c static uint32_t atom_iio_execute(struct atom_context *ctx, int base, uint32_t 108 drivers/gpu/drm/radeon/atom.c uint32_t index, uint32_t data) uint32_t 111 drivers/gpu/drm/radeon/atom.c uint32_t temp = 0xCDCDCDCD; uint32_t 182 drivers/gpu/drm/radeon/atom.c static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, uint32_t 183 drivers/gpu/drm/radeon/atom.c int *ptr, uint32_t *saved, int print) uint32_t 185 drivers/gpu/drm/radeon/atom.c uint32_t idx, val = 0xCDCDCDCD, align, arg; uint32_t 369 drivers/gpu/drm/radeon/atom.c uint32_t align = (attr >> 3) & 7, arg = attr & 7; uint32_t 403 drivers/gpu/drm/radeon/atom.c static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) uint32_t 408 drivers/gpu/drm/radeon/atom.c static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) uint32_t 410 drivers/gpu/drm/radeon/atom.c uint32_t val = 0xCDCDCDCD; uint32_t 434 drivers/gpu/drm/radeon/atom.c static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, uint32_t 435 drivers/gpu/drm/radeon/atom.c int *ptr, uint32_t *saved, int print) uint32_t 451 drivers/gpu/drm/radeon/atom.c int *ptr, uint32_t val, uint32_t saved) uint32_t 453 drivers/gpu/drm/radeon/atom.c uint32_t align = uint32_t 589 drivers/gpu/drm/radeon/atom.c uint32_t dst, src, saved; uint32_t 603 drivers/gpu/drm/radeon/atom.c uint32_t dst, src, saved; uint32_t 638 drivers/gpu/drm/radeon/atom.c uint32_t saved; uint32_t 650 drivers/gpu/drm/radeon/atom.c uint32_t dst, src; uint32_t 676 drivers/gpu/drm/radeon/atom.c uint32_t dst, src; uint32_t 751 drivers/gpu/drm/radeon/atom.c uint32_t dst, mask, src, saved; uint32_t 768 drivers/gpu/drm/radeon/atom.c uint32_t src, saved; uint32_t 785 drivers/gpu/drm/radeon/atom.c uint32_t dst, src; uint32_t 801 drivers/gpu/drm/radeon/atom.c uint32_t dst, src, saved; uint32_t 891 drivers/gpu/drm/radeon/atom.c uint32_t saved, dst; uint32_t 907 drivers/gpu/drm/radeon/atom.c uint32_t saved, dst; uint32_t 923 drivers/gpu/drm/radeon/atom.c uint32_t saved, dst; uint32_t 925 drivers/gpu/drm/radeon/atom.c uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; uint32_t 942 drivers/gpu/drm/radeon/atom.c uint32_t saved, dst; uint32_t 944 drivers/gpu/drm/radeon/atom.c uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; uint32_t 961 drivers/gpu/drm/radeon/atom.c uint32_t dst, src, saved; uint32_t 975 drivers/gpu/drm/radeon/atom.c uint32_t src, val, target; uint32_t 1002 drivers/gpu/drm/radeon/atom.c uint32_t dst, src; uint32_t 1014 drivers/gpu/drm/radeon/atom.c uint32_t dst, src, saved; uint32_t 1158 drivers/gpu/drm/radeon/atom.c static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) uint32_t 1219 drivers/gpu/drm/radeon/atom.c int atom_execute_table_scratch_unlocked(struct atom_context *ctx, int index, uint32_t * params) uint32_t 1240 drivers/gpu/drm/radeon/atom.c int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) uint32_t 1330 drivers/gpu/drm/radeon/atom.c uint32_t ps[16]; uint32_t 114 drivers/gpu/drm/radeon/atom.h void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t 115 drivers/gpu/drm/radeon/atom.h uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */ uint32_t 116 drivers/gpu/drm/radeon/atom.h void (* ioreg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t 117 drivers/gpu/drm/radeon/atom.h uint32_t (* ioreg_read)(struct card_info *, uint32_t); /* filled by driver */ uint32_t 118 drivers/gpu/drm/radeon/atom.h void (* mc_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t 119 drivers/gpu/drm/radeon/atom.h uint32_t (* mc_read)(struct card_info *, uint32_t); /* filled by driver */ uint32_t 120 drivers/gpu/drm/radeon/atom.h void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ uint32_t 121 drivers/gpu/drm/radeon/atom.h uint32_t (* pll_read)(struct card_info *, uint32_t); /* filled by driver */ uint32_t 129 drivers/gpu/drm/radeon/atom.h uint32_t cmd_table, data_table; uint32_t 133 drivers/gpu/drm/radeon/atom.h uint32_t fb_base; uint32_t 134 drivers/gpu/drm/radeon/atom.h uint32_t divmul[2]; uint32_t 140 drivers/gpu/drm/radeon/atom.h uint32_t *scratch; uint32_t 147 drivers/gpu/drm/radeon/atom.h int atom_execute_table(struct atom_context *, int, uint32_t *); uint32_t 148 drivers/gpu/drm/radeon/atom.h int atom_execute_table_scratch_unlocked(struct atom_context *, int, uint32_t *); uint32_t 80 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 160 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 181 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 197 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 213 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 245 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 265 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 347 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 393 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 550 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 703 drivers/gpu/drm/radeon/atombios_crtc.c index, (uint32_t *)&args); uint32_t 736 drivers/gpu/drm/radeon/atombios_crtc.c index, (uint32_t *)&args); uint32_t 820 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 960 drivers/gpu/drm/radeon/atombios_crtc.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1155 drivers/gpu/drm/radeon/atombios_crtc.c uint32_t fb_format, fb_pitch_pixels, tiling_flags; uint32_t 1477 drivers/gpu/drm/radeon/atombios_crtc.c uint32_t fb_format, fb_pitch_pixels, tiling_flags; uint32_t 115 drivers/gpu/drm/radeon/atombios_dp.c atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 356 drivers/gpu/drm/radeon/atombios_dp.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 117 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 120 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 122 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 399 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 455 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 556 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 674 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 997 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1379 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1415 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1537 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1549 drivers/gpu/drm/radeon/atombios_encoders.c uint32_t temp, reg; uint32_t 1572 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1636 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1639 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1647 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1655 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 1658 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2006 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2056 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2073 drivers/gpu/drm/radeon/atombios_encoders.c uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); uint32_t 2122 drivers/gpu/drm/radeon/atombios_encoders.c uint32_t dig_enc_in_use = 0; uint32_t 2380 drivers/gpu/drm/radeon/atombios_encoders.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2394 drivers/gpu/drm/radeon/atombios_encoders.c uint32_t bios_0_scratch; uint32_t 2726 drivers/gpu/drm/radeon/atombios_encoders.c uint32_t encoder_enum, uint32_t 2727 drivers/gpu/drm/radeon/atombios_encoders.c uint32_t supported_device, uint32_t 86 drivers/gpu/drm/radeon/atombios_i2c.c atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3461 drivers/gpu/drm/radeon/cik.c uint32_t scratch; uint32_t 3462 drivers/gpu/drm/radeon/cik.c uint32_t tmp = 0; uint32_t 3786 drivers/gpu/drm/radeon/cik.c uint32_t scratch; uint32_t 3787 drivers/gpu/drm/radeon/cik.c uint32_t tmp = 0; uint32_t 5555 drivers/gpu/drm/radeon/cik.c uint32_t reg; uint32_t 9433 drivers/gpu/drm/radeon/cik.c uint32_t tmp; uint32_t 230 drivers/gpu/drm/radeon/cik_reg.h uint32_t mask:24; uint32_t 231 drivers/gpu/drm/radeon/cik_reg.h uint32_t vmid:4; uint32_t 232 drivers/gpu/drm/radeon/cik_reg.h uint32_t atc:1; uint32_t 233 drivers/gpu/drm/radeon/cik_reg.h uint32_t mode:2; uint32_t 234 drivers/gpu/drm/radeon/cik_reg.h uint32_t valid:1; uint32_t 236 drivers/gpu/drm/radeon/cik_reg.h uint32_t u32All; uint32_t 63 drivers/gpu/drm/radeon/cik_sdma.c uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, uint32_t 90 drivers/gpu/drm/radeon/cik_sdma.c uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, uint32_t 306 drivers/gpu/drm/radeon/cik_sdma.c uint32_t reg_offset, value; uint32_t 845 drivers/gpu/drm/radeon/cik_sdma.c uint32_t incr, uint32_t flags) uint32_t 894 drivers/gpu/drm/radeon/cik_sdma.c uint32_t incr, uint32_t flags) uint32_t 3001 drivers/gpu/drm/radeon/evergreen.c uint32_t cp_me; uint32_t 451 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t *ib = p->ib.ptr; uint32_t 1028 drivers/gpu/drm/radeon/evergreen_cs.c static uint32_t vline_start_end[6] = { uint32_t 1036 drivers/gpu/drm/radeon/evergreen_cs.c static uint32_t vline_status[6] = { uint32_t 1777 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t *ib; uint32_t 2620 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t areg; uint32_t 2621 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t allowed_reg_base; uint32_t 2622 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t source_sel; uint32_t 2642 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t swap; uint32_t 2802 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t *ib = p->ib.ptr; uint32_t 3495 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t areg; uint32_t 3496 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t allowed_reg_base; uint32_t 322 drivers/gpu/drm/radeon/evergreen_hdmi.c uint32_t val; uint32_t 456 drivers/gpu/drm/radeon/evergreen_hdmi.c uint32_t val; uint32_t 43 drivers/gpu/drm/radeon/evergreen_smc.h uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; uint32_t 1437 drivers/gpu/drm/radeon/ni.c uint32_t next_rptr = ring->wptr + 3 + 4 + 8; uint32_t 1689 drivers/gpu/drm/radeon/ni.c uint32_t rb_cntl; uint32_t 53 drivers/gpu/drm/radeon/ni_dma.c uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, uint32_t 80 drivers/gpu/drm/radeon/ni_dma.c uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, uint32_t 357 drivers/gpu/drm/radeon/ni_dma.c uint32_t incr, uint32_t flags) uint32_t 405 drivers/gpu/drm/radeon/ni_dma.c uint32_t incr, uint32_t flags) uint32_t 49 drivers/gpu/drm/radeon/nislands_smc.h uint32_t TDPLimit; uint32_t 50 drivers/gpu/drm/radeon/nislands_smc.h uint32_t NearTDPLimit; uint32_t 51 drivers/gpu/drm/radeon/nislands_smc.h uint32_t SafePowerLimit; uint32_t 52 drivers/gpu/drm/radeon/nislands_smc.h uint32_t PowerBoostLimit; uint32_t 58 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL; uint32_t 59 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL_2; uint32_t 60 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL_3; uint32_t 61 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL_4; uint32_t 62 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vCG_SPLL_SPREAD_SPECTRUM; uint32_t 63 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 64 drivers/gpu/drm/radeon/nislands_smc.h uint32_t sclk_value; uint32_t 71 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMPLL_FUNC_CNTL; uint32_t 72 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMPLL_FUNC_CNTL_1; uint32_t 73 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMPLL_FUNC_CNTL_2; uint32_t 74 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMPLL_AD_FUNC_CNTL; uint32_t 75 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMPLL_AD_FUNC_CNTL_2; uint32_t 76 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMPLL_DQ_FUNC_CNTL; uint32_t 77 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMPLL_DQ_FUNC_CNTL_2; uint32_t 78 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMCLK_PWRMGT_CNTL; uint32_t 79 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vDLL_CNTL; uint32_t 80 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMPLL_SS; uint32_t 81 drivers/gpu/drm/radeon/nislands_smc.h uint32_t vMPLL_SS2; uint32_t 82 drivers/gpu/drm/radeon/nislands_smc.h uint32_t mclk_value; uint32_t 106 drivers/gpu/drm/radeon/nislands_smc.h uint32_t aT; uint32_t 107 drivers/gpu/drm/radeon/nislands_smc.h uint32_t bSP; uint32_t 114 drivers/gpu/drm/radeon/nislands_smc.h uint32_t powergate_en; uint32_t 119 drivers/gpu/drm/radeon/nislands_smc.h uint32_t SQPowerThrottle; uint32_t 120 drivers/gpu/drm/radeon/nislands_smc.h uint32_t SQPowerThrottle_2; uint32_t 121 drivers/gpu/drm/radeon/nislands_smc.h uint32_t reserved[2]; uint32_t 154 drivers/gpu/drm/radeon/nislands_smc.h uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; uint32_t 168 drivers/gpu/drm/radeon/nislands_smc.h uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; uint32_t 200 drivers/gpu/drm/radeon/nislands_smc.h uint32_t tpp[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; uint32_t 201 drivers/gpu/drm/radeon/nislands_smc.h uint32_t cacValue[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; uint32_t 209 drivers/gpu/drm/radeon/nislands_smc.h uint32_t cac_bif_lut[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES]; uint32_t 210 drivers/gpu/drm/radeon/nislands_smc.h uint32_t cac_lkge_lut[SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; uint32_t 212 drivers/gpu/drm/radeon/nislands_smc.h uint32_t pwr_const; uint32_t 214 drivers/gpu/drm/radeon/nislands_smc.h uint32_t dc_cacValue; uint32_t 215 drivers/gpu/drm/radeon/nislands_smc.h uint32_t bif_cacValue; uint32_t 216 drivers/gpu/drm/radeon/nislands_smc.h uint32_t lkge_pwr; uint32_t 224 drivers/gpu/drm/radeon/nislands_smc.h uint32_t last_power; uint32_t 236 drivers/gpu/drm/radeon/nislands_smc.h uint32_t dynPwr_TDP[4]; uint32_t 237 drivers/gpu/drm/radeon/nislands_smc.h uint32_t lkgePwr_TDP[4]; uint32_t 238 drivers/gpu/drm/radeon/nislands_smc.h uint32_t power_TDP[4]; uint32_t 239 drivers/gpu/drm/radeon/nislands_smc.h uint32_t avg_dynPwr_TDP; uint32_t 240 drivers/gpu/drm/radeon/nislands_smc.h uint32_t avg_lkgePwr_TDP; uint32_t 241 drivers/gpu/drm/radeon/nislands_smc.h uint32_t avg_power_TDP; uint32_t 242 drivers/gpu/drm/radeon/nislands_smc.h uint32_t lts_power_TDP; uint32_t 263 drivers/gpu/drm/radeon/nislands_smc.h uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; uint32_t 280 drivers/gpu/drm/radeon/nislands_smc.h uint32_t mc_arb_dram_timing; uint32_t 281 drivers/gpu/drm/radeon/nislands_smc.h uint32_t mc_arb_dram_timing2; uint32_t 299 drivers/gpu/drm/radeon/nislands_smc.h uint32_t freq[256]; uint32_t 300 drivers/gpu/drm/radeon/nislands_smc.h uint32_t ss[256]; uint32_t 172 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) uint32_t 173 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) uint32_t 174 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) uint32_t 175 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a) uint32_t 176 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) uint32_t 177 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) uint32_t 178 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) uint32_t 179 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) uint32_t 180 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) uint32_t 181 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) uint32_t 182 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) uint32_t 183 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121) uint32_t 184 drivers/gpu/drm/radeon/ppsmc.h #define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124) uint32_t 662 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 684 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 693 drivers/gpu/drm/radeon/r100.c uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) uint32_t 714 drivers/gpu/drm/radeon/r100.c uint32_t tmp = 0; uint32_t 757 drivers/gpu/drm/radeon/r100.c static uint32_t r100_irq_ack(struct radeon_device *rdev) uint32_t 759 drivers/gpu/drm/radeon/r100.c uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); uint32_t 760 drivers/gpu/drm/radeon/r100.c uint32_t irq_mask = RADEON_SW_INT_TEST | uint32_t 772 drivers/gpu/drm/radeon/r100.c uint32_t status, msi_rearm; uint32_t 898 drivers/gpu/drm/radeon/r100.c uint32_t cur_pages; uint32_t 899 drivers/gpu/drm/radeon/r100.c uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; uint32_t 900 drivers/gpu/drm/radeon/r100.c uint32_t pitch; uint32_t 901 drivers/gpu/drm/radeon/r100.c uint32_t stride_pixels; uint32_t 1120 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 1309 drivers/gpu/drm/radeon/r100.c volatile uint32_t *ib; uint32_t 1431 drivers/gpu/drm/radeon/r100.c uint32_t header, h_idx, reg; uint32_t 1432 drivers/gpu/drm/radeon/r100.c volatile uint32_t *ib; uint32_t 1498 drivers/gpu/drm/radeon/r100.c static int r100_get_vtx_size(uint32_t vtx_fmt) uint32_t 1557 drivers/gpu/drm/radeon/r100.c volatile uint32_t *ib; uint32_t 1558 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 1780 drivers/gpu/drm/radeon/r100.c uint32_t temp = idx_value >> 4; uint32_t 1916 drivers/gpu/drm/radeon/r100.c volatile uint32_t *ib; uint32_t 2472 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 2487 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 2505 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 2533 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 2701 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 2785 drivers/gpu/drm/radeon/r100.c uint32_t tom; uint32_t 2815 drivers/gpu/drm/radeon/r100.c uint32_t temp; uint32_t 2870 drivers/gpu/drm/radeon/r100.c uint32_t save, tmp; uint32_t 2880 drivers/gpu/drm/radeon/r100.c uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) uint32_t 2883 drivers/gpu/drm/radeon/r100.c uint32_t data; uint32_t 2894 drivers/gpu/drm/radeon/r100.c void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) uint32_t 2928 drivers/gpu/drm/radeon/r100.c uint32_t reg, value; uint32_t 2950 drivers/gpu/drm/radeon/r100.c uint32_t rdp, wdp; uint32_t 2977 drivers/gpu/drm/radeon/r100.c uint32_t csq_stat, csq2_stat, tmp; uint32_t 3027 drivers/gpu/drm/radeon/r100.c uint32_t tmp; uint32_t 3094 drivers/gpu/drm/radeon/r100.c uint32_t tiling_flags, uint32_t pitch, uint32_t 3095 drivers/gpu/drm/radeon/r100.c uint32_t offset, uint32_t obj_size) uint32_t 3153 drivers/gpu/drm/radeon/r100.c uint32_t temp, data, mem_trcd, mem_trp, mem_tras; uint32_t 3216 drivers/gpu/drm/radeon/r100.c uint32_t pixel_bytes1 = 0; uint32_t 3217 drivers/gpu/drm/radeon/r100.c uint32_t pixel_bytes2 = 0; uint32_t 3247 drivers/gpu/drm/radeon/r100.c uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); uint32_t 3653 drivers/gpu/drm/radeon/r100.c uint32_t scratch; uint32_t 3654 drivers/gpu/drm/radeon/r100.c uint32_t tmp = 0; uint32_t 3709 drivers/gpu/drm/radeon/r100.c uint32_t scratch; uint32_t 3710 drivers/gpu/drm/radeon/r100.c uint32_t tmp = 0; uint32_t 4114 drivers/gpu/drm/radeon/r100.c uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) uint32_t 4117 drivers/gpu/drm/radeon/r100.c uint32_t ret; uint32_t 4126 drivers/gpu/drm/radeon/r100.c void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) uint32_t 39 drivers/gpu/drm/radeon/r200.c static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) uint32_t 91 drivers/gpu/drm/radeon/r200.c uint32_t size; uint32_t 92 drivers/gpu/drm/radeon/r200.c uint32_t cur_size; uint32_t 132 drivers/gpu/drm/radeon/r200.c static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) uint32_t 151 drivers/gpu/drm/radeon/r200.c volatile uint32_t *ib; uint32_t 152 drivers/gpu/drm/radeon/r200.c uint32_t tmp; uint32_t 372 drivers/gpu/drm/radeon/r200.c uint32_t temp = idx_value >> 4; uint32_t 61 drivers/gpu/drm/radeon/r300.c uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) uint32_t 64 drivers/gpu/drm/radeon/r300.c uint32_t r; uint32_t 73 drivers/gpu/drm/radeon/r300.c void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) uint32_t 90 drivers/gpu/drm/radeon/r300.c uint32_t tmp; uint32_t 107 drivers/gpu/drm/radeon/r300.c uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) uint32_t 155 drivers/gpu/drm/radeon/r300.c uint32_t table_addr; uint32_t 156 drivers/gpu/drm/radeon/r300.c uint32_t tmp; uint32_t 351 drivers/gpu/drm/radeon/r300.c uint32_t tmp; uint32_t 366 drivers/gpu/drm/radeon/r300.c uint32_t gb_tile_config, tmp; uint32_t 504 drivers/gpu/drm/radeon/r300.c uint32_t link_width_cntl, mask; uint32_t 598 drivers/gpu/drm/radeon/r300.c uint32_t tmp; uint32_t 637 drivers/gpu/drm/radeon/r300.c volatile uint32_t *ib; uint32_t 638 drivers/gpu/drm/radeon/r300.c uint32_t tmp, tile_flags = 0; uint32_t 1181 drivers/gpu/drm/radeon/r300.c volatile uint32_t *ib; uint32_t 488 drivers/gpu/drm/radeon/r420.c uint32_t tmp; uint32_t 39 drivers/gpu/drm/radeon/r520.c uint32_t tmp; uint32_t 95 drivers/gpu/drm/radeon/r520.c uint32_t tmp; uint32_t 1278 drivers/gpu/drm/radeon/r600.c uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) uint32_t 1281 drivers/gpu/drm/radeon/r600.c uint32_t r; uint32_t 1291 drivers/gpu/drm/radeon/r600.c void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) uint32_t 1438 drivers/gpu/drm/radeon/r600.c uint32_t h_addr, l_addr; uint32_t 1985 drivers/gpu/drm/radeon/r600.c int r600_count_pipe_bits(uint32_t val) uint32_t 2689 drivers/gpu/drm/radeon/r600.c uint32_t cp_me; uint32_t 2824 drivers/gpu/drm/radeon/r600.c uint32_t scratch; uint32_t 2825 drivers/gpu/drm/radeon/r600.c uint32_t tmp = 0; uint32_t 3028 drivers/gpu/drm/radeon/r600.c uint32_t tiling_flags, uint32_t pitch, uint32_t 3029 drivers/gpu/drm/radeon/r600.c uint32_t offset, uint32_t obj_size) uint32_t 3191 drivers/gpu/drm/radeon/r600.c uint32_t temp; uint32_t 3402 drivers/gpu/drm/radeon/r600.c uint32_t scratch; uint32_t 3403 drivers/gpu/drm/radeon/r600.c uint32_t tmp = 0; uint32_t 476 drivers/gpu/drm/radeon/r600_cs.c uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]); uint32_t 479 drivers/gpu/drm/radeon/r600_cs.c uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1); uint32_t 494 drivers/gpu/drm/radeon/r600_cs.c uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]); uint32_t 497 drivers/gpu/drm/radeon/r600_cs.c uint32_t bytes = (block_max + 1) * 128; uint32_t 796 drivers/gpu/drm/radeon/r600_cs.c static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END, uint32_t 798 drivers/gpu/drm/radeon/r600_cs.c static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS, uint32_t 826 drivers/gpu/drm/radeon/r600_cs.c uint32_t *vline_start_end, uint32_t 827 drivers/gpu/drm/radeon/r600_cs.c uint32_t *vline_status) uint32_t 834 drivers/gpu/drm/radeon/r600_cs.c uint32_t header, h_idx, reg, wait_reg_mem_info; uint32_t 835 drivers/gpu/drm/radeon/r600_cs.c volatile uint32_t *ib; uint32_t 51 drivers/gpu/drm/radeon/r600_dma.c uint32_t r600_dma_get_rptr(struct radeon_device *rdev, uint32_t 72 drivers/gpu/drm/radeon/r600_dma.c uint32_t r600_dma_get_wptr(struct radeon_device *rdev, uint32_t 62 drivers/gpu/drm/radeon/r600_hdmi.c uint32_t value; uint32_t 184 drivers/gpu/drm/radeon/r600_hdmi.c uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : uint32_t 250 drivers/gpu/drm/radeon/r600_hdmi.c uint32_t offset = dig->afmt->offset; uint32_t 268 drivers/gpu/drm/radeon/r600_hdmi.c uint32_t offset = dig->afmt->offset; uint32_t 301 drivers/gpu/drm/radeon/r600_hdmi.c uint32_t offset = dig->afmt->offset; uint32_t 420 drivers/gpu/drm/radeon/r600_hdmi.c uint32_t offset; uint32_t 421 drivers/gpu/drm/radeon/r600_hdmi.c uint32_t value; uint32_t 270 drivers/gpu/drm/radeon/radeon.h uint32_t default_mclk; uint32_t 271 drivers/gpu/drm/radeon/radeon.h uint32_t default_sclk; uint32_t 272 drivers/gpu/drm/radeon/radeon.h uint32_t default_dispclk; uint32_t 273 drivers/gpu/drm/radeon/radeon.h uint32_t current_dispclk; uint32_t 274 drivers/gpu/drm/radeon/radeon.h uint32_t dp_extclk; uint32_t 275 drivers/gpu/drm/radeon/radeon.h uint32_t max_pixel_clock; uint32_t 276 drivers/gpu/drm/radeon/radeon.h uint32_t vco_freq; uint32_t 361 drivers/gpu/drm/radeon/radeon.h uint32_t scratch_reg; uint32_t 363 drivers/gpu/drm/radeon/radeon.h volatile uint32_t *cpu_addr; uint32_t 466 drivers/gpu/drm/radeon/radeon.h uint32_t tiling_flags; uint32_t 473 drivers/gpu/drm/radeon/radeon.h uint32_t flags; uint32_t 551 drivers/gpu/drm/radeon/radeon.h uint32_t domain; uint32_t 552 drivers/gpu/drm/radeon/radeon.h uint32_t align; uint32_t 587 drivers/gpu/drm/radeon/radeon.h uint32_t handle, uint64_t *offset_p); uint32_t 670 drivers/gpu/drm/radeon/radeon.h dma_addr_t *dma_addr, uint32_t flags); uint32_t 706 drivers/gpu/drm/radeon/radeon.h uint32_t reg_base; uint32_t 708 drivers/gpu/drm/radeon/radeon.h uint32_t reg[32]; uint32_t 711 drivers/gpu/drm/radeon/radeon.h int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); uint32_t 712 drivers/gpu/drm/radeon/radeon.h void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); uint32_t 823 drivers/gpu/drm/radeon/radeon.h uint32_t length_dw; uint32_t 825 drivers/gpu/drm/radeon/radeon.h uint32_t *ptr; uint32_t 835 drivers/gpu/drm/radeon/radeon.h volatile uint32_t *ring; uint32_t 848 drivers/gpu/drm/radeon/radeon.h uint32_t align_mask; uint32_t 849 drivers/gpu/drm/radeon/radeon.h uint32_t ptr_mask; uint32_t 948 drivers/gpu/drm/radeon/radeon.h uint32_t max_pfn; uint32_t 956 drivers/gpu/drm/radeon/radeon.h uint32_t saved_table_addr[RADEON_NUM_VM]; uint32_t 971 drivers/gpu/drm/radeon/radeon.h volatile uint32_t *ring; uint32_t 975 drivers/gpu/drm/radeon/radeon.h uint32_t ptr_mask; uint32_t 989 drivers/gpu/drm/radeon/radeon.h volatile uint32_t *sr_ptr; uint32_t 995 drivers/gpu/drm/radeon/radeon.h volatile uint32_t *cs_ptr; uint32_t 1001 drivers/gpu/drm/radeon/radeon.h volatile uint32_t *cp_table_ptr; uint32_t 1031 drivers/gpu/drm/radeon/radeon.h uint32_t **data); uint32_t 1033 drivers/gpu/drm/radeon/radeon.h unsigned size, uint32_t *data); uint32_t 1052 drivers/gpu/drm/radeon/radeon.h uint32_t length_dw; uint32_t 1053 drivers/gpu/drm/radeon/radeon.h uint32_t *kdata; uint32_t 1129 drivers/gpu/drm/radeon/radeon.h volatile uint32_t *wb; uint32_t 1685 drivers/gpu/drm/radeon/radeon.h uint32_t handle, struct radeon_fence **fence); uint32_t 1687 drivers/gpu/drm/radeon/radeon.h uint32_t handle, struct radeon_fence **fence); uint32_t 1689 drivers/gpu/drm/radeon/radeon.h uint32_t allowed_domains); uint32_t 1720 drivers/gpu/drm/radeon/radeon.h uint32_t keyselect; uint32_t 1728 drivers/gpu/drm/radeon/radeon.h uint32_t handle, struct radeon_fence **fence); uint32_t 1730 drivers/gpu/drm/radeon/radeon.h uint32_t handle, struct radeon_fence **fence); uint32_t 1863 drivers/gpu/drm/radeon/radeon.h uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); uint32_t 1878 drivers/gpu/drm/radeon/radeon.h uint32_t incr, uint32_t flags); uint32_t 1883 drivers/gpu/drm/radeon/radeon.h uint32_t incr, uint32_t flags); uint32_t 1935 drivers/gpu/drm/radeon/radeon.h uint32_t tiling_flags, uint32_t pitch, uint32_t 1936 drivers/gpu/drm/radeon/radeon.h uint32_t offset, uint32_t obj_size); uint32_t 1953 drivers/gpu/drm/radeon/radeon.h uint32_t (*get_engine_clock)(struct radeon_device *rdev); uint32_t 1954 drivers/gpu/drm/radeon/radeon.h void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); uint32_t 1955 drivers/gpu/drm/radeon/radeon.h uint32_t (*get_memory_clock)(struct radeon_device *rdev); uint32_t 1956 drivers/gpu/drm/radeon/radeon.h void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); uint32_t 2155 drivers/gpu/drm/radeon/radeon.h uint32_t tile_mode_array[32]; uint32_t 2156 drivers/gpu/drm/radeon/radeon.h uint32_t active_cus; uint32_t 2186 drivers/gpu/drm/radeon/radeon.h uint32_t tile_mode_array[32]; uint32_t 2187 drivers/gpu/drm/radeon/radeon.h uint32_t macrotile_mode_array[16]; uint32_t 2188 drivers/gpu/drm/radeon/radeon.h uint32_t active_cus; uint32_t 2247 drivers/gpu/drm/radeon/radeon.h volatile uint32_t *ptr; uint32_t 2305 drivers/gpu/drm/radeon/radeon.h typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); uint32_t 2306 drivers/gpu/drm/radeon/radeon.h typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); uint32_t 2359 drivers/gpu/drm/radeon/radeon.h uint32_t pcie_reg_mask; uint32_t 2385 drivers/gpu/drm/radeon/radeon.h uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; uint32_t 2458 drivers/gpu/drm/radeon/radeon.h uint32_t flags); uint32_t 2464 drivers/gpu/drm/radeon/radeon.h uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); uint32_t 2465 drivers/gpu/drm/radeon/radeon.h void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 2466 drivers/gpu/drm/radeon/radeon.h static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, uint32_t 2475 drivers/gpu/drm/radeon/radeon.h static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, uint32_t 2544 drivers/gpu/drm/radeon/radeon.h uint32_t tmp_ = RREG32(reg); \ uint32_t 2553 drivers/gpu/drm/radeon/radeon.h uint32_t tmp_ = RREG32_PLL(reg); \ uint32_t 2560 drivers/gpu/drm/radeon/radeon.h uint32_t tmp_ = RREG32_SMC(reg); \ uint32_t 2580 drivers/gpu/drm/radeon/radeon.h uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t 2581 drivers/gpu/drm/radeon/radeon.h void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 2685 drivers/gpu/drm/radeon/radeon.h static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) uint32_t 2814 drivers/gpu/drm/radeon/radeon.h uint32_t flags); uint32_t 2865 drivers/gpu/drm/radeon/radeon.h uint32_t flags); uint32_t 2913 drivers/gpu/drm/radeon/radeon.h extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); uint32_t 2951 drivers/gpu/drm/radeon/radeon.h uint32_t *vline_start_end, uint32_t 2952 drivers/gpu/drm/radeon/radeon.h uint32_t *vline_status); uint32_t 137 drivers/gpu/drm/radeon/radeon_agp.c uint32_t agp_status; uint32_t 54 drivers/gpu/drm/radeon/radeon_asic.c static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) uint32_t 71 drivers/gpu/drm/radeon/radeon_asic.c static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) uint32_t 34 drivers/gpu/drm/radeon/radeon_asic.h uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); uint32_t 35 drivers/gpu/drm/radeon/radeon_asic.h void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); uint32_t 36 drivers/gpu/drm/radeon/radeon_asic.h uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); uint32_t 39 drivers/gpu/drm/radeon/radeon_asic.h uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); uint32_t 40 drivers/gpu/drm/radeon/radeon_asic.h void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); uint32_t 41 drivers/gpu/drm/radeon/radeon_asic.h uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); uint32_t 42 drivers/gpu/drm/radeon/radeon_asic.h void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); uint32_t 70 drivers/gpu/drm/radeon/radeon_asic.h uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags); uint32_t 83 drivers/gpu/drm/radeon/radeon_asic.h void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 84 drivers/gpu/drm/radeon/radeon_asic.h uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t 91 drivers/gpu/drm/radeon/radeon_asic.h uint32_t tiling_flags, uint32_t pitch, uint32_t 92 drivers/gpu/drm/radeon/radeon_asic.h uint32_t offset, uint32_t obj_size); uint32_t 176 drivers/gpu/drm/radeon/radeon_asic.h extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags); uint32_t 213 drivers/gpu/drm/radeon/radeon_asic.h uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags); uint32_t 216 drivers/gpu/drm/radeon/radeon_asic.h uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t 217 drivers/gpu/drm/radeon/radeon_asic.h void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 238 drivers/gpu/drm/radeon/radeon_asic.h uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags); uint32_t 241 drivers/gpu/drm/radeon/radeon_asic.h uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t 242 drivers/gpu/drm/radeon/radeon_asic.h void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 266 drivers/gpu/drm/radeon/radeon_asic.h uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t 267 drivers/gpu/drm/radeon/radeon_asic.h void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 285 drivers/gpu/drm/radeon/radeon_asic.h uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t 286 drivers/gpu/drm/radeon/radeon_asic.h void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 318 drivers/gpu/drm/radeon/radeon_asic.h uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t 319 drivers/gpu/drm/radeon/radeon_asic.h void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 339 drivers/gpu/drm/radeon/radeon_asic.h uint32_t tiling_flags, uint32_t pitch, uint32_t 340 drivers/gpu/drm/radeon/radeon_asic.h uint32_t offset, uint32_t obj_size); uint32_t 365 drivers/gpu/drm/radeon/radeon_asic.h extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t 366 drivers/gpu/drm/radeon/radeon_asic.h extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 376 drivers/gpu/drm/radeon/radeon_asic.h int r600_count_pipe_bits(uint32_t val); uint32_t 403 drivers/gpu/drm/radeon/radeon_asic.h void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); uint32_t 416 drivers/gpu/drm/radeon/radeon_asic.h uint32_t r600_dma_get_rptr(struct radeon_device *rdev, uint32_t 418 drivers/gpu/drm/radeon/radeon_asic.h uint32_t r600_dma_get_wptr(struct radeon_device *rdev, uint32_t 616 drivers/gpu/drm/radeon/radeon_asic.h uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); uint32_t 632 drivers/gpu/drm/radeon/radeon_asic.h uint32_t incr, uint32_t flags); uint32_t 637 drivers/gpu/drm/radeon/radeon_asic.h uint32_t incr, uint32_t flags); uint32_t 649 drivers/gpu/drm/radeon/radeon_asic.h uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, uint32_t 651 drivers/gpu/drm/radeon/radeon_asic.h uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, uint32_t 738 drivers/gpu/drm/radeon/radeon_asic.h uint32_t incr, uint32_t flags); uint32_t 743 drivers/gpu/drm/radeon/radeon_asic.h uint32_t incr, uint32_t flags); uint32_t 785 drivers/gpu/drm/radeon/radeon_asic.h uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); uint32_t 786 drivers/gpu/drm/radeon/radeon_asic.h void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t 840 drivers/gpu/drm/radeon/radeon_asic.h uint32_t incr, uint32_t flags); uint32_t 845 drivers/gpu/drm/radeon/radeon_asic.h uint32_t incr, uint32_t flags); uint32_t 928 drivers/gpu/drm/radeon/radeon_asic.h uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, uint32_t 930 drivers/gpu/drm/radeon/radeon_asic.h uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, uint32_t 970 drivers/gpu/drm/radeon/radeon_asic.h uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, uint32_t 972 drivers/gpu/drm/radeon/radeon_asic.h uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, uint32_t 976 drivers/gpu/drm/radeon/radeon_asic.h int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data); uint32_t 38 drivers/gpu/drm/radeon/radeon_atombios.c radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t 39 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t supported_device, u16 caps); uint32_t 43 drivers/gpu/drm/radeon/radeon_atombios.c radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t 44 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t supported_device); uint32_t 287 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t supported_device, uint32_t 609 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t slot_config, ct; uint32_t 2859 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2873 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2888 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2908 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2927 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2938 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 2979 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3012 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3015 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) uint32_t 3020 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3024 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) uint32_t 3029 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3034 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t eng_clock) uint32_t 3041 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3045 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t mem_clock) uint32_t 3055 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3074 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3085 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3097 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3141 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3162 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3171 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3207 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3334 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3360 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 3368 drivers/gpu/drm/radeon/radeon_atombios.c atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); uint32_t 4079 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t bios_2_scratch, bios_6_scratch; uint32_t 4111 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t scratch_reg; uint32_t 4125 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t scratch_reg; uint32_t 4141 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t bios_6_scratch; uint32_t 4173 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; uint32_t 4355 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t bios_3_scratch; uint32_t 4410 drivers/gpu/drm/radeon/radeon_atombios.c uint32_t bios_2_scratch; uint32_t 296 drivers/gpu/drm/radeon/radeon_bios.c uint32_t viph_control; uint32_t 297 drivers/gpu/drm/radeon/radeon_bios.c uint32_t bus_cntl; uint32_t 298 drivers/gpu/drm/radeon/radeon_bios.c uint32_t d1vga_control; uint32_t 299 drivers/gpu/drm/radeon/radeon_bios.c uint32_t d2vga_control; uint32_t 300 drivers/gpu/drm/radeon/radeon_bios.c uint32_t vga_render_control; uint32_t 301 drivers/gpu/drm/radeon/radeon_bios.c uint32_t rom_cntl; uint32_t 302 drivers/gpu/drm/radeon/radeon_bios.c uint32_t cg_spll_func_cntl = 0; uint32_t 303 drivers/gpu/drm/radeon/radeon_bios.c uint32_t cg_spll_status; uint32_t 365 drivers/gpu/drm/radeon/radeon_bios.c uint32_t viph_control; uint32_t 366 drivers/gpu/drm/radeon/radeon_bios.c uint32_t bus_cntl; uint32_t 367 drivers/gpu/drm/radeon/radeon_bios.c uint32_t d1vga_control; uint32_t 368 drivers/gpu/drm/radeon/radeon_bios.c uint32_t d2vga_control; uint32_t 369 drivers/gpu/drm/radeon/radeon_bios.c uint32_t vga_render_control; uint32_t 370 drivers/gpu/drm/radeon/radeon_bios.c uint32_t rom_cntl; uint32_t 371 drivers/gpu/drm/radeon/radeon_bios.c uint32_t general_pwrmgt; uint32_t 372 drivers/gpu/drm/radeon/radeon_bios.c uint32_t low_vid_lower_gpio_cntl; uint32_t 373 drivers/gpu/drm/radeon/radeon_bios.c uint32_t medium_vid_lower_gpio_cntl; uint32_t 374 drivers/gpu/drm/radeon/radeon_bios.c uint32_t high_vid_lower_gpio_cntl; uint32_t 375 drivers/gpu/drm/radeon/radeon_bios.c uint32_t ctxsw_vid_lower_gpio_cntl; uint32_t 376 drivers/gpu/drm/radeon/radeon_bios.c uint32_t lower_gpio_enable; uint32_t 442 drivers/gpu/drm/radeon/radeon_bios.c uint32_t seprom_cntl1; uint32_t 443 drivers/gpu/drm/radeon/radeon_bios.c uint32_t viph_control; uint32_t 444 drivers/gpu/drm/radeon/radeon_bios.c uint32_t bus_cntl; uint32_t 445 drivers/gpu/drm/radeon/radeon_bios.c uint32_t d1vga_control; uint32_t 446 drivers/gpu/drm/radeon/radeon_bios.c uint32_t d2vga_control; uint32_t 447 drivers/gpu/drm/radeon/radeon_bios.c uint32_t vga_render_control; uint32_t 448 drivers/gpu/drm/radeon/radeon_bios.c uint32_t gpiopad_a; uint32_t 449 drivers/gpu/drm/radeon/radeon_bios.c uint32_t gpiopad_en; uint32_t 450 drivers/gpu/drm/radeon/radeon_bios.c uint32_t gpiopad_mask; uint32_t 503 drivers/gpu/drm/radeon/radeon_bios.c uint32_t seprom_cntl1; uint32_t 504 drivers/gpu/drm/radeon/radeon_bios.c uint32_t viph_control; uint32_t 505 drivers/gpu/drm/radeon/radeon_bios.c uint32_t bus_cntl; uint32_t 506 drivers/gpu/drm/radeon/radeon_bios.c uint32_t crtc_gen_cntl; uint32_t 507 drivers/gpu/drm/radeon/radeon_bios.c uint32_t crtc2_gen_cntl; uint32_t 508 drivers/gpu/drm/radeon/radeon_bios.c uint32_t crtc_ext_cntl; uint32_t 509 drivers/gpu/drm/radeon/radeon_bios.c uint32_t fp2_gen_cntl; uint32_t 39 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev) uint32_t 42 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t fb_div, ref_div, post_div, sclk; uint32_t 69 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) uint32_t 72 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t fb_div, ref_div, post_div, mclk; uint32_t 350 drivers/gpu/drm/radeon/radeon_clocks.c static uint32_t calc_eng_mem_clock(struct radeon_device *rdev, uint32_t 351 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t req_clock, uint32_t 390 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t eng_clock) uint32_t 392 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t tmp; uint32_t 477 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t tmp; uint32_t 44 drivers/gpu/drm/radeon/radeon_combios.c radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t 45 drivers/gpu/drm/radeon/radeon_combios.c uint32_t supported_device); uint32_t 833 drivers/gpu/drm/radeon/radeon_combios.c static const uint32_t default_primarydac_adj[CHIP_LAST] = { uint32_t 980 drivers/gpu/drm/radeon/radeon_combios.c static const uint32_t default_tvdac_adj[CHIP_LAST] = { uint32_t 1107 drivers/gpu/drm/radeon/radeon_combios.c uint32_t fp_vert_stretch, fp_horz_stretch; uint32_t 1108 drivers/gpu/drm/radeon/radeon_combios.c uint32_t ppll_div_sel, ppll_val; uint32_t 1109 drivers/gpu/drm/radeon/radeon_combios.c uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); uint32_t 1178 drivers/gpu/drm/radeon/radeon_combios.c uint32_t panel_setup; uint32_t 2274 drivers/gpu/drm/radeon/radeon_combios.c uint32_t ext_tmds_info; uint32_t 2309 drivers/gpu/drm/radeon/radeon_combios.c uint32_t conn_info, entry, devices; uint32_t 2602 drivers/gpu/drm/radeon/radeon_combios.c uint32_t tv_info = uint32_t 2891 drivers/gpu/drm/radeon/radeon_combios.c uint32_t index, id; uint32_t 2892 drivers/gpu/drm/radeon/radeon_combios.c uint32_t reg, val, and_mask, or_mask; uint32_t 3022 drivers/gpu/drm/radeon/radeon_combios.c uint32_t addr = (RBIOS16(offset) & 0x1fff); uint32_t 3023 drivers/gpu/drm/radeon/radeon_combios.c uint32_t val, and_mask, or_mask; uint32_t 3024 drivers/gpu/drm/radeon/radeon_combios.c uint32_t tmp; uint32_t 3102 drivers/gpu/drm/radeon/radeon_combios.c uint32_t val, shift, tmp; uint32_t 3103 drivers/gpu/drm/radeon/radeon_combios.c uint32_t and_mask, or_mask; uint32_t 3157 drivers/gpu/drm/radeon/radeon_combios.c uint32_t mclk_cntl = uint32_t 3188 drivers/gpu/drm/radeon/radeon_combios.c uint32_t tmp; uint32_t 3196 drivers/gpu/drm/radeon/radeon_combios.c uint32_t channel_complete_mask; uint32_t 3212 drivers/gpu/drm/radeon/radeon_combios.c uint32_t or_mask = RBIOS16(offset); uint32_t 3231 drivers/gpu/drm/radeon/radeon_combios.c static uint32_t combios_detect_ram(struct drm_device *dev, int ram, uint32_t 3235 drivers/gpu/drm/radeon/radeon_combios.c uint32_t mem_cntl; uint32_t 3236 drivers/gpu/drm/radeon/radeon_combios.c uint32_t mem_size; uint32_t 3237 drivers/gpu/drm/radeon/radeon_combios.c uint32_t addr = 0; uint32_t 3268 drivers/gpu/drm/radeon/radeon_combios.c uint32_t mem_size = 0; uint32_t 3269 drivers/gpu/drm/radeon/radeon_combios.c uint32_t mem_cntl = 0; uint32_t 3420 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; uint32_t 3445 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_6_scratch; uint32_t 3467 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); uint32_t 3468 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); uint32_t 3566 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); uint32_t 3601 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); uint32_t 1858 drivers/gpu/drm/radeon/radeon_connectors.c uint32_t connector_id, uint32_t 1859 drivers/gpu/drm/radeon/radeon_connectors.c uint32_t supported_device, uint32_t 1862 drivers/gpu/drm/radeon/radeon_connectors.c uint32_t igp_lane_info, uint32_t 1873 drivers/gpu/drm/radeon/radeon_connectors.c uint32_t subpixel_order = SubPixelNone; uint32_t 2337 drivers/gpu/drm/radeon/radeon_connectors.c uint32_t connector_id, uint32_t 2338 drivers/gpu/drm/radeon/radeon_connectors.c uint32_t supported_device, uint32_t 2347 drivers/gpu/drm/radeon/radeon_connectors.c uint32_t subpixel_order = SubPixelNone; uint32_t 148 drivers/gpu/drm/radeon/radeon_cs.c uint32_t domain = r->write_domain ? uint32_t 164 drivers/gpu/drm/radeon/radeon_cs.c uint32_t domain = p->relocs[i].preferred_domains; uint32_t 310 drivers/gpu/drm/radeon/radeon_cs.c uint32_t __user *cdata; uint32_t 351 drivers/gpu/drm/radeon/radeon_cs.c p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); uint32_t 352 drivers/gpu/drm/radeon/radeon_cs.c size *= sizeof(uint32_t); uint32_t 738 drivers/gpu/drm/radeon/radeon_cs.c uint32_t header; uint32_t 820 drivers/gpu/drm/radeon/radeon_cs.c volatile uint32_t *ib; uint32_t 36 drivers/gpu/drm/radeon/radeon_cursor.c uint32_t cur_lock; uint32_t 278 drivers/gpu/drm/radeon/radeon_cursor.c uint32_t handle, uint32_t 279 drivers/gpu/drm/radeon/radeon_cursor.c uint32_t width, uint32_t 280 drivers/gpu/drm/radeon/radeon_cursor.c uint32_t height, uint32_t 292 drivers/gpu/drm/radeon/radeon_device.c int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) uint32_t 314 drivers/gpu/drm/radeon/radeon_device.c void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) uint32_t 351 drivers/gpu/drm/radeon/radeon_device.c DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); uint32_t 657 drivers/gpu/drm/radeon/radeon_device.c uint32_t reg; uint32_t 836 drivers/gpu/drm/radeon/radeon_device.c static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) uint32_t 839 drivers/gpu/drm/radeon/radeon_device.c uint32_t r; uint32_t 854 drivers/gpu/drm/radeon/radeon_device.c static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) uint32_t 870 drivers/gpu/drm/radeon/radeon_device.c static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) uint32_t 873 drivers/gpu/drm/radeon/radeon_device.c uint32_t r; uint32_t 888 drivers/gpu/drm/radeon/radeon_device.c static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) uint32_t 904 drivers/gpu/drm/radeon/radeon_device.c static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) uint32_t 920 drivers/gpu/drm/radeon/radeon_device.c static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) uint32_t 923 drivers/gpu/drm/radeon/radeon_device.c uint32_t r; uint32_t 938 drivers/gpu/drm/radeon/radeon_device.c static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) uint32_t 954 drivers/gpu/drm/radeon/radeon_device.c static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) uint32_t 957 drivers/gpu/drm/radeon/radeon_device.c uint32_t r; uint32_t 1290 drivers/gpu/drm/radeon/radeon_device.c uint32_t flags) uint32_t 1783 drivers/gpu/drm/radeon/radeon_device.c uint32_t *ring_data[RADEON_NUM_RINGS]; uint32_t 199 drivers/gpu/drm/radeon/radeon_display.c uint32_t dac2_cntl; uint32_t 203 drivers/gpu/drm/radeon/radeon_display.c dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; uint32_t 239 drivers/gpu/drm/radeon/radeon_display.c u16 *blue, uint32_t size, uint32_t 483 drivers/gpu/drm/radeon/radeon_display.c uint32_t page_flip_flags, uint32_t 484 drivers/gpu/drm/radeon/radeon_display.c uint32_t target, uint32_t 493 drivers/gpu/drm/radeon/radeon_display.c uint32_t tiling_flags, pitch_pixels; uint32_t 578 drivers/gpu/drm/radeon/radeon_display.c work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + uint32_t 774 drivers/gpu/drm/radeon/radeon_display.c uint32_t devices; uint32_t 1098 drivers/gpu/drm/radeon/radeon_display.c static inline uint32_t radeon_div(uint64_t n, uint32_t d) uint32_t 1110 drivers/gpu/drm/radeon/radeon_display.c uint32_t *dot_clock_p, uint32_t 1111 drivers/gpu/drm/radeon/radeon_display.c uint32_t *fb_div_p, uint32_t 1112 drivers/gpu/drm/radeon/radeon_display.c uint32_t *frac_fb_div_p, uint32_t 1113 drivers/gpu/drm/radeon/radeon_display.c uint32_t *ref_div_p, uint32_t 1114 drivers/gpu/drm/radeon/radeon_display.c uint32_t *post_div_p) uint32_t 1116 drivers/gpu/drm/radeon/radeon_display.c uint32_t min_ref_div = pll->min_ref_div; uint32_t 1117 drivers/gpu/drm/radeon/radeon_display.c uint32_t max_ref_div = pll->max_ref_div; uint32_t 1118 drivers/gpu/drm/radeon/radeon_display.c uint32_t min_post_div = pll->min_post_div; uint32_t 1119 drivers/gpu/drm/radeon/radeon_display.c uint32_t max_post_div = pll->max_post_div; uint32_t 1120 drivers/gpu/drm/radeon/radeon_display.c uint32_t min_fractional_feed_div = 0; uint32_t 1121 drivers/gpu/drm/radeon/radeon_display.c uint32_t max_fractional_feed_div = 0; uint32_t 1122 drivers/gpu/drm/radeon/radeon_display.c uint32_t best_vco = pll->best_vco; uint32_t 1123 drivers/gpu/drm/radeon/radeon_display.c uint32_t best_post_div = 1; uint32_t 1124 drivers/gpu/drm/radeon/radeon_display.c uint32_t best_ref_div = 1; uint32_t 1125 drivers/gpu/drm/radeon/radeon_display.c uint32_t best_feedback_div = 1; uint32_t 1126 drivers/gpu/drm/radeon/radeon_display.c uint32_t best_frac_feedback_div = 0; uint32_t 1127 drivers/gpu/drm/radeon/radeon_display.c uint32_t best_freq = -1; uint32_t 1128 drivers/gpu/drm/radeon/radeon_display.c uint32_t best_error = 0xffffffff; uint32_t 1129 drivers/gpu/drm/radeon/radeon_display.c uint32_t best_vco_diff = 1; uint32_t 1130 drivers/gpu/drm/radeon/radeon_display.c uint32_t post_div; uint32_t 1151 drivers/gpu/drm/radeon/radeon_display.c uint32_t mid = (min_ref_div + max_ref_div) / 2; uint32_t 1152 drivers/gpu/drm/radeon/radeon_display.c uint32_t pll_in = pll->reference_freq / mid; uint32_t 1171 drivers/gpu/drm/radeon/radeon_display.c uint32_t ref_div; uint32_t 1190 drivers/gpu/drm/radeon/radeon_display.c uint32_t feedback_div, current_freq = 0, error, vco_diff; uint32_t 1191 drivers/gpu/drm/radeon/radeon_display.c uint32_t pll_in = pll->reference_freq / ref_div; uint32_t 1192 drivers/gpu/drm/radeon/radeon_display.c uint32_t min_feed_div = pll->min_feedback_div; uint32_t 1193 drivers/gpu/drm/radeon/radeon_display.c uint32_t max_feed_div = pll->max_feedback_div + 1; uint32_t 1199 drivers/gpu/drm/radeon/radeon_display.c uint32_t vco; uint32_t 1200 drivers/gpu/drm/radeon/radeon_display.c uint32_t min_frac_feed_div = min_fractional_feed_div; uint32_t 1201 drivers/gpu/drm/radeon/radeon_display.c uint32_t max_frac_feed_div = max_fractional_feed_div + 1; uint32_t 1202 drivers/gpu/drm/radeon/radeon_display.c uint32_t frac_feedback_div; uint32_t 1503 drivers/gpu/drm/radeon/radeon_display.c static uint32_t eg_offsets[] = { uint32_t 62 drivers/gpu/drm/radeon/radeon_dp_auxch.c uint32_t tmp, ack = 0; uint32_t 34 drivers/gpu/drm/radeon/radeon_dp_mst.c uint32_t reg; uint32_t 36 drivers/gpu/drm/radeon/radeon_dp_mst.c uint32_t temp; uint32_t 54 drivers/gpu/drm/radeon/radeon_dp_mst.c uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); uint32_t 169 drivers/gpu/drm/radeon/radeon_dp_mst.c uint32_t val, temp; uint32_t 170 drivers/gpu/drm/radeon/radeon_dp_mst.c uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); uint32_t 172 drivers/gpu/drm/radeon/radeon_dp_mst.c uint32_t x = drm_fixp2int(avg_time_slots_per_mtp); uint32_t 173 drivers/gpu/drm/radeon/radeon_dp_mst.c uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26); uint32_t 147 drivers/gpu/drm/radeon/radeon_drv.c uint32_t handle, uint64_t *offset_p); uint32_t 43 drivers/gpu/drm/radeon/radeon_encoders.c static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) uint32_t 49 drivers/gpu/drm/radeon/radeon_encoders.c uint32_t index_mask = 0; uint32_t 88 drivers/gpu/drm/radeon/radeon_encoders.c uint32_t uint32_t 89 drivers/gpu/drm/radeon/radeon_encoders.c radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac) uint32_t 92 drivers/gpu/drm/radeon/radeon_encoders.c uint32_t ret = 0; uint32_t 291 drivers/gpu/drm/radeon/radeon_gart.c uint32_t flags) uint32_t 97 drivers/gpu/drm/radeon/radeon_gem.c uint32_t rdomain, uint32_t wdomain) uint32_t 100 drivers/gpu/drm/radeon/radeon_gem.c uint32_t domain; uint32_t 261 drivers/gpu/drm/radeon/radeon_gem.c uint32_t handle; uint32_t 296 drivers/gpu/drm/radeon/radeon_gem.c uint32_t handle; uint32_t 412 drivers/gpu/drm/radeon/radeon_gem.c uint32_t handle, uint64_t *offset_p) uint32_t 446 drivers/gpu/drm/radeon/radeon_gem.c uint32_t cur_placement = 0; uint32_t 474 drivers/gpu/drm/radeon/radeon_gem.c uint32_t cur_placement = 0; uint32_t 755 drivers/gpu/drm/radeon/radeon_gem.c uint32_t handle; uint32_t 98 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t temp; uint32_t 168 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t temp; uint32_t 187 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t val; uint32_t 202 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t val; uint32_t 216 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t val; uint32_t 229 drivers/gpu/drm/radeon/radeon_i2c.c uint32_t val; uint32_t 191 drivers/gpu/drm/radeon/radeon_kms.c uint32_t *value) uint32_t 229 drivers/gpu/drm/radeon/radeon_kms.c uint32_t *value, value_tmp, *value_ptr, value_size; uint32_t 234 drivers/gpu/drm/radeon/radeon_kms.c value_ptr = (uint32_t *)((unsigned long)info->value); uint32_t 236 drivers/gpu/drm/radeon/radeon_kms.c value_size = sizeof(uint32_t); uint32_t 256 drivers/gpu/drm/radeon/radeon_kms.c if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { uint32_t 313 drivers/gpu/drm/radeon/radeon_kms.c if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { uint32_t 325 drivers/gpu/drm/radeon/radeon_kms.c if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { uint32_t 433 drivers/gpu/drm/radeon/radeon_kms.c value = (uint32_t*)&value64; uint32_t 461 drivers/gpu/drm/radeon/radeon_kms.c if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { uint32_t 487 drivers/gpu/drm/radeon/radeon_kms.c value_size = sizeof(uint32_t)*32; uint32_t 490 drivers/gpu/drm/radeon/radeon_kms.c value_size = sizeof(uint32_t)*32; uint32_t 499 drivers/gpu/drm/radeon/radeon_kms.c value_size = sizeof(uint32_t)*16; uint32_t 531 drivers/gpu/drm/radeon/radeon_kms.c value = (uint32_t*)&value64; uint32_t 536 drivers/gpu/drm/radeon/radeon_kms.c value = (uint32_t*)&value64; uint32_t 541 drivers/gpu/drm/radeon/radeon_kms.c value = (uint32_t*)&value64; uint32_t 583 drivers/gpu/drm/radeon/radeon_kms.c if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { uint32_t 302 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_ext_cntl = 0; uint32_t 303 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t mask; uint32_t 384 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; uint32_t 385 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_pitch, pitch_pixels; uint32_t 386 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t tiling_flags; uint32_t 388 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t gen_cntl_reg, gen_cntl_val; uint32_t 584 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_h_total_disp; uint32_t 585 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_h_sync_strt_wid; uint32_t 586 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_v_total_disp; uint32_t 587 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_v_sync_strt_wid; uint32_t 651 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc2_gen_cntl; uint32_t 652 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t disp2_merge_cntl; uint32_t 684 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_gen_cntl; uint32_t 685 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_ext_cntl; uint32_t 686 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t disp_merge_cntl; uint32_t 739 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t feedback_div = 0; uint32_t 740 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t frac_fb_div = 0; uint32_t 741 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t reference_div = 0; uint32_t 742 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t post_divider = 0; uint32_t 743 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t freq = 0; uint32_t 747 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t pll_ref_div = 0; uint32_t 748 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t pll_fb_post_div = 0; uint32_t 749 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t htotal_cntl = 0; uint32_t 854 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & uint32_t 871 drivers/gpu/drm/radeon/radeon_legacy_crtc.c | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), uint32_t 918 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t pixclks_cntl; uint32_t 952 drivers/gpu/drm/radeon/radeon_legacy_crtc.c | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), uint32_t 58 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; uint32_t 191 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; uint32_t 523 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); uint32_t 524 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); uint32_t 525 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); uint32_t 592 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; uint32_t 646 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t vclk_ecp_cntl, crtc_ext_cntl; uint32_t 647 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; uint32_t 735 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); uint32_t 789 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; uint32_t 808 drivers/gpu/drm/radeon/radeon_legacy_encoders.c if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { uint32_t 899 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); uint32_t 954 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t fp2_gen_cntl; uint32_t 1043 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; uint32_t 1044 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t tv_master_cntl = 0; uint32_t 1161 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; uint32_t 1162 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; uint32_t 1225 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t dac_cntl; uint32_t 1311 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; uint32_t 1312 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t disp_output_cntl, gpiopad_a, tmp; uint32_t 1382 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t tv_dac_cntl, dac_cntl2; uint32_t 1383 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; uint32_t 1446 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; uint32_t 1447 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; uint32_t 1448 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; uint32_t 1449 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; uint32_t 1450 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; uint32_t 1536 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl; uint32_t 1537 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t gpiopad_a = 0, pixclks_cntl, tmp; uint32_t 1538 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0; uint32_t 1745 drivers/gpu/drm/radeon/radeon_legacy_encoders.c radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) uint32_t 282 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t save_pll_test; uint32_t 302 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint16_t addr, uint32_t value) uint32_t 306 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t tmp; uint32_t 324 drivers/gpu/drm/radeon/radeon_legacy_tv.c static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) uint32_t 328 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t tmp; uint32_t 345 drivers/gpu/drm/radeon/radeon_legacy_tv.c static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) uint32_t 366 drivers/gpu/drm/radeon/radeon_legacy_tv.c static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) uint32_t 393 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t tmp; uint32_t 401 drivers/gpu/drm/radeon/radeon_legacy_tv.c tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); uint32_t 407 drivers/gpu/drm/radeon/radeon_legacy_tv.c tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); uint32_t 536 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t vert_space, flicker_removal, tmp; uint32_t 537 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; uint32_t 538 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t tv_modulator_cntl1, tv_modulator_cntl2; uint32_t 539 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; uint32_t 540 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal; uint32_t 541 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; uint32_t 542 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t m, n, p; uint32_t 831 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, uint32_t 832 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) uint32_t 836 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t tmp; uint32_t 878 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t *htotal_cntl, uint32_t *ppll_ref_div, uint32_t 879 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t *ppll_div_3, uint32_t *pixclks_cntl) uint32_t 898 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, uint32_t 899 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) uint32_t 123 drivers/gpu/drm/radeon/radeon_mode.h uint32_t mask_clk_reg; uint32_t 124 drivers/gpu/drm/radeon/radeon_mode.h uint32_t mask_data_reg; uint32_t 125 drivers/gpu/drm/radeon/radeon_mode.h uint32_t a_clk_reg; uint32_t 126 drivers/gpu/drm/radeon/radeon_mode.h uint32_t a_data_reg; uint32_t 127 drivers/gpu/drm/radeon/radeon_mode.h uint32_t en_clk_reg; uint32_t 128 drivers/gpu/drm/radeon/radeon_mode.h uint32_t en_data_reg; uint32_t 129 drivers/gpu/drm/radeon/radeon_mode.h uint32_t y_clk_reg; uint32_t 130 drivers/gpu/drm/radeon/radeon_mode.h uint32_t y_data_reg; uint32_t 131 drivers/gpu/drm/radeon/radeon_mode.h uint32_t mask_clk_mask; uint32_t 132 drivers/gpu/drm/radeon/radeon_mode.h uint32_t mask_data_mask; uint32_t 133 drivers/gpu/drm/radeon/radeon_mode.h uint32_t a_clk_mask; uint32_t 134 drivers/gpu/drm/radeon/radeon_mode.h uint32_t a_data_mask; uint32_t 135 drivers/gpu/drm/radeon/radeon_mode.h uint32_t en_clk_mask; uint32_t 136 drivers/gpu/drm/radeon/radeon_mode.h uint32_t en_data_mask; uint32_t 137 drivers/gpu/drm/radeon/radeon_mode.h uint32_t y_clk_mask; uint32_t 138 drivers/gpu/drm/radeon/radeon_mode.h uint32_t y_data_mask; uint32_t 142 drivers/gpu/drm/radeon/radeon_mode.h uint32_t freq; uint32_t 143 drivers/gpu/drm/radeon/radeon_mode.h uint32_t value; uint32_t 167 drivers/gpu/drm/radeon/radeon_mode.h uint32_t reference_freq; uint32_t 170 drivers/gpu/drm/radeon/radeon_mode.h uint32_t reference_div; uint32_t 171 drivers/gpu/drm/radeon/radeon_mode.h uint32_t post_div; uint32_t 174 drivers/gpu/drm/radeon/radeon_mode.h uint32_t pll_in_min; uint32_t 175 drivers/gpu/drm/radeon/radeon_mode.h uint32_t pll_in_max; uint32_t 176 drivers/gpu/drm/radeon/radeon_mode.h uint32_t pll_out_min; uint32_t 177 drivers/gpu/drm/radeon/radeon_mode.h uint32_t pll_out_max; uint32_t 178 drivers/gpu/drm/radeon/radeon_mode.h uint32_t lcd_pll_out_min; uint32_t 179 drivers/gpu/drm/radeon/radeon_mode.h uint32_t lcd_pll_out_max; uint32_t 180 drivers/gpu/drm/radeon/radeon_mode.h uint32_t best_vco; uint32_t 183 drivers/gpu/drm/radeon/radeon_mode.h uint32_t min_ref_div; uint32_t 184 drivers/gpu/drm/radeon/radeon_mode.h uint32_t max_ref_div; uint32_t 185 drivers/gpu/drm/radeon/radeon_mode.h uint32_t min_post_div; uint32_t 186 drivers/gpu/drm/radeon/radeon_mode.h uint32_t max_post_div; uint32_t 187 drivers/gpu/drm/radeon/radeon_mode.h uint32_t min_feedback_div; uint32_t 188 drivers/gpu/drm/radeon/radeon_mode.h uint32_t max_feedback_div; uint32_t 189 drivers/gpu/drm/radeon/radeon_mode.h uint32_t min_frac_feedback_div; uint32_t 190 drivers/gpu/drm/radeon/radeon_mode.h uint32_t max_frac_feedback_div; uint32_t 193 drivers/gpu/drm/radeon/radeon_mode.h uint32_t flags; uint32_t 196 drivers/gpu/drm/radeon/radeon_mode.h uint32_t id; uint32_t 279 drivers/gpu/drm/radeon/radeon_mode.h uint32_t active_encoders; uint32_t 299 drivers/gpu/drm/radeon/radeon_mode.h uint32_t tv_uv_adr; uint32_t 300 drivers/gpu/drm/radeon/radeon_mode.h uint32_t timing_cntl; uint32_t 301 drivers/gpu/drm/radeon/radeon_mode.h uint32_t hrestart; uint32_t 302 drivers/gpu/drm/radeon/radeon_mode.h uint32_t vrestart; uint32_t 303 drivers/gpu/drm/radeon/radeon_mode.h uint32_t frestart; uint32_t 334 drivers/gpu/drm/radeon/radeon_mode.h uint32_t crtc_offset; uint32_t 345 drivers/gpu/drm/radeon/radeon_mode.h uint32_t legacy_display_base_addr; uint32_t 378 drivers/gpu/drm/radeon/radeon_mode.h uint32_t ps2_pdac_adj; uint32_t 391 drivers/gpu/drm/radeon/radeon_mode.h uint32_t lvds_gen_cntl; uint32_t 401 drivers/gpu/drm/radeon/radeon_mode.h uint32_t ps2_tvdac_adj; uint32_t 402 drivers/gpu/drm/radeon/radeon_mode.h uint32_t ntsc_tvdac_adj; uint32_t 403 drivers/gpu/drm/radeon/radeon_mode.h uint32_t pal_tvdac_adj; uint32_t 433 drivers/gpu/drm/radeon/radeon_mode.h uint32_t lcd_misc; uint32_t 435 drivers/gpu/drm/radeon/radeon_mode.h uint32_t lcd_ss_id; uint32_t 464 drivers/gpu/drm/radeon/radeon_mode.h uint32_t encoder_enum; uint32_t 465 drivers/gpu/drm/radeon/radeon_mode.h uint32_t encoder_id; uint32_t 466 drivers/gpu/drm/radeon/radeon_mode.h uint32_t devices; uint32_t 467 drivers/gpu/drm/radeon/radeon_mode.h uint32_t active_device; uint32_t 468 drivers/gpu/drm/radeon/radeon_mode.h uint32_t flags; uint32_t 469 drivers/gpu/drm/radeon/radeon_mode.h uint32_t pixel_clock; uint32_t 472 drivers/gpu/drm/radeon/radeon_mode.h uint32_t underscan_hborder; uint32_t 473 drivers/gpu/drm/radeon/radeon_mode.h uint32_t underscan_vborder; uint32_t 482 drivers/gpu/drm/radeon/radeon_mode.h uint32_t offset; uint32_t 488 drivers/gpu/drm/radeon/radeon_mode.h uint32_t igp_lane_info; uint32_t 546 drivers/gpu/drm/radeon/radeon_mode.h uint32_t connector_id; uint32_t 547 drivers/gpu/drm/radeon/radeon_mode.h uint32_t devices; uint32_t 696 drivers/gpu/drm/radeon/radeon_mode.h uint32_t connector_id, uint32_t 697 drivers/gpu/drm/radeon/radeon_mode.h uint32_t supported_device, uint32_t 700 drivers/gpu/drm/radeon/radeon_mode.h uint32_t igp_lane_info, uint32_t 706 drivers/gpu/drm/radeon/radeon_mode.h uint32_t connector_id, uint32_t 707 drivers/gpu/drm/radeon/radeon_mode.h uint32_t supported_device, uint32_t 712 drivers/gpu/drm/radeon/radeon_mode.h extern uint32_t uint32_t 713 drivers/gpu/drm/radeon/radeon_mode.h radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint32_t 817 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *dot_clock_p, uint32_t 818 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *fb_div_p, uint32_t 819 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *frac_fb_div_p, uint32_t 820 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *ref_div_p, uint32_t 821 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *post_div_p); uint32_t 870 drivers/gpu/drm/radeon/radeon_mode.h uint32_t handle, uint32_t 871 drivers/gpu/drm/radeon/radeon_mode.h uint32_t width, uint32_t 872 drivers/gpu/drm/radeon/radeon_mode.h uint32_t height, uint32_t 958 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, uint32_t 959 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); uint32_t 961 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *htotal_cntl, uint32_t *ppll_ref_div, uint32_t 962 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *ppll_div_3, uint32_t *pixclks_cntl); uint32_t 964 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, uint32_t 965 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); uint32_t 676 drivers/gpu/drm/radeon/radeon_object.c uint32_t tiling_flags, uint32_t pitch) uint32_t 736 drivers/gpu/drm/radeon/radeon_object.c uint32_t *tiling_flags, uint32_t 737 drivers/gpu/drm/radeon/radeon_object.c uint32_t *pitch) uint32_t 84 drivers/gpu/drm/radeon/radeon_ring.c uint32_t rptr = radeon_ring_get_rptr(rdev, ring); uint32_t 253 drivers/gpu/drm/radeon/radeon_ring.c uint32_t rptr = radeon_ring_get_rptr(rdev, ring); uint32_t 282 drivers/gpu/drm/radeon/radeon_ring.c uint32_t **data) uint32_t 321 drivers/gpu/drm/radeon/radeon_ring.c *data = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); uint32_t 346 drivers/gpu/drm/radeon/radeon_ring.c unsigned size, uint32_t *data) uint32_t 472 drivers/gpu/drm/radeon/radeon_ring.c uint32_t rptr, wptr, rptr_next; uint32_t 266 drivers/gpu/drm/radeon/radeon_test.c uint32_t handle = ring->idx ^ 0xdeafbeef; uint32_t 85 drivers/gpu/drm/radeon/radeon_trace.h uint32_t incr, uint32_t flags), uint32_t 69 drivers/gpu/drm/radeon/radeon_ttm.c static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) uint32_t 74 drivers/gpu/drm/radeon/radeon_ttm.c static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, uint32_t 481 drivers/gpu/drm/radeon/radeon_ttm.c uint32_t userflags; uint32_t 580 drivers/gpu/drm/radeon/radeon_ttm.c uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | uint32_t 633 drivers/gpu/drm/radeon/radeon_ttm.c uint32_t page_flags) uint32_t 740 drivers/gpu/drm/radeon/radeon_ttm.c uint32_t flags) uint32_t 973 drivers/gpu/drm/radeon/radeon_ttm.c uint32_t value; uint32_t 979 drivers/gpu/drm/radeon/radeon_ttm.c WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); uint32_t 985 drivers/gpu/drm/radeon/radeon_ttm.c r = put_user(value, (uint32_t *)buf); uint32_t 157 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ uint32_t 158 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t header_size_bytes; /* size of just the header in bytes */ uint32_t 163 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t ucode_version; uint32_t 164 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t ucode_size_bytes; /* size of ucode in bytes */ uint32_t 165 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ uint32_t 166 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t crc32; /* crc32 checksum of the payload */ uint32_t 172 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t io_debug_size_bytes; /* size of debug array in dwords */ uint32_t 173 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ uint32_t 179 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t ucode_start_addr; uint32_t 185 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t ucode_feature_version; uint32_t 186 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t jt_offset; /* jt location */ uint32_t 187 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t jt_size; /* size of jt */ uint32_t 193 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t ucode_feature_version; uint32_t 194 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t save_and_restore_offset; uint32_t 195 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t clear_state_descriptor_offset; uint32_t 196 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t avail_scratch_ram_locations; uint32_t 197 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t master_pkt_description_offset; uint32_t 203 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t ucode_feature_version; uint32_t 204 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t ucode_change_version; uint32_t 205 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t jt_offset; /* jt location */ uint32_t 206 drivers/gpu/drm/radeon/radeon_ucode.h uint32_t jt_size; /* size of jt */ uint32_t 257 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t handle = atomic_read(&rdev->uvd.handles[i]); uint32_t 303 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t allowed_domains) uint32_t 332 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t handle = atomic_read(&rdev->uvd.handles[i]); uint32_t 354 drivers/gpu/drm/radeon/radeon_uvd.c static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) uint32_t 778 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t handle, struct radeon_fence **fence) uint32_t 784 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t *msg = rdev->uvd.cpu_addr + offs; uint32_t 814 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t handle, struct radeon_fence **fence) uint32_t 820 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t *msg = rdev->uvd.cpu_addr + offs; uint32_t 1037 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; uint32_t 320 drivers/gpu/drm/radeon/radeon_vce.c uint32_t handle = atomic_read(&rdev->vce.handles[i]); uint32_t 347 drivers/gpu/drm/radeon/radeon_vce.c uint32_t handle, struct radeon_fence **fence) uint32_t 414 drivers/gpu/drm/radeon/radeon_vce.c uint32_t handle, struct radeon_fence **fence) uint32_t 520 drivers/gpu/drm/radeon/radeon_vce.c uint32_t handle, bool *allocated) uint32_t 561 drivers/gpu/drm/radeon/radeon_vce.c uint32_t tmp, handle = 0; uint32_t 562 drivers/gpu/drm/radeon/radeon_vce.c uint32_t *size = &tmp; uint32_t 566 drivers/gpu/drm/radeon/radeon_vce.c uint32_t len = radeon_get_ib_value(p, p->idx); uint32_t 567 drivers/gpu/drm/radeon/radeon_vce.c uint32_t cmd = radeon_get_ib_value(p, p->idx + 1); uint32_t 758 drivers/gpu/drm/radeon/radeon_vce.c uint32_t rptr = vce_v1_0_get_rptr(rdev, ring); uint32_t 363 drivers/gpu/drm/radeon/radeon_vm.c uint32_t incr, uint32_t flags) uint32_t 449 drivers/gpu/drm/radeon/radeon_vm.c uint32_t flags) uint32_t 613 drivers/gpu/drm/radeon/radeon_vm.c static uint32_t radeon_vm_page_flags(uint32_t flags) uint32_t 615 drivers/gpu/drm/radeon/radeon_vm.c uint32_t hw_flags = 0; uint32_t 646 drivers/gpu/drm/radeon/radeon_vm.c uint32_t incr = RADEON_VM_PTE_COUNT * 8; uint32_t 735 drivers/gpu/drm/radeon/radeon_vm.c uint64_t addr, uint32_t flags) uint32_t 818 drivers/gpu/drm/radeon/radeon_vm.c uint64_t dst, uint32_t flags) uint32_t 920 drivers/gpu/drm/radeon/radeon_vm.c uint32_t flags; uint32_t 67 drivers/gpu/drm/radeon/rs400.c uint32_t tmp; uint32_t 114 drivers/gpu/drm/radeon/rs400.c uint32_t size_reg; uint32_t 115 drivers/gpu/drm/radeon/rs400.c uint32_t tmp; uint32_t 201 drivers/gpu/drm/radeon/rs400.c uint32_t tmp; uint32_t 220 drivers/gpu/drm/radeon/rs400.c uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags) uint32_t 222 drivers/gpu/drm/radeon/rs400.c uint32_t entry; uint32_t 245 drivers/gpu/drm/radeon/rs400.c uint32_t tmp; uint32_t 285 drivers/gpu/drm/radeon/rs400.c uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) uint32_t 288 drivers/gpu/drm/radeon/rs400.c uint32_t r; uint32_t 298 drivers/gpu/drm/radeon/rs400.c void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) uint32_t 315 drivers/gpu/drm/radeon/rs400.c uint32_t tmp; uint32_t 523 drivers/gpu/drm/radeon/rs600.c uint32_t tmp; uint32_t 638 drivers/gpu/drm/radeon/rs600.c uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags) uint32_t 662 drivers/gpu/drm/radeon/rs600.c uint32_t tmp = 0; uint32_t 663 drivers/gpu/drm/radeon/rs600.c uint32_t mode_int = 0; uint32_t 715 drivers/gpu/drm/radeon/rs600.c uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); uint32_t 716 drivers/gpu/drm/radeon/rs600.c uint32_t irq_mask = S_000044_SW_INT(1); uint32_t 924 drivers/gpu/drm/radeon/rs600.c uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) uint32_t 937 drivers/gpu/drm/radeon/rs600.c void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) uint32_t 40 drivers/gpu/drm/radeon/rs690.c uint32_t tmp; uint32_t 153 drivers/gpu/drm/radeon/rs690.c uint32_t h_addr, l_addr; uint32_t 651 drivers/gpu/drm/radeon/rs690.c uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) uint32_t 654 drivers/gpu/drm/radeon/rs690.c uint32_t r; uint32_t 664 drivers/gpu/drm/radeon/rs690.c void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) uint32_t 138 drivers/gpu/drm/radeon/rv515.c uint32_t tmp; uint32_t 182 drivers/gpu/drm/radeon/rv515.c uint32_t tmp; uint32_t 212 drivers/gpu/drm/radeon/rv515.c uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) uint32_t 215 drivers/gpu/drm/radeon/rv515.c uint32_t r; uint32_t 226 drivers/gpu/drm/radeon/rv515.c void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) uint32_t 243 drivers/gpu/drm/radeon/rv515.c uint32_t tmp; uint32_t 261 drivers/gpu/drm/radeon/rv515.c uint32_t tmp; uint32_t 1278 drivers/gpu/drm/radeon/rv515.c uint32_t tmp; uint32_t 36 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vCG_SPLL_FUNC_CNTL; uint32_t 37 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vCG_SPLL_FUNC_CNTL_2; uint32_t 38 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vCG_SPLL_FUNC_CNTL_3; uint32_t 39 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vCG_SPLL_SPREAD_SPECTRUM; uint32_t 40 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 41 drivers/gpu/drm/radeon/rv770_smc.h uint32_t sclk_value; uint32_t 48 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_AD_FUNC_CNTL; uint32_t 49 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_AD_FUNC_CNTL_2; uint32_t 50 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_DQ_FUNC_CNTL; uint32_t 51 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_DQ_FUNC_CNTL_2; uint32_t 52 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMCLK_PWRMGT_CNTL; uint32_t 53 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vDLL_CNTL; uint32_t 54 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_SS; uint32_t 55 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_SS2; uint32_t 56 drivers/gpu/drm/radeon/rv770_smc.h uint32_t mclk_value; uint32_t 64 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMCLK_PWRMGT_CNTL; uint32_t 65 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vDLL_CNTL; uint32_t 66 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_FUNC_CNTL; uint32_t 67 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_FUNC_CNTL2; uint32_t 68 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_FUNC_CNTL3; uint32_t 69 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_SS; uint32_t 70 drivers/gpu/drm/radeon/rv770_smc.h uint32_t vMPLL_SS2; uint32_t 71 drivers/gpu/drm/radeon/rv770_smc.h uint32_t mclk_value; uint32_t 106 drivers/gpu/drm/radeon/rv770_smc.h uint32_t aT; uint32_t 107 drivers/gpu/drm/radeon/rv770_smc.h uint32_t bSP; uint32_t 148 drivers/gpu/drm/radeon/rv770_smc.h uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX]; uint32_t 162 drivers/gpu/drm/radeon/rv770_smc.h uint32_t lowSMIO[MAX_NO_VREG_STEPS]; uint32_t 4378 drivers/gpu/drm/radeon/si.c uint32_t reg; uint32_t 7467 drivers/gpu/drm/radeon/si.c uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; uint32_t 109 drivers/gpu/drm/radeon/si_dma.c uint32_t incr, uint32_t flags) uint32_t 156 drivers/gpu/drm/radeon/si_dma.c uint32_t incr, uint32_t flags) uint32_t 52 drivers/gpu/drm/radeon/sislands_smc.h uint32_t dpm2Flags; uint32_t 65 drivers/gpu/drm/radeon/sislands_smc.h uint32_t SwitchDownCounter; uint32_t 66 drivers/gpu/drm/radeon/sislands_smc.h uint32_t SysScalingFactor; uint32_t 73 drivers/gpu/drm/radeon/sislands_smc.h uint32_t TDPLimit; uint32_t 74 drivers/gpu/drm/radeon/sislands_smc.h uint32_t NearTDPLimit; uint32_t 75 drivers/gpu/drm/radeon/sislands_smc.h uint32_t SafePowerLimit; uint32_t 76 drivers/gpu/drm/radeon/sislands_smc.h uint32_t PowerBoostLimit; uint32_t 77 drivers/gpu/drm/radeon/sislands_smc.h uint32_t MinLimitDelta; uint32_t 83 drivers/gpu/drm/radeon/sislands_smc.h uint32_t EstimatedDGPU_T; uint32_t 84 drivers/gpu/drm/radeon/sislands_smc.h uint32_t EstimatedDGPU_P; uint32_t 85 drivers/gpu/drm/radeon/sislands_smc.h uint32_t EstimatedAPU_T; uint32_t 86 drivers/gpu/drm/radeon/sislands_smc.h uint32_t EstimatedAPU_P; uint32_t 94 drivers/gpu/drm/radeon/sislands_smc.h uint32_t NearTDPLimitTherm; uint32_t 95 drivers/gpu/drm/radeon/sislands_smc.h uint32_t NearTDPLimitPAPM; uint32_t 96 drivers/gpu/drm/radeon/sislands_smc.h uint32_t PlatformPowerLimit; uint32_t 97 drivers/gpu/drm/radeon/sislands_smc.h uint32_t dGPU_T_Limit; uint32_t 98 drivers/gpu/drm/radeon/sislands_smc.h uint32_t dGPU_T_Warning; uint32_t 99 drivers/gpu/drm/radeon/sislands_smc.h uint32_t dGPU_T_Hysteresis; uint32_t 105 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL; uint32_t 106 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL_2; uint32_t 107 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL_3; uint32_t 108 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vCG_SPLL_FUNC_CNTL_4; uint32_t 109 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vCG_SPLL_SPREAD_SPECTRUM; uint32_t 110 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; uint32_t 111 drivers/gpu/drm/radeon/sislands_smc.h uint32_t sclk_value; uint32_t 118 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vMPLL_FUNC_CNTL; uint32_t 119 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vMPLL_FUNC_CNTL_1; uint32_t 120 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vMPLL_FUNC_CNTL_2; uint32_t 121 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vMPLL_AD_FUNC_CNTL; uint32_t 122 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vMPLL_DQ_FUNC_CNTL; uint32_t 123 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vMCLK_PWRMGT_CNTL; uint32_t 124 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vDLL_CNTL; uint32_t 125 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vMPLL_SS; uint32_t 126 drivers/gpu/drm/radeon/sislands_smc.h uint32_t vMPLL_SS2; uint32_t 127 drivers/gpu/drm/radeon/sislands_smc.h uint32_t mclk_value; uint32_t 151 drivers/gpu/drm/radeon/sislands_smc.h uint32_t aT; uint32_t 152 drivers/gpu/drm/radeon/sislands_smc.h uint32_t bSP; uint32_t 163 drivers/gpu/drm/radeon/sislands_smc.h uint32_t SQPowerThrottle; uint32_t 164 drivers/gpu/drm/radeon/sislands_smc.h uint32_t SQPowerThrottle_2; uint32_t 165 drivers/gpu/drm/radeon/sislands_smc.h uint32_t MaxPoweredUpCU; uint32_t 168 drivers/gpu/drm/radeon/sislands_smc.h uint32_t reserved[2]; uint32_t 202 drivers/gpu/drm/radeon/sislands_smc.h uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX]; uint32_t 215 drivers/gpu/drm/radeon/sislands_smc.h uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS]; uint32_t 266 drivers/gpu/drm/radeon/sislands_smc.h uint32_t refresh_period; uint32_t 283 drivers/gpu/drm/radeon/sislands_smc.h uint32_t lkge_lut_V0; uint32_t 284 drivers/gpu/drm/radeon/sislands_smc.h uint32_t lkge_lut_Vstep; uint32_t 285 drivers/gpu/drm/radeon/sislands_smc.h uint32_t WinTime; uint32_t 286 drivers/gpu/drm/radeon/sislands_smc.h uint32_t R_LL; uint32_t 287 drivers/gpu/drm/radeon/sislands_smc.h uint32_t calculation_repeats; uint32_t 288 drivers/gpu/drm/radeon/sislands_smc.h uint32_t l2numWin_TDP; uint32_t 289 drivers/gpu/drm/radeon/sislands_smc.h uint32_t dc_cac; uint32_t 294 drivers/gpu/drm/radeon/sislands_smc.h uint32_t lkge_lut_T0; uint32_t 295 drivers/gpu/drm/radeon/sislands_smc.h uint32_t lkge_lut_Tstep; uint32_t 313 drivers/gpu/drm/radeon/sislands_smc.h uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; uint32_t 330 drivers/gpu/drm/radeon/sislands_smc.h uint32_t mc_arb_dram_timing; uint32_t 331 drivers/gpu/drm/radeon/sislands_smc.h uint32_t mc_arb_dram_timing2; uint32_t 350 drivers/gpu/drm/radeon/sislands_smc.h uint32_t freq[256]; uint32_t 351 drivers/gpu/drm/radeon/sislands_smc.h uint32_t ss[256]; uint32_t 371 drivers/gpu/drm/radeon/sislands_smc.h uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; uint32_t 372 drivers/gpu/drm/radeon/sislands_smc.h uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; uint32_t 373 drivers/gpu/drm/radeon/sislands_smc.h uint32_t K; uint32_t 374 drivers/gpu/drm/radeon/sislands_smc.h uint32_t T0; uint32_t 375 drivers/gpu/drm/radeon/sislands_smc.h uint32_t MaxT; uint32_t 381 drivers/gpu/drm/radeon/sislands_smc.h uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; uint32_t 382 drivers/gpu/drm/radeon/sislands_smc.h uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; uint32_t 383 drivers/gpu/drm/radeon/sislands_smc.h uint32_t Tthreshold; uint32_t 87 drivers/gpu/drm/radeon/smu7.h uint32_t Ki; uint32_t 90 drivers/gpu/drm/radeon/smu7.h uint32_t StatePrecision; uint32_t 91 drivers/gpu/drm/radeon/smu7.h uint32_t LfPrecision; uint32_t 92 drivers/gpu/drm/radeon/smu7.h uint32_t LfOffset; uint32_t 93 drivers/gpu/drm/radeon/smu7.h uint32_t MaxState; uint32_t 94 drivers/gpu/drm/radeon/smu7.h uint32_t MaxLfFraction; uint32_t 95 drivers/gpu/drm/radeon/smu7.h uint32_t StateShift; uint32_t 122 drivers/gpu/drm/radeon/smu7.h uint32_t Digest[5]; uint32_t 123 drivers/gpu/drm/radeon/smu7.h uint32_t Version; uint32_t 124 drivers/gpu/drm/radeon/smu7.h uint32_t HeaderSize; uint32_t 125 drivers/gpu/drm/radeon/smu7.h uint32_t Flags; uint32_t 126 drivers/gpu/drm/radeon/smu7.h uint32_t EntryPoint; uint32_t 127 drivers/gpu/drm/radeon/smu7.h uint32_t CodeSize; uint32_t 128 drivers/gpu/drm/radeon/smu7.h uint32_t ImageSize; uint32_t 130 drivers/gpu/drm/radeon/smu7.h uint32_t Rtos; uint32_t 131 drivers/gpu/drm/radeon/smu7.h uint32_t SoftRegisters; uint32_t 132 drivers/gpu/drm/radeon/smu7.h uint32_t DpmTable; uint32_t 133 drivers/gpu/drm/radeon/smu7.h uint32_t FanTable; uint32_t 134 drivers/gpu/drm/radeon/smu7.h uint32_t CacConfigTable; uint32_t 135 drivers/gpu/drm/radeon/smu7.h uint32_t CacStatusTable; uint32_t 137 drivers/gpu/drm/radeon/smu7.h uint32_t mcRegisterTable; uint32_t 139 drivers/gpu/drm/radeon/smu7.h uint32_t mcArbDramTimingTable; uint32_t 141 drivers/gpu/drm/radeon/smu7.h uint32_t PmFuseTable; uint32_t 142 drivers/gpu/drm/radeon/smu7.h uint32_t Globals; uint32_t 143 drivers/gpu/drm/radeon/smu7.h uint32_t Reserved[42]; uint32_t 144 drivers/gpu/drm/radeon/smu7.h uint32_t Signature; uint32_t 40 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t RefClockFrequency; uint32_t 41 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t PmTimerP; uint32_t 42 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t FeatureEnables; uint32_t 43 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t PreVBlankGap; uint32_t 44 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t VBlankTimeout; uint32_t 45 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t TrainTimeGap; uint32_t 47 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MvddSwitchTime; uint32_t 48 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t LongestAcpiTrainTime; uint32_t 49 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t AcpiDelay; uint32_t 50 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t G5TrainTime; uint32_t 51 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DelayMpllPwron; uint32_t 52 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t VoltageChangeTimeout; uint32_t 53 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t HandshakeDisables; uint32_t 65 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t AverageGraphicsA; uint32_t 66 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t AverageMemoryA; uint32_t 67 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t AverageGioA; uint32_t 79 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DRAM_LOG_ADDR_H; uint32_t 80 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DRAM_LOG_ADDR_L; uint32_t 81 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 82 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 83 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 84 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t UlvEnterC; uint32_t 85 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t UlvTime; uint32_t 86 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t Reserved[3]; uint32_t 105 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t Flags; uint32_t 106 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MinVddc; uint32_t 107 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MinVddcPhases; uint32_t 109 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SclkFrequency; uint32_t 114 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 115 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 116 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 117 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 118 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CcPwrDynRm; uint32_t 119 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CcPwrDynRm1; uint32_t 136 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t Flags; uint32_t 137 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MinVddc; uint32_t 138 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MinVddcPhases; uint32_t 139 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SclkFrequency; uint32_t 144 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CgSpllFuncCntl; uint32_t 145 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CgSpllFuncCntl2; uint32_t 146 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CgSpllFuncCntl3; uint32_t 147 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CgSpllFuncCntl4; uint32_t 148 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SpllSpreadSpectrum; uint32_t 149 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SpllSpreadSpectrum2; uint32_t 150 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CcPwrDynRm; uint32_t 151 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CcPwrDynRm1; uint32_t 158 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CcPwrDynRm; uint32_t 159 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t CcPwrDynRm1; uint32_t 163 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t Reserved; uint32_t 170 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MinVddc; uint32_t 171 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MinVddcPhases; uint32_t 172 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MinVddci; uint32_t 173 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MinMvdd; uint32_t 175 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MclkFrequency; uint32_t 196 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MpllFuncCntl; uint32_t 197 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MpllFuncCntl_1; uint32_t 198 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MpllFuncCntl_2; uint32_t 199 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MpllAdFuncCntl; uint32_t 200 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MpllDqFuncCntl; uint32_t 201 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MclkPwrmgtCntl; uint32_t 202 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DllCntl; uint32_t 203 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MpllSs1; uint32_t 204 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MpllSs2; uint32_t 215 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DownT; uint32_t 216 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t UpT; uint32_t 217 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t Reserved; uint32_t 225 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t McArbDramTiming; uint32_t 226 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t McArbDramTiming2; uint32_t 242 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t VclkFrequency; uint32_t 243 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DclkFrequency; uint32_t 255 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t Frequency; uint32_t 265 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SclkFrequency; uint32_t 266 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MclkFrequency; uint32_t 267 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t VclkFrequency; uint32_t 268 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t DclkFrequency; uint32_t 269 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SamclkFrequency; uint32_t 270 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t AclkFrequency; uint32_t 271 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t EclkFrequency; uint32_t 294 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SystemFlags; uint32_t 297 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SmioMaskVddcVid; uint32_t 298 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SmioMaskVddcPhase; uint32_t 299 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SmioMaskVddciVid; uint32_t 300 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SmioMaskMvddVid; uint32_t 302 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t VddcLevelCount; uint32_t 303 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t VddciLevelCount; uint32_t 304 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t MvddLevelCount; uint32_t 319 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t Reserved[5]; uint32_t 333 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t SclkStepSize; uint32_t 334 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t Smio [SMU7_MAX_ENTRIES_SMIO]; uint32_t 399 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t BAPM_TEMP_GRADIENT; uint32_t 401 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t LowSclkInterruptT; uint32_t 419 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; uint32_t 450 drivers/gpu/drm/radeon/smu7_discrete.h uint32_t RefreshPeriod; uint32_t 41 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t RefClockFrequency; uint32_t 42 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t PmTimerP; uint32_t 43 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t FeatureEnables; uint32_t 44 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t HandshakeDisables; uint32_t 56 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t AverageGraphicsA; uint32_t 57 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t AverageMemoryA; uint32_t 58 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t AverageGioA; uint32_t 70 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_ADDR_H; uint32_t 71 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_ADDR_L; uint32_t 72 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 73 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 74 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 75 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t UlvEnterC; uint32_t 76 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t UlvTime; uint32_t 77 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t Reserved[3]; uint32_t 85 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t MinVddNb; uint32_t 87 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t SclkFrequency; uint32_t 109 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t reserved; uint32_t 121 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t MinVddNb; uint32_t 127 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t LclkFrequency; uint32_t 142 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t VclkFrequency; uint32_t 143 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DclkFrequency; uint32_t 160 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t Frequency; uint32_t 165 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t Reserved; uint32_t 171 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t Flags; uint32_t 172 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t MinVddNb; uint32_t 173 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t SclkFrequency; uint32_t 202 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t SclkFrequency; uint32_t 203 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t LclkFrequency; uint32_t 204 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t VclkFrequency; uint32_t 205 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DclkFrequency; uint32_t 206 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t SamclkFrequency; uint32_t 207 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t AclkFrequency; uint32_t 208 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t EclkFrequency; uint32_t 219 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t SystemFlags; uint32_t 258 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DisplayCac; uint32_t 259 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t LowSclkInterruptT; uint32_t 261 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_ADDR_H; uint32_t 262 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_ADDR_L; uint32_t 263 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_PHY_ADDR_H; uint32_t 264 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_PHY_ADDR_L; uint32_t 265 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t DRAM_LOG_BUFF_SIZE; uint32_t 276 drivers/gpu/drm/radeon/smu7_fusion.h uint32_t GIOLevelCount; uint32_t 39 drivers/gpu/drm/radeon/uvd_v1_0.c uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, uint32_t 53 drivers/gpu/drm/radeon/uvd_v1_0.c uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, uint32_t 113 drivers/gpu/drm/radeon/uvd_v1_0.c uint32_t size; uint32_t 145 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); uint32_t 160 drivers/gpu/drm/radeon/uvd_v1_0.c uint32_t tmp; uint32_t 266 drivers/gpu/drm/radeon/uvd_v1_0.c uint32_t rb_bufsz; uint32_t 330 drivers/gpu/drm/radeon/uvd_v1_0.c uint32_t status; uint32_t 423 drivers/gpu/drm/radeon/uvd_v1_0.c uint32_t tmp = 0; uint32_t 101 drivers/gpu/drm/radeon/uvd_v2_2.c uint32_t chip_id, size; uint32_t 41 drivers/gpu/drm/radeon/uvd_v4_2.c uint32_t size; uint32_t 41 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t len; uint32_t 44 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t chip_id; uint32_t 45 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t keyselect; uint32_t 46 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t nonce[4]; uint32_t 47 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t sigval[4]; uint32_t 59 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, uint32_t 76 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, uint32_t 157 drivers/gpu/drm/radeon/vce_v1_0.c int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data) uint32_t 160 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t chip_id; uint32_t 219 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t size; uint32_t 326 drivers/gpu/drm/radeon/vce_v1_0.c uint32_t status; uint32_t 160 drivers/gpu/drm/radeon/vce_v2_0.c uint32_t size; uint32_t 740 drivers/gpu/drm/rcar-du/rcar_du_plane.c static const uint32_t formats[] = { uint32_t 578 drivers/gpu/drm/rockchip/inno_hdmi.c uint32_t maxX, uint32_t maxY) uint32_t 509 drivers/gpu/drm/rockchip/rk3066_hdmi.c uint32_t maxX, uint32_t maxY) uint32_t 102 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static const uint32_t bt601_yuv2rgb[] = { uint32_t 140 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t *regsbak; uint32_t 144 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t len; uint32_t 171 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) uint32_t 177 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) uint32_t 182 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, uint32_t 189 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t _offset, uint32_t _mask, uint32_t v, uint32_t 206 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t cached_val = vop->regsbak[offset >> 2]; uint32_t 218 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline uint32_t vop_get_intr_type(struct vop *vop, uint32_t 221 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t i, ret = 0; uint32_t 222 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t regs = vop_read_reg(vop, 0, reg); uint32_t 237 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static bool has_rb_swapped(uint32_t format) uint32_t 250 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static enum vop_data_format vop_convert_format(uint32_t format) uint32_t 276 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, uint32_t 277 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t dst, bool is_horizontal, uint32_t 311 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t 312 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t dst_h, const struct drm_format_info *info) uint32_t 322 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t val; uint32_t 467 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t line_flag_irq; uint32_t 791 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t act_info, dsp_info, dsp_st; uint32_t 798 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t val; uint32_t 1099 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t pin_pol, val; uint32_t 1427 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t active_irqs; uint32_t 30 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t mask; uint32_t 82 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t nintrs; uint32_t 129 drivers/gpu/drm/rockchip/rockchip_drm_vop.h const uint32_t *data_formats; uint32_t 130 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t nformats; uint32_t 152 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t base; uint32_t 158 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t base; uint32_t 164 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t version; uint32_t 343 drivers/gpu/drm/rockchip/rockchip_drm_vop.h static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) uint32_t 345 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t vskiplines; uint32_t 38 drivers/gpu/drm/rockchip/rockchip_vop_reg.c static const uint32_t formats_win_full[] = { uint32_t 52 drivers/gpu/drm/rockchip/rockchip_vop_reg.c static const uint32_t formats_win_lite[] = { uint32_t 49 drivers/gpu/drm/savage/savage_bci.c uint32_t mask = dev_priv->status_used_mask; uint32_t 50 drivers/gpu/drm/savage/savage_bci.c uint32_t threshold = dev_priv->bci_threshold_hi; uint32_t 51 drivers/gpu/drm/savage/savage_bci.c uint32_t status; uint32_t 78 drivers/gpu/drm/savage/savage_bci.c uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; uint32_t 79 drivers/gpu/drm/savage/savage_bci.c uint32_t status; uint32_t 99 drivers/gpu/drm/savage/savage_bci.c uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; uint32_t 100 drivers/gpu/drm/savage/savage_bci.c uint32_t status; uint32_t 131 drivers/gpu/drm/savage/savage_bci.c uint32_t status; uint32_t 154 drivers/gpu/drm/savage/savage_bci.c uint32_t status; uint32_t 194 drivers/gpu/drm/savage/savage_bci.c dev_priv->status_ptr[1023] = (uint32_t) count; uint32_t 207 drivers/gpu/drm/savage/savage_bci.c BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count); uint32_t 372 drivers/gpu/drm/savage/savage_bci.c uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n) uint32_t 379 drivers/gpu/drm/savage/savage_bci.c uint32_t *dma_ptr; uint32_t 386 drivers/gpu/drm/savage/savage_bci.c dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + uint32_t 402 drivers/gpu/drm/savage/savage_bci.c dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle; uint32_t 453 drivers/gpu/drm/savage/savage_bci.c uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + uint32_t 527 drivers/gpu/drm/savage/savage_bci.c uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + uint32_t 853 drivers/gpu/drm/savage/savage_bci.c dev_priv->bci_ptr = (volatile uint32_t *) uint32_t 862 drivers/gpu/drm/savage/savage_bci.c (volatile uint32_t *)dev_priv->status->handle; uint32_t 83 drivers/gpu/drm/savage/savage_drv.h uint32_t vbaddr; uint32_t 87 drivers/gpu/drm/savage/savage_drv.h uint32_t texctrl, texaddr; uint32_t 88 drivers/gpu/drm/savage/savage_drv.h uint32_t scstart, new_scstart; uint32_t 89 drivers/gpu/drm/savage/savage_drv.h uint32_t scend, new_scend; uint32_t 93 drivers/gpu/drm/savage/savage_drv.h uint32_t texdescr, texaddr0, texaddr1; uint32_t 94 drivers/gpu/drm/savage/savage_drv.h uint32_t drawctrl0, new_drawctrl0; uint32_t 95 drivers/gpu/drm/savage/savage_drv.h uint32_t drawctrl1, new_drawctrl1; uint32_t 172 drivers/gpu/drm/savage/savage_drv.h volatile uint32_t *status_ptr, *bci_ptr; uint32_t 173 drivers/gpu/drm/savage/savage_drv.h uint32_t status_used_mask; uint32_t 183 drivers/gpu/drm/savage/savage_drv.h uint32_t hw_draw_ctrl, hw_zbuf_ctrl; uint32_t 185 drivers/gpu/drm/savage/savage_drv.h uint32_t hw_scissors_start, hw_scissors_end; uint32_t 212 drivers/gpu/drm/savage/savage_drv.h extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, uint32_t 463 drivers/gpu/drm/savage/savage_drv.h ((uint32_t)(n) & 0xff) << 16 | \ uint32_t 464 drivers/gpu/drm/savage/savage_drv.h ((uint32_t)(first) & 0xffff)) uint32_t 467 drivers/gpu/drm/savage/savage_drv.h ((uint32_t)(n) & 0xff) << 16 | \ uint32_t 468 drivers/gpu/drm/savage/savage_drv.h ((uint32_t)(first) & 0xffff)) uint32_t 501 drivers/gpu/drm/savage/savage_drv.h #define BCI_LOCALS volatile uint32_t *bci_ptr; uint32_t 508 drivers/gpu/drm/savage/savage_drv.h #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) uint32_t 515 drivers/gpu/drm/savage/savage_drv.h #define DMA_LOCALS uint32_t *dma_ptr; uint32_t 524 drivers/gpu/drm/savage/savage_drv.h dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ uint32_t 533 drivers/gpu/drm/savage/savage_drv.h #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) uint32_t 543 drivers/gpu/drm/savage/savage_drv.h uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ uint32_t 39 drivers/gpu/drm/savage/savage_state.c uint32_t scstart = dev_priv->state.s3d.new_scstart; uint32_t 40 drivers/gpu/drm/savage/savage_state.c uint32_t scend = dev_priv->state.s3d.new_scend; uint32_t 42 drivers/gpu/drm/savage/savage_state.c ((uint32_t) pbox->x1 & 0x000007ff) | uint32_t 43 drivers/gpu/drm/savage/savage_state.c (((uint32_t) pbox->y1 << 16) & 0x07ff0000); uint32_t 45 drivers/gpu/drm/savage/savage_state.c (((uint32_t) pbox->x2 - 1) & 0x000007ff) | uint32_t 46 drivers/gpu/drm/savage/savage_state.c ((((uint32_t) pbox->y2 - 1) << 16) & 0x07ff0000); uint32_t 65 drivers/gpu/drm/savage/savage_state.c uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0; uint32_t 66 drivers/gpu/drm/savage/savage_state.c uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1; uint32_t 68 drivers/gpu/drm/savage/savage_state.c ((uint32_t) pbox->x1 & 0x000007ff) | uint32_t 69 drivers/gpu/drm/savage/savage_state.c (((uint32_t) pbox->y1 << 12) & 0x00fff000); uint32_t 71 drivers/gpu/drm/savage/savage_state.c (((uint32_t) pbox->x2 - 1) & 0x000007ff) | uint32_t 72 drivers/gpu/drm/savage/savage_state.c ((((uint32_t) pbox->y2 - 1) << 12) & 0x00fff000); uint32_t 89 drivers/gpu/drm/savage/savage_state.c uint32_t addr) uint32_t 128 drivers/gpu/drm/savage/savage_state.c uint32_t tmp; \ uint32_t 137 drivers/gpu/drm/savage/savage_state.c const uint32_t *regs) uint32_t 167 drivers/gpu/drm/savage/savage_state.c const uint32_t *regs) uint32_t 206 drivers/gpu/drm/savage/savage_state.c const uint32_t *regs) uint32_t 428 drivers/gpu/drm/savage/savage_state.c const uint32_t *vtxbuf, unsigned int vb_size, uint32_t 690 drivers/gpu/drm/savage/savage_state.c const uint32_t *vtxbuf, uint32_t 947 drivers/gpu/drm/savage/savage_state.c (const uint32_t *)vtxbuf, vb_size, uint32_t 1104 drivers/gpu/drm/savage/savage_state.c (const uint32_t *)cmdbuf->cmd_addr); uint32_t 31 drivers/gpu/drm/selftests/test-drm_damage_helper.c struct drm_mode_rect *r, uint32_t size) uint32_t 78 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 109 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 142 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 174 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 207 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 236 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 264 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 289 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 325 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 360 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 396 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 431 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 469 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 508 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 546 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 583 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 622 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 663 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 706 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 743 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 782 drivers/gpu/drm/selftests/test-drm_damage_helper.c uint32_t num_hits = 0; uint32_t 408 drivers/gpu/drm/shmobile/shmob_drm_crtc.c uint32_t page_flip_flags, uint32_t 173 drivers/gpu/drm/shmobile/shmob_drm_plane.c uint32_t src_x, uint32_t src_y, uint32_t 174 drivers/gpu/drm/shmobile/shmob_drm_plane.c uint32_t src_w, uint32_t src_h, uint32_t 230 drivers/gpu/drm/shmobile/shmob_drm_plane.c static const uint32_t formats[] = { uint32_t 243 drivers/gpu/drm/sis/sis_mm.c uint32_t idle_reg; uint32_t 73 drivers/gpu/drm/sti/sti_cursor.c static const uint32_t cursor_supported_formats[] = { uint32_t 135 drivers/gpu/drm/sti/sti_gdp.c static const uint32_t gdp_supported_formats[] = { uint32_t 45 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c uint32_t min; uint32_t 46 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c uint32_t max; uint32_t 47 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c uint32_t idf; uint32_t 48 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c uint32_t odf; uint32_t 362 drivers/gpu/drm/sti/sti_hqvdp.c static const uint32_t hqvdp_supported_formats[] = { uint32_t 138 drivers/gpu/drm/sun4i/sun4i_backend.c static const uint32_t sun4i_backend_formats[] = { uint32_t 153 drivers/gpu/drm/sun4i/sun4i_backend.c bool sun4i_backend_format_is_supported(uint32_t fmt, uint64_t modifier) uint32_t 205 drivers/gpu/drm/sun4i/sun4i_backend.c const uint32_t fmt = format->format; uint32_t 306 drivers/gpu/drm/sun4i/sun4i_backend.c int layer, uint32_t fmt) uint32_t 428 drivers/gpu/drm/sun4i/sun4i_backend.c uint32_t format = state->fb->format->format; uint32_t 197 drivers/gpu/drm/sun4i/sun4i_backend.h bool sun4i_backend_format_is_supported(uint32_t fmt, uint64_t modifier); uint32_t 205 drivers/gpu/drm/sun4i/sun4i_backend.h int layer, uint32_t in_fmt); uint32_t 242 drivers/gpu/drm/sun4i/sun4i_crtc.c uint32_t possible_crtcs = drm_crtc_mask(&scrtc->crtc); uint32_t 122 drivers/gpu/drm/sun4i/sun4i_frontend.c static bool sun4i_frontend_format_chroma_requires_swap(uint32_t fmt) uint32_t 136 drivers/gpu/drm/sun4i/sun4i_frontend.c static bool sun4i_frontend_format_supports_tiling(uint32_t fmt) uint32_t 349 drivers/gpu/drm/sun4i/sun4i_frontend.c static int sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt, u32 *val) uint32_t 365 drivers/gpu/drm/sun4i/sun4i_frontend.c static const uint32_t sun4i_frontend_formats[] = { uint32_t 386 drivers/gpu/drm/sun4i/sun4i_frontend.c bool sun4i_frontend_format_is_supported(uint32_t fmt, uint64_t modifier) uint32_t 404 drivers/gpu/drm/sun4i/sun4i_frontend.c struct drm_plane *plane, uint32_t out_fmt) uint32_t 499 drivers/gpu/drm/sun4i/sun4i_frontend.c uint32_t luma_width, luma_height; uint32_t 500 drivers/gpu/drm/sun4i/sun4i_frontend.c uint32_t chroma_width, chroma_height; uint32_t 151 drivers/gpu/drm/sun4i/sun4i_frontend.h struct drm_plane *plane, uint32_t out_fmt); uint32_t 152 drivers/gpu/drm/sun4i/sun4i_frontend.h bool sun4i_frontend_format_is_supported(uint32_t fmt, uint64_t modifier); uint32_t 113 drivers/gpu/drm/sun4i/sun4i_layer.c uint32_t format, uint64_t modifier) uint32_t 140 drivers/gpu/drm/sun4i/sun4i_layer.c static const uint32_t sun4i_layer_formats[] = { uint32_t 168 drivers/gpu/drm/sun4i/sun4i_layer.c static const uint32_t sun4i_backend_layer_formats[] = { uint32_t 194 drivers/gpu/drm/sun4i/sun4i_layer.c const uint32_t *formats = sun4i_layer_formats; uint32_t 74 drivers/gpu/drm/tegra/plane.c uint32_t format, uint32_t 280 drivers/gpu/drm/tilcdc/tilcdc_crtc.c uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; uint32_t 735 drivers/gpu/drm/tilcdc/tilcdc_crtc.c uint32_t hbp, hfp, hsw, vbp, vfp, vsw; uint32_t 870 drivers/gpu/drm/tilcdc/tilcdc_crtc.c uint32_t stat, reg; uint32_t 424 drivers/gpu/drm/tilcdc/tilcdc_drv.c uint32_t reg; uint32_t 48 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t max_bandwidth; uint32_t 53 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t max_pixelclock; uint32_t 58 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t max_width; uint32_t 61 drivers/gpu/drm/tilcdc/tilcdc_drv.h const uint32_t *pixelformats; uint32_t 62 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t num_pixelformats; uint32_t 119 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t ac_bias; uint32_t 122 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t ac_bias_intrpt; uint32_t 125 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t dma_burst_sz; uint32_t 128 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t bpp; uint32_t 131 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t fdd; uint32_t 140 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t sync_edge; uint32_t 143 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t sync_ctrl; uint32_t 146 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t raster_order; uint32_t 149 drivers/gpu/drm/tilcdc/tilcdc_drv.h uint32_t fifo_th; uint32_t 279 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c uint32_t i2c_phandle; uint32_t 633 drivers/gpu/drm/tiny/gm12u320.c static const uint32_t gm12u320_pipe_formats[] = { uint32_t 930 drivers/gpu/drm/tiny/repaper.c static const uint32_t repaper_formats[] = { uint32_t 116 drivers/gpu/drm/ttm/ttm_agp_backend.c uint32_t page_flags) uint32_t 67 drivers/gpu/drm/ttm/ttm_bo.c uint32_t *mem_type) uint32_t 142 drivers/gpu/drm/ttm/ttm_bo.c static inline uint32_t ttm_bo_type_flags(unsigned type) uint32_t 841 drivers/gpu/drm/ttm/ttm_bo.c uint32_t mem_type, uint32_t 990 drivers/gpu/drm/ttm/ttm_bo.c static uint32_t ttm_bo_select_caching(struct ttm_mem_type_manager *man, uint32_t 991 drivers/gpu/drm/ttm/ttm_bo.c uint32_t cur_placement, uint32_t 992 drivers/gpu/drm/ttm/ttm_bo.c uint32_t proposed_placement) uint32_t 994 drivers/gpu/drm/ttm/ttm_bo.c uint32_t caching = proposed_placement & TTM_PL_MASK_CACHING; uint32_t 995 drivers/gpu/drm/ttm/ttm_bo.c uint32_t result = proposed_placement & ~TTM_PL_MASK_CACHING; uint32_t 1016 drivers/gpu/drm/ttm/ttm_bo.c uint32_t mem_type, uint32_t 1018 drivers/gpu/drm/ttm/ttm_bo.c uint32_t *masked_placement) uint32_t 1020 drivers/gpu/drm/ttm/ttm_bo.c uint32_t cur_flags = ttm_bo_type_flags(mem_type); uint32_t 1051 drivers/gpu/drm/ttm/ttm_bo.c uint32_t mem_type = TTM_PL_SYSTEM; uint32_t 1053 drivers/gpu/drm/ttm/ttm_bo.c uint32_t cur_flags = 0; uint32_t 1212 drivers/gpu/drm/ttm/ttm_bo.c uint32_t *new_flags) uint32_t 1235 drivers/gpu/drm/ttm/ttm_bo.c uint32_t *new_flags) uint32_t 1257 drivers/gpu/drm/ttm/ttm_bo.c uint32_t new_flags; uint32_t 1292 drivers/gpu/drm/ttm/ttm_bo.c uint32_t page_alignment, uint32_t 1407 drivers/gpu/drm/ttm/ttm_bo.c uint32_t page_alignment, uint32_t 1462 drivers/gpu/drm/ttm/ttm_bo.c uint32_t page_alignment, uint32_t 253 drivers/gpu/drm/ttm/ttm_bo_util.c uint32_t *dstP = uint32_t 254 drivers/gpu/drm/ttm/ttm_bo_util.c (uint32_t *) ((unsigned long)dst + (page << PAGE_SHIFT)); uint32_t 255 drivers/gpu/drm/ttm/ttm_bo_util.c uint32_t *srcP = uint32_t 256 drivers/gpu/drm/ttm/ttm_bo_util.c (uint32_t *) ((unsigned long)src + (page << PAGE_SHIFT)); uint32_t 259 drivers/gpu/drm/ttm/ttm_bo_util.c for (i = 0; i < PAGE_SIZE / sizeof(uint32_t); ++i) uint32_t 529 drivers/gpu/drm/ttm/ttm_bo_util.c pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp) uint32_t 49 drivers/gpu/drm/ttm/ttm_tt.c uint32_t page_flags = 0; uint32_t 193 drivers/gpu/drm/ttm/ttm_tt.c int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement) uint32_t 227 drivers/gpu/drm/ttm/ttm_tt.c uint32_t page_flags) uint32_t 239 drivers/gpu/drm/ttm/ttm_tt.c uint32_t page_flags) uint32_t 260 drivers/gpu/drm/ttm/ttm_tt.c uint32_t page_flags) uint32_t 277 drivers/gpu/drm/ttm/ttm_tt.c uint32_t page_flags) uint32_t 70 drivers/gpu/drm/udl/udl_drv.h uint32_t mode_buf_len; uint32_t 130 drivers/gpu/drm/udl/udl_drv.h uint32_t handle, uint64_t *offset); uint32_t 58 drivers/gpu/drm/udl/udl_fb.c static uint8_t rgb8(uint32_t col) uint32_t 67 drivers/gpu/drm/udl/udl_fb.c static uint16_t rgb16(uint32_t col) uint32_t 360 drivers/gpu/drm/udl/udl_fb.c uint32_t size; uint32_t 503 drivers/gpu/drm/udl/udl_fb.c uint32_t size; uint32_t 36 drivers/gpu/drm/udl/udl_gem.c uint32_t *handle_p) uint32_t 202 drivers/gpu/drm/udl/udl_gem.c uint32_t handle, uint64_t *offset) uint32_t 362 drivers/gpu/drm/udl/udl_modeset.c uint32_t page_flip_flags, uint32_t 68 drivers/gpu/drm/udl/udl_transfer.c static inline u16 pixel32_to_be16(const uint32_t pixel) uint32_t 81 drivers/gpu/drm/udl/udl_transfer.c pixel_val16 = pixel32_to_be16(*(const uint32_t *)pixel); uint32_t 115 drivers/gpu/drm/udl/udl_transfer.c uint32_t *device_address_ptr, uint32_t 121 drivers/gpu/drm/udl/udl_transfer.c uint32_t dev_addr = *device_address_ptr; uint32_t 217 drivers/gpu/drm/v3d/v3d_debugfs.c uint32_t cycles; uint32_t 157 drivers/gpu/drm/vc4/vc4_bo.c static uint32_t bo_page_index(size_t size) uint32_t 194 drivers/gpu/drm/vc4/vc4_bo.c uint32_t page_index = bo_page_index(size); uint32_t 197 drivers/gpu/drm/vc4/vc4_bo.c uint32_t new_size = max(vc4->bo_cache.size_list_size * 2, uint32_t 200 drivers/gpu/drm/vc4/vc4_bo.c uint32_t i; uint32_t 349 drivers/gpu/drm/vc4/vc4_bo.c uint32_t size, uint32_t 353 drivers/gpu/drm/vc4/vc4_bo.c uint32_t page_index = bo_page_index(size); uint32_t 895 drivers/gpu/drm/vc4/vc4_crtc.c uint32_t flags) uint32_t 966 drivers/gpu/drm/vc4/vc4_crtc.c uint32_t flags, uint32_t 94 drivers/gpu/drm/vc4/vc4_drv.h uint32_t size_list_size; uint32_t 181 drivers/gpu/drm/vc4/vc4_drv.h uint32_t bin_alloc_size; uint32_t 186 drivers/gpu/drm/vc4/vc4_drv.h uint32_t bin_alloc_used; uint32_t 189 drivers/gpu/drm/vc4/vc4_drv.h uint32_t bin_alloc_overflow; uint32_t 497 drivers/gpu/drm/vc4/vc4_drv.h uint32_t last_ct0ca, last_ct1ca; uint32_t 506 drivers/gpu/drm/vc4/vc4_drv.h uint32_t bo_count; uint32_t 513 drivers/gpu/drm/vc4/vc4_drv.h uint32_t rcl_write_bo_count; uint32_t 526 drivers/gpu/drm/vc4/vc4_drv.h uint32_t bo_index[2]; uint32_t 540 drivers/gpu/drm/vc4/vc4_drv.h uint32_t addr; uint32_t 544 drivers/gpu/drm/vc4/vc4_drv.h uint32_t max_index; uint32_t 548 drivers/gpu/drm/vc4/vc4_drv.h uint32_t shader_state_size; uint32_t 550 drivers/gpu/drm/vc4/vc4_drv.h uint32_t shader_state_count; uint32_t 560 drivers/gpu/drm/vc4/vc4_drv.h uint32_t tile_alloc_offset; uint32_t 562 drivers/gpu/drm/vc4/vc4_drv.h uint32_t bin_slots; uint32_t 568 drivers/gpu/drm/vc4/vc4_drv.h uint32_t ct0ca, ct0ea; uint32_t 569 drivers/gpu/drm/vc4/vc4_drv.h uint32_t ct1ca, ct1ea; uint32_t 581 drivers/gpu/drm/vc4/vc4_drv.h uint32_t shader_rec_p; uint32_t 582 drivers/gpu/drm/vc4/vc4_drv.h uint32_t shader_rec_size; uint32_t 589 drivers/gpu/drm/vc4/vc4_drv.h uint32_t uniforms_p; uint32_t 590 drivers/gpu/drm/vc4/vc4_drv.h uint32_t uniforms_size; uint32_t 654 drivers/gpu/drm/vc4/vc4_drv.h uint32_t p_offset[4]; uint32_t 668 drivers/gpu/drm/vc4/vc4_drv.h uint32_t uniforms_size; uint32_t 669 drivers/gpu/drm/vc4/vc4_drv.h uint32_t uniforms_src_size; uint32_t 670 drivers/gpu/drm/vc4/vc4_drv.h uint32_t num_texture_samples; uint32_t 673 drivers/gpu/drm/vc4/vc4_drv.h uint32_t num_uniform_addr_offsets; uint32_t 674 drivers/gpu/drm/vc4/vc4_drv.h uint32_t *uniform_addr_offsets; uint32_t 867 drivers/gpu/drm/vc4/vc4_drv.h uint32_t hindex); uint32_t 873 drivers/gpu/drm/vc4/vc4_drv.h uint32_t offset, uint8_t tiling_format, uint32_t 874 drivers/gpu/drm/vc4/vc4_drv.h uint32_t width, uint32_t height, uint8_t cpp); uint32_t 327 drivers/gpu/drm/vc4/vc4_gem.c uint32_t ct0ca, ct1ca; uint32_t 369 drivers/gpu/drm/vc4/vc4_gem.c submit_cl(struct drm_device *dev, uint32_t thread, uint32_t start, uint32_t end) uint32_t 733 drivers/gpu/drm/vc4/vc4_gem.c uint32_t *handles; uint32_t 755 drivers/gpu/drm/vc4/vc4_gem.c handles = kvmalloc_array(exec->bo_count, sizeof(uint32_t), GFP_KERNEL); uint32_t 763 drivers/gpu/drm/vc4/vc4_gem.c exec->bo_count * sizeof(uint32_t))) { uint32_t 829 drivers/gpu/drm/vc4/vc4_gem.c uint32_t bin_offset = 0; uint32_t 830 drivers/gpu/drm/vc4/vc4_gem.c uint32_t shader_rec_offset = roundup(bin_offset + args->bin_cl_size, uint32_t 832 drivers/gpu/drm/vc4/vc4_gem.c uint32_t uniforms_offset = shader_rec_offset + args->shader_rec_size; uint32_t 833 drivers/gpu/drm/vc4/vc4_gem.c uint32_t exec_size = uniforms_offset + args->uniforms_size; uint32_t 834 drivers/gpu/drm/vc4/vc4_gem.c uint32_t temp_size = exec_size + (sizeof(struct vc4_shader_state) * uint32_t 200 drivers/gpu/drm/vc4/vc4_irq.c uint32_t intctl; uint32_t 725 drivers/gpu/drm/vc4/vc4_plane.c uint32_t param = fourcc_mod_broadcom_param(fb->modifier); uint32_t 997 drivers/gpu/drm/vc4/vc4_plane.c uint32_t addr; uint32_t 1175 drivers/gpu/drm/vc4/vc4_plane.c uint32_t format, uint32_t 211 drivers/gpu/drm/vc4/vc4_qpu_defines.h ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) uint32_t 15 drivers/gpu/drm/vc4/vc4_regs.h uint32_t fieldval = (value) << field##_SHIFT; \ uint32_t 99 drivers/gpu/drm/vc4/vc4_render_cl.c static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec, uint32_t 116 drivers/gpu/drm/vc4/vc4_render_cl.c uint32_t x, uint32_t y) uint32_t 193 drivers/gpu/drm/vc4/vc4_render_cl.c uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS; uint32_t 209 drivers/gpu/drm/vc4/vc4_render_cl.c uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR; uint32_t 265 drivers/gpu/drm/vc4/vc4_render_cl.c uint32_t size, loop_body_size; uint32_t 107 drivers/gpu/drm/vc4/vc4_v3d.c uint32_t ident1 = V3D_READ(V3D_IDENT1); uint32_t 108 drivers/gpu/drm/vc4/vc4_v3d.c uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC); uint32_t 109 drivers/gpu/drm/vc4/vc4_v3d.c uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS); uint32_t 110 drivers/gpu/drm/vc4/vc4_v3d.c uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS); uint32_t 233 drivers/gpu/drm/vc4/vc4_v3d.c uint32_t size = 16 * 1024 * 1024; uint32_t 56 drivers/gpu/drm/vc4/vc4_validate.c static uint32_t uint32_t 74 drivers/gpu/drm/vc4/vc4_validate.c static uint32_t uint32_t 99 drivers/gpu/drm/vc4/vc4_validate.c size_is_lt(uint32_t width, uint32_t height, int cpp) uint32_t 106 drivers/gpu/drm/vc4/vc4_validate.c vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex) uint32_t 129 drivers/gpu/drm/vc4/vc4_validate.c vc4_use_handle(struct vc4_exec_info *exec, uint32_t gem_handles_packet_index) uint32_t 135 drivers/gpu/drm/vc4/vc4_validate.c validate_bin_pos(struct vc4_exec_info *exec, void *untrusted, uint32_t pos) uint32_t 143 drivers/gpu/drm/vc4/vc4_validate.c static uint32_t uint32_t 144 drivers/gpu/drm/vc4/vc4_validate.c gl_shader_rec_size(uint32_t pointer_bits) uint32_t 146 drivers/gpu/drm/vc4/vc4_validate.c uint32_t attribute_count = pointer_bits & 7; uint32_t 160 drivers/gpu/drm/vc4/vc4_validate.c uint32_t offset, uint8_t tiling_format, uint32_t 161 drivers/gpu/drm/vc4/vc4_validate.c uint32_t width, uint32_t height, uint8_t cpp) uint32_t 163 drivers/gpu/drm/vc4/vc4_validate.c uint32_t aligned_width, aligned_height, stride, size; uint32_t 164 drivers/gpu/drm/vc4/vc4_validate.c uint32_t utile_w = utile_width(cpp); uint32_t 165 drivers/gpu/drm/vc4/vc4_validate.c uint32_t utile_h = utile_height(cpp); uint32_t 259 drivers/gpu/drm/vc4/vc4_validate.c uint32_t length = *(uint32_t *)(untrusted + 1); uint32_t 260 drivers/gpu/drm/vc4/vc4_validate.c uint32_t offset = *(uint32_t *)(untrusted + 5); uint32_t 261 drivers/gpu/drm/vc4/vc4_validate.c uint32_t max_index = *(uint32_t *)(untrusted + 9); uint32_t 262 drivers/gpu/drm/vc4/vc4_validate.c uint32_t index_size = (*(uint8_t *)(untrusted + 0) >> 4) ? 2 : 1; uint32_t 289 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)(validated + 5) = ib->paddr + offset; uint32_t 297 drivers/gpu/drm/vc4/vc4_validate.c uint32_t length = *(uint32_t *)(untrusted + 1); uint32_t 298 drivers/gpu/drm/vc4/vc4_validate.c uint32_t base_index = *(uint32_t *)(untrusted + 5); uint32_t 299 drivers/gpu/drm/vc4/vc4_validate.c uint32_t max_index; uint32_t 324 drivers/gpu/drm/vc4/vc4_validate.c uint32_t i = exec->shader_state_count++; uint32_t 331 drivers/gpu/drm/vc4/vc4_validate.c exec->shader_state[i].addr = *(uint32_t *)untrusted; uint32_t 339 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)validated = (exec->shader_rec_p + uint32_t 354 drivers/gpu/drm/vc4/vc4_validate.c uint32_t tile_state_size; uint32_t 355 drivers/gpu/drm/vc4/vc4_validate.c uint32_t tile_count, bin_addr; uint32_t 415 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)(validated + 0) = exec->tile_alloc_offset; uint32_t 417 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)(validated + 4) = (bin_addr + vc4->bin_alloc_size - uint32_t 420 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)(validated + 8) = bin_addr; uint32_t 485 drivers/gpu/drm/vc4/vc4_validate.c uint32_t len = exec->args->bin_cl_size; uint32_t 486 drivers/gpu/drm/vc4/vc4_validate.c uint32_t dst_offset = 0; uint32_t 487 drivers/gpu/drm/vc4/vc4_validate.c uint32_t src_offset = 0; uint32_t 564 drivers/gpu/drm/vc4/vc4_validate.c uint32_t texture_handle_index, bool is_cs) uint32_t 567 drivers/gpu/drm/vc4/vc4_validate.c uint32_t p0 = *(uint32_t *)(uniform_data_u + sample->p_offset[0]); uint32_t 568 drivers/gpu/drm/vc4/vc4_validate.c uint32_t p1 = *(uint32_t *)(uniform_data_u + sample->p_offset[1]); uint32_t 569 drivers/gpu/drm/vc4/vc4_validate.c uint32_t p2 = (sample->p_offset[2] != ~0 ? uint32_t 570 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)(uniform_data_u + sample->p_offset[2]) : 0); uint32_t 571 drivers/gpu/drm/vc4/vc4_validate.c uint32_t p3 = (sample->p_offset[3] != ~0 ? uint32_t 572 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)(uniform_data_u + sample->p_offset[3]) : 0); uint32_t 573 drivers/gpu/drm/vc4/vc4_validate.c uint32_t *validated_p0 = exec->uniforms_v + sample->p_offset[0]; uint32_t 574 drivers/gpu/drm/vc4/vc4_validate.c uint32_t offset = p0 & VC4_TEX_P0_OFFSET_MASK; uint32_t 575 drivers/gpu/drm/vc4/vc4_validate.c uint32_t miplevels = VC4_GET_FIELD(p0, VC4_TEX_P0_MIPLVLS); uint32_t 576 drivers/gpu/drm/vc4/vc4_validate.c uint32_t width = VC4_GET_FIELD(p1, VC4_TEX_P1_WIDTH); uint32_t 577 drivers/gpu/drm/vc4/vc4_validate.c uint32_t height = VC4_GET_FIELD(p1, VC4_TEX_P1_HEIGHT); uint32_t 578 drivers/gpu/drm/vc4/vc4_validate.c uint32_t cpp, tiling_format, utile_w, utile_h; uint32_t 579 drivers/gpu/drm/vc4/vc4_validate.c uint32_t i; uint32_t 580 drivers/gpu/drm/vc4/vc4_validate.c uint32_t cube_map_stride = 0; uint32_t 588 drivers/gpu/drm/vc4/vc4_validate.c uint32_t remaining_size = tex->base.size - p0; uint32_t 687 drivers/gpu/drm/vc4/vc4_validate.c uint32_t level_width = max(width >> i, 1u); uint32_t 688 drivers/gpu/drm/vc4/vc4_validate.c uint32_t level_height = max(height >> i, 1u); uint32_t 689 drivers/gpu/drm/vc4/vc4_validate.c uint32_t aligned_width, aligned_height; uint32_t 690 drivers/gpu/drm/vc4/vc4_validate.c uint32_t level_size; uint32_t 748 drivers/gpu/drm/vc4/vc4_validate.c uint32_t *src_handles; uint32_t 750 drivers/gpu/drm/vc4/vc4_validate.c static const uint32_t shader_reloc_offsets[] = { uint32_t 755 drivers/gpu/drm/vc4/vc4_validate.c uint32_t shader_reloc_count = ARRAY_SIZE(shader_reloc_offsets); uint32_t 757 drivers/gpu/drm/vc4/vc4_validate.c uint32_t nr_attributes, nr_relocs, packet_size; uint32_t 825 drivers/gpu/drm/vc4/vc4_validate.c uint32_t o = shader_reloc_offsets[i]; uint32_t 826 drivers/gpu/drm/vc4/vc4_validate.c uint32_t src_offset = *(uint32_t *)(pkt_u + o); uint32_t 827 drivers/gpu/drm/vc4/vc4_validate.c uint32_t *texture_handles_u; uint32_t 829 drivers/gpu/drm/vc4/vc4_validate.c uint32_t tex, uni; uint32_t 831 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset; uint32_t 875 drivers/gpu/drm/vc4/vc4_validate.c uint32_t o = validated_shader->uniform_addr_offsets[uni]; uint32_t 876 drivers/gpu/drm/vc4/vc4_validate.c ((uint32_t *)exec->uniforms_v)[o] = exec->uniforms_p; uint32_t 879 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p; uint32_t 889 drivers/gpu/drm/vc4/vc4_validate.c uint32_t o = 36 + i * 8; uint32_t 890 drivers/gpu/drm/vc4/vc4_validate.c uint32_t offset = *(uint32_t *)(pkt_u + o + 0); uint32_t 891 drivers/gpu/drm/vc4/vc4_validate.c uint32_t attr_size = *(uint8_t *)(pkt_u + o + 4) + 1; uint32_t 892 drivers/gpu/drm/vc4/vc4_validate.c uint32_t stride = *(uint8_t *)(pkt_u + o + 5); uint32_t 893 drivers/gpu/drm/vc4/vc4_validate.c uint32_t max_index; uint32_t 899 drivers/gpu/drm/vc4/vc4_validate.c stride |= (*(uint32_t *)(pkt_u + 100 + i * 4)) & ~0xff; uint32_t 919 drivers/gpu/drm/vc4/vc4_validate.c *(uint32_t *)(pkt_v + o) = vbo->paddr + offset; uint32_t 929 drivers/gpu/drm/vc4/vc4_validate.c uint32_t i; uint32_t 51 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t ip; uint32_t 54 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t max_ip; uint32_t 67 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t live_min_clamp_offsets[LIVE_REG_COUNT]; uint32_t 69 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t live_immediates[LIVE_REG_COUNT]; uint32_t 100 drivers/gpu/drm/vc4/vc4_validate_shaders.c static uint32_t uint32_t 101 drivers/gpu/drm/vc4/vc4_validate_shaders.c waddr_to_live_reg_index(uint32_t waddr, bool is_b) uint32_t 115 drivers/gpu/drm/vc4/vc4_validate_shaders.c static uint32_t uint32_t 118 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); uint32_t 119 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); uint32_t 120 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A); uint32_t 121 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); uint32_t 134 drivers/gpu/drm/vc4/vc4_validate_shaders.c live_reg_is_upper_half(uint32_t lri) uint32_t 141 drivers/gpu/drm/vc4/vc4_validate_shaders.c is_tmu_submit(uint32_t waddr) uint32_t 148 drivers/gpu/drm/vc4/vc4_validate_shaders.c is_tmu_write(uint32_t waddr) uint32_t 159 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t s = validated_shader->num_texture_samples; uint32_t 188 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr = (is_mul ? uint32_t 191 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A); uint32_t 192 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); uint32_t 196 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); uint32_t 199 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B); uint32_t 200 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t clamp_reg, clamp_offset; uint32_t 289 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t o = validated_shader->num_uniform_addr_offsets; uint32_t 290 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t num_uniforms = validated_shader->uniforms_size / 4; uint32_t 391 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr = (is_mul ? uint32_t 394 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); uint32_t 400 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD); uint32_t 401 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t cond_mul = QPU_GET_FIELD(inst, QPU_COND_MUL); uint32_t 482 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD); uint32_t 483 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD); uint32_t 484 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL); uint32_t 485 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD); uint32_t 486 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); uint32_t 487 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B); uint32_t 488 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A); uint32_t 489 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); uint32_t 490 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); uint32_t 492 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t lri_add_a, lri_add, lri_mul; uint32_t 557 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD); uint32_t 558 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL); uint32_t 581 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD); uint32_t 582 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL); uint32_t 604 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A); uint32_t 605 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); uint32_t 606 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); uint32_t 637 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t max_branch_target = 0; uint32_t 644 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); uint32_t 645 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t after_delay_ip = ip + 4; uint32_t 646 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t branch_target_ip; uint32_t 747 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t ip = validation_state->ip; uint32_t 783 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t last_thread_switch_ip = -3; uint32_t 784 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t ip; uint32_t 809 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); uint32_t 233 drivers/gpu/drm/vgem/vgem_drv.c uint32_t handle, uint64_t *offset) uint32_t 64 drivers/gpu/drm/via/via_dma.c *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \ uint32_t 65 drivers/gpu/drm/via/via_dma.c *((uint32_t *)(vb) + 1) = (nData); \ uint32_t 66 drivers/gpu/drm/via/via_dma.c vb = ((uint32_t *)vb) + 2; \ uint32_t 89 drivers/gpu/drm/via/via_dma.c static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv) uint32_t 91 drivers/gpu/drm/via/via_dma.c uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; uint32_t 92 drivers/gpu/drm/via/via_dma.c uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; uint32_t 103 drivers/gpu/drm/via/via_dma.c static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv) uint32_t 105 drivers/gpu/drm/via/via_dma.c uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; uint32_t 106 drivers/gpu/drm/via/via_dma.c uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; uint32_t 120 drivers/gpu/drm/via/via_dma.c uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; uint32_t 121 drivers/gpu/drm/via/via_dma.c uint32_t cur_addr, hw_addr, next_addr; uint32_t 122 drivers/gpu/drm/via/via_dma.c volatile uint32_t *hw_addr_ptr; uint32_t 123 drivers/gpu/drm/via/via_dma.c uint32_t count; uint32_t 149 drivers/gpu/drm/via/via_dma.c static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv, uint32_t 159 drivers/gpu/drm/via/via_dma.c return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); uint32_t 228 drivers/gpu/drm/via/via_dma.c (volatile uint32_t *)((char *)dev_priv->mmio->handle + uint32_t 270 drivers/gpu/drm/via/via_dma.c uint32_t *vb; uint32_t 293 drivers/gpu/drm/via/via_dma.c via_verify_command_stream((uint32_t *) dev_priv->pci_buf, uint32_t 360 drivers/gpu/drm/via/via_dma.c via_verify_command_stream((uint32_t *) dev_priv->pci_buf, uint32_t 366 drivers/gpu/drm/via/via_dma.c via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, uint32_t 384 drivers/gpu/drm/via/via_dma.c static inline uint32_t *via_align_buffer(drm_via_private_t *dev_priv, uint32_t 385 drivers/gpu/drm/via/via_dma.c uint32_t * vb, int qw_count) uint32_t 397 drivers/gpu/drm/via/via_dma.c static inline uint32_t *via_get_dma(drm_via_private_t *dev_priv) uint32_t 399 drivers/gpu/drm/via/via_dma.c return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); uint32_t 408 drivers/gpu/drm/via/via_dma.c uint32_t pause_addr_hi, uint32_t pause_addr_lo, uint32_t 412 drivers/gpu/drm/via/via_dma.c volatile uint32_t *paused_at = dev_priv->last_pause_ptr; uint32_t 413 drivers/gpu/drm/via/via_dma.c uint32_t reader, ptr; uint32_t 414 drivers/gpu/drm/via/via_dma.c uint32_t diff; uint32_t 418 drivers/gpu/drm/via/via_dma.c (void) *(volatile uint32_t *)(via_get_dma(dev_priv) - 1); uint32_t 426 drivers/gpu/drm/via/via_dma.c dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; uint32_t 437 drivers/gpu/drm/via/via_dma.c diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; uint32_t 444 drivers/gpu/drm/via/via_dma.c diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; uint32_t 451 drivers/gpu/drm/via/via_dma.c diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; uint32_t 487 drivers/gpu/drm/via/via_dma.c static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type, uint32_t 488 drivers/gpu/drm/via/via_dma.c uint32_t addr, uint32_t *cmd_addr_hi, uint32_t 489 drivers/gpu/drm/via/via_dma.c uint32_t *cmd_addr_lo, int skip_wait) uint32_t 491 drivers/gpu/drm/via/via_dma.c uint32_t agp_base; uint32_t 492 drivers/gpu/drm/via/via_dma.c uint32_t cmd_addr, addr_lo, addr_hi; uint32_t 493 drivers/gpu/drm/via/via_dma.c uint32_t *vb; uint32_t 494 drivers/gpu/drm/via/via_dma.c uint32_t qw_pad_count; uint32_t 502 drivers/gpu/drm/via/via_dma.c agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; uint32_t 519 drivers/gpu/drm/via/via_dma.c uint32_t pause_addr_lo, pause_addr_hi; uint32_t 520 drivers/gpu/drm/via/via_dma.c uint32_t start_addr, start_addr_lo; uint32_t 521 drivers/gpu/drm/via/via_dma.c uint32_t end_addr, end_addr_lo; uint32_t 522 drivers/gpu/drm/via/via_dma.c uint32_t command; uint32_t 523 drivers/gpu/drm/via/via_dma.c uint32_t agp_base; uint32_t 524 drivers/gpu/drm/via/via_dma.c uint32_t ptr; uint32_t 525 drivers/gpu/drm/via/via_dma.c uint32_t reader; uint32_t 530 drivers/gpu/drm/via/via_dma.c agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; uint32_t 544 drivers/gpu/drm/via/via_dma.c (void) *(volatile uint32_t *)dev_priv->last_pause_ptr; uint32_t 564 drivers/gpu/drm/via/via_dma.c dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; uint32_t 578 drivers/gpu/drm/via/via_dma.c uint32_t *vb; uint32_t 588 drivers/gpu/drm/via/via_dma.c uint32_t *vb = via_get_dma(dev_priv); uint32_t 596 drivers/gpu/drm/via/via_dma.c uint32_t agp_base; uint32_t 597 drivers/gpu/drm/via/via_dma.c uint32_t pause_addr_lo, pause_addr_hi; uint32_t 598 drivers/gpu/drm/via/via_dma.c uint32_t jump_addr_lo, jump_addr_hi; uint32_t 599 drivers/gpu/drm/via/via_dma.c volatile uint32_t *last_pause_ptr; uint32_t 600 drivers/gpu/drm/via/via_dma.c uint32_t dma_low_save1, dma_low_save2; uint32_t 602 drivers/gpu/drm/via/via_dma.c agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; uint32_t 657 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_flush(drm_via_private_t *dev_priv, uint32_t cmd_type) uint32_t 659 drivers/gpu/drm/via/via_dma.c uint32_t pause_addr_lo, pause_addr_hi; uint32_t 684 drivers/gpu/drm/via/via_dma.c uint32_t tmp_size, count; uint32_t 53 drivers/gpu/drm/via/via_dmablit.c uint32_t mem_addr; uint32_t 54 drivers/gpu/drm/via/via_dmablit.c uint32_t dev_addr; uint32_t 55 drivers/gpu/drm/via/via_dmablit.c uint32_t size; uint32_t 56 drivers/gpu/drm/via/via_dmablit.c uint32_t next; uint32_t 108 drivers/gpu/drm/via/via_dmablit.c uint32_t fb_addr = xfer->fb_addr; uint32_t 109 drivers/gpu/drm/via/via_dmablit.c uint32_t cur_fb; uint32_t 141 drivers/gpu/drm/via/via_dmablit.c desc_ptr->next = (uint32_t) next; uint32_t 319 drivers/gpu/drm/via/via_dmablit.c uint32_t status = 0; uint32_t 395 drivers/gpu/drm/via/via_dmablit.c via_dmablit_active(drm_via_blitq_t *blitq, int engine, uint32_t handle, wait_queue_head_t **queue) uint32_t 398 drivers/gpu/drm/via/via_dmablit.c uint32_t slot; uint32_t 427 drivers/gpu/drm/via/via_dmablit.c via_dmablit_sync(struct drm_device *dev, uint32_t handle, int engine) uint32_t 49 drivers/gpu/drm/via/via_dmablit.h uint32_t free_on_sequence; uint32_t 63 drivers/gpu/drm/via/via_dmablit.h uint32_t cur_blit_handle; uint32_t 64 drivers/gpu/drm/via/via_dmablit.h uint32_t done_blit_handle; uint32_t 61 drivers/gpu/drm/via/via_drv.h typedef uint32_t maskarray_t[5]; uint32_t 65 drivers/gpu/drm/via/via_drv.h uint32_t pending_mask; uint32_t 66 drivers/gpu/drm/via/via_drv.h uint32_t enable_mask; uint32_t 81 drivers/gpu/drm/via/via_drv.h uint32_t dma_wrap; uint32_t 82 drivers/gpu/drm/via/via_drv.h volatile uint32_t *last_pause_ptr; uint32_t 83 drivers/gpu/drm/via/via_drv.h volatile uint32_t *hw_addr_ptr; uint32_t 91 drivers/gpu/drm/via/via_drv.h const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE]; uint32_t 92 drivers/gpu/drm/via/via_drv.h uint32_t num_fire_offsets; uint32_t 97 drivers/gpu/drm/via/via_drv.h uint32_t irq_enable_mask; uint32_t 98 drivers/gpu/drm/via/via_drv.h uint32_t irq_pending_mask; uint32_t 110 drivers/gpu/drm/via/via_drv.h uint32_t dma_diff; uint32_t 239 drivers/gpu/drm/via/via_verifier.c eat_words(const uint32_t **buf, const uint32_t *buf_end, unsigned num_words) uint32_t 306 drivers/gpu/drm/via/via_verifier.c uint32_t *addr, *pitch, *height, tex; uint32_t 348 drivers/gpu/drm/via/via_verifier.c investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) uint32_t 350 drivers/gpu/drm/via/via_verifier.c register uint32_t tmp, *tmp_addr; uint32_t 521 drivers/gpu/drm/via/via_verifier.c via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end, uint32_t 526 drivers/gpu/drm/via/via_verifier.c uint32_t a_fire, bcmd, dw_count; uint32_t 529 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 625 drivers/gpu/drm/via/via_verifier.c via_check_header2(uint32_t const **buffer, const uint32_t *buf_end, uint32_t 628 drivers/gpu/drm/via/via_verifier.c uint32_t cmd; uint32_t 631 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 717 drivers/gpu/drm/via/via_verifier.c via_parse_header2(drm_via_private_t *dev_priv, uint32_t const **buffer, uint32_t 718 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf_end, int *fire_count) uint32_t 720 drivers/gpu/drm/via/via_verifier.c uint32_t cmd; uint32_t 721 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 722 drivers/gpu/drm/via/via_verifier.c const uint32_t *next_fire; uint32_t 765 drivers/gpu/drm/via/via_verifier.c static __inline__ int verify_mmio_address(uint32_t address) uint32_t 784 drivers/gpu/drm/via/via_verifier.c verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end, uint32_t 785 drivers/gpu/drm/via/via_verifier.c uint32_t dwords) uint32_t 787 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 804 drivers/gpu/drm/via/via_verifier.c via_check_header1(uint32_t const **buffer, const uint32_t * buf_end) uint32_t 806 drivers/gpu/drm/via/via_verifier.c uint32_t cmd; uint32_t 807 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 836 drivers/gpu/drm/via/via_verifier.c via_parse_header1(drm_via_private_t *dev_priv, uint32_t const **buffer, uint32_t 837 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf_end) uint32_t 839 drivers/gpu/drm/via/via_verifier.c register uint32_t cmd; uint32_t 840 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 854 drivers/gpu/drm/via/via_verifier.c via_check_vheader5(uint32_t const **buffer, const uint32_t *buf_end) uint32_t 856 drivers/gpu/drm/via/via_verifier.c uint32_t data; uint32_t 857 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 887 drivers/gpu/drm/via/via_verifier.c via_parse_vheader5(drm_via_private_t *dev_priv, uint32_t const **buffer, uint32_t 888 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf_end) uint32_t 890 drivers/gpu/drm/via/via_verifier.c uint32_t addr, count, i; uint32_t 891 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 905 drivers/gpu/drm/via/via_verifier.c via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end) uint32_t 907 drivers/gpu/drm/via/via_verifier.c uint32_t data; uint32_t 908 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 909 drivers/gpu/drm/via/via_verifier.c uint32_t i; uint32_t 942 drivers/gpu/drm/via/via_verifier.c via_parse_vheader6(drm_via_private_t *dev_priv, uint32_t const **buffer, uint32_t 943 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf_end) uint32_t 946 drivers/gpu/drm/via/via_verifier.c uint32_t addr, count, i; uint32_t 947 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf = *buffer; uint32_t 963 drivers/gpu/drm/via/via_verifier.c via_verify_command_stream(const uint32_t * buf, unsigned int size, uint32_t 970 drivers/gpu/drm/via/via_verifier.c uint32_t cmd; uint32_t 971 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf_end = buf + (size >> 2); uint32_t 1039 drivers/gpu/drm/via/via_verifier.c via_parse_command_stream(struct drm_device *dev, const uint32_t *buf, uint32_t 1044 drivers/gpu/drm/via/via_verifier.c uint32_t cmd; uint32_t 1045 drivers/gpu/drm/via/via_verifier.c const uint32_t *buf_end = buf + (size >> 2); uint32_t 38 drivers/gpu/drm/via/via_verifier.h uint32_t z_addr; uint32_t 39 drivers/gpu/drm/via/via_verifier.h uint32_t d_addr; uint32_t 40 drivers/gpu/drm/via/via_verifier.h uint32_t t_addr[2][10]; uint32_t 41 drivers/gpu/drm/via/via_verifier.h uint32_t pitch[2][10]; uint32_t 42 drivers/gpu/drm/via/via_verifier.h uint32_t height[2][10]; uint32_t 43 drivers/gpu/drm/via/via_verifier.h uint32_t tex_level_lo[2]; uint32_t 44 drivers/gpu/drm/via/via_verifier.h uint32_t tex_level_hi[2]; uint32_t 45 drivers/gpu/drm/via/via_verifier.h uint32_t tex_palette_size[2]; uint32_t 46 drivers/gpu/drm/via/via_verifier.h uint32_t tex_npot[2]; uint32_t 52 drivers/gpu/drm/via/via_verifier.h uint32_t vertex_count; uint32_t 54 drivers/gpu/drm/via/via_verifier.h const uint32_t *buf_start; uint32_t 57 drivers/gpu/drm/via/via_verifier.h extern int via_verify_command_stream(const uint32_t *buf, unsigned int size, uint32_t 59 drivers/gpu/drm/via/via_verifier.h extern int via_parse_command_stream(struct drm_device *dev, const uint32_t *buf, uint32_t 54 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t format; uint32_t 55 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t width; uint32_t 56 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t height; uint32_t 61 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t target; uint32_t 62 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t bind; uint32_t 63 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t depth; uint32_t 64 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t array_size; uint32_t 65 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t last_level; uint32_t 66 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t nr_samples; uint32_t 67 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t flags; uint32_t 72 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t hw_res_handle; uint32_t 75 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t mapped; uint32_t 114 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t data_size; uint32_t 162 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t id; uint32_t 163 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t max_version; uint32_t 164 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t max_size; uint32_t 170 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t id; uint32_t 171 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t version; uint32_t 172 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t size; uint32_t 185 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t num_scanouts; uint32_t 209 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t num_capsets; uint32_t 214 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t ctx_id; uint32_t 238 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t *handle_p); uint32_t 252 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t handle, uint64_t *offset_p); uint32_t 262 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t resource_id); uint32_t 270 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t resource_id, uint32_t 271 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t x, uint32_t y, uint32_t 272 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t width, uint32_t height); uint32_t 274 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t scanout_id, uint32_t resource_id, uint32_t 275 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t width, uint32_t height, uint32_t 276 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t x, uint32_t y); uint32_t 292 drivers/gpu/drm/virtio/virtgpu_drv.h void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id, uint32_t 293 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t nlen, const char *name); uint32_t 295 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t id); uint32_t 297 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t ctx_id, uint32_t 298 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t resource_id); uint32_t 300 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t ctx_id, uint32_t 301 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t resource_id); uint32_t 303 drivers/gpu/drm/virtio/virtgpu_drv.h void *data, uint32_t data_size, uint32_t 304 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t ctx_id, struct virtio_gpu_fence *fence); uint32_t 306 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t resource_id, uint32_t ctx_id, uint32_t 307 drivers/gpu/drm/virtio/virtgpu_drv.h uint64_t offset, uint32_t level, uint32_t 312 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t ctx_id, uint32_t 313 drivers/gpu/drm/virtio/virtgpu_drv.h uint64_t offset, uint32_t level, uint32_t 337 drivers/gpu/drm/virtio/virtgpu_drv.h uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc); uint32_t 59 drivers/gpu/drm/virtio/virtgpu_gem.c uint32_t *handle_p) uint32_t 91 drivers/gpu/drm/virtio/virtgpu_gem.c uint32_t pitch; uint32_t 119 drivers/gpu/drm/virtio/virtgpu_gem.c uint32_t handle, uint64_t *offset_p) uint32_t 114 drivers/gpu/drm/virtio/virtgpu_ioctl.c uint32_t *bo_handles = NULL; uint32_t 164 drivers/gpu/drm/virtio/virtgpu_ioctl.c sizeof(uint32_t), GFP_KERNEL); uint32_t 175 drivers/gpu/drm/virtio/virtgpu_ioctl.c exbuf->num_bo_handles * sizeof(uint32_t))) { uint32_t 282 drivers/gpu/drm/virtio/virtgpu_ioctl.c uint32_t handle = 0; uint32_t 55 drivers/gpu/drm/virtio/virtgpu_kms.c uint32_t nlen, const char *name) uint32_t 67 drivers/gpu/drm/virtio/virtgpu_kms.c uint32_t ctx_id) uint32_t 185 drivers/gpu/drm/virtio/virtgpu_kms.c vgdev->num_scanouts = min_t(uint32_t, num_scanouts, uint32_t 36 drivers/gpu/drm/virtio/virtgpu_object.c uint32_t *resid) uint32_t 59 drivers/gpu/drm/virtio/virtgpu_object.c static void virtio_gpu_resource_id_put(struct virtio_gpu_device *vgdev, uint32_t id) uint32_t 32 drivers/gpu/drm/virtio/virtgpu_plane.c static const uint32_t virtio_gpu_formats[] = { uint32_t 36 drivers/gpu/drm/virtio/virtgpu_plane.c static const uint32_t virtio_gpu_cursor_formats[] = { uint32_t 40 drivers/gpu/drm/virtio/virtgpu_plane.c uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc) uint32_t 42 drivers/gpu/drm/virtio/virtgpu_plane.c uint32_t format; uint32_t 98 drivers/gpu/drm/virtio/virtgpu_plane.c uint32_t handle; uint32_t 188 drivers/gpu/drm/virtio/virtgpu_plane.c uint32_t handle; uint32_t 273 drivers/gpu/drm/virtio/virtgpu_plane.c const uint32_t *formats; uint32_t 71 drivers/gpu/drm/virtio/virtgpu_ttm.c uint32_t flags) uint32_t 115 drivers/gpu/drm/virtio/virtgpu_ttm.c static int virtio_gpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, uint32_t 234 drivers/gpu/drm/virtio/virtgpu_ttm.c uint32_t page_flags) uint32_t 410 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t resource_id) uint32_t 425 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t resource_id, uint32_t 441 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t scanout_id, uint32_t resource_id, uint32_t 442 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t width, uint32_t height, uint32_t 443 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t x, uint32_t y) uint32_t 463 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t resource_id, uint32_t 464 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t x, uint32_t y, uint32_t 465 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t width, uint32_t height) uint32_t 515 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t resource_id, uint32_t 517 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t nents, uint32_t 626 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t scanout = le32_to_cpu(cmd->scanout); uint32_t 796 drivers/gpu/drm/virtio/virtgpu_vq.c void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id, uint32_t 797 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t nlen, const char *name) uint32_t 814 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t id) uint32_t 828 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t ctx_id, uint32_t 829 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t resource_id) uint32_t 845 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t ctx_id, uint32_t 846 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t resource_id) uint32_t 892 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t ctx_id, uint32_t 893 drivers/gpu/drm/virtio/virtgpu_vq.c uint64_t offset, uint32_t level, uint32_t 920 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t resource_id, uint32_t ctx_id, uint32_t 921 drivers/gpu/drm/virtio/virtgpu_vq.c uint64_t offset, uint32_t level, uint32_t 942 drivers/gpu/drm/virtio/virtgpu_vq.c void *data, uint32_t data_size, uint32_t 943 drivers/gpu/drm/virtio/virtgpu_vq.c uint32_t ctx_id, struct virtio_gpu_fence *fence) uint32_t 21 drivers/gpu/drm/vkms/vkms_composer.c static uint32_t compute_crc(void *vaddr_out, struct vkms_composer *composer) uint32_t 111 drivers/gpu/drm/vkms/vkms_composer.c static uint32_t _vkms_get_crc(struct vkms_composer *primary_composer, uint32_t 73 drivers/gpu/drm/vmwgfx/ttm_lock.h uint32_t flags; uint32_t 245 drivers/gpu/drm/vmwgfx/ttm_object.c ttm_base_object_noref_lookup(struct ttm_object_file *tfile, uint32_t key) uint32_t 264 drivers/gpu/drm/vmwgfx/ttm_object.c uint32_t key) uint32_t 285 drivers/gpu/drm/vmwgfx/ttm_object.c ttm_base_object_lookup_for_ref(struct ttm_object_device *tdev, uint32_t key) uint32_t 684 drivers/gpu/drm/vmwgfx/ttm_object.c uint32_t handle, uint32_t flags, uint32_t 197 drivers/gpu/drm/vmwgfx/ttm_object.h *tfile, uint32_t key); uint32_t 211 drivers/gpu/drm/vmwgfx/ttm_object.h ttm_base_object_lookup_for_ref(struct ttm_object_device *tdev, uint32_t key); uint32_t 349 drivers/gpu/drm/vmwgfx/ttm_object.h uint32_t handle, uint32_t flags, uint32_t 363 drivers/gpu/drm/vmwgfx/ttm_object.h ttm_base_object_noref_lookup(struct ttm_object_file *tfile, uint32_t key); uint32_t 97 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t new_flags; uint32_t 146 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t new_flags; uint32_t 223 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t new_flags; uint32_t 341 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t old_mem_type = bo->mem.mem_type; uint32_t 592 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t size, uint32_t 594 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t *handle, uint32_t 683 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t flags) uint32_t 724 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c static int vmw_user_bo_synccpu_release(uint32_t handle, uint32_t 726 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t flags) uint32_t 825 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t handle; uint32_t 890 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t handle, struct vmw_buffer_object **out, uint32_t 974 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t *handle) uint32_t 1070 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct drm_device *dev, uint32_t handle, uint32_t 1099 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c uint32_t handle) uint32_t 517 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c uint32_t dummy; uint32_t 379 drivers/gpu/drm/vmwgfx/vmwgfx_context.c uint32_t submit_size; uint32_t 586 drivers/gpu/drm/vmwgfx/vmwgfx_context.c uint32_t submit_size; uint32_t 279 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static void vmw_print_capabilities2(uint32_t capabilities2) uint32_t 288 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static void vmw_print_capabilities(uint32_t capabilities) uint32_t 528 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c uint32_t width; uint32_t 529 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c uint32_t height; uint32_t 534 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); uint32_t 535 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); uint32_t 615 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c uint32_t svga_id; uint32_t 630 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->last_read_seqno = (uint32_t) -100; uint32_t 211 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t *image; uint32_t 220 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t format; uint32_t 221 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; uint32_t 224 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t num_sizes; uint32_t 226 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t array_size; uint32_t 231 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t multisample_count; uint32_t 250 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t capabilities; uint32_t 270 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t handle; uint32_t 378 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t *cmd_bounce; uint32_t 379 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t cmd_bounce_size; uint32_t 383 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t *buf_start; uint32_t 402 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t width; uint32_t 403 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t height; uint32_t 404 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t primary; uint32_t 405 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t pos_x; uint32_t 406 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t pos_y; uint32_t 443 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t vram_start; uint32_t 444 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t vram_size; uint32_t 445 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t prim_bb_mem; uint32_t 446 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t mmio_start; uint32_t 447 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t mmio_size; uint32_t 448 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t fb_max_width; uint32_t 449 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t fb_max_height; uint32_t 450 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t texture_max_width; uint32_t 451 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t texture_max_height; uint32_t 452 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t stdu_max_width; uint32_t 453 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t stdu_max_height; uint32_t 454 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t initial_width; uint32_t 455 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t initial_height; uint32_t 457 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t capabilities; uint32_t 458 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t capabilities2; uint32_t 459 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t max_gmr_ids; uint32_t 460 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t max_gmr_pages; uint32_t 461 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t max_mob_pages; uint32_t 462 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t max_mob_size; uint32_t 463 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t memory_size; uint32_t 477 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t vga_width; uint32_t 478 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t vga_height; uint32_t 479 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t vga_bpp; uint32_t 480 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t vga_bpl; uint32_t 481 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t vga_pitchlock; uint32_t 483 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t num_displays; uint32_t 526 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t last_read_seqno; uint32_t 528 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t irq_mask; /* Updates protected by waiter_lock */ uint32_t 534 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t traces_state; uint32_t 535 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t enable_state; uint32_t 536 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t config_done_state; uint32_t 579 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t query_cid; uint32_t 580 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t query_cid_valid; uint32_t 591 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t used_memory_size; uint32_t 633 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h unsigned int offset, uint32_t value) uint32_t 641 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h static inline uint32_t vmw_read(struct vmw_private *dev_priv, uint32_t 683 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t handle, uint32_t 689 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t handle, uint32_t 695 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t handle, uint32_t 704 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t *inout_id, uint32_t 772 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t size, uint32_t 774 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t *handle, uint32_t 779 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t *handle); uint32_t 787 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t id, struct vmw_buffer_object **out, uint32_t 883 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, int ctx_id); uint32_t 884 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes); uint32_t 885 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes); uint32_t 887 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t *seqno); uint32_t 888 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_fifo_ping_host_locked(struct vmw_private *, uint32_t reason); uint32_t 889 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason); uint32_t 893 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t cid); uint32_t 990 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t command_size, uint32_t 992 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t dx_context_handle, uint32_t 996 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t flags); uint32_t 1004 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t *p_handle); uint32_t 1011 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t fence_handle, uint32_t 1021 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t seqno, bool interruptible, uint32_t 1026 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t seqno); uint32_t 1030 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t seqno, uint32_t 1052 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t seqno); uint32_t 1054 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t signaled_seqno); uint32_t 1056 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct vmw_marker_queue *queue, uint32_t us); uint32_t 1086 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t pitch, uint32_t 1087 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t height); uint32_t 1095 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t sid, int32_t destX, int32_t destY, uint32_t 1097 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t num_clips); uint32_t 1110 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct drm_device *dev, uint32_t handle, uint32_t 1114 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t handle); uint32_t 1130 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_claim(struct vmw_private *dev_priv, uint32_t *out); uint32_t 1131 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_unref(struct vmw_private *dev_priv, uint32_t stream_id); uint32_t 1151 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t handle, uint32_t flags, uint32_t 1220 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t handle, int *id); uint32_t 1224 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t user_accounting_size, uint32_t 1228 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t num_mip_levels, uint32_t 1229 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t multisample_count, uint32_t 1230 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t array_size, uint32_t 555 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static void vmw_resource_relocations_apply(uint32_t *cb, uint32_t 647 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t *id_loc, uint32_t 832 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c VMW_DECLARE_CMD_VAR(*cmd, uint32_t) = uint32_t 1160 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t handle = *id; uint32_t 1215 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t handle = ptr->gmrId; uint32_t 1521 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t bo_size; uint32_t 1576 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t i; uint32_t 1577 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t maxnum; uint32_t 1685 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t header; uint32_t 1710 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_resource *res, uint32_t *buf_id, uint32_t 1750 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c *converter, uint32_t *res_id, uint32_t *buf_id, uint32_t 2801 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c void *buf, uint32_t *size) uint32_t 2803 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t size_remaining = *size; uint32_t 2804 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t cmd_id; uint32_t 2806 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c cmd_id = ((uint32_t *)buf)[0]; uint32_t 2809 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdUpdate); uint32_t 2812 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdDefineGMRFB); uint32_t 2815 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen); uint32_t 2818 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen); uint32_t 3203 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t *size) uint32_t 3205 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t cmd_id; uint32_t 3206 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t size_remaining = *size; uint32_t 3212 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c cmd_id = ((uint32_t *)buf)[0]; uint32_t 3269 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t size) uint32_t 3325 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t size) uint32_t 3365 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t *p_handle) uint32_t 3367 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t sequence; uint32_t 3420 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_fence_obj *fence, uint32_t fence_handle, uint32_t 3597 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t handle) uint32_t 3633 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t command_size, uint64_t throttle_us, uint32_t 3634 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t dx_context_handle, uint32_t 3636 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_fence_obj **out_fence, uint32_t flags) uint32_t 3641 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c uint32_t handle = 0; uint32_t 4021 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c arg->context_handle = (uint32_t) -1; uint32_t 45 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t pending_actions[VMW_ACTION_MAX]; uint32_t 80 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t *tv_sec; uint32_t 81 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t *tv_usec; uint32_t 470 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t seqno, new_seqno; uint32_t 551 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t seqno, uint32_t 602 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t seqno, uint32_t 604 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t *p_handle) uint32_t 1018 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t *tv_sec, uint32_t 1019 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t *tv_usec, uint32_t 1052 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t flags, uint32_t 1115 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c uint32_t handle; uint32_t 100 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h uint32_t seqno, uint32_t 105 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h uint32_t sequence, uint32_t 107 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h uint32_t *p_handle); uint32_t 129 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h uint32_t *tv_sec, uint32_t 130 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h uint32_t *tv_usec, uint32_t 42 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t fifo_min, hwversion; uint32_t 49 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t result; uint32_t 91 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t caps; uint32_t 106 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t max; uint32_t 107 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t min; uint32_t 168 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) uint32_t 208 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) uint32_t 211 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); uint32_t 212 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); uint32_t 213 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); uint32_t 214 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP); uint32_t 220 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t bytes, bool interruptible, uint32_t 253 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t bytes, bool interruptible, uint32_t 300 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t bytes) uint32_t 304 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t max; uint32_t 305 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t min; uint32_t 306 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t next_cmd; uint32_t 307 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; uint32_t 324 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP); uint32_t 354 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (reserveable || bytes <= sizeof(uint32_t)) { uint32_t 386 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, uint32_t 408 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t next_cmd, uint32_t 409 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t max, uint32_t min, uint32_t bytes) uint32_t 411 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t chunk_size = max - next_cmd; uint32_t 412 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t rest; uint32_t 413 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? uint32_t 429 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t next_cmd, uint32_t 430 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t max, uint32_t min, uint32_t bytes) uint32_t 432 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? uint32_t 437 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c next_cmd += sizeof(uint32_t); uint32_t 443 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c bytes -= sizeof(uint32_t); uint32_t 447 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) uint32_t 451 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); uint32_t 452 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); uint32_t 453 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); uint32_t 497 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) uint32_t 512 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes) uint32_t 537 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) uint32_t 543 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence); uint32_t 590 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t cid) uint32_t 636 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t cid) uint32_t 687 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t cid) uint32_t 45 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t *cmd; uint32_t 46 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t *cmd_orig; uint32_t 47 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t define_size = sizeof(define_cmd) + sizeof(*cmd); uint32_t 48 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t remap_num = num_pages / VMW_PPN_PER_REMAP + ((num_pages % VMW_PPN_PER_REMAP) > 0); uint32_t 49 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t remap_size = VMW_PPN_SIZE * num_pages + (sizeof(remap_cmd) + sizeof(*cmd)) * remap_num; uint32_t 50 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t remap_pos = 0; uint32_t 51 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t cmd_size = define_size + remap_size; uint32_t 52 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t i; uint32_t 110 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t define_size = sizeof(define_cmd) + 4; uint32_t 111 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c uint32_t *cmd; uint32_t 42 drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c uint32_t max_gmr_ids; uint32_t 43 drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c uint32_t max_gmr_pages; uint32_t 44 drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c uint32_t used_gmr_pages; uint32_t 96 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = SVGA3D_DEVCAP_MAX * sizeof(uint32_t); uint32_t 99 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c sizeof(uint32_t); uint32_t 103 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c sizeof(uint32_t); uint32_t 182 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c uint32_t size; uint32_t 196 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c size = SVGA3D_DEVCAP_MAX * sizeof(uint32_t); uint32_t 198 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c size = sizeof(struct svga_3d_compat_cap) + sizeof(uint32_t); uint32_t 201 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c sizeof(uint32_t); uint32_t 214 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c uint32_t *bounce32 = (uint32_t *) bounce; uint32_t 216 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c num = size / sizeof(uint32_t); uint32_t 261 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c uint32_t num_clips; uint32_t 344 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c uint32_t num_clips; uint32_t 82 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c uint32_t status, masked_status; uint32_t 111 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) uint32_t 121 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c uint32_t seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE); uint32_t 131 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c uint32_t seqno) uint32_t 162 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c uint32_t seqno, uint32_t 168 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c uint32_t count = 0; uint32_t 169 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c uint32_t signal_seq; uint32_t 172 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c bool (*wait_condition)(struct vmw_private *, uint32_t); uint32_t 286 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c bool lazy, uint32_t seqno, uint32_t 334 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c uint32_t status; uint32_t 343 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c uint32_t status; uint32_t 132 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t count; uint32_t 860 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t num_clips) uint32_t 1147 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t format; uint32_t 1287 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_kms_srf_ok(struct vmw_private *dev_priv, uint32_t width, uint32_t height) uint32_t 1453 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t num_rects, uint32_t 1607 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t i; uint32_t 1735 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t sid, uint32_t 1738 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t num_clips) uint32_t 1750 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t sid, uint32_t 1753 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t num_clips) uint32_t 1903 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t i; uint32_t 1952 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t i; uint32_t 1982 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t pitch, uint32_t 1983 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t height) uint32_t 2097 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t size, uint32_t 2122 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t num_displays; uint32_t 2234 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t max_width, uint32_t max_height) uint32_t 2562 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t handle = 0; uint32_t 2802 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t reserved_size = 0; uint32_t 2803 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t submit_size = 0; uint32_t 2804 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t curr_size = 0; uint32_t 2805 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t num_hits = 0; uint32_t 2871 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t fb_x = clip.x1; uint32_t 2872 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c uint32_t fb_y = clip.y1; uint32_t 64 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t (*calc_fifo_size)(struct vmw_du_update_plane *update, uint32_t 65 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t num_hits); uint32_t 79 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t (*post_prepare)(struct vmw_du_update_plane *update, void *cmd); uint32_t 91 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t (*pre_clip)(struct vmw_du_update_plane *update, void *cmd, uint32_t 92 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t num_hits); uint32_t 107 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t (*clip)(struct vmw_du_update_plane *update, void *cmd, uint32_t 108 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct drm_rect *clip, uint32_t src_x, uint32_t src_y); uint32_t 118 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t (*post_clip)(struct vmw_du_update_plane *update, void *cmd, uint32_t 223 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t user_handle; uint32_t 248 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h static const uint32_t vmw_primary_plane_formats[] = { uint32_t 256 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h static const uint32_t vmw_cursor_plane_formats[] = { uint32_t 394 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t size, uint32_t 414 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t max_width, uint32_t max_height); uint32_t 435 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t num_clips); uint32_t 534 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t num_clips, uint32_t 557 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h uint32_t num_clips, uint32_t 554 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c uint32_t header; uint32_t 33 drivers/gpu/drm/vmwgfx/vmwgfx_marker.c uint32_t seqno; uint32_t 57 drivers/gpu/drm/vmwgfx/vmwgfx_marker.c uint32_t seqno) uint32_t 74 drivers/gpu/drm/vmwgfx/vmwgfx_marker.c uint32_t signaled_seqno) uint32_t 121 drivers/gpu/drm/vmwgfx/vmwgfx_marker.c uint32_t us) uint32_t 129 drivers/gpu/drm/vmwgfx/vmwgfx_marker.c struct vmw_marker_queue *queue, uint32_t us) uint32_t 132 drivers/gpu/drm/vmwgfx/vmwgfx_marker.c uint32_t seqno; uint32_t 63 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c uint32_t id; uint32_t 63 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c uint32_t cmd; uint32_t 73 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c uint32_t size) uint32_t 81 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c uint32_t stream_id) uint32_t 108 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c uint32_t cmdType; uint32_t 109 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c uint32_t streamId; uint32_t 113 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c uint32_t registerId; uint32_t 114 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c uint32_t value; uint32_t 184 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c uint32_t stream_id, uint32_t 251 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c uint32_t stream_id, bool pause, uint32_t 527 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_claim(struct vmw_private *dev_priv, uint32_t *out) uint32_t 552 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_unref(struct vmw_private *dev_priv, uint32_t stream_id) uint32_t 117 drivers/gpu/drm/vmwgfx/vmwgfx_prime.c uint32_t handle, uint32_t flags, uint32_t 235 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c uint32_t handle, uint32_t 280 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c uint32_t handle, uint32_t 305 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c uint32_t handle, uint32_t 137 drivers/gpu/drm/vmwgfx/vmwgfx_resource_priv.h uint32_t handle, uint32_t 83 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t header; uint32_t 127 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t cmdType; uint32_t 174 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t cmdType; uint32_t 468 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static uint32_t vmw_sou_bo_fifo_size(struct vmw_du_update_plane *update, uint32_t 469 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t num_hits) uint32_t 475 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static uint32_t vmw_sou_bo_define_gmrfb(struct vmw_du_update_plane *update, uint32_t 501 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static uint32_t vmw_sou_bo_populate_clip(struct vmw_du_update_plane *update, uint32_t 503 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t fb_x, uint32_t fb_y) uint32_t 519 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static uint32_t vmw_stud_bo_post_clip(struct vmw_du_update_plane *update, uint32_t 564 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static uint32_t vmw_sou_surface_fifo_size(struct vmw_du_update_plane *update, uint32_t 565 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t num_hits) uint32_t 571 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static uint32_t vmw_sou_surface_post_prepare(struct vmw_du_update_plane *update, uint32_t 588 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static uint32_t vmw_sou_surface_pre_clip(struct vmw_du_update_plane *update, uint32_t 589 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c void *cmd, uint32_t num_hits) uint32_t 617 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static uint32_t vmw_sou_surface_clip_rect(struct vmw_du_update_plane *update, uint32_t 619 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t src_x, uint32_t src_y) uint32_t 635 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static uint32_t vmw_sou_surface_post_clip(struct vmw_du_update_plane *update, uint32_t 643 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t num_hits; uint32_t 986 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t header; uint32_t 1354 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c uint32_t num_clips, uint32_t 37 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c uint32_t size; uint32_t 161 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c uint32_t size, uint32_t 843 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c uint32_t *shader_handle) uint32_t 233 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c uint32_t handle, uint32_t 677 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t num_clips, uint32_t 1042 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t hdisplay = new_state->crtc_w, vdisplay = new_state->crtc_h; uint32_t 1184 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t vmw_stdu_bo_fifo_size(struct vmw_du_update_plane *update, uint32_t 1185 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t num_hits) uint32_t 1192 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t vmw_stdu_bo_fifo_size_cpu(struct vmw_du_update_plane *update, uint32_t 1193 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t num_hits) uint32_t 1199 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t vmw_stdu_bo_populate_dma(struct vmw_du_update_plane *update, uint32_t 1200 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c void *cmd, uint32_t num_hits) uint32_t 1223 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t vmw_stdu_bo_populate_clip(struct vmw_du_update_plane *update, uint32_t 1225 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t fb_x, uint32_t fb_y) uint32_t 1242 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t vmw_stdu_bo_populate_update(struct vmw_du_update_plane *update, uint32_t 1261 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t vmw_stdu_bo_pre_clip_cpu(struct vmw_du_update_plane *update, uint32_t 1262 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c void *cmd, uint32_t num_hits) uint32_t 1273 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t vmw_stdu_bo_clip_cpu(struct vmw_du_update_plane *update, uint32_t 1275 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t fb_x, uint32_t fb_y) uint32_t 1286 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t uint32_t 1400 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t uint32_t 1402 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t num_hits) uint32_t 1405 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t size = 0; uint32_t 1417 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t vmw_stdu_surface_fifo_size(struct vmw_du_update_plane *update, uint32_t 1418 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t num_hits) uint32_t 1421 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t size = 0; uint32_t 1434 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t uint32_t 1443 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t copy_size = 0; uint32_t 1475 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t uint32_t 1477 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t num_hits) uint32_t 1495 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t uint32_t 1497 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct drm_rect *clip, uint32_t fb_x, uint32_t 1498 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c uint32_t fb_y) uint32_t 1515 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static uint32_t uint32_t 52 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t size; uint32_t 66 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t face; uint32_t 67 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t mip; uint32_t 68 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t bo_offset; uint32_t 174 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c static inline uint32_t vmw_surface_dma_size(const struct vmw_surface *srf) uint32_t 188 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c static inline uint32_t vmw_surface_define_size(const struct vmw_surface *srf) uint32_t 201 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c static inline uint32_t vmw_surface_destroy_size(void) uint32_t 212 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c static void vmw_surface_destroy_encode(uint32_t id, uint32_t 236 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t cmd_len; uint32_t 279 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t i; uint32_t 386 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t submit_size; uint32_t 463 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t submit_size; uint32_t 546 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t submit_size; uint32_t 642 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t size = user_srf->size; uint32_t 719 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t cur_bo_offset; uint32_t 722 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t num_sizes; uint32_t 723 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t size; uint32_t 808 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t stride = svga3dsurface_calculate_pitch uint32_t 856 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t backup_handle; uint32_t 903 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t u_handle, uint32_t 909 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t handle; uint32_t 1001 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->flags = (uint32_t)srf->flags; uint32_t 1032 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t cmd_len, cmd_id, submit_len; uint32_t 1151 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t submit_size; uint32_t 1198 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t submit_size; uint32_t 1357 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t user_accounting_size, uint32_t 1361 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t num_mip_levels, uint32_t 1362 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t multisample_count, uint32_t 1363 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t array_size, uint32_t 1559 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t size; uint32_t 1560 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t backup_handle = 0; uint32_t 1706 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c uint32_t backup_handle; uint32_t 713 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c uint32_t page_flags) uint32_t 739 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c static int vmw_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) uint32_t 744 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c static int vmw_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, uint32_t 154 drivers/gpu/drm/vmwgfx/vmwgfx_va.c uint32_t *inout_id, struct vmw_resource **out) uint32_t 21 drivers/gpu/drm/zte/zx_plane.c static const uint32_t gl_formats[] = { uint32_t 30 drivers/gpu/drm/zte/zx_plane.c static const uint32_t vl_formats[] = { uint32_t 78 drivers/gpu/drm/zte/zx_plane.c static int zx_vl_get_fmt(uint32_t format) uint32_t 113 drivers/gpu/drm/zte/zx_plane.c static int zx_vl_rsz_get_fmt(uint32_t format) uint32_t 147 drivers/gpu/drm/zte/zx_plane.c static void zx_vl_rsz_setup(struct zx_plane *zplane, uint32_t format, uint32_t 196 drivers/gpu/drm/zte/zx_plane.c uint32_t format; uint32_t 306 drivers/gpu/drm/zte/zx_plane.c static int zx_gl_get_fmt(uint32_t format) uint32_t 361 drivers/gpu/drm/zte/zx_plane.c uint32_t format; uint32_t 501 drivers/gpu/drm/zte/zx_plane.c const uint32_t *formats; uint32_t 398 drivers/gpu/ipu-v3/ipu-di.c uint32_t val; uint32_t 124 drivers/gpu/ipu-v3/ipu-prg.c bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format, uint32_t 1394 drivers/gpu/vga/vgaarb.c uint32_t new_decodes; uint32_t 151 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h (((drbl_reg)&IPC_DRBL_BUSY_BIT) == ((uint32_t)IPC_DRBL_BUSY_BIT)) uint32_t 203 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h ((uint32_t)IPC_ISH_ISHTP_READY_BIT)) uint32_t 206 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h (((ish_status) & IPC_ILUP_BIT) == ((uint32_t)IPC_ILUP_BIT)) uint32_t 29 drivers/hid/intel-ish-hid/ipc/ipc.c static inline uint32_t ish_reg_read(const struct ishtp_device *dev, uint32_t 47 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t value) uint32_t 62 drivers/hid/intel-ish-hid/ipc/ipc.c static inline uint32_t _ish_read_fw_sts_reg(struct ishtp_device *dev) uint32_t 78 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t pisr_val = 0; uint32_t 105 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t doorbell_val; uint32_t 131 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t host_comm_val; uint32_t 138 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t host_pimr_val; uint32_t 162 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t ish_status = _ish_read_fw_sts_reg(dev); uint32_t 176 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM); uint32_t 190 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM); uint32_t 204 drivers/hid/intel-ish-hid/ipc/ipc.c static uint32_t _ishtp_read_hdr(const struct ishtp_device *dev) uint32_t 222 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t i; uint32_t 223 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t *r_buf = (uint32_t *)buffer; uint32_t 224 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t msg_offs; uint32_t 227 drivers/hid/intel-ish-hid/ipc/ipc.c for (i = 0; i < buffer_length; i += sizeof(uint32_t)) uint32_t 248 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t doorbell_val; uint32_t 249 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t *r_buf; uint32_t 250 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t reg_addr; uint32_t 276 drivers/hid/intel-ish-hid/ipc/ipc.c length = ipc_link->length - sizeof(uint32_t); uint32_t 277 drivers/hid/intel-ish-hid/ipc/ipc.c doorbell_val = *(uint32_t *)ipc_link->inline_data; uint32_t 278 drivers/hid/intel-ish-hid/ipc/ipc.c r_buf = (uint32_t *)(ipc_link->inline_data + sizeof(uint32_t)); uint32_t 307 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t reg = 0; uint32_t 396 drivers/hid/intel-ish-hid/ipc/ipc.c static int ipc_send_mng_msg(struct ishtp_device *dev, uint32_t msg_code, uint32_t 400 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t drbl_val = IPC_BUILD_MNG_MSG(msg_code, size); uint32_t 402 drivers/hid/intel-ish-hid/ipc/ipc.c memcpy(ipc_msg, &drbl_val, sizeof(uint32_t)); uint32_t 403 drivers/hid/intel-ish-hid/ipc/ipc.c memcpy(ipc_msg + sizeof(uint32_t), msg, size); uint32_t 405 drivers/hid/intel-ish-hid/ipc/ipc.c sizeof(uint32_t) + size); uint32_t 471 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t reset_id; uint32_t 499 drivers/hid/intel-ish-hid/ipc/ipc.c sizeof(uint32_t)); uint32_t 506 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t ish_status; uint32_t 571 drivers/hid/intel-ish-hid/ipc/ipc.c static void recv_ipc(struct ishtp_device *dev, uint32_t doorbell_val) uint32_t 573 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t mng_cmd; uint32_t 620 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t doorbell_val; uint32_t 855 drivers/hid/intel-ish-hid/ipc/ipc.c static uint32_t ish_ipc_get_header(struct ishtp_device *dev, int length, uint32_t 858 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t drbl_val; uint32_t 47 drivers/hid/intel-ish-hid/ishtp-hid.h uint32_t dev_id; uint32_t 38 drivers/hid/intel-ish-hid/ishtp/bus.c uint32_t msg_hdr; uint32_t 89 drivers/hid/intel-ish-hid/ishtp/bus.c uint32_t drbl_val; uint32_t 95 drivers/hid/intel-ish-hid/ishtp/bus.c memcpy(ipc_msg, &drbl_val, sizeof(uint32_t)); uint32_t 96 drivers/hid/intel-ish-hid/ishtp/bus.c memcpy(ipc_msg + sizeof(uint32_t), hdr, sizeof(uint32_t)); uint32_t 97 drivers/hid/intel-ish-hid/ishtp/bus.c memcpy(ipc_msg + 2 * sizeof(uint32_t), msg, hdr->length); uint32_t 99 drivers/hid/intel-ish-hid/ishtp/bus.c ipc_msg, 2 * sizeof(uint32_t) + hdr->length); uint32_t 133 drivers/hid/intel-ish-hid/ishtp/client.h uint32_t size); uint32_t 99 drivers/hid/intel-ish-hid/ishtp/dma-if.c uint32_t size) uint32_t 916 drivers/hid/intel-ish-hid/ishtp/hbm.c static uint32_t current_state; uint32_t 917 drivers/hid/intel-ish-hid/ishtp/hbm.c static uint32_t supported_states = 0 | SUSPEND_STATE_BIT; uint32_t 76 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t fw_addr:8; uint32_t 77 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t host_addr:8; uint32_t 78 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t length:9; uint32_t 79 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t reserved:6; uint32_t 80 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t msg_complete:1; uint32_t 149 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t max_msg_length; uint32_t 215 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t buf_size; uint32_t 226 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t msg_length; uint32_t 227 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t reserved2; uint32_t 241 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t cmd; uint32_t 242 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t cmd_status; /*responses will have this set*/ uint32_t 247 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t states; uint32_t 252 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t supported_states; uint32_t 253 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t states_status; uint32_t 262 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t requested_states; uint32_t 263 drivers/hid/intel-ish-hid/ishtp/hbm.h uint32_t states_status; uint32_t 111 drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h uint32_t (*ipc_get_header)(struct ishtp_device *dev, int length, uint32_t 116 drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h uint32_t (*ishtp_read_hdr)(const struct ishtp_device *dev); uint32_t 119 drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h uint32_t (*get_fw_status)(struct ishtp_device *dev); uint32_t 216 drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h uint32_t ishtp_msg_hdr; uint32_t 398 drivers/i2c/busses/i2c-bcm-iproc.c uint32_t val; uint32_t 794 drivers/i2c/busses/i2c-bcm-iproc.c static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) uint32_t 221 drivers/i2c/busses/i2c-bcm-kona.c uint32_t status = readl(dev->base + ISR_OFFSET); uint32_t 703 drivers/i2c/busses/i2c-bcm-kona.c static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap) uint32_t 120 drivers/i2c/busses/i2c-mxs.c uint32_t timing0; uint32_t 121 drivers/i2c/busses/i2c-mxs.c uint32_t timing1; uint32_t 122 drivers/i2c/busses/i2c-mxs.c uint32_t timing2; uint32_t 126 drivers/i2c/busses/i2c-mxs.c uint32_t pio_data[2]; uint32_t 127 drivers/i2c/busses/i2c-mxs.c uint32_t addr_data; uint32_t 173 drivers/i2c/busses/i2c-mxs.c struct i2c_msg *msg, uint32_t flags) uint32_t 366 drivers/i2c/busses/i2c-mxs.c struct i2c_msg *msg, uint32_t flags) uint32_t 369 drivers/i2c/busses/i2c-mxs.c uint32_t addr_data = i2c_8bit_addr_from_msg(msg); uint32_t 370 drivers/i2c/busses/i2c-mxs.c uint32_t data = 0; uint32_t 372 drivers/i2c/busses/i2c-mxs.c uint32_t start; uint32_t 687 drivers/i2c/busses/i2c-mxs.c static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed) uint32_t 690 drivers/i2c/busses/i2c-mxs.c const uint32_t clk = 24000000; uint32_t 691 drivers/i2c/busses/i2c-mxs.c uint32_t divider; uint32_t 693 drivers/i2c/busses/i2c-mxs.c uint32_t bus_free, leadin; uint32_t 764 drivers/i2c/busses/i2c-mxs.c uint32_t speed; uint32_t 423 drivers/iio/adc/at91_adc.c const uint32_t ts_data_irq_mask = uint32_t 62 drivers/iio/adc/ingenic-adc.c uint32_t mask, uint32_t 63 drivers/iio/adc/ingenic-adc.c uint32_t val) uint32_t 65 drivers/iio/adc/ingenic-adc.c uint32_t cfg; uint32_t 116 drivers/iio/adc/xilinx-xadc-core.c uint32_t val) uint32_t 122 drivers/iio/adc/xilinx-xadc-core.c uint32_t *val) uint32_t 137 drivers/iio/adc/xilinx-xadc-core.c static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd, uint32_t 148 drivers/iio/adc/xilinx-xadc-core.c uint32_t status, tmp; uint32_t 171 drivers/iio/adc/xilinx-xadc-core.c uint32_t cmd[1]; uint32_t 172 drivers/iio/adc/xilinx-xadc-core.c uint32_t tmp; uint32_t 205 drivers/iio/adc/xilinx-xadc-core.c uint32_t cmd[2]; uint32_t 206 drivers/iio/adc/xilinx-xadc-core.c uint32_t resp, tmp; uint32_t 292 drivers/iio/adc/xilinx-xadc-core.c uint32_t status; uint32_t 401 drivers/iio/adc/xilinx-xadc-core.c uint32_t val; uint32_t 426 drivers/iio/adc/xilinx-xadc-core.c uint32_t status; uint32_t 455 drivers/iio/adc/xilinx-xadc-core.c uint32_t val32; uint32_t 486 drivers/iio/adc/xilinx-xadc-core.c uint32_t status, mask; uint32_t 519 drivers/iio/adc/xilinx-xadc-core.c uint32_t val; uint32_t 299 drivers/iio/gyro/adis16136.c uint32_t val32; uint32_t 450 drivers/iio/imu/adis16480.c uint32_t val32; uint32_t 427 drivers/infiniband/core/nldev.c struct rdma_restrack_entry *res, uint32_t port) uint32_t 488 drivers/infiniband/core/nldev.c struct rdma_restrack_entry *res, uint32_t port) uint32_t 541 drivers/infiniband/core/nldev.c struct rdma_restrack_entry *res, uint32_t port) uint32_t 579 drivers/infiniband/core/nldev.c struct rdma_restrack_entry *res, uint32_t port) uint32_t 614 drivers/infiniband/core/nldev.c struct rdma_restrack_entry *res, uint32_t port) uint32_t 775 drivers/infiniband/core/nldev.c uint32_t port) uint32_t 56 drivers/infiniband/core/uverbs_std_types_device.c static uint32_t * uint32_t 452 drivers/infiniband/hw/mlx5/cq.c uint32_t qpn; uint32_t 4908 drivers/infiniband/hw/mlx5/qp.c *(uint32_t *)(*seg + 8) = 0; uint32_t 1922 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c static inline uint32_t ocrdma_sglist_len(struct ib_sge *sg_list, int num_sge) uint32_t 1924 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c uint32_t total_len = 0, i; uint32_t 7780 drivers/infiniband/hw/qib/qib_iba7322.c rd_data = (uint32_t)(trans >> AHB_DATA_LSB); uint32_t 1046 drivers/infiniband/hw/qib/qib_sd7220.c uint32_t dds_reg_map; uint32_t 1195 drivers/infiniband/hw/qib/qib_sd7220.c uint32_t regmap; uint32_t 59 drivers/infiniband/hw/usnic/usnic_abi.h uint32_t sock_fd; uint32_t 255 drivers/infiniband/hw/usnic/usnic_fwd.c flow->flow_id = (uint32_t) a0; uint32_t 64 drivers/infiniband/hw/usnic/usnic_fwd.h uint32_t flow_id; uint32_t 98 drivers/infiniband/hw/usnic/usnic_fwd.h uint32_t usnic_id) uint32_t 112 drivers/infiniband/hw/usnic/usnic_fwd.h uint32_t daddr, uint16_t dport) uint32_t 274 drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c uint32_t addr; uint32_t 637 drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c uint32_t *id) uint32_t 68 drivers/infiniband/hw/usnic/usnic_transport.c uint32_t addr; uint32_t 175 drivers/infiniband/hw/usnic/usnic_transport.c uint32_t *addr, uint16_t *port) uint32_t 63 drivers/infiniband/hw/usnic/usnic_transport.h uint32_t *addr, uint16_t *port); uint32_t 451 drivers/infiniband/sw/siw/siw.h uint32_t sq_get; /* consumer index into sq array */ uint32_t 452 drivers/infiniband/sw/siw/siw.h uint32_t sq_put; /* kernel prod. index into sq array */ uint32_t 457 drivers/infiniband/sw/siw/siw.h uint32_t orq_get; /* consumer index into orq array */ uint32_t 458 drivers/infiniband/sw/siw/siw.h uint32_t orq_put; /* shared producer index for ORQ */ uint32_t 466 drivers/infiniband/sw/siw/siw.h uint32_t rq_get; /* consumer index into rq array */ uint32_t 467 drivers/infiniband/sw/siw/siw.h uint32_t rq_put; /* kernel prod. index into rq array */ uint32_t 470 drivers/infiniband/sw/siw/siw.h uint32_t irq_get; /* consumer index into irq array */ uint32_t 471 drivers/infiniband/sw/siw/siw.h uint32_t irq_put; /* producer index into irq array */ uint32_t 666 drivers/infiniband/sw/siw/siw_qp_rx.c uint32_t length = be32_to_cpu(srx->hdr.rreq.read_size), uint32_t 22 drivers/infiniband/sw/siw/siw_qp_tx.c (((uint32_t)(sizeof(struct siw_rreq_pkt) - \ uint32_t 426 drivers/infiniband/ulp/iser/iscsi_iser.c uint32_t conn_idx) uint32_t 608 drivers/infiniband/ulp/iser/iscsi_iser.c uint32_t initial_cmdsn) uint32_t 443 drivers/infiniband/ulp/iser/iser_initiator.c uint32_t itt; uint32_t 447 drivers/infiniband/ulp/iser/iser_initiator.c itt = (__force uint32_t)hdr->itt; uint32_t 1300 drivers/infiniband/ulp/isert/ib_isert.c uint32_t read_stag, uint64_t read_va, uint32_t 1301 drivers/infiniband/ulp/isert/ib_isert.c uint32_t write_stag, uint64_t write_va) uint32_t 1404 drivers/infiniband/ulp/isert/ib_isert.c uint32_t read_stag = 0, write_stag = 0; uint32_t 115 drivers/infiniband/ulp/isert/ib_isert.h uint32_t read_stag; uint32_t 116 drivers/infiniband/ulp/isert/ib_isert.h uint32_t write_stag; uint32_t 119 drivers/infiniband/ulp/isert/ib_isert.h uint32_t inv_rkey; uint32_t 298 drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.c static uint32_t opa_vnic_chk_mac_tbl(struct opa_vnic_adapter *adapter, uint32_t 333 drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.c static uint32_t opa_vnic_get_dlid(struct opa_vnic_adapter *adapter, uint32_t 348 drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.c dlid = ((uint32_t)mac_hdr->h_dest[5] << 16) | uint32_t 349 drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.c ((uint32_t)mac_hdr->h_dest[4] << 8) | uint32_t 836 drivers/infiniband/ulp/srp/ib_srp.c static int srp_send_req(struct srp_rdma_ch *ch, uint32_t max_iu_len, uint32_t 1164 drivers/infiniband/ulp/srp/ib_srp.c static int srp_connect_ch(struct srp_rdma_ch *ch, uint32_t max_iu_len, uint32_t 1365 drivers/infiniband/ulp/srp/ib_srp.c static uint32_t srp_max_it_iu_len(int cmd_sg_cnt, bool use_imm_data) uint32_t 1367 drivers/infiniband/ulp/srp/ib_srp.c uint32_t max_iu_len = sizeof(struct srp_cmd) + SRP_MAX_ADD_CDB_LEN + uint32_t 1391 drivers/infiniband/ulp/srp/ib_srp.c uint32_t max_iu_len = srp_max_it_iu_len(target->cmd_sg_cnt, uint32_t 2499 drivers/infiniband/ulp/srp/ib_srp.c static uint32_t srp_compute_rq_tmo(struct ib_qp_attr *qp_attr, int attr_mask) uint32_t 2502 drivers/infiniband/ulp/srp/ib_srp.c uint32_t rq_tmo_jiffies; uint32_t 3781 drivers/infiniband/ulp/srp/ib_srp.c uint32_t max_iu_len; uint32_t 162 drivers/infiniband/ulp/srp/ib_srp.h uint32_t max_it_iu_len; uint32_t 163 drivers/infiniband/ulp/srp/ib_srp.h uint32_t max_ti_iu_len; uint32_t 1065 drivers/infiniband/ulp/srpt/ib_srpt.c uint32_t len = be32_to_cpu(imm_buf->len); uint32_t 1066 drivers/infiniband/ulp/srpt/ib_srpt.c uint32_t req_size = imm_data_offset + len; uint32_t 178 drivers/infiniband/ulp/srpt/ib_srpt.h uint32_t offset; uint32_t 179 drivers/infiniband/ulp/srpt/ib_srpt.h uint32_t index; uint32_t 32 drivers/input/keyboard/matrix_keypad.c uint32_t last_key_state[MATRIX_MAX_COLS]; uint32_t 121 drivers/input/keyboard/matrix_keypad.c uint32_t new_state[MATRIX_MAX_COLS]; uint32_t 142 drivers/input/keyboard/matrix_keypad.c uint32_t bits_changed; uint32_t 111 drivers/input/keyboard/pxa27x_keypad.c uint32_t matrix_key_state[MAX_MATRIX_KEY_COLS]; uint32_t 112 drivers/input/keyboard/pxa27x_keypad.c uint32_t direct_key_state; uint32_t 413 drivers/input/keyboard/pxa27x_keypad.c uint32_t new_state[MAX_MATRIX_KEY_COLS]; uint32_t 414 drivers/input/keyboard/pxa27x_keypad.c uint32_t kpas = keypad_readl(KPAS); uint32_t 437 drivers/input/keyboard/pxa27x_keypad.c uint32_t kpasmkp0 = keypad_readl(KPASMKP0); uint32_t 438 drivers/input/keyboard/pxa27x_keypad.c uint32_t kpasmkp1 = keypad_readl(KPASMKP1); uint32_t 439 drivers/input/keyboard/pxa27x_keypad.c uint32_t kpasmkp2 = keypad_readl(KPASMKP2); uint32_t 440 drivers/input/keyboard/pxa27x_keypad.c uint32_t kpasmkp3 = keypad_readl(KPASMKP3); uint32_t 453 drivers/input/keyboard/pxa27x_keypad.c uint32_t bits_changed; uint32_t 477 drivers/input/keyboard/pxa27x_keypad.c static inline int rotary_delta(uint32_t kprec) uint32_t 514 drivers/input/keyboard/pxa27x_keypad.c uint32_t kprec; uint32_t 532 drivers/input/keyboard/pxa27x_keypad.c uint32_t kpdk, bits_changed; uint32_t 31 drivers/input/keyboard/pxa930_rotary.c uint32_t sbcr = __raw_readl(r->mmio_base + SBCR); uint32_t 247 drivers/input/keyboard/samsung-keypad.c uint32_t *keymap, num_rows = 0, num_cols = 0; uint32_t 280 drivers/input/keyboard/samsung-keypad.c keymap = devm_kcalloc(dev, key_count, sizeof(uint32_t), GFP_KERNEL); uint32_t 39 drivers/input/misc/cobalt_btns.c uint32_t status; uint32_t 203 drivers/input/misc/hp_sdc_rtc.c uint32_t tenms; uint32_t 209 drivers/input/misc/hp_sdc_rtc.c tenms = (uint32_t)raw & 0xffffff; uint32_t 239 drivers/input/misc/hp_sdc_rtc.c uint32_t tenms; uint32_t 244 drivers/input/misc/hp_sdc_rtc.c tenms = (uint32_t)raw & 0xffffff; uint32_t 256 drivers/input/misc/hp_sdc_rtc.c uint32_t tenms; uint32_t 261 drivers/input/misc/hp_sdc_rtc.c tenms = (uint32_t)raw & 0xffffff; uint32_t 273 drivers/input/misc/hp_sdc_rtc.c uint32_t tenms; uint32_t 278 drivers/input/misc/hp_sdc_rtc.c tenms = (uint32_t)raw & 0xffffff; uint32_t 291 drivers/input/misc/hp_sdc_rtc.c uint32_t tenms; uint32_t 331 drivers/input/misc/hp_sdc_rtc.c uint32_t tenms; uint32_t 371 drivers/input/misc/hp_sdc_rtc.c uint32_t tenms; uint32_t 98 drivers/input/mouse/pxa930_trkball.c uint32_t tbcr; uint32_t 129 drivers/input/mouse/pxa930_trkball.c uint32_t tbcr = __raw_readl(trkball->mmio_base + TBCR); uint32_t 388 drivers/iommu/fsl_pamu.h u32 omi, unsigned long rpn, u32 snoopid, uint32_t stashid, uint32_t 392 drivers/iommu/fsl_pamu.h uint32_t snoopid, u32 stashid, int enable, int prot); uint32_t 6084 drivers/iommu/intel-iommu.c uint32_t vtisochctrl; uint32_t 30 drivers/irqchip/irq-ingenic-tcu.c uint32_t irq_reg, irq_mask; uint32_t 38 drivers/irqchip/irq-ingenic.c uint32_t irq_reg; uint32_t 53 drivers/irqchip/irq-ingenic.c static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask) uint32_t 133 drivers/irqchip/irq-sa11x0.c uint32_t icip, icmr, mask; uint32_t 45 drivers/irqchip/irq-tb10x.c uint32_t im, mod, pol; uint32_t 21 drivers/mcb/mcb-parse.c static inline uint32_t get_next_dtype(void __iomem *p) uint32_t 23 drivers/mcb/mcb-parse.c uint32_t dtype; uint32_t 184 drivers/mcb/mcb-parse.c uint32_t dtype; uint32_t 1103 drivers/md/bcache/super.c uint32_t rtime = cpu_to_le32((u32)ktime_get_real_seconds()); uint32_t 47 drivers/md/bcache/writeback.c uint32_t bdev_share = uint32_t 89 drivers/md/bcache/writeback.c uint32_t new_rate; uint32_t 21 drivers/md/dm-cache-block-types.h typedef uint32_t __bitwise dm_cblock_t; uint32_t 34 drivers/md/dm-cache-block-types.h static inline dm_cblock_t to_cblock(uint32_t b) uint32_t 39 drivers/md/dm-cache-block-types.h static inline uint32_t from_cblock(dm_cblock_t b) uint32_t 41 drivers/md/dm-cache-block-types.h return (__force uint32_t) b; uint32_t 185 drivers/md/dm-cache-metadata.c uint32_t metadata_version = le32_to_cpu(disk_super->version); uint32_t 439 drivers/md/dm-cache-metadata.c uint32_t incompat_flags, features; uint32_t 562 drivers/md/dm-cache-metadata.c uint32_t sb_flags = mutator(le32_to_cpu(disk_super->flags)); uint32_t 1153 drivers/md/dm-cache-metadata.c uint32_t b; uint32_t 1585 drivers/md/dm-cache-metadata.c static int is_dirty_callback(uint32_t index, bool *value, void *context) uint32_t 1690 drivers/md/dm-cache-metadata.c static int get_hint(uint32_t index, void *value_le, void *context) uint32_t 1692 drivers/md/dm-cache-metadata.c uint32_t value; uint32_t 92 drivers/md/dm-cache-metadata.h uint32_t hint, bool hint_valid); uint32_t 102 drivers/md/dm-cache-metadata.h uint32_t read_hits; uint32_t 103 drivers/md/dm-cache-metadata.h uint32_t read_misses; uint32_t 104 drivers/md/dm-cache-metadata.h uint32_t write_hits; uint32_t 105 drivers/md/dm-cache-metadata.h uint32_t write_misses; uint32_t 59 drivers/md/dm-cache-policy-internal.h bool dirty, uint32_t hint, bool hint_valid) uint32_t 70 drivers/md/dm-cache-policy-internal.h static inline uint32_t policy_get_hint(struct dm_cache_policy *p, uint32_t 1557 drivers/md/dm-cache-policy-smq.c bool dirty, uint32_t hint, bool hint_valid) uint32_t 1592 drivers/md/dm-cache-policy-smq.c static uint32_t smq_get_hint(struct dm_cache_policy *p, dm_cblock_t cblock) uint32_t 97 drivers/md/dm-cache-policy.h uint32_t hint, bool hint_valid); uint32_t 109 drivers/md/dm-cache-policy.h uint32_t (*get_hint)(struct dm_cache_policy *p, dm_cblock_t cblock); uint32_t 438 drivers/md/dm-cache-target.c uint32_t discard_block_size; /* a power of 2 times sectors per block */ uint32_t 732 drivers/md/dm-cache-target.c static dm_block_t block_div(dm_block_t b, uint32_t n) uint32_t 2085 drivers/md/dm-cache-target.c uint32_t block_size; uint32_t 2885 drivers/md/dm-cache-target.c bool dirty, uint32_t hint, bool hint_valid) uint32_t 29 drivers/md/dm-era-target.c uint32_t nr_bits; uint32_t 133 drivers/md/dm-era-target.c struct writeset *ws, uint32_t block) uint32_t 205 drivers/md/dm-era-target.c uint32_t metadata_version = le32_to_cpu(disk->version); uint32_t 267 drivers/md/dm-era-target.c uint32_t nr_blocks; uint32_t 269 drivers/md/dm-era-target.c uint32_t current_era; uint32_t 655 drivers/md/dm-era-target.c uint32_t era; uint32_t 1107 drivers/md/dm-era-target.c uint32_t era; uint32_t 1146 drivers/md/dm-era-target.c uint32_t sectors_per_block; uint32_t 52 drivers/md/dm-ioctl.c uint32_t flags; uint32_t 513 drivers/md/dm-ioctl.c uint32_t *event_nr; uint32_t 524 drivers/md/dm-ioctl.c needed += align_val(sizeof(uint32_t)); uint32_t 546 drivers/md/dm-ioctl.c old_nl->next = (uint32_t) ((void *) nl - uint32_t 592 drivers/md/dm-ioctl.c info->old_vers->next = (uint32_t) ((void *)info->vers - uint32_t 1270 drivers/md/dm-ioctl.c static int next_target(struct dm_target_spec *last, uint32_t next, void *end, uint32_t 1288 drivers/md/dm-ioctl.c uint32_t next = param->data_start; uint32_t 1708 drivers/md/dm-ioctl.c uint32_t version[3]; uint32_t 41 drivers/md/dm-log-userspace-base.c uint32_t usr_argc; uint32_t 43 drivers/md/dm-log-userspace-base.c uint32_t region_size; uint32_t 77 drivers/md/dm-log-userspace-base.c uint32_t integrated_flush; uint32_t 284 drivers/md/dm-log-userspace-base.c lc->region_size = (uint32_t)rdata; uint32_t 392 drivers/md/dm-log-userspace-base.c static uint32_t userspace_get_region_size(struct dm_dirty_log *log) uint32_t 488 drivers/md/dm-log-userspace-base.c uint32_t type = 0; uint32_t 18 drivers/md/dm-log-userspace-transfer.c static uint32_t dm_ulog_seq; uint32_t 46 drivers/md/dm-log-userspace-transfer.c uint32_t seq; uint32_t 84 drivers/md/dm-log-userspace-transfer.c uint32_t rtn_seq = (msg) ? msg->seq : (tfr) ? tfr->seq : 0; uint32_t 212 drivers/md/dm-log.c uint32_t magic; uint32_t 213 drivers/md/dm-log.c uint32_t version; uint32_t 222 drivers/md/dm-log.c uint32_t region_size; uint32_t 227 drivers/md/dm-log.c uint32_t *clean_bits; uint32_t 228 drivers/md/dm-log.c uint32_t *sync_bits; uint32_t 229 drivers/md/dm-log.c uint32_t *recovering_bits; /* FIXME: this seems excessive */ uint32_t 258 drivers/md/dm-log.c static inline int log_test_bit(uint32_t *bs, unsigned bit) uint32_t 264 drivers/md/dm-log.c uint32_t *bs, unsigned bit) uint32_t 271 drivers/md/dm-log.c uint32_t *bs, unsigned bit) uint32_t 346 drivers/md/dm-log.c static int _check_region_size(struct dm_target *ti, uint32_t region_size) uint32_t 370 drivers/md/dm-log.c uint32_t region_size; uint32_t 590 drivers/md/dm-log.c size_t size = lc->bitset_uint32_count * sizeof(uint32_t); uint32_t 625 drivers/md/dm-log.c lc->bitset_uint32_count * sizeof(uint32_t)); uint32_t 649 drivers/md/dm-log.c static uint32_t core_get_region_size(struct dm_dirty_log *log) uint32_t 228 drivers/md/dm-raid.c uint32_t stripe_cache_entries; uint32_t 340 drivers/md/dm-raid.c static const char *dm_raid_arg_name_by_flag(const uint32_t flag) uint32_t 1534 drivers/md/dm-raid.c uint32_t min_stripes = max(mddev->chunk_sectors, mddev->new_chunk_sectors) / 2; uint32_t 1535 drivers/md/dm-raid.c uint32_t nr_stripes = rs->stripe_cache_entries; uint32_t 2231 drivers/md/dm-raid.c uint32_t new_devs = 0, rebuild_and_new = 0, rebuilds = 0; uint32_t 877 drivers/md/dm-raid1.c uint32_t region_size, uint32_t 58 drivers/md/dm-region-hash.c uint32_t region_size; uint32_t 167 drivers/md/dm-region-hash.c struct dm_dirty_log *log, uint32_t region_size, uint32_t 106 drivers/md/dm-snap-persistent.c uint32_t exceptions_per_area; uint32_t 157 drivers/md/dm-snap-persistent.c uint32_t current_committed; uint32_t 160 drivers/md/dm-snap-persistent.c uint32_t callback_count; uint32_t 275 drivers/md/dm-snap-persistent.c uint32_t stride = ps->exceptions_per_area + 1; uint32_t 407 drivers/md/dm-snap-persistent.c uint32_t index) uint32_t 415 drivers/md/dm-snap-persistent.c uint32_t index, struct core_exception *result) uint32_t 425 drivers/md/dm-snap-persistent.c uint32_t index, struct core_exception *e) uint32_t 434 drivers/md/dm-snap-persistent.c static void clear_exception(struct pstore *ps, uint32_t index) uint32_t 43 drivers/md/dm-snap.c uint32_t hash_mask; uint32_t 624 drivers/md/dm-snap.c static uint32_t exception_hash(struct dm_exception_table *et, chunk_t chunk); uint32_t 655 drivers/md/dm-snap.c uint32_t size, unsigned hash_shift) uint32_t 690 drivers/md/dm-snap.c static uint32_t exception_hash(struct dm_exception_table *et, chunk_t chunk) uint32_t 849 drivers/md/dm-snap.c static uint32_t __minimum_chunk_size(struct origin *o) uint32_t 859 drivers/md/dm-snap.c return (uint32_t) chunk_size; uint32_t 2282 drivers/md/dm-snap.c static uint32_t get_origin_minimum_chunksize(struct block_device *bdev) uint32_t 2284 drivers/md/dm-snap.c uint32_t min_chunksize; uint32_t 29 drivers/md/dm-stripe.c uint32_t stripes; uint32_t 35 drivers/md/dm-stripe.c uint32_t chunk_size; uint32_t 102 drivers/md/dm-stripe.c uint32_t stripes; uint32_t 103 drivers/md/dm-stripe.c uint32_t chunk_size; uint32_t 217 drivers/md/dm-stripe.c uint32_t *stripe, sector_t *result) uint32_t 245 drivers/md/dm-stripe.c uint32_t target_stripe, sector_t *result) uint32_t 247 drivers/md/dm-stripe.c uint32_t stripe; uint32_t 265 drivers/md/dm-stripe.c uint32_t target_stripe) uint32_t 289 drivers/md/dm-stripe.c uint32_t stripe; uint32_t 324 drivers/md/dm-stripe.c uint32_t stripe; uint32_t 345 drivers/md/dm-stripe.c uint32_t stripe; uint32_t 364 drivers/md/dm-stripe.c uint32_t stripe; uint32_t 183 drivers/md/dm-thin-metadata.c uint32_t time; uint32_t 238 drivers/md/dm-thin-metadata.c uint32_t creation_time; uint32_t 239 drivers/md/dm-thin-metadata.c uint32_t snapshotted_time; uint32_t 303 drivers/md/dm-thin-metadata.c static uint64_t pack_block_time(dm_block_t b, uint32_t t) uint32_t 308 drivers/md/dm-thin-metadata.c static void unpack_block_time(uint64_t v, dm_block_t *b, uint32_t *t) uint32_t 319 drivers/md/dm-thin-metadata.c uint32_t t; uint32_t 331 drivers/md/dm-thin-metadata.c uint32_t t; uint32_t 342 drivers/md/dm-thin-metadata.c uint32_t t; uint32_t 627 drivers/md/dm-thin-metadata.c uint32_t features; uint32_t 1102 drivers/md/dm-thin-metadata.c dm_thin_id origin, uint32_t time) uint32_t 1470 drivers/md/dm-thin-metadata.c static bool __snapshotted_since(struct dm_thin_device *td, uint32_t time) uint32_t 1480 drivers/md/dm-thin-metadata.c uint32_t exception_time; uint32_t 1746 drivers/md/dm-thin-metadata.c uint32_t ref_count; uint32_t 239 drivers/md/dm-thin.c uint32_t sectors_per_block; uint32_t 2846 drivers/md/dm-thin.c static bool is_factor(sector_t block_size, uint32_t n) uint32_t 15 drivers/md/dm-unstripe.c uint32_t stripes; uint32_t 17 drivers/md/dm-unstripe.c uint32_t unstripe; uint32_t 21 drivers/md/dm-unstripe.c uint32_t chunk_size; uint32_t 1057 drivers/md/dm.c ti->max_io_len = (uint32_t) len; uint32_t 2902 drivers/md/dm.c uint32_t dm_next_uevent_seq(struct mapped_device *md) uint32_t 2907 drivers/md/dm.c uint32_t dm_get_event_nr(struct mapped_device *md) uint32_t 23 drivers/md/md-cluster.c uint32_t flags; /* flags to pass to dlm_lock() */ uint32_t 391 drivers/md/md-cluster.c uint32_t generation) uint32_t 144 drivers/md/persistent-data/dm-array.c static uint32_t calc_max_entries(size_t value_size, size_t size_of_block) uint32_t 153 drivers/md/persistent-data/dm-array.c uint32_t max_entries, uint32_t 179 drivers/md/persistent-data/dm-array.c uint32_t nr_entries; uint32_t 203 drivers/md/persistent-data/dm-array.c uint32_t nr_entries; uint32_t 352 drivers/md/persistent-data/dm-array.c uint32_t max_entries, uint32_t 353 drivers/md/persistent-data/dm-array.c unsigned block_index, uint32_t nr, uint32_t 505 drivers/md/persistent-data/dm-array.c static int grow_extend_tail_block(struct resize *resize, uint32_t new_nr_entries) uint32_t 590 drivers/md/persistent-data/dm-array.c uint32_t ref_count; uint32_t 656 drivers/md/persistent-data/dm-array.c uint32_t old_size, uint32_t new_size, uint32_t 688 drivers/md/persistent-data/dm-array.c uint32_t old_size, uint32_t new_size, uint32_t 722 drivers/md/persistent-data/dm-array.c uint32_t size, value_fn fn, void *context) uint32_t 769 drivers/md/persistent-data/dm-array.c uint32_t index, void *value_le) uint32_t 797 drivers/md/persistent-data/dm-array.c uint32_t index, const void *value, dm_block_t *new_root) uint32_t 838 drivers/md/persistent-data/dm-array.c uint32_t index, const void *value, dm_block_t *new_root) uint32_t 979 drivers/md/persistent-data/dm-array.c int dm_array_cursor_skip(struct dm_array_cursor *c, uint32_t count) uint32_t 984 drivers/md/persistent-data/dm-array.c uint32_t remaining = le32_to_cpu(c->ab->nr_entries) - c->index; uint32_t 110 drivers/md/persistent-data/dm-array.h uint32_t old_size, uint32_t new_size, uint32_t 129 drivers/md/persistent-data/dm-array.h typedef int (*value_fn)(uint32_t index, void *value_le, void *context); uint32_t 131 drivers/md/persistent-data/dm-array.h uint32_t size, value_fn fn, void *context); uint32_t 150 drivers/md/persistent-data/dm-array.h uint32_t index, void *value); uint32_t 168 drivers/md/persistent-data/dm-array.h uint32_t index, const void *value, dm_block_t *new_root) uint32_t 208 drivers/md/persistent-data/dm-array.h uint32_t dm_array_cursor_index(struct dm_array_cursor *c); uint32_t 210 drivers/md/persistent-data/dm-array.h int dm_array_cursor_skip(struct dm_array_cursor *c, uint32_t count); uint32_t 48 drivers/md/persistent-data/dm-bitset.c static int pack_bits(uint32_t index, void *value, void *context) uint32_t 73 drivers/md/persistent-data/dm-bitset.c uint32_t size, bit_value_fn fn, void *context) uint32_t 85 drivers/md/persistent-data/dm-bitset.c uint32_t old_nr_entries, uint32_t new_nr_entries, uint32_t 88 drivers/md/persistent-data/dm-bitset.c uint32_t old_blocks = dm_div_up(old_nr_entries, BITS_PER_ARRAY_ENTRY); uint32_t 89 drivers/md/persistent-data/dm-bitset.c uint32_t new_blocks = dm_div_up(new_nr_entries, BITS_PER_ARRAY_ENTRY); uint32_t 129 drivers/md/persistent-data/dm-bitset.c uint32_t array_index) uint32_t 147 drivers/md/persistent-data/dm-bitset.c uint32_t index, dm_block_t *new_root) uint32_t 165 drivers/md/persistent-data/dm-bitset.c uint32_t index, dm_block_t *new_root) uint32_t 182 drivers/md/persistent-data/dm-bitset.c uint32_t index, dm_block_t *new_root) uint32_t 199 drivers/md/persistent-data/dm-bitset.c uint32_t index, dm_block_t *new_root, bool *result) uint32_t 230 drivers/md/persistent-data/dm-bitset.c dm_block_t root, uint32_t nr_entries, uint32_t 276 drivers/md/persistent-data/dm-bitset.c int dm_bitset_cursor_skip(struct dm_bitset_cursor *c, uint32_t count) uint32_t 280 drivers/md/persistent-data/dm-bitset.c uint32_t nr_array_skip; uint32_t 281 drivers/md/persistent-data/dm-bitset.c uint32_t remaining_in_word = 64 - c->bit_index; uint32_t 70 drivers/md/persistent-data/dm-bitset.h uint32_t current_index; uint32_t 107 drivers/md/persistent-data/dm-bitset.h typedef int (*bit_value_fn)(uint32_t index, bool *value, void *context); uint32_t 109 drivers/md/persistent-data/dm-bitset.h uint32_t size, bit_value_fn fn, void *context); uint32_t 122 drivers/md/persistent-data/dm-bitset.h uint32_t old_nr_entries, uint32_t new_nr_entries, uint32_t 141 drivers/md/persistent-data/dm-bitset.h uint32_t index, dm_block_t *new_root); uint32_t 154 drivers/md/persistent-data/dm-bitset.h uint32_t index, dm_block_t *new_root); uint32_t 168 drivers/md/persistent-data/dm-bitset.h uint32_t index, dm_block_t *new_root, bool *result); uint32_t 184 drivers/md/persistent-data/dm-bitset.h uint32_t entries_remaining; uint32_t 185 drivers/md/persistent-data/dm-bitset.h uint32_t array_index; uint32_t 186 drivers/md/persistent-data/dm-bitset.h uint32_t bit_index; uint32_t 195 drivers/md/persistent-data/dm-bitset.h dm_block_t root, uint32_t nr_entries, uint32_t 200 drivers/md/persistent-data/dm-bitset.h int dm_bitset_cursor_skip(struct dm_bitset_cursor *c, uint32_t count); uint32_t 108 drivers/md/persistent-data/dm-btree-internal.h static inline __le64 *key_ptr(struct btree_node *n, uint32_t index) uint32_t 118 drivers/md/persistent-data/dm-btree-internal.h static inline void *value_ptr(struct btree_node *n, uint32_t index) uint32_t 120 drivers/md/persistent-data/dm-btree-internal.h uint32_t value_size = le32_to_cpu(n->header.value_size); uint32_t 127 drivers/md/persistent-data/dm-btree-internal.h static inline uint64_t value64(struct btree_node *n, uint32_t index) uint32_t 58 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_entries = le32_to_cpu(n->header.nr_entries); uint32_t 59 drivers/md/persistent-data/dm-btree-remove.c uint32_t value_size = le32_to_cpu(n->header.value_size); uint32_t 84 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_left = le32_to_cpu(left->header.nr_entries); uint32_t 85 drivers/md/persistent-data/dm-btree-remove.c uint32_t value_size = le32_to_cpu(left->header.value_size); uint32_t 115 drivers/md/persistent-data/dm-btree-remove.c uint32_t value_size = le32_to_cpu(n->header.value_size); uint32_t 175 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_left = le32_to_cpu(left->header.nr_entries); uint32_t 176 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_right = le32_to_cpu(right->header.nr_entries); uint32_t 177 drivers/md/persistent-data/dm-btree-remove.c uint32_t max_entries = le32_to_cpu(left->header.max_entries); uint32_t 178 drivers/md/persistent-data/dm-btree-remove.c uint32_t r_max_entries = le32_to_cpu(right->header.max_entries); uint32_t 204 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_left = le32_to_cpu(left->header.nr_entries); uint32_t 205 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_right = le32_to_cpu(right->header.nr_entries); uint32_t 272 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_left, uint32_t nr_center, uint32_t nr_right) uint32_t 274 drivers/md/persistent-data/dm-btree-remove.c uint32_t max_entries = le32_to_cpu(left->header.max_entries); uint32_t 303 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_left, uint32_t nr_center, uint32_t nr_right) uint32_t 306 drivers/md/persistent-data/dm-btree-remove.c uint32_t max_entries = le32_to_cpu(left->header.max_entries); uint32_t 354 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_left = le32_to_cpu(left->header.nr_entries); uint32_t 355 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_center = le32_to_cpu(center->header.nr_entries); uint32_t 356 drivers/md/persistent-data/dm-btree-remove.c uint32_t nr_right = le32_to_cpu(right->header.nr_entries); uint32_t 45 drivers/md/persistent-data/dm-btree-spine.c uint32_t flags; uint32_t 75 drivers/md/persistent-data/dm-btree.c uint32_t nr_entries = le32_to_cpu(n->header.nr_entries); uint32_t 89 drivers/md/persistent-data/dm-btree.c uint32_t nr_entries = le32_to_cpu(node->header.nr_entries); uint32_t 114 drivers/md/persistent-data/dm-btree.c static uint32_t calc_max_entries(size_t value_size, size_t block_size) uint32_t 116 drivers/md/persistent-data/dm-btree.c uint32_t total, n; uint32_t 132 drivers/md/persistent-data/dm-btree.c uint32_t max_entries; uint32_t 211 drivers/md/persistent-data/dm-btree.c uint32_t ref_count; uint32_t 230 drivers/md/persistent-data/dm-btree.c uint32_t flags; uint32_t 292 drivers/md/persistent-data/dm-btree.c uint32_t flags; uint32_t 349 drivers/md/persistent-data/dm-btree.c uint32_t flags, nr_entries; uint32_t 423 drivers/md/persistent-data/dm-btree.c uint32_t flags, nr_entries; uint32_t 872 drivers/md/persistent-data/dm-btree.c uint32_t flags; uint32_t 1137 drivers/md/persistent-data/dm-btree.c int dm_btree_cursor_skip(struct dm_btree_cursor *c, uint32_t count) uint32_t 46 drivers/md/persistent-data/dm-btree.h uint32_t size; uint32_t 212 drivers/md/persistent-data/dm-btree.h int dm_btree_cursor_skip(struct dm_btree_cursor *c, uint32_t count); uint32_t 212 drivers/md/persistent-data/dm-space-map-common.c ll->ref_count_info.value_type.size = sizeof(uint32_t); uint32_t 277 drivers/md/persistent-data/dm-space-map-common.c int sm_ll_lookup_bitmap(struct ll_disk *ll, dm_block_t b, uint32_t *result) uint32_t 302 drivers/md/persistent-data/dm-space-map-common.c uint32_t *result) uint32_t 316 drivers/md/persistent-data/dm-space-map-common.c int sm_ll_lookup(struct ll_disk *ll, dm_block_t b, uint32_t *result) uint32_t 346 drivers/md/persistent-data/dm-space-map-common.c uint32_t bit_end; uint32_t 387 drivers/md/persistent-data/dm-space-map-common.c uint32_t count; uint32_t 411 drivers/md/persistent-data/dm-space-map-common.c int (*mutator)(void *context, uint32_t old, uint32_t *new), uint32_t 415 drivers/md/persistent-data/dm-space-map-common.c uint32_t bit, old, ref_count; uint32_t 498 drivers/md/persistent-data/dm-space-map-common.c static int set_ref_count(void *context, uint32_t old, uint32_t *new) uint32_t 500 drivers/md/persistent-data/dm-space-map-common.c *new = *((uint32_t *) context); uint32_t 505 drivers/md/persistent-data/dm-space-map-common.c uint32_t ref_count, enum allocation_event *ev) uint32_t 510 drivers/md/persistent-data/dm-space-map-common.c static int inc_ref_count(void *context, uint32_t old, uint32_t *new) uint32_t 521 drivers/md/persistent-data/dm-space-map-common.c static int dec_ref_count(void *context, uint32_t old, uint32_t *new) uint32_t 62 drivers/md/persistent-data/dm-space-map-common.h uint32_t block_size; uint32_t 63 drivers/md/persistent-data/dm-space-map-common.h uint32_t entries_per_block; uint32_t 108 drivers/md/persistent-data/dm-space-map-common.h int sm_ll_lookup_bitmap(struct ll_disk *ll, dm_block_t b, uint32_t *result); uint32_t 109 drivers/md/persistent-data/dm-space-map-common.h int sm_ll_lookup(struct ll_disk *ll, dm_block_t b, uint32_t *result); uint32_t 114 drivers/md/persistent-data/dm-space-map-common.h int sm_ll_insert(struct ll_disk *ll, dm_block_t b, uint32_t ref_count, enum allocation_event *ev); uint32_t 65 drivers/md/persistent-data/dm-space-map-disk.c uint32_t *result) uint32_t 75 drivers/md/persistent-data/dm-space-map-disk.c uint32_t count; uint32_t 87 drivers/md/persistent-data/dm-space-map-disk.c uint32_t count) uint32_t 90 drivers/md/persistent-data/dm-space-map-disk.c uint32_t old_count; uint32_t 146 drivers/md/persistent-data/dm-space-map-disk.c uint32_t old_count; uint32_t 301 drivers/md/persistent-data/dm-space-map-metadata.c uint32_t *result) uint32_t 346 drivers/md/persistent-data/dm-space-map-metadata.c uint32_t rc; uint32_t 393 drivers/md/persistent-data/dm-space-map-metadata.c uint32_t count) uint32_t 604 drivers/md/persistent-data/dm-space-map-metadata.c uint32_t *result) uint32_t 622 drivers/md/persistent-data/dm-space-map-metadata.c uint32_t count) uint32_t 42 drivers/md/persistent-data/dm-space-map.h int (*get_count)(struct dm_space_map *sm, dm_block_t b, uint32_t *result); uint32_t 45 drivers/md/persistent-data/dm-space-map.h int (*set_count)(struct dm_space_map *sm, dm_block_t b, uint32_t count); uint32_t 98 drivers/md/persistent-data/dm-space-map.h uint32_t *result) uint32_t 110 drivers/md/persistent-data/dm-space-map.h uint32_t count) uint32_t 374 drivers/md/persistent-data/dm-transaction-manager.c uint32_t *result) uint32_t 107 drivers/md/persistent-data/dm-transaction-manager.h uint32_t *result); uint32_t 23 drivers/media/dvb-frontends/as102_fe.c uint32_t ber; uint32_t 14 drivers/media/dvb-frontends/as102_fe.h int (*stream_ctrl)(void *priv, int acquire, uint32_t elna_cfg); uint32_t 114 drivers/media/dvb-frontends/as102_fe_types.h uint32_t freq; uint32_t 146 drivers/media/dvb-frontends/as102_fe_types.h uint32_t frame_count; uint32_t 148 drivers/media/dvb-frontends/as102_fe_types.h uint32_t bad_frame_count; uint32_t 150 drivers/media/dvb-frontends/as102_fe_types.h uint32_t bytes_fixed_by_rs; uint32_t 168 drivers/media/dvb-frontends/as102_fe_types.h uint32_t value32; /* 32 bit value */ uint32_t 174 drivers/media/dvb-frontends/as102_fe_types.h uint32_t addr; uint32_t 1735 drivers/media/dvb-frontends/cxd2841er.c static uint32_t sony_log(uint32_t x) uint32_t 504 drivers/media/dvb-frontends/dib0070.c uint32_t ret; uint32_t 1968 drivers/media/dvb-frontends/dib8000.c static u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf) uint32_t 53 drivers/media/dvb-frontends/dib8000.h u32 (*ctrl_timf)(struct dvb_frontend *fe, uint8_t op, uint32_t timf); uint32_t 518 drivers/media/dvb-frontends/helene.c uint32_t frequency4kHz = 0; uint32_t 19 drivers/media/i2c/smiapp-pll.c static inline uint32_t clk_div_even(uint32_t a) uint32_t 21 drivers/media/i2c/smiapp-pll.c return max_t(uint32_t, 1, a & ~1); uint32_t 25 drivers/media/i2c/smiapp-pll.c static inline uint32_t clk_div_even_up(uint32_t a) uint32_t 32 drivers/media/i2c/smiapp-pll.c static inline uint32_t is_one_or_even(uint32_t a) uint32_t 42 drivers/media/i2c/smiapp-pll.c static int bounds_check(struct device *dev, uint32_t val, uint32_t 43 drivers/media/i2c/smiapp-pll.c uint32_t min, uint32_t max, char *str) uint32_t 154 drivers/media/i2c/smiapp-pll.c struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul, uint32_t 155 drivers/media/i2c/smiapp-pll.c uint32_t div, uint32_t lane_op_clock_ratio) uint32_t 157 drivers/media/i2c/smiapp-pll.c uint32_t sys_div; uint32_t 158 drivers/media/i2c/smiapp-pll.c uint32_t best_pix_div = INT_MAX >> 1; uint32_t 159 drivers/media/i2c/smiapp-pll.c uint32_t vt_op_binning_div; uint32_t 166 drivers/media/i2c/smiapp-pll.c uint32_t more_mul_min, more_mul_max; uint32_t 167 drivers/media/i2c/smiapp-pll.c uint32_t more_mul_factor; uint32_t 168 drivers/media/i2c/smiapp-pll.c uint32_t min_vt_div, max_vt_div, vt_div; uint32_t 169 drivers/media/i2c/smiapp-pll.c uint32_t min_sys_div, max_sys_div; uint32_t 184 drivers/media/i2c/smiapp-pll.c min_t(uint32_t, uint32_t 298 drivers/media/i2c/smiapp-pll.c min_vt_div = max_t(uint32_t, min_vt_div, uint32_t 394 drivers/media/i2c/smiapp-pll.c uint32_t lane_op_clock_ratio; uint32_t 395 drivers/media/i2c/smiapp-pll.c uint32_t mul, div; uint32_t 25 drivers/media/i2c/smiapp-pll.h uint32_t sys_clk_freq_hz; uint32_t 26 drivers/media/i2c/smiapp-pll.h uint32_t pix_clk_freq_hz; uint32_t 46 drivers/media/i2c/smiapp-pll.h uint32_t link_freq; uint32_t 47 drivers/media/i2c/smiapp-pll.h uint32_t ext_clk_freq_hz; uint32_t 52 drivers/media/i2c/smiapp-pll.h uint32_t pll_ip_clk_freq_hz; uint32_t 53 drivers/media/i2c/smiapp-pll.h uint32_t pll_op_clk_freq_hz; uint32_t 57 drivers/media/i2c/smiapp-pll.h uint32_t pixel_rate_csi; uint32_t 58 drivers/media/i2c/smiapp-pll.h uint32_t pixel_rate_pixel_array; uint32_t 64 drivers/media/i2c/smiapp-pll.h uint32_t min_sys_clk_freq_hz; uint32_t 65 drivers/media/i2c/smiapp-pll.h uint32_t max_sys_clk_freq_hz; uint32_t 68 drivers/media/i2c/smiapp-pll.h uint32_t min_pix_clk_freq_hz; uint32_t 69 drivers/media/i2c/smiapp-pll.h uint32_t max_pix_clk_freq_hz; uint32_t 74 drivers/media/i2c/smiapp-pll.h uint32_t min_ext_clk_freq_hz; uint32_t 75 drivers/media/i2c/smiapp-pll.h uint32_t max_ext_clk_freq_hz; uint32_t 78 drivers/media/i2c/smiapp-pll.h uint32_t min_pll_ip_freq_hz; uint32_t 79 drivers/media/i2c/smiapp-pll.h uint32_t max_pll_ip_freq_hz; uint32_t 82 drivers/media/i2c/smiapp-pll.h uint32_t min_pll_op_freq_hz; uint32_t 83 drivers/media/i2c/smiapp-pll.h uint32_t max_pll_op_freq_hz; uint32_t 89 drivers/media/i2c/smiapp-pll.h uint32_t min_line_length_pck_bin; uint32_t 90 drivers/media/i2c/smiapp-pll.h uint32_t min_line_length_pck; uint32_t 17 drivers/media/i2c/smiapp/smiapp-regs.c static uint32_t float_to_u32_mul_1000000(struct i2c_client *client, uint32_t 18 drivers/media/i2c/smiapp/smiapp-regs.c uint32_t phloat) uint32_t 4236 drivers/media/pci/bt8xx/bttv-cards.c uint32_t dataRead = 0; uint32_t 50 drivers/media/pci/cobalt/cobalt-irq.c uint32_t stat = ioread32(&vmr->irq_status); uint32_t 15 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t irq_status; /* Reg 0x0000 */ uint32_t 17 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t vsync_time; /* Reg 0x0004 */ uint32_t 18 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t vback_porch; /* Reg 0x0008 */ uint32_t 19 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t vactive_area; /* Reg 0x000c */ uint32_t 20 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t vfront_porch; /* Reg 0x0010 */ uint32_t 22 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t hsync_time; /* Reg 0x0014 */ uint32_t 23 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t hback_porch; /* Reg 0x0018 */ uint32_t 24 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t hactive_area; /* Reg 0x001c */ uint32_t 25 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t hfront_porch; /* Reg 0x0020 */ uint32_t 26 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t control; /* Reg 0x0024, Default=0x0 */ uint32_t 27 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t irq_triggers; /* Reg 0x0028, Default=0xff */ uint32_t 30 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t hsync_timeout_val; /* Reg 0x002c, Default=0x1fff */ uint32_t 31 drivers/media/pci/cobalt/m00233_video_measure_memmap_package.h uint32_t status; /* Reg 0x0030 */ uint32_t 15 drivers/media/pci/cobalt/m00235_fdma_packer_memmap_package.h uint32_t control; /* Reg 0x0000, Default=0x0 */ uint32_t 15 drivers/media/pci/cobalt/m00389_cvi_memmap_package.h uint32_t control; /* Reg 0x0000, Default=0x0 */ uint32_t 16 drivers/media/pci/cobalt/m00389_cvi_memmap_package.h uint32_t frame_width; /* Reg 0x0004, Default=0x10 */ uint32_t 17 drivers/media/pci/cobalt/m00389_cvi_memmap_package.h uint32_t frame_height; /* Reg 0x0008, Default=0xc */ uint32_t 18 drivers/media/pci/cobalt/m00389_cvi_memmap_package.h uint32_t freewheel_period; /* Reg 0x000c, Default=0x0 */ uint32_t 19 drivers/media/pci/cobalt/m00389_cvi_memmap_package.h uint32_t error_color; /* Reg 0x0010, Default=0x0 */ uint32_t 20 drivers/media/pci/cobalt/m00389_cvi_memmap_package.h uint32_t status; /* Reg 0x0014 */ uint32_t 15 drivers/media/pci/cobalt/m00460_evcnt_memmap_package.h uint32_t control; /* Reg 0x0000, Default=0x0 */ uint32_t 16 drivers/media/pci/cobalt/m00460_evcnt_memmap_package.h uint32_t count; /* Reg 0x0004 */ uint32_t 15 drivers/media/pci/cobalt/m00473_freewheel_memmap_package.h uint32_t ctrl; /* Reg 0x0000, Default=0x0 */ uint32_t 16 drivers/media/pci/cobalt/m00473_freewheel_memmap_package.h uint32_t status; /* Reg 0x0004 */ uint32_t 17 drivers/media/pci/cobalt/m00473_freewheel_memmap_package.h uint32_t active_length; /* Reg 0x0008, Default=0x1fa400 */ uint32_t 18 drivers/media/pci/cobalt/m00473_freewheel_memmap_package.h uint32_t total_length; /* Reg 0x000c, Default=0x31151b */ uint32_t 19 drivers/media/pci/cobalt/m00473_freewheel_memmap_package.h uint32_t data_width; /* Reg 0x0010 */ uint32_t 20 drivers/media/pci/cobalt/m00473_freewheel_memmap_package.h uint32_t output_color; /* Reg 0x0014, Default=0xffff */ uint32_t 21 drivers/media/pci/cobalt/m00473_freewheel_memmap_package.h uint32_t clk_freq; /* Reg 0x0018 */ uint32_t 16 drivers/media/pci/cobalt/m00479_clk_loss_detector_memmap_package.h uint32_t ctrl; /* Reg 0x0000, Default=0x0 */ uint32_t 17 drivers/media/pci/cobalt/m00479_clk_loss_detector_memmap_package.h uint32_t status; /* Reg 0x0004 */ uint32_t 19 drivers/media/pci/cobalt/m00479_clk_loss_detector_memmap_package.h uint32_t ref_clk_cnt_val; /* Reg 0x0008, Default=0xc4 */ uint32_t 22 drivers/media/pci/cobalt/m00479_clk_loss_detector_memmap_package.h uint32_t test_clk_cnt_val; /* Reg 0x000c, Default=0xa */ uint32_t 15 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t control; /* Reg 0x0000, Default=0x0 */ uint32_t 16 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t sync_generator_h_sync_length; /* Reg 0x0004, Default=0x0 */ uint32_t 17 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t sync_generator_h_backporch_length; /* Reg 0x0008, Default=0x0 */ uint32_t 18 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t sync_generator_h_active_length; /* Reg 0x000c, Default=0x0 */ uint32_t 19 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t sync_generator_h_frontporch_length; /* Reg 0x0010, Default=0x0 */ uint32_t 20 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t sync_generator_v_sync_length; /* Reg 0x0014, Default=0x0 */ uint32_t 21 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t sync_generator_v_backporch_length; /* Reg 0x0018, Default=0x0 */ uint32_t 22 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t sync_generator_v_active_length; /* Reg 0x001c, Default=0x0 */ uint32_t 23 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t sync_generator_v_frontporch_length; /* Reg 0x0020, Default=0x0 */ uint32_t 24 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t error_color; /* Reg 0x0024, Default=0x0 */ uint32_t 25 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t rd_status; /* Reg 0x0028 */ uint32_t 26 drivers/media/pci/cobalt/m00514_syncgen_flow_evcnt_memmap_package.h uint32_t rd_evcnt_count; /* Reg 0x002c */ uint32_t 609 drivers/media/pci/cx23885/cx23885-core.c uint32_t reg1_val, reg2_val; uint32_t 1533 drivers/media/pci/cx23885/cx23885-core.c uint32_t reg1_val; uint32_t 1534 drivers/media/pci/cx23885/cx23885-core.c uint32_t reg2_val; uint32_t 938 drivers/media/pci/cx23885/cx23885-dvb.c uint32_t mem = 0; uint32_t 145 drivers/media/pci/tw686x/tw686x.h static inline uint32_t reg_read(struct tw686x_dev *dev, unsigned int reg) uint32_t 151 drivers/media/pci/tw686x/tw686x.h uint32_t value) uint32_t 1299 drivers/media/platform/coda/coda-common.c static uint32_t coda_timeperframe_to_frate(struct v4l2_fract *timeperframe) uint32_t 57 drivers/media/platform/cros-ec-cec/cros-ec-cec.c uint32_t events = cros_ec->event_data.data.cec_events; uint32_t 32 drivers/media/platform/mtk-mdp/mtk_mdp_ipi.h uint32_t msg_id; uint32_t 33 drivers/media/platform/mtk-mdp/mtk_mdp_ipi.h uint32_t ipi_id; uint32_t 45 drivers/media/platform/mtk-mdp/mtk_mdp_ipi.h uint32_t msg_id; uint32_t 46 drivers/media/platform/mtk-mdp/mtk_mdp_ipi.h uint32_t ipi_id; uint32_t 48 drivers/media/platform/mtk-mdp/mtk_mdp_ipi.h uint32_t vpu_inst_addr; uint32_t 60 drivers/media/platform/mtk-mdp/mtk_mdp_ipi.h uint32_t msg_id; uint32_t 61 drivers/media/platform/mtk-mdp/mtk_mdp_ipi.h uint32_t ipi_id; uint32_t 63 drivers/media/platform/mtk-mdp/mtk_mdp_ipi.h uint32_t vpu_inst_addr; uint32_t 95 drivers/media/platform/mtk-mdp/mtk_mdp_vpu.c static int mtk_mdp_vpu_send_ap_ipi(struct mtk_mdp_vpu *vpu, uint32_t msg_id) uint32_t 23 drivers/media/platform/mtk-mdp/mtk_mdp_vpu.h uint32_t inst_addr; uint32_t 48 drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c uint32_t reserved; uint32_t 79 drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c uint32_t dpb_sz; uint32_t 80 drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c uint32_t resolution_changed; uint32_t 81 drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c uint32_t realloc_mv_buf; uint32_t 82 drivers/media/platform/mtk-vcodec/vdec/vdec_h264_if.c uint32_t reserved; uint32_t 70 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c uint32_t bs_sz; uint32_t 71 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c uint32_t resolution_changed; uint32_t 72 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c uint32_t show_frame; uint32_t 73 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c uint32_t wait_key_frame; uint32_t 87 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c uint32_t dec_table[VP8_DEC_TABLE_SZ]; uint32_t 88 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c uint32_t segment_buf[VP8_HW_SEGMENT_DATA_SZ][VP8_HW_SEGMENT_UINT]; uint32_t 89 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c uint32_t load_data; uint32_t 123 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c uint32_t inst_addr; uint32_t 35 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t msg_id; uint32_t 36 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t vpu_inst_addr; uint32_t 46 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t msg_id; uint32_t 58 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t msg_id; uint32_t 59 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t reserved; uint32_t 74 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t msg_id; uint32_t 75 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t vpu_inst_addr; uint32_t 76 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t data[3]; uint32_t 77 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t reserved; uint32_t 88 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t msg_id; uint32_t 91 drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h uint32_t vpu_inst_addr; uint32_t 66 drivers/media/platform/mtk-vcodec/vdec_vpu_if.c mtk_vcodec_debug(vpu, "id=%X", *(uint32_t *)msg); uint32_t 74 drivers/media/platform/mtk-vcodec/vdec_vpu_if.c vpu->id, *(uint32_t *)msg, err); uint32_t 123 drivers/media/platform/mtk-vcodec/vdec_vpu_if.c int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t *data, unsigned int len) uint32_t 29 drivers/media/platform/mtk-vcodec/vdec_vpu_if.h uint32_t inst_addr; uint32_t 52 drivers/media/platform/mtk-vcodec/vdec_vpu_if.h int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t *data, unsigned int len); uint32_t 43 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t msg_id; uint32_t 44 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t reserved; uint32_t 58 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t msg_id; uint32_t 59 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t vpu_inst_addr; uint32_t 60 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t param_id; uint32_t 61 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t data_item; uint32_t 62 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t data[8]; uint32_t 77 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t msg_id; uint32_t 78 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t vpu_inst_addr; uint32_t 79 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t bs_mode; uint32_t 80 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t input_addr[3]; uint32_t 81 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t bs_addr; uint32_t 82 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t bs_size; uint32_t 92 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t msg_id; uint32_t 93 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t vpu_inst_addr; uint32_t 111 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t msg_id; uint32_t 112 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t status; uint32_t 128 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t msg_id; uint32_t 129 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t status; uint32_t 131 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t vpu_inst_addr; uint32_t 132 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t reserved; uint32_t 145 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t msg_id; uint32_t 146 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t status; uint32_t 148 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t param_id; uint32_t 149 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t data_item; uint32_t 150 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t data[6]; uint32_t 180 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t msg_id; uint32_t 181 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t status; uint32_t 183 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t state; uint32_t 184 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t is_key_frm; uint32_t 185 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t bs_size; uint32_t 186 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t reserved; uint32_t 196 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t msg_id; uint32_t 197 drivers/media/platform/mtk-vcodec/venc_ipi_msg.h uint32_t status; uint32_t 74 drivers/media/platform/mtk-vcodec/venc_vpu_if.c *(uint32_t *)msg, len, status); uint32_t 41 drivers/media/rc/iguanair.c uint32_t carrier; uint32_t 280 drivers/media/rc/iguanair.c static int iguanair_set_tx_carrier(struct rc_dev *dev, uint32_t carrier) uint32_t 290 drivers/media/rc/iguanair.c uint32_t cycles, fours, sevens; uint32_t 322 drivers/media/rc/iguanair.c static int iguanair_set_tx_mask(struct rc_dev *dev, uint32_t mask) uint32_t 254 drivers/media/usb/as102/as102_drv.c static int as102_stream_ctrl(void *priv, int acquire, uint32_t elna_cfg) uint32_t 507 drivers/media/usb/as102/as10x_cmd.h uint32_t value); uint32_t 510 drivers/media/usb/as102/as10x_cmd.h uint32_t *pvalue); uint32_t 24 drivers/media/usb/as102/as10x_cmd_cfg.c uint32_t *pvalue) uint32_t 80 drivers/media/usb/as102/as10x_cmd_cfg.c uint32_t value) uint32_t 35 drivers/media/usb/as102/as10x_handle.h uint32_t rd_addr, uint16_t rd_len, uint32_t 36 drivers/media/usb/as102/as10x_handle.h uint32_t wr_addr, uint16_t wr_len); uint32_t 55 drivers/media/usb/dvb-usb/cinergyT2.h uint32_t freq; uint32_t 62 drivers/media/usb/dvb-usb/cinergyT2.h uint32_t rs_error_rate; uint32_t 36 drivers/media/usb/gspca/kinect.c uint32_t timestamp; uint32_t 54 drivers/memory/jz4780-nemc.c uint32_t clk_period; uint32_t 95 drivers/memory/jz4780-nemc.c uint32_t nfcsr; uint32_t 126 drivers/memory/jz4780-nemc.c uint32_t nfcsr; uint32_t 139 drivers/memory/jz4780-nemc.c static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc) uint32_t 151 drivers/memory/jz4780-nemc.c static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns) uint32_t 160 drivers/memory/jz4780-nemc.c uint32_t smcr, val, cycles; uint32_t 683 drivers/memstick/core/mspro_block.c param.data_address = cpu_to_be32((uint32_t)offset); uint32_t 102 drivers/message/fusion/mptfc.c static void mptfc_set_rport_loss_tmo(struct fc_rport *rport, uint32_t timeout); uint32_t 256 drivers/message/fusion/mptfc.c mptfc_set_rport_loss_tmo(struct fc_rport *rport, uint32_t timeout) uint32_t 63 drivers/mfd/da903x.c uint32_t events_mask; uint32_t 18 drivers/misc/cb710/core.c int reg, uint32_t mask, uint32_t xor) uint32_t 25 drivers/misc/cb710/sgbuf2.c static uint32_t sg_dwiter_read_buffer(struct sg_mapping_iter *miter) uint32_t 28 drivers/misc/cb710/sgbuf2.c uint32_t data; uint32_t 54 drivers/misc/cb710/sgbuf2.c static bool sg_dwiter_get_next_block(struct sg_mapping_iter *miter, uint32_t **ptr) uint32_t 90 drivers/misc/cb710/sgbuf2.c uint32_t cb710_sg_dwiter_read_next_block(struct sg_mapping_iter *miter) uint32_t 92 drivers/misc/cb710/sgbuf2.c uint32_t *ptr = NULL; uint32_t 101 drivers/misc/cb710/sgbuf2.c static void sg_dwiter_write_slow(struct sg_mapping_iter *miter, uint32_t data) uint32_t 130 drivers/misc/cb710/sgbuf2.c void cb710_sg_dwiter_write_next_block(struct sg_mapping_iter *miter, uint32_t data) uint32_t 132 drivers/misc/cb710/sgbuf2.c uint32_t *ptr = NULL; uint32_t 47 drivers/misc/cs5535-mfgpt.c uint32_t msr, mask, value, dummy; uint32_t 99 drivers/misc/cs5535-mfgpt.c uint32_t zsel, lpc, dummy; uint32_t 251 drivers/misc/cs5535-mfgpt.c uint32_t val, dummy; uint32_t 884 drivers/misc/fastrpc.c u32 kernel, uint32_t handle) uint32_t 464 drivers/misc/habanalabs/device.c uint32_t hl_device_utilization(struct hl_device *hdev, uint32_t period_ms) uint32_t 1479 drivers/misc/habanalabs/habanalabs.h uint32_t hl_device_utilization(struct hl_device *hdev, uint32_t period_ms); uint32_t 70 drivers/misc/ibmvmc.c static inline void h_free_crq(uint32_t unit_address) uint32_t 514 drivers/misc/mic/host/mic_x100.c uint32_t smpt_reg_val = BUILD_SMPT(SNOOP_ON, uint32_t 524 drivers/mmc/core/mmc_test.c do_div(bytes, (uint32_t)ns); uint32_t 427 drivers/mmc/host/android-goldfish.c uint32_t state; uint32_t 152 drivers/mmc/host/jz4740_mmc.c uint32_t cmdat; uint32_t 154 drivers/mmc/host/jz4740_mmc.c uint32_t irq_mask; uint32_t 175 drivers/mmc/host/jz4740_mmc.c uint32_t val) uint32_t 184 drivers/mmc/host/jz4740_mmc.c uint32_t val) uint32_t 192 drivers/mmc/host/jz4740_mmc.c static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host) uint32_t 385 drivers/mmc/host/jz4740_mmc.c uint32_t status; uint32_t 396 drivers/mmc/host/jz4740_mmc.c uint32_t status; uint32_t 424 drivers/mmc/host/jz4740_mmc.c uint32_t status; uint32_t 470 drivers/mmc/host/jz4740_mmc.c uint32_t *buf; uint32_t 525 drivers/mmc/host/jz4740_mmc.c uint32_t *buf; uint32_t 526 drivers/mmc/host/jz4740_mmc.c uint32_t d; uint32_t 527 drivers/mmc/host/jz4740_mmc.c uint32_t status; uint32_t 634 drivers/mmc/host/jz4740_mmc.c uint32_t cmdat = host->cmdat; uint32_t 794 drivers/mmc/host/jz4740_mmc.c uint32_t irq_reg, status, tmp; uint32_t 1307 drivers/mmc/host/omap_hsmmc.c uint32_t reg, clkd, dto = 0; uint32_t 176 drivers/mtd/chips/cfi_cmdset_0001.c uint32_t features = 0; uint32_t 40 drivers/mtd/chips/cfi_util.c uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, uint32_t 46 drivers/mtd/chips/cfi_util.c uint32_t addr; uint32_t 203 drivers/mtd/chips/cfi_util.c uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base, uint32_t 208 drivers/mtd/chips/cfi_util.c uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, map, cfi); uint32_t 248 drivers/mtd/chips/cfi_util.c int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map, uint32_t 286 drivers/mtd/chips/cfi_util.c void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map, uint32_t 205 drivers/mtd/chips/jedec_probe.c uint32_t addr1; uint32_t 206 drivers/mtd/chips/jedec_probe.c uint32_t addr2; uint32_t 274 drivers/mtd/chips/jedec_probe.c const uint32_t regions[6]; uint32_t 1910 drivers/mtd/chips/jedec_probe.c static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, uint32_t 1922 drivers/mtd/chips/jedec_probe.c uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi); uint32_t 1933 drivers/mtd/chips/jedec_probe.c static inline u32 jedec_read_id(struct map_info *map, uint32_t base, uint32_t 2030 drivers/mtd/chips/jedec_probe.c static inline int jedec_match( uint32_t base, uint32_t 2069 drivers/mtd/chips/jedec_probe.c id = (uint32_t)finfo->dev_id; uint32_t 142 drivers/mtd/devices/sst25l.c static int sst25l_erase_sector(struct sst25l_flash *flash, uint32_t offset) uint32_t 169 drivers/mtd/devices/sst25l.c uint32_t addr, end; uint32_t 173 drivers/mtd/devices/sst25l.c if ((uint32_t)instr->len % mtd->erasesize) uint32_t 176 drivers/mtd/devices/sst25l.c if ((uint32_t)instr->addr % mtd->erasesize) uint32_t 256 drivers/mtd/devices/sst25l.c if ((uint32_t)to % mtd->writesize) uint32_t 285 drivers/mtd/devices/sst25l.c bytes = min_t(uint32_t, mtd->writesize, len - i); uint32_t 243 drivers/mtd/devices/st_spi_fsm.c uint32_t data_size; uint32_t 244 drivers/mtd/devices/st_spi_fsm.c uint32_t addr1; uint32_t 245 drivers/mtd/devices/st_spi_fsm.c uint32_t addr2; uint32_t 246 drivers/mtd/devices/st_spi_fsm.c uint32_t addr_cfg; uint32_t 247 drivers/mtd/devices/st_spi_fsm.c uint32_t seq_opc[5]; uint32_t 248 drivers/mtd/devices/st_spi_fsm.c uint32_t mode; uint32_t 249 drivers/mtd/devices/st_spi_fsm.c uint32_t dummy; uint32_t 250 drivers/mtd/devices/st_spi_fsm.c uint32_t status; uint32_t 252 drivers/mtd/devices/st_spi_fsm.c uint32_t seq_cfg; uint32_t 264 drivers/mtd/devices/st_spi_fsm.c uint32_t configuration; uint32_t 265 drivers/mtd/devices/st_spi_fsm.c uint32_t fifo_dir_delay; uint32_t 277 drivers/mtd/devices/st_spi_fsm.c uint32_t flags; /* flags to support config */ uint32_t 708 drivers/mtd/devices/st_spi_fsm.c static inline uint32_t stfsm_fifo_available(struct stfsm *fsm) uint32_t 717 drivers/mtd/devices/st_spi_fsm.c const uint32_t *src = (const uint32_t *)seq; uint32_t 749 drivers/mtd/devices/st_spi_fsm.c static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, uint32_t size) uint32_t 751 drivers/mtd/devices/st_spi_fsm.c uint32_t remaining = size >> 2; uint32_t 752 drivers/mtd/devices/st_spi_fsm.c uint32_t avail; uint32_t 753 drivers/mtd/devices/st_spi_fsm.c uint32_t words; uint32_t 803 drivers/mtd/devices/st_spi_fsm.c uint32_t words, i; uint32_t 836 drivers/mtd/devices/st_spi_fsm.c static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf, uint32_t 837 drivers/mtd/devices/st_spi_fsm.c uint32_t size) uint32_t 839 drivers/mtd/devices/st_spi_fsm.c uint32_t words = size >> 2; uint32_t 853 drivers/mtd/devices/st_spi_fsm.c uint32_t cmd = enter ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; uint32_t 871 drivers/mtd/devices/st_spi_fsm.c uint32_t status; uint32_t 918 drivers/mtd/devices/st_spi_fsm.c uint32_t tmp; uint32_t 956 drivers/mtd/devices/st_spi_fsm.c seq->status = (uint32_t)data | STA_PADS_1 | STA_CSDEASSERT; uint32_t 1120 drivers/mtd/devices/st_spi_fsm.c uint32_t flags = fsm->info->flags; uint32_t 1151 drivers/mtd/devices/st_spi_fsm.c uint32_t flags = fsm->info->flags; uint32_t 1152 drivers/mtd/devices/st_spi_fsm.c uint32_t data_pads; uint32_t 1209 drivers/mtd/devices/st_spi_fsm.c uint32_t flags = fsm->info->flags; uint32_t 1285 drivers/mtd/devices/st_spi_fsm.c static void stfsm_s25fl_read_dyb(struct stfsm *fsm, uint32_t offs, uint8_t *dby) uint32_t 1287 drivers/mtd/devices/st_spi_fsm.c uint32_t tmp; uint32_t 1321 drivers/mtd/devices/st_spi_fsm.c static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby) uint32_t 1333 drivers/mtd/devices/st_spi_fsm.c .status = (uint32_t)dby | STA_PADS_1 | STA_CSDEASSERT, uint32_t 1390 drivers/mtd/devices/st_spi_fsm.c uint32_t flags = info->flags; uint32_t 1391 drivers/mtd/devices/st_spi_fsm.c uint32_t data_pads; uint32_t 1392 drivers/mtd/devices/st_spi_fsm.c uint32_t offs; uint32_t 1478 drivers/mtd/devices/st_spi_fsm.c uint32_t data_pads; uint32_t 1514 drivers/mtd/devices/st_spi_fsm.c static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size, uint32_t 1515 drivers/mtd/devices/st_spi_fsm.c uint32_t offset) uint32_t 1518 drivers/mtd/devices/st_spi_fsm.c uint32_t data_pads; uint32_t 1519 drivers/mtd/devices/st_spi_fsm.c uint32_t read_mask; uint32_t 1520 drivers/mtd/devices/st_spi_fsm.c uint32_t size_ub; uint32_t 1521 drivers/mtd/devices/st_spi_fsm.c uint32_t size_lb; uint32_t 1522 drivers/mtd/devices/st_spi_fsm.c uint32_t size_mop; uint32_t 1523 drivers/mtd/devices/st_spi_fsm.c uint32_t tmp[4]; uint32_t 1524 drivers/mtd/devices/st_spi_fsm.c uint32_t page_buf[FLASH_PAGESIZE_32]; uint32_t 1552 drivers/mtd/devices/st_spi_fsm.c stfsm_read_fifo(fsm, (uint32_t *)p, size_lb); uint32_t 1576 drivers/mtd/devices/st_spi_fsm.c uint32_t size, uint32_t offset) uint32_t 1579 drivers/mtd/devices/st_spi_fsm.c uint32_t data_pads; uint32_t 1580 drivers/mtd/devices/st_spi_fsm.c uint32_t write_mask; uint32_t 1581 drivers/mtd/devices/st_spi_fsm.c uint32_t size_ub; uint32_t 1582 drivers/mtd/devices/st_spi_fsm.c uint32_t size_lb; uint32_t 1583 drivers/mtd/devices/st_spi_fsm.c uint32_t size_mop; uint32_t 1584 drivers/mtd/devices/st_spi_fsm.c uint32_t tmp[4]; uint32_t 1585 drivers/mtd/devices/st_spi_fsm.c uint32_t i; uint32_t 1586 drivers/mtd/devices/st_spi_fsm.c uint32_t page_buf[FLASH_PAGESIZE_32]; uint32_t 1635 drivers/mtd/devices/st_spi_fsm.c stfsm_write_fifo(fsm, (uint32_t *)p, size_lb); uint32_t 1674 drivers/mtd/devices/st_spi_fsm.c uint32_t bytes; uint32_t 1698 drivers/mtd/devices/st_spi_fsm.c static int stfsm_erase_sector(struct stfsm *fsm, uint32_t offset) uint32_t 1835 drivers/mtd/devices/st_spi_fsm.c uint32_t tmp[2]; uint32_t 1877 drivers/mtd/devices/st_spi_fsm.c static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode) uint32_t 1897 drivers/mtd/devices/st_spi_fsm.c static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq) uint32_t 1899 drivers/mtd/devices/st_spi_fsm.c uint32_t emi_freq; uint32_t 1900 drivers/mtd/devices/st_spi_fsm.c uint32_t clk_div; uint32_t 1976 drivers/mtd/devices/st_spi_fsm.c uint32_t boot_device_reg; uint32_t 1977 drivers/mtd/devices/st_spi_fsm.c uint32_t boot_device_spi; uint32_t 1978 drivers/mtd/devices/st_spi_fsm.c uint32_t boot_device; /* Value we read from *boot_device_reg */ uint32_t 112 drivers/mtd/ftl.c uint32_t state; uint32_t 113 drivers/mtd/ftl.c uint32_t *VirtualBlockMap; uint32_t 114 drivers/mtd/ftl.c uint32_t FreeTotal; uint32_t 116 drivers/mtd/ftl.c uint32_t Offset; uint32_t 117 drivers/mtd/ftl.c uint32_t EraseCount; uint32_t 118 drivers/mtd/ftl.c uint32_t Free; uint32_t 119 drivers/mtd/ftl.c uint32_t Deleted; uint32_t 122 drivers/mtd/ftl.c uint32_t Offset; uint32_t 123 drivers/mtd/ftl.c uint32_t EraseCount; uint32_t 127 drivers/mtd/ftl.c uint32_t *bam_cache; uint32_t 129 drivers/mtd/ftl.c uint32_t BlocksPerUnit; uint32_t 266 drivers/mtd/ftl.c part->VirtualBlockMap = vmalloc(array_size(blocks, sizeof(uint32_t))); uint32_t 270 drivers/mtd/ftl.c memset(part->VirtualBlockMap, 0xff, blocks * sizeof(uint32_t)); uint32_t 273 drivers/mtd/ftl.c part->bam_cache = kmalloc_array(part->BlocksPerUnit, sizeof(uint32_t), uint32_t 287 drivers/mtd/ftl.c part->BlocksPerUnit * sizeof(uint32_t), &retval, uint32_t 375 drivers/mtd/ftl.c uint32_t ctl; uint32_t 397 drivers/mtd/ftl.c nbam = DIV_ROUND_UP(part->BlocksPerUnit * sizeof(uint32_t) + uint32_t 403 drivers/mtd/ftl.c for (i = 0; i < nbam; i++, offset += sizeof(uint32_t)) { uint32_t 405 drivers/mtd/ftl.c ret = mtd_write(part->mbd.mtd, offset, sizeof(uint32_t), &retlen, uint32_t 434 drivers/mtd/ftl.c uint32_t src, dest, free, i; uint32_t 453 drivers/mtd/ftl.c part->BlocksPerUnit * sizeof(uint32_t), &retlen, uint32_t 571 drivers/mtd/ftl.c uint32_t best; uint32_t 687 drivers/mtd/ftl.c static uint32_t find_free(partition_t *part) uint32_t 690 drivers/mtd/ftl.c uint32_t blk; uint32_t 713 drivers/mtd/ftl.c part->BlocksPerUnit * sizeof(uint32_t), uint32_t 751 drivers/mtd/ftl.c uint32_t log_addr, bsize; uint32_t 794 drivers/mtd/ftl.c static int set_bam_entry(partition_t *part, uint32_t log_addr, uint32_t 795 drivers/mtd/ftl.c uint32_t virt_addr) uint32_t 797 drivers/mtd/ftl.c uint32_t bsize, blk, le_virt_addr; uint32_t 799 drivers/mtd/ftl.c uint32_t old_addr; uint32_t 810 drivers/mtd/ftl.c offset = (part->EUNInfo[eun].Offset + blk * sizeof(uint32_t) + uint32_t 814 drivers/mtd/ftl.c ret = mtd_read(part->mbd.mtd, offset, sizeof(uint32_t), &retlen, uint32_t 851 drivers/mtd/ftl.c ret = mtd_write(part->mbd.mtd, offset, sizeof(uint32_t), &retlen, uint32_t 865 drivers/mtd/ftl.c uint32_t bsize, log_addr, virt_addr, old_addr, blk; uint32_t 973 drivers/mtd/ftl.c uint32_t bsize = 1 << part->header.EraseUnitSize; uint32_t 979 drivers/mtd/ftl.c uint32_t old_addr = part->VirtualBlockMap[sector]; uint32_t 689 drivers/mtd/lpddr/lpddr_cmds.c static int do_xxlock(struct mtd_info *mtd, loff_t adr, uint32_t len, int thunk) uint32_t 71 drivers/mtd/maps/dc21285.c val.x[0] = *(uint32_t*)(map->virt + ofs); uint32_t 102 drivers/mtd/maps/dc21285.c *(uint32_t*)(map->virt + adr) = d.x[0]; uint32_t 109 drivers/mtd/maps/dc21285.c d.x[0] = *((uint32_t*)from); uint32_t 349 drivers/mtd/mtdchar.c uint64_t start, uint32_t length, void __user *ptr, uint32_t 350 drivers/mtd/mtdchar.c uint32_t __user *retp) uint32_t 354 drivers/mtd/mtdchar.c uint32_t retlen; uint32_t 393 drivers/mtd/mtdchar.c uint64_t start, uint32_t length, void __user *ptr, uint32_t 394 drivers/mtd/mtdchar.c uint32_t __user *retp) uint32_t 652 drivers/mtd/mtdchar.c uint32_t ur_idx; uint32_t 603 drivers/mtd/mtdconcat.c uint32_t max_erasesize, curr_erasesize; uint32_t 65 drivers/mtd/nand/raw/cafe_nand.c uint32_t ctl1; uint32_t 66 drivers/mtd/nand/raw/cafe_nand.c uint32_t ctl2; uint32_t 108 drivers/mtd/nand/raw/cafe_nand.c uint32_t irqs = cafe_readl(cafe, NAND_IRQ); uint32_t 166 drivers/mtd/nand/raw/cafe_nand.c uint32_t ctl1; uint32_t 167 drivers/mtd/nand/raw/cafe_nand.c uint32_t doneint = 0x80000000; uint32_t 255 drivers/mtd/nand/raw/cafe_nand.c uint32_t dmactl = 0xc0000000 + cafe->datalen; uint32_t 282 drivers/mtd/nand/raw/cafe_nand.c uint32_t irqs; uint32_t 336 drivers/mtd/nand/raw/cafe_nand.c uint32_t irqs = cafe_readl(cafe, NAND_IRQ); uint32_t 391 drivers/mtd/nand/raw/cafe_nand.c uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2)); uint32_t 671 drivers/mtd/nand/raw/cafe_nand.c uint32_t ctrl; uint32_t 838 drivers/mtd/nand/raw/cafe_nand.c uint32_t ctrl; uint32_t 158 drivers/mtd/nand/raw/cs553x_nand.c uint32_t ecc; uint32_t 52 drivers/mtd/nand/raw/davinci_nand.c uint32_t mask_chipsel; uint32_t 53 drivers/mtd/nand/raw/davinci_nand.c uint32_t mask_ale; uint32_t 54 drivers/mtd/nand/raw/davinci_nand.c uint32_t mask_cle; uint32_t 56 drivers/mtd/nand/raw/davinci_nand.c uint32_t core_chipsel; uint32_t 127 drivers/mtd/nand/raw/davinci_nand.c static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd) uint32_t 138 drivers/mtd/nand/raw/davinci_nand.c uint32_t nandcfr; uint32_t 177 drivers/mtd/nand/raw/davinci_nand.c uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) | uint32_t 179 drivers/mtd/nand/raw/davinci_nand.c uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) | uint32_t 181 drivers/mtd/nand/raw/davinci_nand.c uint32_t diff = eccCalc ^ eccNand; uint32_t 697 drivers/mtd/nand/raw/davinci_nand.c uint32_t val; uint32_t 364 drivers/mtd/nand/raw/diskonchip.c *(uint32_t *) (&buf[i]) = readl(docptr + DoC_2k_CDSN_IO + i); uint32_t 392 drivers/mtd/nand/raw/diskonchip.c uint32_t dword; uint32_t 253 drivers/mtd/nand/raw/fsl_elbc_nand.c uint32_t lteccr = in_be32(&lbc->lteccr); uint32_t 669 drivers/mtd/nand/raw/fsl_elbc_nand.c static int fsl_elbc_write_subpage(struct nand_chip *chip, uint32_t offset, uint32_t 670 drivers/mtd/nand/raw/fsl_elbc_nand.c uint32_t data_len, const uint8_t *buf, uint32_t 758 drivers/mtd/nand/raw/fsl_ifc_nand.c uint32_t csor = 0, csor_8k = 0, csor_ext = 0; uint32_t 759 drivers/mtd/nand/raw/fsl_ifc_nand.c uint32_t cs = priv->bank; uint32_t 38 drivers/mtd/nand/raw/fsl_upm.c uint32_t mchip_offsets[NAND_MAX_CHIPS]; uint32_t 39 drivers/mtd/nand/raw/fsl_upm.c uint32_t mchip_count; uint32_t 40 drivers/mtd/nand/raw/fsl_upm.c uint32_t mchip_number; uint32_t 42 drivers/mtd/nand/raw/fsl_upm.c uint32_t wait_flags; uint32_t 228 drivers/mtd/nand/raw/fsl_upm.c if (!prop || size != sizeof(uint32_t)) { uint32_t 236 drivers/mtd/nand/raw/fsl_upm.c if (!prop || size != sizeof(uint32_t)) { uint32_t 245 drivers/mtd/nand/raw/fsl_upm.c if (prop && (size / sizeof(uint32_t)) > 0) { uint32_t 246 drivers/mtd/nand/raw/fsl_upm.c fun->mchip_count = size / sizeof(uint32_t); uint32_t 282 drivers/mtd/nand/raw/fsl_upm.c if (prop && size == sizeof(uint32_t)) uint32_t 1494 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c static int gpmi_ecc_read_subpage(struct nand_chip *chip, uint32_t offs, uint32_t 1495 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c uint32_t len, uint8_t *buf, int page) uint32_t 144 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h uint32_t bch_flashlayout0; uint32_t 145 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h uint32_t bch_flashlayout1; uint32_t 47 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c uint32_t reg; uint32_t 69 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c uint32_t reg, status; uint32_t 122 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c uint32_t reg, status, error; uint32_t 119 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t tcea_delay; uint32_t 120 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t busy_delay; uint32_t 121 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t nand_ta; uint32_t 122 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t rd_high; uint32_t 123 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t rd_low; uint32_t 124 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t wr_high; uint32_t 125 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t wr_low; uint32_t 186 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t llptr; uint32_t 234 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t clkrate, tmp; uint32_t 441 drivers/mtd/nand/raw/lpc32xx_mlc.c uint32_t mlc_isr; uint32_t 482 drivers/mtd/nand/raw/lpc32xx_mlc.c *((uint32_t *)(buf)) = uint32_t 488 drivers/mtd/nand/raw/lpc32xx_mlc.c *((uint32_t *)(oobbuf)) = uint32_t 530 drivers/mtd/nand/raw/lpc32xx_mlc.c writel(*((uint32_t *)(buf)), uint32_t 535 drivers/mtd/nand/raw/lpc32xx_mlc.c writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base)); uint32_t 204 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t wdr_clks; uint32_t 205 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t wwidth; uint32_t 206 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t whold; uint32_t 207 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t wsetup; uint32_t 208 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t rdr_clks; uint32_t 209 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t rwidth; uint32_t 210 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t rhold; uint32_t 211 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t rsetup; uint32_t 226 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t dma_buf_len; uint32_t 233 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t *ecc_buf; uint32_t 240 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t clkrate, tmp; uint32_t 275 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t tmp; uint32_t 380 drivers/mtd/nand/raw/lpc32xx_slc.c writel((uint32_t)*buf++, SLC_DATA(host->io_base)); uint32_t 407 drivers/mtd/nand/raw/lpc32xx_slc.c static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) uint32_t 412 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t ce = ecc[i / 3]; uint32_t 621 drivers/mtd/nand/raw/lpc32xx_slc.c lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps); uint32_t 695 drivers/mtd/nand/raw/lpc32xx_slc.c lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps); uint32_t 779 drivers/mtd/nand/raw/lpc32xx_slc.c host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE); uint32_t 948 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t tmp; uint32_t 987 drivers/mtd/nand/raw/lpc32xx_slc.c uint32_t tmp; uint32_t 346 drivers/mtd/nand/raw/mxc_nand.c uint32_t tmp; uint32_t 360 drivers/mtd/nand/raw/mxc_nand.c uint32_t tmp; uint32_t 388 drivers/mtd/nand/raw/mxc_nand.c uint32_t tmp; uint32_t 559 drivers/mtd/nand/raw/mxc_nand.c uint32_t tmp; uint32_t 645 drivers/mtd/nand/raw/mxc_nand.c uint32_t store; uint32_t 688 drivers/mtd/nand/raw/mxc_nand.c uint32_t config2; uint32_t 1269 drivers/mtd/nand/raw/mxc_nand.c uint32_t config2, config3; uint32_t 2745 drivers/mtd/nand/raw/nand_base.c static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs, uint32_t 2746 drivers/mtd/nand/raw/nand_base.c uint32_t readlen, uint8_t *bufpoi, int page) uint32_t 3159 drivers/mtd/nand/raw/nand_base.c uint32_t readlen = ops->len; uint32_t 3160 drivers/mtd/nand/raw/nand_base.c uint32_t oobreadlen = ops->ooblen; uint32_t 3161 drivers/mtd/nand/raw/nand_base.c uint32_t max_oobsize = mtd_oobavail(mtd, ops); uint32_t 3433 drivers/mtd/nand/raw/nand_base.c uint32_t fill = 0xFFFFFFFF; uint32_t 3777 drivers/mtd/nand/raw/nand_base.c static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset, uint32_t 3778 drivers/mtd/nand/raw/nand_base.c uint32_t data_len, const uint8_t *buf, uint32_t 3787 drivers/mtd/nand/raw/nand_base.c uint32_t start_step = offset / ecc_size; uint32_t 3788 drivers/mtd/nand/raw/nand_base.c uint32_t end_step = (offset + data_len - 1) / ecc_size; uint32_t 3918 drivers/mtd/nand/raw/nand_base.c static int nand_write_page(struct nand_chip *chip, uint32_t offset, uint32_t 3961 drivers/mtd/nand/raw/nand_base.c uint32_t writelen = ops->len; uint32_t 3963 drivers/mtd/nand/raw/nand_base.c uint32_t oobwritelen = ops->ooblen; uint32_t 3964 drivers/mtd/nand/raw/nand_base.c uint32_t oobmaxlen = mtd_oobavail(mtd, ops); uint32_t 127 drivers/mtd/nand/raw/nand_ecc.c const uint32_t *bp = (uint32_t *)buf; uint32_t 129 drivers/mtd/nand/raw/nand_ecc.c const uint32_t eccsize_mult = eccsize >> 8; uint32_t 130 drivers/mtd/nand/raw/nand_ecc.c uint32_t cur; /* current value in buffer */ uint32_t 132 drivers/mtd/nand/raw/nand_ecc.c uint32_t rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7; uint32_t 133 drivers/mtd/nand/raw/nand_ecc.c uint32_t rp8, rp9, rp10, rp11, rp12, rp13, rp14, rp15, rp16; uint32_t 134 drivers/mtd/nand/raw/nand_ecc.c uint32_t uninitialized_var(rp17); /* to make compiler happy */ uint32_t 135 drivers/mtd/nand/raw/nand_ecc.c uint32_t par; /* the cumulative parity for all data */ uint32_t 136 drivers/mtd/nand/raw/nand_ecc.c uint32_t tmppar; /* the cumulative parity for this iteration; uint32_t 397 drivers/mtd/nand/raw/nand_ecc.c const uint32_t eccsize_mult = eccsize >> 8; uint32_t 55 drivers/mtd/nand/raw/nand_toshiba.c toshiba_nand_read_subpage_benand(struct nand_chip *chip, uint32_t data_offs, uint32_t 56 drivers/mtd/nand/raw/nand_toshiba.c uint32_t readlen, uint8_t *bufpoi, int page) uint32_t 295 drivers/mtd/nand/raw/nandsim.c uint32_t options; /* chip's characteristic bits */ uint32_t 296 drivers/mtd/nand/raw/nandsim.c uint32_t state; /* current chip state */ uint32_t 297 drivers/mtd/nand/raw/nandsim.c uint32_t nxstate; /* next expected state */ uint32_t 299 drivers/mtd/nand/raw/nandsim.c uint32_t *op; /* current operation, NULL operations isn't known yet */ uint32_t 300 drivers/mtd/nand/raw/nandsim.c uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */ uint32_t 316 drivers/mtd/nand/raw/nandsim.c uint32_t secsz; /* flash sector (erase block) size, bytes */ uint32_t 363 drivers/mtd/nand/raw/nandsim.c uint32_t reqopts; /* options which are required to perform the operation */ uint32_t 364 drivers/mtd/nand/raw/nandsim.c uint32_t states[NS_OPER_STATES]; /* operation's states */ uint32_t 1004 drivers/mtd/nand/raw/nandsim.c static char *get_state_name(uint32_t state) uint32_t 1091 drivers/mtd/nand/raw/nandsim.c static uint32_t get_state_by_command(unsigned command) uint32_t 1206 drivers/mtd/nand/raw/nandsim.c static int find_operation(struct nandsim *ns, uint32_t flag) uint32_t 1555 drivers/mtd/nand/raw/nandsim.c static int do_state_action(struct nandsim *ns, uint32_t action) uint32_t 44 drivers/mtd/nand/raw/ndfc.c uint32_t ccr; uint32_t 78 drivers/mtd/nand/raw/ndfc.c uint32_t ccr; uint32_t 91 drivers/mtd/nand/raw/ndfc.c uint32_t ecc; uint32_t 114 drivers/mtd/nand/raw/ndfc.c uint32_t *p = (uint32_t *) buf; uint32_t 123 drivers/mtd/nand/raw/ndfc.c uint32_t *p = (uint32_t *) buf; uint32_t 345 drivers/mtd/nand/raw/omap2.c uint32_t r_count = 0; uint32_t 393 drivers/mtd/nand/raw/omap2.c uint32_t w_count = 0; uint32_t 49 drivers/mtd/nand/raw/r852.c static inline uint32_t r852_read_reg_dword(struct r852_device *dev, int address) uint32_t 51 drivers/mtd/nand/raw/r852.c uint32_t reg = le32_to_cpu(readl(dev->mmio + address)); uint32_t 57 drivers/mtd/nand/raw/r852.c int address, uint32_t value) uint32_t 233 drivers/mtd/nand/raw/r852.c uint32_t reg; uint32_t 267 drivers/mtd/nand/raw/r852.c uint32_t reg; uint32_t 435 drivers/mtd/nand/raw/r852.c uint32_t ecc1, ecc2; uint32_t 465 drivers/mtd/nand/raw/r852.c uint32_t ecc_reg; uint32_t 133 drivers/mtd/nand/raw/sh_flctl.c uint32_t timeout = LOOP_TIMEOUT_MAX; uint32_t 226 drivers/mtd/nand/raw/sh_flctl.c uint32_t addr = 0; uint32_t 240 drivers/mtd/nand/raw/sh_flctl.c uint32_t addr2; uint32_t 256 drivers/mtd/nand/raw/sh_flctl.c uint32_t timeout = LOOP_TIMEOUT_MAX; uint32_t 259 drivers/mtd/nand/raw/sh_flctl.c uint32_t val; uint32_t 271 drivers/mtd/nand/raw/sh_flctl.c uint32_t len, timeout = LOOP_TIMEOUT_MAX; uint32_t 286 drivers/mtd/nand/raw/sh_flctl.c uint32_t timeout = LOOP_TIMEOUT_MAX; uint32_t 290 drivers/mtd/nand/raw/sh_flctl.c uint32_t data, size; uint32_t 365 drivers/mtd/nand/raw/sh_flctl.c uint32_t timeout = LOOP_TIMEOUT_MAX; uint32_t 366 drivers/mtd/nand/raw/sh_flctl.c uint32_t len; uint32_t 386 drivers/mtd/nand/raw/sh_flctl.c uint32_t reg; uint32_t 537 drivers/mtd/nand/raw/sh_flctl.c static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val) uint32_t 540 drivers/mtd/nand/raw/sh_flctl.c uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT; uint32_t 541 drivers/mtd/nand/raw/sh_flctl.c uint32_t flcmdcr_val, addr_len_bytes = 0; uint32_t 743 drivers/mtd/nand/raw/sh_flctl.c uint32_t read_cmd = 0; uint32_t 11 drivers/mtd/nand/raw/sm_common.h uint32_t reserved; uint32_t 51 drivers/mtd/nand/raw/sm_common.h static const uint32_t erased_pattern[4] = { uint32_t 60 drivers/mtd/nand/raw/socrates_nand.c uint32_t val; uint32_t 89 drivers/mtd/nand/raw/socrates_nand.c uint32_t val; uint32_t 93 drivers/mtd/parsers/ar7part.c root_offset &= ~(uint32_t)0xff; uint32_t 46 drivers/mtd/parsers/bcm47xxpart.c uint32_t magic; uint32_t 47 drivers/mtd/parsers/bcm47xxpart.c uint32_t length; uint32_t 48 drivers/mtd/parsers/bcm47xxpart.c uint32_t crc32; uint32_t 51 drivers/mtd/parsers/bcm47xxpart.c uint32_t offset[3]; uint32_t 55 drivers/mtd/parsers/bcm47xxpart.c u64 offset, uint32_t mask_flags) uint32_t 92 drivers/mtd/parsers/bcm47xxpart.c uint32_t *buf; uint32_t 94 drivers/mtd/parsers/bcm47xxpart.c uint32_t offset; uint32_t 95 drivers/mtd/parsers/bcm47xxpart.c uint32_t blocksize = master->erasesize; uint32_t 185 drivers/mtd/parsers/bcm47xxpart.c uint32_t last_subpart; uint32_t 186 drivers/mtd/parsers/bcm47xxpart.c uint32_t trx_size; uint32_t 97 drivers/mtd/parsers/bcm63xxpart.c cfe_erasesize = max_t(uint32_t, master->erasesize, uint32_t 20 drivers/mtd/parsers/parser_trx.c uint32_t magic; uint32_t 21 drivers/mtd/parsers/parser_trx.c uint32_t length; uint32_t 22 drivers/mtd/parsers/parser_trx.c uint32_t crc32; uint32_t 25 drivers/mtd/parsers/parser_trx.c uint32_t offset[3]; uint32_t 31 drivers/mtd/parsers/parser_trx.c uint32_t buf; uint32_t 21 drivers/mtd/parsers/redboot.c uint32_t flash_base; // Address within FLASH of image uint32_t 22 drivers/mtd/parsers/redboot.c uint32_t mem_base; // Address in memory where it executes uint32_t 23 drivers/mtd/parsers/redboot.c uint32_t size; // Length of image uint32_t 24 drivers/mtd/parsers/redboot.c uint32_t entry_point; // Execution entry point uint32_t 25 drivers/mtd/parsers/redboot.c uint32_t data_length; // Length of actual data uint32_t 26 drivers/mtd/parsers/redboot.c unsigned char _pad[256-(16+7*sizeof(uint32_t))]; uint32_t 27 drivers/mtd/parsers/redboot.c uint32_t desc_cksum; // Checksum over image descriptor uint32_t 28 drivers/mtd/parsers/redboot.c uint32_t file_cksum; // Checksum over image data uint32_t 150 drivers/mtd/sm_ftl.c static const uint32_t erased_pattern[4] = { uint32_t 1243 drivers/mtd/spi-nor/spi-nor.c uint32_t rem; uint32_t 52 drivers/mtd/tests/pagetest.c uint32_t j; uint32_t 323 drivers/mtd/tests/pagetest.c uint32_t i; uint32_t 214 drivers/mtd/tests/subpagetest.c uint32_t j; uint32_t 271 drivers/mtd/tests/subpagetest.c uint32_t i; uint32_t 442 drivers/mtd/ubi/attach.c uint32_t data_crc, crc; uint32_t 602 drivers/mtd/ubi/eba.c uint32_t uninitialized_var(crc); uint32_t 712 drivers/mtd/ubi/eba.c uint32_t crc1 = crc32(UBI_CRC32_INIT, buf, len); uint32_t 814 drivers/mtd/ubi/eba.c uint32_t crc; uint32_t 1117 drivers/mtd/ubi/eba.c uint32_t crc; uint32_t 1195 drivers/mtd/ubi/eba.c uint32_t crc; uint32_t 1308 drivers/mtd/ubi/eba.c uint32_t crc; uint32_t 454 drivers/mtd/ubi/io.c uint32_t data = 0; uint32_t 691 drivers/mtd/ubi/io.c uint32_t crc, magic, hdr_crc; uint32_t 800 drivers/mtd/ubi/io.c uint32_t crc; uint32_t 968 drivers/mtd/ubi/io.c uint32_t crc, magic, hdr_crc; uint32_t 1053 drivers/mtd/ubi/io.c uint32_t crc; uint32_t 1117 drivers/mtd/ubi/io.c uint32_t magic; uint32_t 1154 drivers/mtd/ubi/io.c uint32_t crc, hdr_crc; uint32_t 1200 drivers/mtd/ubi/io.c uint32_t magic; uint32_t 1239 drivers/mtd/ubi/io.c uint32_t crc, hdr_crc; uint32_t 94 drivers/mtd/ubi/vtbl.c uint32_t crc; uint32_t 127 drivers/mtd/ubi/vtbl.c uint32_t crc; uint32_t 162 drivers/mtd/ubi/vtbl.c uint32_t crc; uint32_t 94 drivers/net/can/softing/softing_fw.c static int fw_parse(const uint8_t **pmem, uint16_t *ptype, uint32_t *paddr, uint32_t 140 drivers/net/can/softing/softing_fw.c uint32_t addr; uint32_t 224 drivers/net/can/softing/softing_fw.c uint32_t addr, start_addr = 0; uint32_t 158 drivers/net/can/softing/softing_main.c uint32_t tmp_u32; uint32_t 30 drivers/net/dsa/lan9303_mdio.c static int lan9303_mdio_write(void *ctx, uint32_t reg, uint32_t val) uint32_t 48 drivers/net/dsa/lan9303_mdio.c static int lan9303_mdio_read(void *ctx, uint32_t reg, uint32_t *val) uint32_t 208 drivers/net/dsa/qca8k.c qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) uint32_t 218 drivers/net/dsa/qca8k.c qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val) uint32_t 83 drivers/net/ethernet/8390/xsurf100.c *(uint32_t *)dst = z_readl(src); uint32_t 93 drivers/net/ethernet/8390/xsurf100.c z_writel(*(const uint32_t *)src, dst); uint32_t 189 drivers/net/ethernet/altera/altera_tse_ethtool.c static void tse_set_msglevel(struct net_device *dev, uint32_t data) uint32_t 3098 drivers/net/ethernet/cadence/macb_main.c uint32_t cnt = 0; uint32_t 34 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c static int lio_reset_queues(struct net_device *netdev, uint32_t num_qs); uint32_t 469 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c lio_send_queue_count_update(struct net_device *netdev, uint32_t num_queues) uint32_t 541 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c lio_irq_reallocate_irqs(struct octeon_device *oct, uint32_t num_ioqs) uint32_t 1082 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c static int lio_reset_queues(struct net_device *netdev, uint32_t num_qs) uint32_t 53 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 54 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t addr; uint32_t 55 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t val; uint32_t 59 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 60 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cntxt_type; uint32_t 61 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cntxt_id; uint32_t 62 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t data[4]; uint32_t 69 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 70 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t queue_num; uint32_t 71 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t idx; uint32_t 72 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t size; uint32_t 77 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 78 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t mem_id; uint32_t 79 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t addr; uint32_t 80 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t len; uint32_t 81 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t version; uint32_t 86 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 87 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t qset_idx; uint32_t 100 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 118 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 119 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t nmtus; uint32_t 124 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 125 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t tx_pg_sz; uint32_t 126 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t tx_num_pg; uint32_t 127 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t rx_pg_sz; uint32_t 128 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t rx_num_pg; uint32_t 129 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t pm_total; uint32_t 133 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 134 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t tcam_size; uint32_t 135 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t nservers; uint32_t 136 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t nroutes; uint32_t 137 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t nfilters; uint32_t 141 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 142 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t tcb_index; uint32_t 143 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t tcb_data[TCB_WORDS]; uint32_t 147 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 148 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t addr; uint32_t 149 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t buf[3]; uint32_t 153 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t cmd; uint32_t 154 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t sip; uint32_t 155 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t sip_mask; uint32_t 156 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t dip; uint32_t 157 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t dip_mask; uint32_t 162 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t vlan:12; uint32_t 163 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t vlan_mask:12; uint32_t 164 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t intf:4; uint32_t 165 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h uint32_t intf_mask:4; uint32_t 279 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t dack_re; /* DACK timer resolution */ uint32_t 1144 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ uint32_t 1145 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ uint32_t 1146 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t ivlan_vld:1; /* inner VLAN valid */ uint32_t 1147 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t ovlan_vld:1; /* outer VLAN valid */ uint32_t 1148 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t pfvf_vld:1; /* PF/VF valid */ uint32_t 1149 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t encap_vld:1; /* Encapsulation valid */ uint32_t 1150 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ uint32_t 1151 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ uint32_t 1152 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t iport:IPORT_BITWIDTH; /* ingress port */ uint32_t 1153 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ uint32_t 1154 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t proto:PROTO_BITWIDTH; /* protocol type */ uint32_t 1155 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ uint32_t 1156 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ uint32_t 1157 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ uint32_t 1158 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ uint32_t 1159 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ uint32_t 1160 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ uint32_t 1176 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t hitcnts:1; /* count filter hits in TCB */ uint32_t 1177 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t prio:1; /* filter has priority over active/server */ uint32_t 1182 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ uint32_t 1189 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t action:2; /* drop, pass, switch */ uint32_t 1191 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t rpttid:1; /* report TID in RSS hash field */ uint32_t 1193 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ uint32_t 1194 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t iq:10; /* ingress queue */ uint32_t 1196 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ uint32_t 1197 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ uint32_t 1204 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t eport:2; /* egress port to switch packet out */ uint32_t 1205 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t newdmac:1; /* rewrite destination MAC address */ uint32_t 1206 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t newsmac:1; /* rewrite source MAC address */ uint32_t 1207 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t newvlan:2; /* rewrite VLAN Tag */ uint32_t 1208 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h uint32_t nat_mode:3; /* specify NAT operation mode */ uint32_t 946 drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.c uint32_t tc_info; uint32_t 3503 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c sizeof(*card_fw) / sizeof(uint32_t), uint32_t 3504 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c (uint32_t *)card_fw, 1); uint32_t 3546 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c uint32_t d, c, k; uint32_t 426 drivers/net/ethernet/emulex/benet/be_ethtool.c static void be_get_stat_strings(struct net_device *netdev, uint32_t stringset, uint32_t 83 drivers/net/ethernet/freescale/fsl_pq_mdio.c uint32_t __iomem * (*get_tbipa)(void __iomem *p); uint32_t 201 drivers/net/ethernet/freescale/fsl_pq_mdio.c static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p) uint32_t 212 drivers/net/ethernet/freescale/fsl_pq_mdio.c static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p) uint32_t 220 drivers/net/ethernet/freescale/fsl_pq_mdio.c static uint32_t __iomem *get_etsec_tbipa(void __iomem *p) uint32_t 231 drivers/net/ethernet/freescale/fsl_pq_mdio.c static uint32_t __iomem *get_ucc_tbipa(void __iomem *p) uint32_t 259 drivers/net/ethernet/freescale/fsl_pq_mdio.c const uint32_t *iprop; uint32_t 260 drivers/net/ethernet/freescale/fsl_pq_mdio.c uint32_t id; uint32_t 376 drivers/net/ethernet/freescale/fsl_pq_mdio.c uint32_t __iomem * (*get_tbipa)(void __iomem *), uint32_t 380 drivers/net/ethernet/freescale/fsl_pq_mdio.c uint32_t __iomem *tbipa; uint32_t 1127 drivers/net/ethernet/freescale/gianfar.h uint32_t msg_enable; uint32_t 561 drivers/net/ethernet/freescale/gianfar_ethtool.c static uint32_t gfar_get_msglevel(struct net_device *dev) uint32_t 568 drivers/net/ethernet/freescale/gianfar_ethtool.c static void gfar_set_msglevel(struct net_device *dev, uint32_t data) uint32_t 96 drivers/net/ethernet/freescale/ucc_geth.c .extendedFilteringChainPointer = ((uint32_t) NULL), uint32_t 120 drivers/net/ethernet/freescale/ucc_geth.c .ecamptr = ((uint32_t) NULL), uint32_t 1217 drivers/net/ethernet/freescale/ucc_geth.h uint32_t msg_enable; uint32_t 175 drivers/net/ethernet/freescale/ucc_geth_ethtool.c static uint32_t uint32_t 183 drivers/net/ethernet/freescale/ucc_geth_ethtool.c uec_set_msglevel(struct net_device *netdev, uint32_t data) uint32_t 188 drivers/net/ethernet/freescale/xgmac_mdio.c uint32_t mdio_stat; uint32_t 189 drivers/net/ethernet/freescale/xgmac_mdio.c uint32_t mdio_ctl; uint32_t 1692 drivers/net/ethernet/marvell/mv643xx_eth.c uint32_t stringset, uint8_t *data) uint32_t 1727 drivers/net/ethernet/marvell/mv643xx_eth.c *(uint64_t *)p : *(uint32_t *)p; uint32_t 817 drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h uint32_t reserved_20_31 : 12; uint32_t 818 drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h uint32_t rq : 20; uint32_t 820 drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h uint32_t rq : 20; uint32_t 821 drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h uint32_t reserved_20_31 : 12; uint32_t 445 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c uint32_t stringset, uint8_t *data) uint32_t 1137 drivers/net/ethernet/mellanox/mlx5/core/en.h uint32_t stringset, uint8_t *data); uint32_t 251 drivers/net/ethernet/mellanox/mlx5/core/fw.c int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id) uint32_t 121 drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id); uint32_t 425 drivers/net/ethernet/qlogic/netxen/netxen_nic.h uint32_t findex; uint32_t 426 drivers/net/ethernet/qlogic/netxen/netxen_nic.h uint32_t num_entries; uint32_t 427 drivers/net/ethernet/qlogic/netxen/netxen_nic.h uint32_t entry_size; uint32_t 428 drivers/net/ethernet/qlogic/netxen/netxen_nic.h uint32_t reserved[5]; uint32_t 432 drivers/net/ethernet/qlogic/netxen/netxen_nic.h uint32_t findex; uint32_t 433 drivers/net/ethernet/qlogic/netxen/netxen_nic.h uint32_t size; uint32_t 434 drivers/net/ethernet/qlogic/netxen/netxen_nic.h uint32_t reserved[5]; uint32_t 972 drivers/net/ethernet/qlogic/netxen/netxen_nic.h uint32_t low_threshold; uint32_t 973 drivers/net/ethernet/qlogic/netxen/netxen_nic.h uint32_t high_threshold; uint32_t 1169 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define LSD(x) ((uint32_t)((uint64_t)(x))) uint32_t 1170 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) uint32_t 145 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c int count = adapter->mdump.md_template_size/sizeof(uint32_t) ; uint32_t 749 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), uint32_t 879 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c sizeof(uint32_t), uint32_t 1006 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h uint32_t int_vec_bit; uint32_t 1007 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h uint32_t tgt_status_reg; uint32_t 1008 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h uint32_t tgt_mask_reg; uint32_t 1009 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h uint32_t pci_int_reg; uint32_t 1025 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c uint32_t crbaddr, mac_hi, mac_lo; uint32_t 569 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c uint32_t i; uint32_t 709 drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c uint32_t flagbit; uint32_t 97 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c static uint32_t crb_cmd_producer[4] = { uint32_t 109 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c static uint32_t crb_cmd_consumer[4] = { uint32_t 121 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c static uint32_t msi_tgt_status[8] = { uint32_t 2147 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c uint32_t temp, temp_state, temp_val; uint32_t 733 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define LSW(x) ((uint16_t)((uint32_t)(x))) uint32_t 734 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) uint32_t 736 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define LSD(x) ((uint32_t)((uint64_t)(x))) uint32_t 737 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) uint32_t 851 drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c uint32_t producer, handle; uint32_t 1083 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c static uint32_t qlcnic_temp_checksum(uint32_t *temp_buffer, u32 temp_size) uint32_t 1086 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c int count = temp_size / sizeof(uint32_t); uint32_t 1252 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c csum = qlcnic_temp_checksum((uint32_t *)tmp_buf, temp_size); uint32_t 24 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c uint32_t phy_intf_sel; uint32_t 27 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c static uint32_t gmac_read_reg(struct anarion_gmac *gmac, uint8_t reg) uint32_t 32 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val) uint32_t 39 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c uint32_t sw_config; uint32_t 88 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c uint32_t id; uint32_t 147 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c uint32_t clk_bits, val; uint32_t 1771 drivers/net/ethernet/ti/netcp_ethss.c uint32_t stringset, uint8_t *data) uint32_t 363 drivers/net/ieee802154/mac802154_hwsim.c static struct hwsim_phy *hwsim_get_radio_by_id(uint32_t idx) uint32_t 77 drivers/net/phy/mdio-mux-mmioreg.c case sizeof(uint32_t): { uint32_t 78 drivers/net/phy/mdio-mux-mmioreg.c uint32_t x, y; uint32_t 122 drivers/net/phy/mdio-mux-mmioreg.c s->iosize != sizeof(uint32_t)) { uint32_t 128 drivers/net/phy/mdio-mux-mmioreg.c if (!iprop || len != sizeof(uint32_t)) { uint32_t 144 drivers/net/phy/mdio-mux-mmioreg.c if (!iprop || len != sizeof(uint32_t)) { uint32_t 194 drivers/net/team/team_mode_loadbalance.c uint32_t lhash; uint32_t 1585 drivers/net/usb/cdc_ncm.c uint32_t rx_speed = le32_to_cpu(data->DLBitRRate); uint32_t 1586 drivers/net/usb/cdc_ncm.c uint32_t tx_speed = le32_to_cpu(data->ULBitRate); uint32_t 236 drivers/net/usb/lg-vl600.c static uint32_t serial = 1; uint32_t 362 drivers/net/wireless/ath/ath9k/htc_hst.c uint32_t *pattern = (uint32_t *)skb->data; uint32_t 277 drivers/net/wireless/ath/wil6210/pcie_bus.c static int wil_platform_rop_ramdump(void *wil_handle, void *buf, uint32_t size) uint32_t 48 drivers/net/wireless/ath/wil6210/wil_platform.h int (*bus_request)(void *handle, uint32_t kbps /* KBytes/Sec */); uint32_t 68 drivers/net/wireless/ath/wil6210/wil_platform.h int (*ramdump)(void *wil_handle, void *buf, uint32_t size); uint32_t 180 drivers/net/wireless/marvell/libertas/cmd.c int lbs_host_sleep_cfg(struct lbs_private *priv, uint32_t criteria, uint32_t 364 drivers/net/wireless/marvell/libertas/cmd.c uint32_t criteria = EHS_REMOVE_WAKEUP; uint32_t 90 drivers/net/wireless/marvell/libertas/cmd.h int lbs_host_sleep_cfg(struct lbs_private *priv, uint32_t criteria, uint32_t 154 drivers/net/wireless/marvell/libertas/dev.h uint32_t wol_criteria; uint32_t 214 drivers/net/wireless/marvell/libertas/if_usb.c cardp->model = (uint32_t) id->driver_info; uint32_t 660 drivers/net/wireless/marvell/libertas/if_usb.c uint32_t recvtype = 0; uint32_t 662 drivers/net/wireless/marvell/libertas/if_usb.c uint32_t event; uint32_t 776 drivers/net/wireless/marvell/libertas/if_usb.c static int check_fwfile_format(const uint8_t *data, uint32_t totlen) uint32_t 778 drivers/net/wireless/marvell/libertas/if_usb.c uint32_t bincmd, exit; uint32_t 779 drivers/net/wireless/marvell/libertas/if_usb.c uint32_t blksize, offset, len; uint32_t 47 drivers/net/wireless/marvell/libertas/if_usb.h uint32_t model; /* MODEL_* */ uint32_t 70 drivers/net/wireless/marvell/libertas/if_usb.h uint32_t fwseqnum; uint32_t 71 drivers/net/wireless/marvell/libertas/if_usb.h uint32_t totalbytes; uint32_t 72 drivers/net/wireless/marvell/libertas/if_usb.h uint32_t fwlastblksent; uint32_t 187 drivers/net/wireless/marvell/libertas/mesh.c uint32_t datum; uint32_t 385 drivers/net/wireless/marvell/libertas/mesh.c uint32_t datum; uint32_t 394 drivers/net/wireless/marvell/libertas/mesh.c cmd.length = cpu_to_le16(sizeof(uint32_t)); uint32_t 435 drivers/net/wireless/marvell/libertas/mesh.c uint32_t datum; uint32_t 494 drivers/net/wireless/marvell/libertas/mesh.c uint32_t datum; uint32_t 621 drivers/net/wireless/marvell/libertas/mesh.c uint32_t datum; uint32_t 682 drivers/net/wireless/marvell/libertas/mesh.c uint32_t datum; uint32_t 743 drivers/net/wireless/marvell/libertas/mesh.c uint32_t datum; uint32_t 1162 drivers/net/wireless/marvell/libertas/mesh.c uint32_t stringset, uint8_t *s) uint32_t 58 drivers/net/wireless/marvell/libertas/mesh.h uint32_t stringset, uint8_t *s); uint32_t 631 drivers/net/wireless/marvell/libertas_tf/if_usb.c uint32_t recvtype = 0; uint32_t 61 drivers/net/wireless/marvell/libertas_tf/if_usb.h uint32_t fwseqnum; uint32_t 62 drivers/net/wireless/marvell/libertas_tf/if_usb.h uint32_t totalbytes; uint32_t 63 drivers/net/wireless/marvell/libertas_tf/if_usb.h uint32_t fwlastblksent; uint32_t 1179 drivers/net/wireless/marvell/mwifiex/cmdevt.c uint32_t conditions = le32_to_cpu(phs_cfg->params.hs_config.conditions); uint32_t 865 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c static int qtnf_ep_fw_send(struct pci_dev *pdev, uint32_t size, uint32_t 69 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BD_EMPTY ((uint32_t)0x00000001) uint32_t 70 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BD_WRAP ((uint32_t)0x00000002) uint32_t 71 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BD_MASK_LEN ((uint32_t)0xFFFF0000) uint32_t 72 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BD_MASK_OFFSET ((uint32_t)0x0000FF00) uint32_t 280 drivers/net/xen-netback/rx.c *(uint32_t *)extra->u.hash.value = skb_get_hash_raw(skb); uint32_t 40 drivers/nfc/nfcmrvl/fw_dnld.h uint32_t baudrate; uint32_t 44 drivers/nfc/nfcmrvl/fw_dnld.h uint32_t clk; uint32_t 48 drivers/nfc/nfcmrvl/fw_dnld.h uint32_t clk; uint32_t 52 drivers/nfc/nfcmrvl/fw_dnld.h uint32_t offset; uint32_t 63 drivers/nfc/nfcmrvl/fw_dnld.h uint32_t magic; uint32_t 64 drivers/nfc/nfcmrvl/fw_dnld.h uint32_t ref_clock; uint32_t 65 drivers/nfc/nfcmrvl/fw_dnld.h uint32_t phy; uint32_t 1313 drivers/of/base.c uint32_t count = 0; uint32_t 1392 drivers/of/base.c uint32_t *args, uint32_t 68 drivers/of/fdt.c cell_size = sizeof(uint32_t)*(nr_address_cells + nr_size_cells); uint32_t 781 drivers/of/fdt.c uint32_t __init of_get_flat_dt_phandle(unsigned long node) uint32_t 115 drivers/parisc/ccio-dma.c uint32_t io_command; /* Offset 12 */ uint32_t 116 drivers/parisc/ccio-dma.c uint32_t io_status; /* Offset 13 */ uint32_t 117 drivers/parisc/ccio-dma.c uint32_t io_control; /* Offset 14 */ uint32_t 121 drivers/parisc/ccio-dma.c uint32_t io_err_resp; /* Offset 0 */ uint32_t 122 drivers/parisc/ccio-dma.c uint32_t io_err_info; /* Offset 1 */ uint32_t 123 drivers/parisc/ccio-dma.c uint32_t io_err_req; /* Offset 2 */ uint32_t 124 drivers/parisc/ccio-dma.c uint32_t io_err_resp_hi; /* Offset 3 */ uint32_t 125 drivers/parisc/ccio-dma.c uint32_t io_tlb_entry_m; /* Offset 4 */ uint32_t 126 drivers/parisc/ccio-dma.c uint32_t io_tlb_entry_l; /* Offset 5 */ uint32_t 127 drivers/parisc/ccio-dma.c uint32_t unused3[1]; uint32_t 128 drivers/parisc/ccio-dma.c uint32_t io_pdir_base; /* Offset 7 */ uint32_t 129 drivers/parisc/ccio-dma.c uint32_t io_io_low_hv; /* Offset 8 */ uint32_t 130 drivers/parisc/ccio-dma.c uint32_t io_io_high_hv; /* Offset 9 */ uint32_t 131 drivers/parisc/ccio-dma.c uint32_t unused4[1]; uint32_t 132 drivers/parisc/ccio-dma.c uint32_t io_chain_id_mask; /* Offset 11 */ uint32_t 133 drivers/parisc/ccio-dma.c uint32_t unused5[2]; uint32_t 134 drivers/parisc/ccio-dma.c uint32_t io_io_low; /* Offset 14 */ uint32_t 135 drivers/parisc/ccio-dma.c uint32_t io_io_high; /* Offset 15 */ uint32_t 118 drivers/pcmcia/pxa2xx_base.c uint32_t val; uint32_t 134 drivers/pcmcia/pxa2xx_base.c uint32_t val; uint32_t 150 drivers/pcmcia/pxa2xx_base.c uint32_t val; uint32_t 222 drivers/pcmcia/pxa2xx_base.c uint32_t mecr = MECR_CIT; uint32_t 82 drivers/pcmcia/vrc4173_cardu.c static inline uint32_t cardbus_socket_readl(vrc4173_socket_t *socket, u16 offset) uint32_t 87 drivers/pcmcia/vrc4173_cardu.c static inline void cardbus_socket_writel(vrc4173_socket_t *socket, u16 offset, uint32_t val) uint32_t 168 drivers/pcmcia/vrc4173_cardu.c uint32_t state; uint32_t 308 drivers/pcmcia/vrc4173_cardu.c uint32_t start, stop, offset, page; uint32_t 110 drivers/phy/broadcom/phy-bcm-sr-usb.c uint32_t type; uint32_t 111 drivers/phy/broadcom/phy-bcm-sr-usb.c uint32_t version; uint32_t 126 drivers/phy/broadcom/phy-bcm-sr-usb.c static inline void bcm_usb_reg32_clrbits(void __iomem *addr, uint32_t clear) uint32_t 131 drivers/phy/broadcom/phy-bcm-sr-usb.c static inline void bcm_usb_reg32_setbits(void __iomem *addr, uint32_t set) uint32_t 287 drivers/phy/broadcom/phy-bcm-sr-usb.c void __iomem *regs, uint32_t version) uint32_t 122 drivers/pinctrl/pinctrl-at91.c uint32_t bank; uint32_t 123 drivers/pinctrl/pinctrl-at91.c uint32_t pin; uint32_t 198 drivers/pinctrl/pinctrl-at91.c uint32_t *mux_mask; uint32_t 826 drivers/pinctrl/pinctrl-at91.c uint32_t npins = info->groups[group].npins; uint32_t 1274 drivers/pinctrl/pinctrl-at91.c uint32_t *tmp; uint32_t 1459 drivers/pinctrl/pinctrl-at91.c uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); uint32_t 1460 drivers/pinctrl/pinctrl-at91.c uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); uint32_t 1822 drivers/pinctrl/pinctrl-at91.c uint32_t ngpio; uint32_t 89 drivers/pinctrl/pxa/pinctrl-pxa2xx.c uint32_t val; uint32_t 107 drivers/platform/chrome/cros_ec_lightbar.c uint32_t *ver_ptr, uint32_t *flg_ptr) uint32_t 158 drivers/platform/chrome/cros_ec_lightbar.c uint32_t version = 0, flags = 0; uint32_t 177 drivers/platform/chrome/cros_ec_proto.c uint32_t *mask) uint32_t 522 drivers/platform/chrome/cros_ec_proto.c int version, uint32_t size) uint32_t 25 drivers/platform/chrome/cros_ec_trace.h __field(uint32_t, version) uint32_t 26 drivers/platform/chrome/cros_ec_trace.h __field(uint32_t, command) uint32_t 165 drivers/power/supply/goldfish_battery.c uint32_t status; uint32_t 58 drivers/pwm/pwm-jz4740.c uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm); uint32_t 69 drivers/pwm/pwm-jz4740.c uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); uint32_t 212 drivers/remoteproc/qcom_sysmon.c .elem_size = sizeof(uint32_t), uint32_t 232 drivers/remoteproc/qcom_sysmon.c .elem_size = sizeof(uint32_t), uint32_t 691 drivers/rpmsg/qcom_glink_native.c u32 cid, uint32_t iid, uint32_t 102 drivers/rtc/rtc-ds1511.c rtc_write(uint8_t val, uint32_t reg) uint32_t 69 drivers/rtc/rtc-jz4740.c static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg) uint32_t 76 drivers/rtc/rtc-jz4740.c uint32_t ctrl; uint32_t 88 drivers/rtc/rtc-jz4740.c uint32_t ctrl; uint32_t 105 drivers/rtc/rtc-jz4740.c uint32_t val) uint32_t 119 drivers/rtc/rtc-jz4740.c static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask, uint32_t 124 drivers/rtc/rtc-jz4740.c uint32_t ctrl; uint32_t 148 drivers/rtc/rtc-jz4740.c uint32_t secs, secs2; uint32_t 189 drivers/rtc/rtc-jz4740.c uint32_t secs; uint32_t 190 drivers/rtc/rtc-jz4740.c uint32_t ctrl; uint32_t 208 drivers/rtc/rtc-jz4740.c uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time)); uint32_t 235 drivers/rtc/rtc-jz4740.c uint32_t ctrl; uint32_t 196 drivers/rtc/rtc-rk808.c uint32_t int_reg; uint32_t 190 drivers/rtc/rtc-st-lpc.c uint32_t mode; uint32_t 397 drivers/s390/cio/vfio_ccw_ops.c uint32_t flags, uint32_t 1025 drivers/scsi/aacraid/commsup.c static inline int aac_aif_data(struct aac_aifcmd *aifcmd, uint32_t index) uint32_t 105 drivers/scsi/aic7xxx/aic7770.c aic7770_find_device(uint32_t id) uint32_t 396 drivers/scsi/aic7xxx/aic79xx.h uint32_t residual_datacnt; /* Residual in the current S/G seg */ uint32_t 397 drivers/scsi/aic7xxx/aic79xx.h uint32_t residual_sgptr; /* The next S/G for this transfer */ uint32_t 402 drivers/scsi/aic7xxx/aic79xx.h uint32_t residual_datacnt; /* Residual in the current S/G seg */ uint32_t 403 drivers/scsi/aic7xxx/aic79xx.h uint32_t residual_sgptr; /* The next S/G for this transfer */ uint32_t 417 drivers/scsi/aic7xxx/aic79xx.h typedef uint32_t sense_addr_t; uint32_t 436 drivers/scsi/aic7xxx/aic79xx.h uint32_t spare[2]; uint32_t 501 drivers/scsi/aic7xxx/aic79xx.h /*32*/ uint32_t datacnt; /* Byte 3 is spare. */ uint32_t 502 drivers/scsi/aic7xxx/aic79xx.h /*36*/ uint32_t sgptr; uint32_t 503 drivers/scsi/aic7xxx/aic79xx.h /*40*/ uint32_t hscb_busaddr; uint32_t 504 drivers/scsi/aic7xxx/aic79xx.h /*44*/ uint32_t next_hscb_busaddr; uint32_t 527 drivers/scsi/aic7xxx/aic79xx.h uint32_t addr; uint32_t 528 drivers/scsi/aic7xxx/aic79xx.h uint32_t len; uint32_t 536 drivers/scsi/aic7xxx/aic79xx.h uint32_t len; uint32_t 537 drivers/scsi/aic7xxx/aic79xx.h uint32_t pad; uint32_t 1004 drivers/scsi/aic7xxx/aic79xx.h uint32_t devconfig; uint32_t 1125 drivers/scsi/aic7xxx/aic79xx.h uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; uint32_t 1126 drivers/scsi/aic7xxx/aic79xx.h uint32_t cmdcmplt_total; uint32_t 1314 drivers/scsi/aic7xxx/aic79xx.h uint32_t full_id; uint32_t 1315 drivers/scsi/aic7xxx/aic79xx.h uint32_t id_mask; uint32_t 1378 drivers/scsi/aic7xxx/aic79xx.h role_t role, uint32_t status, uint32_t 1439 drivers/scsi/aic7xxx/aic79xx.h extern uint32_t ahd_debug; uint32_t 190 drivers/scsi/aic7xxx/aic79xx_core.c role_t role, uint32_t status, uint32_t 234 drivers/scsi/aic7xxx/aic79xx_core.c role_t role, uint32_t status); uint32_t 464 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t *dataptr_words; uint32_t 467 drivers/scsi/aic7xxx/aic79xx_core.c dataptr_words = (uint32_t*)&scb->hscb->dataptr; uint32_t 497 drivers/scsi/aic7xxx/aic79xx_core.c ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr) uint32_t 506 drivers/scsi/aic7xxx/aic79xx_core.c static uint32_t uint32_t 549 drivers/scsi/aic7xxx/aic79xx_core.c static uint32_t uint32_t 601 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t uint32_t 611 drivers/scsi/aic7xxx/aic79xx_core.c ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value) uint32_t 773 drivers/scsi/aic7xxx/aic79xx_core.c static uint32_t uint32_t 806 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t saved_hscb_busaddr; uint32_t 1094 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t sgptr; uint32_t 1104 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t sgptr; uint32_t 1430 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t datacnt; uint32_t 1431 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t sgptr; uint32_t 1476 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t sgptr; uint32_t 1477 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t resid; uint32_t 1545 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t sgptr; uint32_t 1547 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t data_len; uint32_t 1738 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t len; uint32_t 1744 drivers/scsi/aic7xxx/aic79xx_core.c (uint32_t)((addr >> 32) & 0xFFFFFFFF), uint32_t 1745 drivers/scsi/aic7xxx/aic79xx_core.c (uint32_t)(addr & 0xFFFFFFFF), uint32_t 1755 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t len; uint32_t 3587 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t ahd_debug = AHD_DEBUG_OPTS; uint32_t 3608 drivers/scsi/aic7xxx/aic79xx_core.c (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), uint32_t 3609 drivers/scsi/aic7xxx/aic79xx_core.c (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), uint32_t 5710 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t sgptr; uint32_t 5723 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t data_cnt; uint32_t 5725 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t sglen; uint32_t 5841 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t sgptr; uint32_t 5842 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t resid; uint32_t 6245 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t cmd; uint32_t 6259 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t mod_cmd; uint32_t 7241 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t busaddr; uint32_t 8071 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t busaddr; uint32_t 8130 drivers/scsi/aic7xxx/aic79xx_core.c ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status) uint32_t 8146 drivers/scsi/aic7xxx/aic79xx_core.c int lun, u_int tag, role_t role, uint32_t status, uint32_t 8161 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t busaddr; uint32_t 8376 drivers/scsi/aic7xxx/aic79xx_core.c int lun, u_int tag, role_t role, uint32_t status, uint32_t 8533 drivers/scsi/aic7xxx/aic79xx_core.c int lun, u_int tag, role_t role, uint32_t status) uint32_t 9092 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t sgptr; uint32_t 9093 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t resid_sgptr; uint32_t 9094 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t resid; uint32_t 9535 drivers/scsi/aic7xxx/aic79xx_core.c instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); uint32_t 9573 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t mask; uint32_t 10090 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t checksum; uint32_t 10118 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t checksum; uint32_t 126 drivers/scsi/aic7xxx/aic79xx_inline.h uint32_t uint32_t 129 drivers/scsi/aic7xxx/aic79xx_inline.h uint32_t value); uint32_t 144 drivers/scsi/aic7xxx/aic79xx_inline.h static inline uint32_t ahd_get_sense_bufaddr(struct ahd_softc *ahd, uint32_t 163 drivers/scsi/aic7xxx/aic79xx_inline.h static inline uint32_t uint32_t 244 drivers/scsi/aic7xxx/aic79xx_osm.c static uint32_t aic79xx_no_reset; uint32_t 251 drivers/scsi/aic7xxx/aic79xx_osm.c static uint32_t aic79xx_extended; uint32_t 267 drivers/scsi/aic7xxx/aic79xx_osm.c static uint32_t aic79xx_pci_parity = ~0; uint32_t 275 drivers/scsi/aic7xxx/aic79xx_osm.c uint32_t aic79xx_allow_memio = ~0; uint32_t 287 drivers/scsi/aic7xxx/aic79xx_osm.c static uint32_t aic79xx_seltime; uint32_t 297 drivers/scsi/aic7xxx/aic79xx_osm.c static uint32_t aic79xx_periodic_otag; uint32_t 312 drivers/scsi/aic7xxx/aic79xx_osm.c uint32_t aic79xx_slowcrc; uint32_t 481 drivers/scsi/aic7xxx/aic79xx_osm.c uint32_t uint32_t 500 drivers/scsi/aic7xxx/aic79xx_osm.c uint32_t retval; uint32_t 512 drivers/scsi/aic7xxx/aic79xx_osm.c ahd_pci_write_config(ahd_dev_softc_t pci, int reg, uint32_t value, int width) uint32_t 1150 drivers/scsi/aic7xxx/aic79xx_osm.c uint32_t *flag; uint32_t 1220 drivers/scsi/aic7xxx/aic79xx_osm.c uint32_t aic79xx_verbose; uint32_t 1487 drivers/scsi/aic7xxx/aic79xx_osm.c int lun, u_int tag, role_t role, uint32_t status) uint32_t 1803 drivers/scsi/aic7xxx/aic79xx_osm.c uint32_t amount_xferred; uint32_t 113 drivers/scsi/aic7xxx/aic79xx_osm.h extern uint32_t aic79xx_allow_memio; uint32_t 118 drivers/scsi/aic7xxx/aic79xx_osm.h typedef uint32_t bus_size_t; uint32_t 329 drivers/scsi/aic7xxx/aic79xx_osm.h uint32_t xfer_len; uint32_t 330 drivers/scsi/aic7xxx/aic79xx_osm.h uint32_t sense_resid; /* Auto-Sense residual */ uint32_t 348 drivers/scsi/aic7xxx/aic79xx_osm.h #define AHD_LINUX_NOIRQ ((uint32_t)~0) uint32_t 349 drivers/scsi/aic7xxx/aic79xx_osm.h uint32_t irq; /* IRQ for this adapter */ uint32_t 350 drivers/scsi/aic7xxx/aic79xx_osm.h uint32_t bios_address; uint32_t 460 drivers/scsi/aic7xxx/aic79xx_osm.h uint32_t ahd_pci_read_config(ahd_dev_softc_t pci, uint32_t 463 drivers/scsi/aic7xxx/aic79xx_osm.h int reg, uint32_t value, uint32_t 500 drivers/scsi/aic7xxx/aic79xx_osm.h static inline void ahd_cmd_set_transaction_status(struct scsi_cmnd *, uint32_t); uint32_t 501 drivers/scsi/aic7xxx/aic79xx_osm.h static inline void ahd_set_transaction_status(struct scb *, uint32_t); uint32_t 502 drivers/scsi/aic7xxx/aic79xx_osm.h static inline void ahd_cmd_set_scsi_status(struct scsi_cmnd *, uint32_t); uint32_t 503 drivers/scsi/aic7xxx/aic79xx_osm.h static inline void ahd_set_scsi_status(struct scb *, uint32_t); uint32_t 504 drivers/scsi/aic7xxx/aic79xx_osm.h static inline uint32_t ahd_cmd_get_transaction_status(struct scsi_cmnd *cmd); uint32_t 505 drivers/scsi/aic7xxx/aic79xx_osm.h static inline uint32_t ahd_get_transaction_status(struct scb *); uint32_t 506 drivers/scsi/aic7xxx/aic79xx_osm.h static inline uint32_t ahd_cmd_get_scsi_status(struct scsi_cmnd *cmd); uint32_t 507 drivers/scsi/aic7xxx/aic79xx_osm.h static inline uint32_t ahd_get_scsi_status(struct scb *); uint32_t 516 drivers/scsi/aic7xxx/aic79xx_osm.h static inline uint32_t ahd_get_sense_bufsize(struct ahd_softc *, uint32_t 525 drivers/scsi/aic7xxx/aic79xx_osm.h void ahd_cmd_set_transaction_status(struct scsi_cmnd *cmd, uint32_t status) uint32_t 532 drivers/scsi/aic7xxx/aic79xx_osm.h void ahd_set_transaction_status(struct scb *scb, uint32_t status) uint32_t 538 drivers/scsi/aic7xxx/aic79xx_osm.h void ahd_cmd_set_scsi_status(struct scsi_cmnd *cmd, uint32_t status) uint32_t 545 drivers/scsi/aic7xxx/aic79xx_osm.h void ahd_set_scsi_status(struct scb *scb, uint32_t status) uint32_t 551 drivers/scsi/aic7xxx/aic79xx_osm.h uint32_t ahd_cmd_get_transaction_status(struct scsi_cmnd *cmd) uint32_t 557 drivers/scsi/aic7xxx/aic79xx_osm.h uint32_t ahd_get_transaction_status(struct scb *scb) uint32_t 563 drivers/scsi/aic7xxx/aic79xx_osm.h uint32_t ahd_cmd_get_scsi_status(struct scsi_cmnd *cmd) uint32_t 569 drivers/scsi/aic7xxx/aic79xx_osm.h uint32_t ahd_get_scsi_status(struct scb *scb) uint32_t 630 drivers/scsi/aic7xxx/aic79xx_osm.h static inline uint32_t uint32_t 667 drivers/scsi/aic7xxx/aic79xx_osm.h role_t role, uint32_t status); uint32_t 681 drivers/scsi/aic7xxx/aic79xx_osm.h extern uint32_t aic79xx_verbose; uint32_t 311 drivers/scsi/aic7xxx/aic79xx_osm_pci.c uint32_t command; uint32_t 292 drivers/scsi/aic7xxx/aic79xx_pci.c uint32_t devconfig; uint32_t 416 drivers/scsi/aic7xxx/aic79xx_pci.c uint32_t cmd; uint32_t 644 drivers/scsi/aic7xxx/aic79xx_pci.c uint32_t devconfig; uint32_t 968 drivers/scsi/aic7xxx/aic79xx_pci.c extern uint32_t aic79xx_slowcrc; uint32_t 387 drivers/scsi/aic7xxx/aic7xxx.h uint32_t residual_datacnt; /* Residual in the current S/G seg */ uint32_t 388 drivers/scsi/aic7xxx/aic7xxx.h uint32_t residual_sg_ptr; /* The next S/G for this transfer */ uint32_t 396 drivers/scsi/aic7xxx/aic7xxx.h uint32_t residual_datacnt; /* Residual in the current S/G seg */ uint32_t 397 drivers/scsi/aic7xxx/aic7xxx.h uint32_t residual_sg_ptr; /* The next S/G for this transfer */ uint32_t 413 drivers/scsi/aic7xxx/aic7xxx.h uint32_t cdb_ptr; uint32_t 454 drivers/scsi/aic7xxx/aic7xxx.h /*12*/ uint32_t dataptr; uint32_t 455 drivers/scsi/aic7xxx/aic7xxx.h /*16*/ uint32_t datacnt; /* uint32_t 460 drivers/scsi/aic7xxx/aic7xxx.h /*20*/ uint32_t sgptr; uint32_t 505 drivers/scsi/aic7xxx/aic7xxx.h uint32_t addr; uint32_t 506 drivers/scsi/aic7xxx/aic7xxx.h uint32_t len; uint32_t 880 drivers/scsi/aic7xxx/aic7xxx.h uint32_t devconfig; uint32_t 1118 drivers/scsi/aic7xxx/aic7xxx.h uint32_t full_id; uint32_t 1119 drivers/scsi/aic7xxx/aic7xxx.h uint32_t id_mask; uint32_t 1142 drivers/scsi/aic7xxx/aic7xxx.h struct aic7770_identity *aic7770_find_device(uint32_t); uint32_t 1180 drivers/scsi/aic7xxx/aic7xxx.h role_t role, uint32_t status, uint32_t 1185 drivers/scsi/aic7xxx/aic7xxx.h int lun, uint32_t status, uint32_t 1250 drivers/scsi/aic7xxx/aic7xxx.h extern uint32_t ahc_debug; uint32_t 303 drivers/scsi/aic7xxx/aic7xxx_93cx6.c uint32_t checksum; uint32_t 263 drivers/scsi/aic7xxx/aic7xxx_core.c role_t role, uint32_t status); uint32_t 365 drivers/scsi/aic7xxx/aic7xxx_core.c ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr) uint32_t 376 drivers/scsi/aic7xxx/aic7xxx_core.c static uint32_t uint32_t 387 drivers/scsi/aic7xxx/aic7xxx_core.c static uint32_t uint32_t 416 drivers/scsi/aic7xxx/aic7xxx_core.c static uint32_t uint32_t 431 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t sgptr; uint32_t 472 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t uint32_t 482 drivers/scsi/aic7xxx/aic7xxx_core.c ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value) uint32_t 655 drivers/scsi/aic7xxx/aic7xxx_core.c static uint32_t uint32_t 896 drivers/scsi/aic7xxx/aic7xxx_core.c *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; uint32_t 2089 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t ahc_debug = AHC_DEBUG_OPTS; uint32_t 4175 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t sgptr; uint32_t 4188 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t data_cnt; uint32_t 4189 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t data_addr; uint32_t 4190 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t sglen; uint32_t 4264 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t sgptr; uint32_t 4265 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t resid; uint32_t 4266 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t dataptr; uint32_t 5075 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t physaddr; uint32_t 5830 drivers/scsi/aic7xxx/aic7xxx_core.c int lun, u_int tag, role_t role, uint32_t status, uint32_t 6039 drivers/scsi/aic7xxx/aic7xxx_core.c int target, char channel, int lun, uint32_t status, uint32_t 6300 drivers/scsi/aic7xxx/aic7xxx_core.c int lun, u_int tag, role_t role, uint32_t status) uint32_t 6625 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t sgptr; uint32_t 6626 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t resid_sgptr; uint32_t 6627 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t resid; uint32_t 6972 drivers/scsi/aic7xxx/aic7xxx_core.c instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); uint32_t 7051 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t mask; uint32_t 76 drivers/scsi/aic7xxx/aic7xxx_inline.h uint32_t uint32_t 79 drivers/scsi/aic7xxx/aic7xxx_inline.h uint32_t value); uint32_t 273 drivers/scsi/aic7xxx/aic7xxx_osm.c static uint32_t aic7xxx_no_reset; uint32_t 280 drivers/scsi/aic7xxx/aic7xxx_osm.c static uint32_t aic7xxx_extended; uint32_t 292 drivers/scsi/aic7xxx/aic7xxx_osm.c static uint32_t aic7xxx_pci_parity = ~0; uint32_t 300 drivers/scsi/aic7xxx/aic7xxx_osm.c uint32_t aic7xxx_allow_memio = ~0; uint32_t 312 drivers/scsi/aic7xxx/aic7xxx_osm.c static uint32_t aic7xxx_seltime; uint32_t 322 drivers/scsi/aic7xxx/aic7xxx_osm.c static uint32_t aic7xxx_periodic_otag; uint32_t 1028 drivers/scsi/aic7xxx/aic7xxx_osm.c uint32_t *flag; uint32_t 1083 drivers/scsi/aic7xxx/aic7xxx_osm.c uint32_t aic7xxx_verbose; uint32_t 1351 drivers/scsi/aic7xxx/aic7xxx_osm.c int lun, u_int tag, role_t role, uint32_t status) uint32_t 1732 drivers/scsi/aic7xxx/aic7xxx_osm.c uint32_t amount_xferred; uint32_t 131 drivers/scsi/aic7xxx/aic7xxx_osm.h typedef uint32_t bus_size_t; uint32_t 340 drivers/scsi/aic7xxx/aic7xxx_osm.h uint32_t xfer_len; uint32_t 341 drivers/scsi/aic7xxx/aic7xxx_osm.h uint32_t sense_resid; /* Auto-Sense residual */ uint32_t 360 drivers/scsi/aic7xxx/aic7xxx_osm.h #define AHC_LINUX_NOIRQ ((uint32_t)~0) uint32_t 361 drivers/scsi/aic7xxx/aic7xxx_osm.h uint32_t irq; /* IRQ for this adapter */ uint32_t 362 drivers/scsi/aic7xxx/aic7xxx_osm.h uint32_t bios_address; uint32_t 469 drivers/scsi/aic7xxx/aic7xxx_osm.h uint32_t ahc_pci_read_config(ahc_dev_softc_t pci, uint32_t 473 drivers/scsi/aic7xxx/aic7xxx_osm.h int reg, uint32_t value, uint32_t 518 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline void ahc_cmd_set_transaction_status(struct scsi_cmnd *, uint32_t); uint32_t 519 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline void ahc_set_transaction_status(struct scb *, uint32_t); uint32_t 520 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline void ahc_cmd_set_scsi_status(struct scsi_cmnd *, uint32_t); uint32_t 521 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline void ahc_set_scsi_status(struct scb *, uint32_t); uint32_t 522 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline uint32_t ahc_cmd_get_transaction_status(struct scsi_cmnd *cmd); uint32_t 523 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline uint32_t ahc_get_transaction_status(struct scb *); uint32_t 524 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline uint32_t ahc_cmd_get_scsi_status(struct scsi_cmnd *cmd); uint32_t 525 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline uint32_t ahc_get_scsi_status(struct scb *); uint32_t 534 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline uint32_t ahc_get_sense_bufsize(struct ahc_softc *, uint32_t 543 drivers/scsi/aic7xxx/aic7xxx_osm.h void ahc_cmd_set_transaction_status(struct scsi_cmnd *cmd, uint32_t status) uint32_t 550 drivers/scsi/aic7xxx/aic7xxx_osm.h void ahc_set_transaction_status(struct scb *scb, uint32_t status) uint32_t 556 drivers/scsi/aic7xxx/aic7xxx_osm.h void ahc_cmd_set_scsi_status(struct scsi_cmnd *cmd, uint32_t status) uint32_t 563 drivers/scsi/aic7xxx/aic7xxx_osm.h void ahc_set_scsi_status(struct scb *scb, uint32_t status) uint32_t 569 drivers/scsi/aic7xxx/aic7xxx_osm.h uint32_t ahc_cmd_get_transaction_status(struct scsi_cmnd *cmd) uint32_t 575 drivers/scsi/aic7xxx/aic7xxx_osm.h uint32_t ahc_get_transaction_status(struct scb *scb) uint32_t 581 drivers/scsi/aic7xxx/aic7xxx_osm.h uint32_t ahc_cmd_get_scsi_status(struct scsi_cmnd *cmd) uint32_t 587 drivers/scsi/aic7xxx/aic7xxx_osm.h uint32_t ahc_get_scsi_status(struct scb *scb) uint32_t 648 drivers/scsi/aic7xxx/aic7xxx_osm.h static inline uint32_t uint32_t 683 drivers/scsi/aic7xxx/aic7xxx_osm.h role_t role, uint32_t status); uint32_t 273 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c uint32_t uint32_t 292 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c uint32_t retval; uint32_t 304 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width) uint32_t 389 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c uint32_t command; uint32_t 712 drivers/scsi/aic7xxx/aic7xxx_pci.c uint32_t devconfig; uint32_t 860 drivers/scsi/aic7xxx/aic7xxx_pci.c uint32_t devconfig; uint32_t 974 drivers/scsi/aic7xxx/aic7xxx_pci.c uint32_t devconfig; uint32_t 1008 drivers/scsi/aic7xxx/aic7xxx_pci.c uint32_t devconfig; uint32_t 1168 drivers/scsi/aic7xxx/aic7xxx_pci.c uint32_t cmd; uint32_t 1500 drivers/scsi/aic7xxx/aic7xxx_pci.c uint32_t devconfig; uint32_t 2311 drivers/scsi/aic7xxx/aic7xxx_pci.c uint32_t devconfig; uint32_t 50 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t immediate : 8, uint32_t 57 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t parity : 1, uint32_t 69 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t shift_control : 8, uint32_t 76 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t parity : 1, uint32_t 88 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t immediate : 8, uint32_t 94 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t parity : 1, uint32_t 105 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t opcode_ext : 8, uint32_t 112 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t parity : 1, uint32_t 124 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t opcode_ext : 8, uint32_t 130 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t parity : 1, uint32_t 141 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t page : 3, uint32_t 148 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t parity : 1, uint32_t 165 drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h uint32_t integer; uint32_t 144 drivers/scsi/aic7xxx/aiclib.h static inline uint32_t uint32_t 147 drivers/scsi/aic7xxx/aiclib.h uint32_t rv; uint32_t 97 drivers/scsi/arcmsr/arcmsr.h #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) uint32_t 98 drivers/scsi/arcmsr/arcmsr.h #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) uint32_t 106 drivers/scsi/arcmsr/arcmsr.h uint32_t HeaderLength; uint32_t 108 drivers/scsi/arcmsr/arcmsr.h uint32_t Timeout; uint32_t 109 drivers/scsi/arcmsr/arcmsr.h uint32_t ControlCode; uint32_t 110 drivers/scsi/arcmsr/arcmsr.h uint32_t ReturnCode; uint32_t 111 drivers/scsi/arcmsr/arcmsr.h uint32_t Length; uint32_t 189 drivers/scsi/arcmsr/arcmsr.h uint32_t data_len; uint32_t 199 drivers/scsi/arcmsr/arcmsr.h uint32_t signature; /*0, 00-03*/ uint32_t 200 drivers/scsi/arcmsr/arcmsr.h uint32_t request_len; /*1, 04-07*/ uint32_t 201 drivers/scsi/arcmsr/arcmsr.h uint32_t numbers_queue; /*2, 08-11*/ uint32_t 202 drivers/scsi/arcmsr/arcmsr.h uint32_t sdram_size; /*3, 12-15*/ uint32_t 203 drivers/scsi/arcmsr/arcmsr.h uint32_t ide_channels; /*4, 16-19*/ uint32_t 208 drivers/scsi/arcmsr/arcmsr.h uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ uint32_t 210 drivers/scsi/arcmsr/arcmsr.h uint32_t cfgPicStatus; /*30,120-123*/ uint32_t 461 drivers/scsi/arcmsr/arcmsr.h uint32_t msgContext; uint32_t 462 drivers/scsi/arcmsr/arcmsr.h uint32_t DataLength; uint32_t 484 drivers/scsi/arcmsr/arcmsr.h uint32_t resrved0[4]; /*0000 000F*/ uint32_t 485 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_msgaddr0; /*0010 0013*/ uint32_t 486 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_msgaddr1; /*0014 0017*/ uint32_t 487 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_msgaddr0; /*0018 001B*/ uint32_t 488 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_msgaddr1; /*001C 001F*/ uint32_t 489 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_doorbell; /*0020 0023*/ uint32_t 490 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_intstatus; /*0024 0027*/ uint32_t 491 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_intmask; /*0028 002B*/ uint32_t 492 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_doorbell; /*002C 002F*/ uint32_t 493 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_intstatus; /*0030 0033*/ uint32_t 494 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_intmask; /*0034 0037*/ uint32_t 495 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved1[2]; /*0038 003F*/ uint32_t 496 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_queueport; /*0040 0043*/ uint32_t 497 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_queueport; /*0044 0047*/ uint32_t 498 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved2[2]; /*0048 004F*/ uint32_t 499 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved3[492]; /*0050 07FF 492*/ uint32_t 500 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved4[128]; /*0800 09FF 128*/ uint32_t 501 drivers/scsi/arcmsr/arcmsr.h uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ uint32_t 502 drivers/scsi/arcmsr/arcmsr.h uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/ uint32_t 503 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved5[32]; /*0E80 0EFF 32*/ uint32_t 504 drivers/scsi/arcmsr/arcmsr.h uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ uint32_t 505 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved6[32]; /*0F80 0FFF 32*/ uint32_t 510 drivers/scsi/arcmsr/arcmsr.h uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; uint32_t 511 drivers/scsi/arcmsr/arcmsr.h uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; uint32_t 512 drivers/scsi/arcmsr/arcmsr.h uint32_t postq_index; uint32_t 513 drivers/scsi/arcmsr/arcmsr.h uint32_t doneq_index; uint32_t 514 drivers/scsi/arcmsr/arcmsr.h uint32_t __iomem *drv2iop_doorbell; uint32_t 515 drivers/scsi/arcmsr/arcmsr.h uint32_t __iomem *drv2iop_doorbell_mask; uint32_t 516 drivers/scsi/arcmsr/arcmsr.h uint32_t __iomem *iop2drv_doorbell; uint32_t 517 drivers/scsi/arcmsr/arcmsr.h uint32_t __iomem *iop2drv_doorbell_mask; uint32_t 518 drivers/scsi/arcmsr/arcmsr.h uint32_t __iomem *message_rwbuffer; uint32_t 519 drivers/scsi/arcmsr/arcmsr.h uint32_t __iomem *message_wbuffer; uint32_t 520 drivers/scsi/arcmsr/arcmsr.h uint32_t __iomem *message_rbuffer; uint32_t 528 drivers/scsi/arcmsr/arcmsr.h uint32_t message_unit_status; /*0000 0003*/ uint32_t 529 drivers/scsi/arcmsr/arcmsr.h uint32_t slave_error_attribute; /*0004 0007*/ uint32_t 530 drivers/scsi/arcmsr/arcmsr.h uint32_t slave_error_address; /*0008 000B*/ uint32_t 531 drivers/scsi/arcmsr/arcmsr.h uint32_t posted_outbound_doorbell; /*000C 000F*/ uint32_t 532 drivers/scsi/arcmsr/arcmsr.h uint32_t master_error_attribute; /*0010 0013*/ uint32_t 533 drivers/scsi/arcmsr/arcmsr.h uint32_t master_error_address_low; /*0014 0017*/ uint32_t 534 drivers/scsi/arcmsr/arcmsr.h uint32_t master_error_address_high; /*0018 001B*/ uint32_t 535 drivers/scsi/arcmsr/arcmsr.h uint32_t hcb_size; /*001C 001F*/ uint32_t 536 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_doorbell; /*0020 0023*/ uint32_t 537 drivers/scsi/arcmsr/arcmsr.h uint32_t diagnostic_rw_data; /*0024 0027*/ uint32_t 538 drivers/scsi/arcmsr/arcmsr.h uint32_t diagnostic_rw_address_low; /*0028 002B*/ uint32_t 539 drivers/scsi/arcmsr/arcmsr.h uint32_t diagnostic_rw_address_high; /*002C 002F*/ uint32_t 540 drivers/scsi/arcmsr/arcmsr.h uint32_t host_int_status; /*0030 0033*/ uint32_t 541 drivers/scsi/arcmsr/arcmsr.h uint32_t host_int_mask; /*0034 0037*/ uint32_t 542 drivers/scsi/arcmsr/arcmsr.h uint32_t dcr_data; /*0038 003B*/ uint32_t 543 drivers/scsi/arcmsr/arcmsr.h uint32_t dcr_address; /*003C 003F*/ uint32_t 544 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_queueport; /*0040 0043*/ uint32_t 545 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_queueport; /*0044 0047*/ uint32_t 546 drivers/scsi/arcmsr/arcmsr.h uint32_t hcb_pci_address_low; /*0048 004B*/ uint32_t 547 drivers/scsi/arcmsr/arcmsr.h uint32_t hcb_pci_address_high; /*004C 004F*/ uint32_t 548 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_int_status; /*0050 0053*/ uint32_t 549 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_int_mask; /*0054 0057*/ uint32_t 550 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_inbound_queue_port; /*0058 005B*/ uint32_t 551 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_outbound_queue_port; /*005C 005F*/ uint32_t 552 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_free_list_index; /*0060 0063*/ uint32_t 553 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_post_list_index; /*0064 0067*/ uint32_t 554 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_free_list_index; /*0068 006B*/ uint32_t 555 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_post_list_index; /*006C 006F*/ uint32_t 556 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_doorbell_clear; /*0070 0073*/ uint32_t 557 drivers/scsi/arcmsr/arcmsr.h uint32_t i2o_message_unit_control; /*0074 0077*/ uint32_t 558 drivers/scsi/arcmsr/arcmsr.h uint32_t last_used_message_source_address_low; /*0078 007B*/ uint32_t 559 drivers/scsi/arcmsr/arcmsr.h uint32_t last_used_message_source_address_high; /*007C 007F*/ uint32_t 560 drivers/scsi/arcmsr/arcmsr.h uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ uint32_t 561 drivers/scsi/arcmsr/arcmsr.h uint32_t message_dest_address_index; /*0090 0093*/ uint32_t 562 drivers/scsi/arcmsr/arcmsr.h uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ uint32_t 563 drivers/scsi/arcmsr/arcmsr.h uint32_t utility_A_int_counter_timer; /*0098 009B*/ uint32_t 564 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_doorbell; /*009C 009F*/ uint32_t 565 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_doorbell_clear; /*00A0 00A3*/ uint32_t 566 drivers/scsi/arcmsr/arcmsr.h uint32_t message_source_address_index; /*00A4 00A7*/ uint32_t 567 drivers/scsi/arcmsr/arcmsr.h uint32_t message_done_queue_index; /*00A8 00AB*/ uint32_t 568 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved0; /*00AC 00AF*/ uint32_t 569 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_msgaddr0; /*00B0 00B3*/ uint32_t 570 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_msgaddr1; /*00B4 00B7*/ uint32_t 571 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_msgaddr0; /*00B8 00BB*/ uint32_t 572 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_msgaddr1; /*00BC 00BF*/ uint32_t 573 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_queueport_low; /*00C0 00C3*/ uint32_t 574 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_queueport_high; /*00C4 00C7*/ uint32_t 575 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_queueport_low; /*00C8 00CB*/ uint32_t 576 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_queueport_high; /*00CC 00CF*/ uint32_t 577 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ uint32_t 578 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ uint32_t 579 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ uint32_t 580 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ uint32_t 581 drivers/scsi/arcmsr/arcmsr.h uint32_t message_dest_queue_port_low; /*00E0 00E3*/ uint32_t 582 drivers/scsi/arcmsr/arcmsr.h uint32_t message_dest_queue_port_high; /*00E4 00E7*/ uint32_t 583 drivers/scsi/arcmsr/arcmsr.h uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ uint32_t 584 drivers/scsi/arcmsr/arcmsr.h uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ uint32_t 585 drivers/scsi/arcmsr/arcmsr.h uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ uint32_t 586 drivers/scsi/arcmsr/arcmsr.h uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ uint32_t 587 drivers/scsi/arcmsr/arcmsr.h uint32_t host_diagnostic; /*00F8 00FB*/ uint32_t 588 drivers/scsi/arcmsr/arcmsr.h uint32_t write_sequence; /*00FC 00FF*/ uint32_t 589 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved1[34]; /*0100 0187*/ uint32_t 590 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved2[1950]; /*0188 1FFF*/ uint32_t 591 drivers/scsi/arcmsr/arcmsr.h uint32_t message_wbuffer[32]; /*2000 207F*/ uint32_t 592 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved3[32]; /*2080 20FF*/ uint32_t 593 drivers/scsi/arcmsr/arcmsr.h uint32_t message_rbuffer[32]; /*2100 217F*/ uint32_t 594 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved4[32]; /*2180 21FF*/ uint32_t 595 drivers/scsi/arcmsr/arcmsr.h uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/ uint32_t 603 drivers/scsi/arcmsr/arcmsr.h uint32_t addressLow; /* pointer to SRB block */ uint32_t 604 drivers/scsi/arcmsr/arcmsr.h uint32_t addressHigh; uint32_t 605 drivers/scsi/arcmsr/arcmsr.h uint32_t length; /* in DWORDs */ uint32_t 606 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved0; uint32_t 610 drivers/scsi/arcmsr/arcmsr.h uint32_t addressLow; /* pointer to SRB block */ uint32_t 611 drivers/scsi/arcmsr/arcmsr.h uint32_t addressHigh; uint32_t 653 drivers/scsi/arcmsr/arcmsr.h uint32_t iobound_doorbell; /*0000 0003*/ uint32_t 654 drivers/scsi/arcmsr/arcmsr.h uint32_t write_sequence_3xxx; /*0004 0007*/ uint32_t 655 drivers/scsi/arcmsr/arcmsr.h uint32_t host_diagnostic_3xxx; /*0008 000B*/ uint32_t 656 drivers/scsi/arcmsr/arcmsr.h uint32_t posted_outbound_doorbell; /*000C 000F*/ uint32_t 657 drivers/scsi/arcmsr/arcmsr.h uint32_t master_error_attribute; /*0010 0013*/ uint32_t 658 drivers/scsi/arcmsr/arcmsr.h uint32_t master_error_address_low; /*0014 0017*/ uint32_t 659 drivers/scsi/arcmsr/arcmsr.h uint32_t master_error_address_high; /*0018 001B*/ uint32_t 660 drivers/scsi/arcmsr/arcmsr.h uint32_t hcb_size; /*001C 001F*/ uint32_t 661 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_doorbell; /*0020 0023*/ uint32_t 662 drivers/scsi/arcmsr/arcmsr.h uint32_t diagnostic_rw_data; /*0024 0027*/ uint32_t 663 drivers/scsi/arcmsr/arcmsr.h uint32_t diagnostic_rw_address_low; /*0028 002B*/ uint32_t 664 drivers/scsi/arcmsr/arcmsr.h uint32_t diagnostic_rw_address_high; /*002C 002F*/ uint32_t 665 drivers/scsi/arcmsr/arcmsr.h uint32_t host_int_status; /*0030 0033*/ uint32_t 666 drivers/scsi/arcmsr/arcmsr.h uint32_t host_int_mask; /*0034 0037*/ uint32_t 667 drivers/scsi/arcmsr/arcmsr.h uint32_t dcr_data; /*0038 003B*/ uint32_t 668 drivers/scsi/arcmsr/arcmsr.h uint32_t dcr_address; /*003C 003F*/ uint32_t 669 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_queueport; /*0040 0043*/ uint32_t 670 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_queueport; /*0044 0047*/ uint32_t 671 drivers/scsi/arcmsr/arcmsr.h uint32_t hcb_pci_address_low; /*0048 004B*/ uint32_t 672 drivers/scsi/arcmsr/arcmsr.h uint32_t hcb_pci_address_high; /*004C 004F*/ uint32_t 673 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_int_status; /*0050 0053*/ uint32_t 674 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_int_mask; /*0054 0057*/ uint32_t 675 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_inbound_queue_port; /*0058 005B*/ uint32_t 676 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_outbound_queue_port; /*005C 005F*/ uint32_t 677 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_free_list_index; /*0060 0063*/ uint32_t 678 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_post_list_index; /*0064 0067*/ uint32_t 679 drivers/scsi/arcmsr/arcmsr.h uint32_t reply_post_producer_index; /*0068 006B*/ uint32_t 680 drivers/scsi/arcmsr/arcmsr.h uint32_t reply_post_consumer_index; /*006C 006F*/ uint32_t 681 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_doorbell_clear; /*0070 0073*/ uint32_t 682 drivers/scsi/arcmsr/arcmsr.h uint32_t i2o_message_unit_control; /*0074 0077*/ uint32_t 683 drivers/scsi/arcmsr/arcmsr.h uint32_t last_used_message_source_address_low; /*0078 007B*/ uint32_t 684 drivers/scsi/arcmsr/arcmsr.h uint32_t last_used_message_source_address_high; /*007C 007F*/ uint32_t 685 drivers/scsi/arcmsr/arcmsr.h uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ uint32_t 686 drivers/scsi/arcmsr/arcmsr.h uint32_t message_dest_address_index; /*0090 0093*/ uint32_t 687 drivers/scsi/arcmsr/arcmsr.h uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ uint32_t 688 drivers/scsi/arcmsr/arcmsr.h uint32_t utility_A_int_counter_timer; /*0098 009B*/ uint32_t 689 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_doorbell; /*009C 009F*/ uint32_t 690 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_doorbell_clear; /*00A0 00A3*/ uint32_t 691 drivers/scsi/arcmsr/arcmsr.h uint32_t message_source_address_index; /*00A4 00A7*/ uint32_t 692 drivers/scsi/arcmsr/arcmsr.h uint32_t message_done_queue_index; /*00A8 00AB*/ uint32_t 693 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved0; /*00AC 00AF*/ uint32_t 694 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_msgaddr0; /*00B0 00B3*/ uint32_t 695 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_msgaddr1; /*00B4 00B7*/ uint32_t 696 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_msgaddr0; /*00B8 00BB*/ uint32_t 697 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_msgaddr1; /*00BC 00BF*/ uint32_t 698 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_queueport_low; /*00C0 00C3*/ uint32_t 699 drivers/scsi/arcmsr/arcmsr.h uint32_t inbound_queueport_high; /*00C4 00C7*/ uint32_t 700 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_queueport_low; /*00C8 00CB*/ uint32_t 701 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_queueport_high; /*00CC 00CF*/ uint32_t 702 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ uint32_t 703 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ uint32_t 704 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ uint32_t 705 drivers/scsi/arcmsr/arcmsr.h uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ uint32_t 706 drivers/scsi/arcmsr/arcmsr.h uint32_t message_dest_queue_port_low; /*00E0 00E3*/ uint32_t 707 drivers/scsi/arcmsr/arcmsr.h uint32_t message_dest_queue_port_high; /*00E4 00E7*/ uint32_t 708 drivers/scsi/arcmsr/arcmsr.h uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ uint32_t 709 drivers/scsi/arcmsr/arcmsr.h uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ uint32_t 710 drivers/scsi/arcmsr/arcmsr.h uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ uint32_t 711 drivers/scsi/arcmsr/arcmsr.h uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ uint32_t 712 drivers/scsi/arcmsr/arcmsr.h uint32_t host_diagnostic; /*00F8 00FB*/ uint32_t 713 drivers/scsi/arcmsr/arcmsr.h uint32_t write_sequence; /*00FC 00FF*/ uint32_t 714 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved1[34]; /*0100 0187*/ uint32_t 715 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved2[1950]; /*0188 1FFF*/ uint32_t 716 drivers/scsi/arcmsr/arcmsr.h uint32_t message_wbuffer[32]; /*2000 207F*/ uint32_t 717 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved3[32]; /*2080 20FF*/ uint32_t 718 drivers/scsi/arcmsr/arcmsr.h uint32_t message_rbuffer[32]; /*2100 217F*/ uint32_t 719 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved4[32]; /*2180 21FF*/ uint32_t 720 drivers/scsi/arcmsr/arcmsr.h uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/ uint32_t 736 drivers/scsi/arcmsr/arcmsr.h uint32_t adapter_type; /* adapter A,B..... */ uint32_t 747 drivers/scsi/arcmsr/arcmsr.h uint32_t outbound_int_enable; uint32_t 748 drivers/scsi/arcmsr/arcmsr.h uint32_t cdb_phyaddr_hi32; uint32_t 749 drivers/scsi/arcmsr/arcmsr.h uint32_t reg_mu_acc_handle0; uint32_t 767 drivers/scsi/arcmsr/arcmsr.h uint32_t acb_flags; uint32_t 822 drivers/scsi/arcmsr/arcmsr.h uint32_t num_resets; uint32_t 823 drivers/scsi/arcmsr/arcmsr.h uint32_t num_aborts; uint32_t 824 drivers/scsi/arcmsr/arcmsr.h uint32_t signature; uint32_t 825 drivers/scsi/arcmsr/arcmsr.h uint32_t firm_request_len; uint32_t 826 drivers/scsi/arcmsr/arcmsr.h uint32_t firm_numbers_queue; uint32_t 827 drivers/scsi/arcmsr/arcmsr.h uint32_t firm_sdram_size; uint32_t 828 drivers/scsi/arcmsr/arcmsr.h uint32_t firm_hd_channels; uint32_t 829 drivers/scsi/arcmsr/arcmsr.h uint32_t firm_cfg_version; uint32_t 841 drivers/scsi/arcmsr/arcmsr.h uint32_t maxOutstanding; uint32_t 843 drivers/scsi/arcmsr/arcmsr.h uint32_t maxFreeCCB; uint32_t 845 drivers/scsi/arcmsr/arcmsr.h uint32_t doneq_index; uint32_t 846 drivers/scsi/arcmsr/arcmsr.h uint32_t ccbsize; uint32_t 847 drivers/scsi/arcmsr/arcmsr.h uint32_t in_doorbell; uint32_t 848 drivers/scsi/arcmsr/arcmsr.h uint32_t out_doorbell; uint32_t 849 drivers/scsi/arcmsr/arcmsr.h uint32_t completionQ_entry; uint32_t 864 drivers/scsi/arcmsr/arcmsr.h uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/ uint32_t 876 drivers/scsi/arcmsr/arcmsr.h uint32_t smid; uint32_t 879 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved[3]; /*12 byte*/ uint32_t 882 drivers/scsi/arcmsr/arcmsr.h uint32_t reserved[8]; /*32 byte*/ uint32_t 943 drivers/scsi/arcmsr/arcmsr.h extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *, uint32_t 457 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t read_doorbell; uint32_t 672 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t completeQ_size; uint32_t 705 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t firm_config_version, curr_phy_upper32; uint32_t 788 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t __iomem *signature = NULL; uint32_t 799 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); uint32_t 806 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); uint32_t 813 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); uint32_t 820 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); uint32_t 827 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); uint32_t 1075 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t intmask_org; uint32_t 1116 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t i; uint32_t 1411 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t flag_ccb; uint32_t 1421 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_intstatus; uint32_t 1478 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_write_pointer; uint32_t 1479 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t doneq_index, index_stripped, addressLow, residual, toggle; uint32_t 1781 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t cdb_phyaddr = ccb->cdb_phyaddr; uint32_t 1799 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t ending_index, index = reg->postq_index; uint32_t 1817 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t ccb_post_stamp, arc_cdb_size; uint32_t 2106 drivers/scsi/arcmsr/arcmsr_hba.c static uint32_t uint32_t 2112 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t __iomem *iop_data; uint32_t 2113 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t iop_len, data_len, *buf2 = NULL; uint32_t 2115 drivers/scsi/arcmsr/arcmsr_hba.c iop_data = (uint32_t __iomem *)prbuffer->data; uint32_t 2119 drivers/scsi/arcmsr/arcmsr_hba.c buf2 = (uint32_t *)buf1; uint32_t 2130 drivers/scsi/arcmsr/arcmsr_hba.c buf2 = (uint32_t *)buf1; uint32_t 2147 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t uint32_t 2153 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t iop_len; uint32_t 2194 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t __iomem *iop_data; uint32_t 2195 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data; uint32_t 2199 drivers/scsi/arcmsr/arcmsr_hba.c buf2 = (uint32_t *)buf1; uint32_t 2205 drivers/scsi/arcmsr/arcmsr_hba.c iop_data = (uint32_t __iomem *)pwbuffer->data; uint32_t 2278 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_doorbell; uint32_t 2293 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_doorbell; uint32_t 2320 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_doorbell; uint32_t 2340 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_doorbell, in_doorbell, tmp; uint32_t 2367 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t flag_ccb; uint32_t 2386 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t index; uint32_t 2387 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t flag_ccb; uint32_t 2415 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t flag_ccb, throttling = 0; uint32_t 2448 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t addressLow; uint32_t 2493 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t doneq_index; uint32_t 2582 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_intstatus; uint32_t 2606 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_doorbell; uint32_t 2634 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t host_interrupt_status; uint32_t 2685 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t host_interrupt_status; uint32_t 2733 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t intmask_org; uint32_t 2746 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t i; uint32_t 2775 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 | uint32_t 2776 drivers/scsi/arcmsr/arcmsr_hba.c (uint32_t)cmd->cmnd[6] << 16 | uint32_t 2777 drivers/scsi/arcmsr/arcmsr_hba.c (uint32_t)cmd->cmnd[7] << 8 | uint32_t 2778 drivers/scsi/arcmsr/arcmsr_hba.c (uint32_t)cmd->cmnd[8]; uint32_t 2799 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t allxfer_len = 0; uint32_t 2847 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t user_len; uint32_t 3123 drivers/scsi/arcmsr/arcmsr_hba.c static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer) uint32_t 3126 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model; uint32_t 3127 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version; uint32_t 3128 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t *acb_device_map = (uint32_t *)pACB->device_map; uint32_t 3129 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t *firm_model = &rwbuffer[15]; uint32_t 3130 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t *firm_version = &rwbuffer[17]; uint32_t 3131 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t *device_map = &rwbuffer[21]; uint32_t 3202 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t intmask_org; uint32_t 3248 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t intmask_org; uint32_t 3311 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0; uint32_t 3372 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0; uint32_t 3439 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t flag_ccb; uint32_t 3443 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t poll_ccb_done = 0, poll_count = 0; uint32_t 3501 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb; uint32_t 3579 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index; uint32_t 3690 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t msg_time[2]; uint32_t 3713 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t __iomem *rwbuffer; uint32_t 3730 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t __iomem *rwbuffer; uint32_t 3757 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t cdb_phyaddr, cdb_phyaddr_hi32; uint32_t 3809 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t __iomem *rwbuffer; uint32_t 3863 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t __iomem *rwbuffer; uint32_t 3890 drivers/scsi/arcmsr/arcmsr_hba.c cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff); uint32_t 3891 drivers/scsi/arcmsr/arcmsr_hba.c cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16); uint32_t 3911 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t firmware_state = 0; uint32_t 4110 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_doorbell; uint32_t 4121 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_doorbell, i; uint32_t 4138 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_doorbell, i; uint32_t 4159 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t outbound_doorbell, i; uint32_t 4181 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t i, tmp; uint32_t 4318 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t intmask_org; uint32_t 4336 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t intmask_org; uint32_t 4439 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t intmask_org; uint32_t 178 drivers/scsi/be2iscsi/be_cmds.c uint32_t mcc_tag_status; uint32_t 1335 drivers/scsi/be2iscsi/be_cmds.c uint32_t cid_count, icd_count; uint32_t 1792 drivers/scsi/be2iscsi/be_cmds.c uint32_t ue_mask_hi = 0, ue_mask_lo = 0; uint32_t 1793 drivers/scsi/be2iscsi/be_cmds.c uint32_t ue_hi = 0, ue_lo = 0; uint32_t 353 drivers/scsi/be2iscsi/be_cmds.h uint32_t session_handle; uint32_t 358 drivers/scsi/be2iscsi/be_cmds.h uint32_t session_status; uint32_t 332 drivers/scsi/be2iscsi/be_iscsi.c void *data, uint32_t dt_len) uint32_t 397 drivers/scsi/be2iscsi/be_iscsi.c void *data, uint32_t dt_len) uint32_t 421 drivers/scsi/be2iscsi/be_iscsi.c void *data, uint32_t dt_len) uint32_t 426 drivers/scsi/be2iscsi/be_iscsi.c uint32_t rm_len = dt_len; uint32_t 25 drivers/scsi/be2iscsi/be_iscsi.h void *data, uint32_t count); uint32_t 39 drivers/scsi/be2iscsi/be_iscsi.h uint32_t initial_cmdsn); uint32_t 46 drivers/scsi/be2iscsi/be_iscsi.h *cls_session, uint32_t cid); uint32_t 82 drivers/scsi/be2iscsi/be_main.c beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\ uint32_t 107 drivers/scsi/be2iscsi/be_main.c uint32_t param_val = 0;\ uint32_t 120 drivers/scsi/be2iscsi/be_main.c beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \ uint32_t 560 drivers/scsi/be2iscsi/be_main.c uint32_t total_cid_count = 0; uint32_t 561 drivers/scsi/be2iscsi/be_main.c uint32_t total_icd_count = 0; uint32_t 568 drivers/scsi/be2iscsi/be_main.c uint32_t align_mask = 0; uint32_t 569 drivers/scsi/be2iscsi/be_main.c uint32_t icd_post_per_page = 0; uint32_t 570 drivers/scsi/be2iscsi/be_main.c uint32_t icd_count_unavailable = 0; uint32_t 571 drivers/scsi/be2iscsi/be_main.c uint32_t icd_start = 0, icd_count = 0; uint32_t 572 drivers/scsi/be2iscsi/be_main.c uint32_t icd_start_align = 0, icd_count_align = 0; uint32_t 241 drivers/scsi/be2iscsi/be_main.h uint32_t doorbell_offset; uint32_t 375 drivers/scsi/be2iscsi/be_main.h uint32_t num_sg, uint32_t xferlen, uint32_t 376 drivers/scsi/be2iscsi/be_main.h uint32_t writedir); uint32_t 469 drivers/scsi/be2iscsi/be_main.h uint32_t mtask_data_count; uint32_t 1025 drivers/scsi/be2iscsi/be_main.h uint32_t log_value = phba->attr_log_enable; \ uint32_t 548 drivers/scsi/be2iscsi/be_mgmt.c uint32_t ip_len; uint32_t 738 drivers/scsi/be2iscsi/be_mgmt.c uint32_t ioctl_size = sizeof(struct be_cmd_get_if_info_resp); uint32_t 240 drivers/scsi/be2iscsi/be_mgmt.h uint32_t fw_sess_handle); uint32_t 1469 drivers/scsi/bfa/bfa_fcs.c bfa_trc(fcs, (uint32_t) *nlports); uint32_t 5229 drivers/scsi/bfa/bfa_ioc.c bfa_boolean_t link_e2e_beacon, uint32_t sec) uint32_t 19 drivers/scsi/bfa/bfa_ioc_ct.c ((uint32_t) (1 << bfa_ioc_pcifn(__ioc))) uint32_t 172 drivers/scsi/bfa/bfa_ioc_ct.c static struct { uint32_t hfn_mbox, lpu_mbox, hfn_pgn, hfn, lpu, lpu_read; } uint32_t 406 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync); uint32_t 407 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t sync_reqd = bfa_ioc_ct_get_sync_reqd(r32); uint32_t 433 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync); uint32_t 434 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t sync_pos = bfa_ioc_ct_sync_reqd_pos(ioc); uint32_t 442 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync); uint32_t 443 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t sync_msk = bfa_ioc_ct_sync_reqd_pos(ioc) | uint32_t 452 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync); uint32_t 461 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync); uint32_t 462 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t sync_reqd = bfa_ioc_ct_get_sync_reqd(r32); uint32_t 463 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t sync_ackd = bfa_ioc_ct_get_sync_ackd(r32); uint32_t 464 drivers/scsi/bfa/bfa_ioc_ct.c uint32_t tmp_ackd; uint32_t 1963 drivers/scsi/bfa/bfa_svc.c bfa_lps_set_n2n_pid(struct bfa_lps_s *lps, uint32_t n2n_pid) uint32_t 53 drivers/scsi/bfa/bfa_svc.h BFI_MEM_DMA_NSEGS(BFA_SGPG_MAX, (uint32_t)sizeof(struct bfi_sgpg_s)) uint32_t 448 drivers/scsi/bfa/bfad_attr.c uint32_t status; uint32_t 875 drivers/scsi/bfa/bfad_bsg.c uint32_t nports = iocmd->nports; uint32_t 3127 drivers/scsi/bfa/bfad_bsg.c uint32_t vendor_cmd = bsg_request->rqst_data.h_vendor.vendor_cmd[0]; uint32_t 3174 drivers/scsi/bfa/bfad_bsg.c job->reply_len = sizeof(uint32_t); uint32_t 3241 drivers/scsi/bfa/bfad_bsg.c uint32_t payload_len, uint32_t *num_sgles) uint32_t 3285 drivers/scsi/bfa/bfad_bsg.c uint32_t num_sgles) uint32_t 3354 drivers/scsi/bfa/bfad_bsg.c uint32_t command_type = bsg_request->msgcode; uint32_t 3360 drivers/scsi/bfa/bfad_bsg.c job->reply_len = sizeof(uint32_t); /* Atleast uint32_t reply_len */ uint32_t 3514 drivers/scsi/bfa/bfad_bsg.c job->reply_len = sizeof(uint32_t); uint32_t 3555 drivers/scsi/bfa/bfad_bsg.c uint32_t rc = BFA_STATUS_OK; uint32_t 1289 drivers/scsi/bnx2i/bnx2i_iscsi.c uint32_t initial_cmdsn) uint32_t 1358 drivers/scsi/bnx2i/bnx2i_iscsi.c bnx2i_conn_create(struct iscsi_cls_session *cls_session, uint32_t cid) uint32_t 380 drivers/scsi/csiostor/csio_attr.c csio_set_rport_loss_tmo(struct fc_rport *rport, uint32_t timeout) uint32_t 76 drivers/scsi/csiostor/csio_defs.h typedef void (*csio_sm_state_t)(void *, uint32_t); uint32_t 96 drivers/scsi/csiostor/csio_defs.h csio_post_event(void *smp, uint32_t evt) uint32_t 54 drivers/scsi/csiostor/csio_hw.c static uint32_t csio_evtq_sz = CSIO_EVTQ_SIZE; uint32_t 133 drivers/scsi/csiostor/csio_hw.c csio_hw_wait_op_done_val(struct csio_hw *hw, int reg, uint32_t mask, uint32_t 134 drivers/scsi/csiostor/csio_hw.c int polarity, int attempts, int delay, uint32_t *valp) uint32_t 136 drivers/scsi/csiostor/csio_hw.c uint32_t val; uint32_t 172 drivers/scsi/csiostor/csio_hw.c csio_set_reg_field(struct csio_hw *hw, uint32_t reg, uint32_t mask, uint32_t 173 drivers/scsi/csiostor/csio_hw.c uint32_t value) uint32_t 175 drivers/scsi/csiostor/csio_hw.c uint32_t val = csio_rd_reg32(hw, reg) & ~mask; uint32_t 212 drivers/scsi/csiostor/csio_hw.c csio_hw_seeprom_read(struct csio_hw *hw, uint32_t addr, uint32_t *data) uint32_t 216 drivers/scsi/csiostor/csio_hw.c uint32_t base = hw->params.pci.vpd_cap_addr; uint32_t 327 drivers/scsi/csiostor/csio_hw.c ret = csio_hw_seeprom_read(hw, VPD_BASE, (uint32_t *)(vpd)); uint32_t 331 drivers/scsi/csiostor/csio_hw.c ret = csio_hw_seeprom_read(hw, addr + i, (uint32_t *)(vpd + i)); uint32_t 392 drivers/scsi/csiostor/csio_hw.c csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont, uint32_t 393 drivers/scsi/csiostor/csio_hw.c int32_t lock, uint32_t *valp) uint32_t 424 drivers/scsi/csiostor/csio_hw.c csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont, uint32_t 425 drivers/scsi/csiostor/csio_hw.c int32_t lock, uint32_t val) uint32_t 452 drivers/scsi/csiostor/csio_hw.c uint32_t status; uint32_t 486 drivers/scsi/csiostor/csio_hw.c csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords, uint32_t 487 drivers/scsi/csiostor/csio_hw.c uint32_t *data, int32_t byte_oriented) uint32_t 491 drivers/scsi/csiostor/csio_hw.c if (addr + nwords * sizeof(uint32_t) > hw->params.sf_size || (addr & 3)) uint32_t 527 drivers/scsi/csiostor/csio_hw.c csio_hw_write_flash(struct csio_hw *hw, uint32_t addr, uint32_t 528 drivers/scsi/csiostor/csio_hw.c uint32_t n, const uint8_t *data) uint32_t 531 drivers/scsi/csiostor/csio_hw.c uint32_t buf[64]; uint32_t 532 drivers/scsi/csiostor/csio_hw.c uint32_t i, c, left, val, offset = addr & 0xff; uint32_t 637 drivers/scsi/csiostor/csio_hw.c csio_hw_get_fw_version(struct csio_hw *hw, uint32_t *vers) uint32_t 668 drivers/scsi/csiostor/csio_hw.c csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size) uint32_t 670 drivers/scsi/csiostor/csio_hw.c uint32_t csum; uint32_t 673 drivers/scsi/csiostor/csio_hw.c uint32_t i; uint32_t 677 drivers/scsi/csiostor/csio_hw.c uint32_t sf_sec_size; uint32_t 884 drivers/scsi/csiostor/csio_hw.c uint32_t reg; uint32_t 978 drivers/scsi/csiostor/csio_hw.c uint32_t pcie_fw; uint32_t 1180 drivers/scsi/csiostor/csio_hw.c csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force) uint32_t 1259 drivers/scsi/csiostor/csio_hw.c csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset) uint32_t 1322 drivers/scsi/csiostor/csio_hw.c csio_hw_fw_upgrade(struct csio_hw *hw, uint32_t mbox, uint32_t 1323 drivers/scsi/csiostor/csio_hw.c const u8 *fw_data, uint32_t size, int32_t force) uint32_t 1724 drivers/scsi/csiostor/csio_hw.c uint32_t *rcaps) uint32_t 1975 drivers/scsi/csiostor/csio_hw.c uint32_t *cfg_data; uint32_t 2058 drivers/scsi/csiostor/csio_hw.c uint32_t finiver = 0, finicsum = 0, cfcsum = 0; uint32_t 2327 drivers/scsi/csiostor/csio_hw.c sizeof(*card_fw) / sizeof(uint32_t), uint32_t 2328 drivers/scsi/csiostor/csio_hw.c (uint32_t *)card_fw, 1); uint32_t 2370 drivers/scsi/csiostor/csio_hw.c uint32_t d, c, k; uint32_t 2683 drivers/scsi/csiostor/csio_hw.c uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE_A); uint32_t 3191 drivers/scsi/csiostor/csio_hw.c csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF), uint32_t 3193 drivers/scsi/csiostor/csio_hw.c csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2_A); uint32_t 3489 drivers/scsi/csiostor/csio_hw.c uint32_t cnt = ECC_CECNT_G(csio_rd_reg32(hw, cnt_addr)); uint32_t 3508 drivers/scsi/csiostor/csio_hw.c uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE_A); uint32_t 3561 drivers/scsi/csiostor/csio_hw.c uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)); uint32_t 3601 drivers/scsi/csiostor/csio_hw.c uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE_A); uint32_t 3821 drivers/scsi/csiostor/csio_hw.c uint32_t off = 0; uint32_t 3887 drivers/scsi/csiostor/csio_hw.c uint32_t count; uint32_t 3933 drivers/scsi/csiostor/csio_hw.c csio_process_fwevtq_entry(struct csio_hw *hw, void *wr, uint32_t len, uint32_t 3938 drivers/scsi/csiostor/csio_hw.c uint32_t msg_len = 0; uint32_t 4120 drivers/scsi/csiostor/csio_hw.c io_req->tmo -= min_t(uint32_t, io_req->tmo, ECM_MIN_TMO); uint32_t 4149 drivers/scsi/csiostor/csio_hw.c uint32_t count; uint32_t 4313 drivers/scsi/csiostor/csio_hw.c uint32_t adap_type, prot_type; uint32_t 4342 drivers/scsi/csiostor/csio_hw.c uint32_t i; uint32_t 4367 drivers/scsi/csiostor/csio_hw.c hw->params.log_level = (uint32_t) csio_dbg_level; uint32_t 106 drivers/scsi/csiostor/csio_hw.h uint32_t intr_idx; /* MSIX Vector index */ uint32_t 214 drivers/scsi/csiostor/csio_hw.h uint32_t n_abort_req; /* Total abort request */ uint32_t 215 drivers/scsi/csiostor/csio_hw.h uint32_t n_abort_rsp; /* Total abort response */ uint32_t 216 drivers/scsi/csiostor/csio_hw.h uint32_t n_close_req; /* Total close request */ uint32_t 217 drivers/scsi/csiostor/csio_hw.h uint32_t n_close_rsp; /* Total close response */ uint32_t 218 drivers/scsi/csiostor/csio_hw.h uint32_t n_err; /* Total Errors */ uint32_t 219 drivers/scsi/csiostor/csio_hw.h uint32_t n_drop; /* Total request dropped */ uint32_t 220 drivers/scsi/csiostor/csio_hw.h uint32_t n_active; /* Count of active_q */ uint32_t 221 drivers/scsi/csiostor/csio_hw.h uint32_t n_cbfn; /* Count of cbfn_q */ uint32_t 254 drivers/scsi/csiostor/csio_hw.h uint32_t sf_size; /* serial flash uint32_t 257 drivers/scsi/csiostor/csio_hw.h uint32_t sf_nsec; /* # of flash sectors */ uint32_t 259 drivers/scsi/csiostor/csio_hw.h uint32_t log_level; /* Module-level for uint32_t 265 drivers/scsi/csiostor/csio_hw.h uint32_t cclk; uint32_t 344 drivers/scsi/csiostor/csio_hw.h uint32_t max_xchgs; uint32_t 345 drivers/scsi/csiostor/csio_hw.h uint32_t max_ssns; uint32_t 346 drivers/scsi/csiostor/csio_hw.h uint32_t used_xchgs; uint32_t 347 drivers/scsi/csiostor/csio_hw.h uint32_t used_ssns; uint32_t 348 drivers/scsi/csiostor/csio_hw.h uint32_t max_fcfs; uint32_t 349 drivers/scsi/csiostor/csio_hw.h uint32_t max_vnps; uint32_t 350 drivers/scsi/csiostor/csio_hw.h uint32_t used_fcfs; uint32_t 351 drivers/scsi/csiostor/csio_hw.h uint32_t used_vnps; uint32_t 356 drivers/scsi/csiostor/csio_hw.h CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */ uint32_t 375 drivers/scsi/csiostor/csio_hw.h uint32_t n_evt_activeq; /* Number of event in active Q */ uint32_t 376 drivers/scsi/csiostor/csio_hw.h uint32_t n_evt_freeq; /* Number of event in free Q */ uint32_t 377 drivers/scsi/csiostor/csio_hw.h uint32_t n_evt_drop; /* Number of event droped */ uint32_t 378 drivers/scsi/csiostor/csio_hw.h uint32_t n_evt_unexp; /* Number of unexpected events */ uint32_t 379 drivers/scsi/csiostor/csio_hw.h uint32_t n_pcich_offline;/* Number of pci channel offline */ uint32_t 380 drivers/scsi/csiostor/csio_hw.h uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */ uint32_t 381 drivers/scsi/csiostor/csio_hw.h uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/ uint32_t 382 drivers/scsi/csiostor/csio_hw.h uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/ uint32_t 383 drivers/scsi/csiostor/csio_hw.h uint32_t n_cpl_unexp; /* Number of unexpected cpl */ uint32_t 384 drivers/scsi/csiostor/csio_hw.h uint32_t n_mbint_unexp; /* Number of unexpected mbox */ uint32_t 386 drivers/scsi/csiostor/csio_hw.h uint32_t n_plint_unexp; /* Number of unexpected PL */ uint32_t 388 drivers/scsi/csiostor/csio_hw.h uint32_t n_plint_cnt; /* Number of PL interrupt */ uint32_t 389 drivers/scsi/csiostor/csio_hw.h uint32_t n_int_stray; /* Number of stray interrupt */ uint32_t 390 drivers/scsi/csiostor/csio_hw.h uint32_t n_err; /* Number of hw errors */ uint32_t 391 drivers/scsi/csiostor/csio_hw.h uint32_t n_err_fatal; /* Number of fatal errors */ uint32_t 392 drivers/scsi/csiostor/csio_hw.h uint32_t n_err_nomem; /* Number of memory alloc failure */ uint32_t 393 drivers/scsi/csiostor/csio_hw.h uint32_t n_err_io; /* Number of IO failure */ uint32_t 396 drivers/scsi/csiostor/csio_hw.h uint32_t rsvd1; uint32_t 463 drivers/scsi/csiostor/csio_hw.h uint32_t num_sqsets; /* Number of SCSI uint32_t 465 drivers/scsi/csiostor/csio_hw.h uint32_t num_scsi_msix_cpus; /* Number of CPUs that uint32_t 474 drivers/scsi/csiostor/csio_hw.h uint32_t evtflag; /* Event flag */ uint32_t 475 drivers/scsi/csiostor/csio_hw.h uint32_t flags; /* HW flags */ uint32_t 481 drivers/scsi/csiostor/csio_hw.h uint32_t num_lns; /* Number of lnodes */ uint32_t 504 drivers/scsi/csiostor/csio_hw.h uint32_t optrom_ver; uint32_t 505 drivers/scsi/csiostor/csio_hw.h uint32_t fwrev; uint32_t 506 drivers/scsi/csiostor/csio_hw.h uint32_t tp_vers; uint32_t 515 drivers/scsi/csiostor/csio_hw.h uint32_t port_vec; /* Port vector */ uint32_t 522 drivers/scsi/csiostor/csio_hw.h uint32_t dev_num; /* device number */ uint32_t 532 drivers/scsi/csiostor/csio_hw.h uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt uint32_t 535 drivers/scsi/csiostor/csio_hw.h uint32_t nondata_intr_idx; /* nondata MSIX/intr uint32_t 575 drivers/scsi/csiostor/csio_hw.h void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t); uint32_t 578 drivers/scsi/csiostor/csio_hw.h static inline uint32_t uint32_t 579 drivers/scsi/csiostor/csio_hw.h csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks) uint32_t 585 drivers/scsi/csiostor/csio_hw.h static inline uint32_t uint32_t 586 drivers/scsi/csiostor/csio_hw.h csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us) uint32_t 630 drivers/scsi/csiostor/csio_hw.h int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int, uint32_t 631 drivers/scsi/csiostor/csio_hw.h int, int, uint32_t *); uint32_t 121 drivers/scsi/csiostor/csio_hw_chip.h int (*chip_set_mem_win)(struct csio_hw *, uint32_t); uint32_t 123 drivers/scsi/csiostor/csio_hw_chip.h uint32_t (*chip_flash_cfg_addr)(struct csio_hw *); uint32_t 124 drivers/scsi/csiostor/csio_hw_chip.h int (*chip_mc_read)(struct csio_hw *, int, uint32_t, uint32_t 126 drivers/scsi/csiostor/csio_hw_chip.h int (*chip_edc_read)(struct csio_hw *, int, uint32_t, uint32_t 129 drivers/scsi/csiostor/csio_hw_chip.h u32, uint32_t *, int); uint32_t 38 drivers/scsi/csiostor/csio_hw_t5.c csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win) uint32_t 146 drivers/scsi/csiostor/csio_hw_t5.c csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, uint32_t 150 drivers/scsi/csiostor/csio_hw_t5.c uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; uint32_t 151 drivers/scsi/csiostor/csio_hw_t5.c uint32_t mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; uint32_t 194 drivers/scsi/csiostor/csio_hw_t5.c csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, uint32_t 198 drivers/scsi/csiostor/csio_hw_t5.c uint32_t edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; uint32_t 199 drivers/scsi/csiostor/csio_hw_t5.c uint32_t edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; uint32_t 256 drivers/scsi/csiostor/csio_hw_t5.c u32 len, uint32_t *buf, int dir) uint32_t 631 drivers/scsi/csiostor/csio_init.c shost->max_id = min_t(uint32_t, csio_fcoe_rnodes, uint32_t 60 drivers/scsi/csiostor/csio_init.h void csio_scsi_intx_handler(struct csio_hw *, void *, uint32_t, uint32_t 63 drivers/scsi/csiostor/csio_init.h void csio_fwevt_intx_handler(struct csio_hw *, void *, uint32_t, uint32_t 131 drivers/scsi/csiostor/csio_isr.c csio_fwevt_intx_handler(struct csio_hw *hw, void *wr, uint32_t len, uint32_t 146 drivers/scsi/csiostor/csio_isr.c csio_process_scsi_cmpl(struct csio_hw *hw, void *wr, uint32_t len, uint32_t 285 drivers/scsi/csiostor/csio_isr.c csio_scsi_intx_handler(struct csio_hw *hw, void *wr, uint32_t len, uint32_t 65 drivers/scsi/csiostor/csio_lnode.c enum fcoe_cmn_type, struct csio_dma_buf *, uint32_t); uint32_t 138 drivers/scsi/csiostor/csio_lnode.c csio_ln_lookup_by_vnpi(struct csio_hw *hw, uint32_t vnp_id) uint32_t 295 drivers/scsi/csiostor/csio_lnode.c uint32_t len = 0; uint32_t 298 drivers/scsi/csiostor/csio_lnode.c uint32_t numattrs = 0; uint32_t 386 drivers/scsi/csiostor/csio_lnode.c len = (uint32_t)(pld - (uint8_t *)cmd); uint32_t 408 drivers/scsi/csiostor/csio_lnode.c uint32_t len = 0; uint32_t 409 drivers/scsi/csiostor/csio_lnode.c uint32_t numattrs = 0; uint32_t 491 drivers/scsi/csiostor/csio_lnode.c len = (uint32_t)(pld - (uint8_t *)cmd); uint32_t 516 drivers/scsi/csiostor/csio_lnode.c uint32_t len; uint32_t 571 drivers/scsi/csiostor/csio_lnode.c uint32_t len; uint32_t 873 drivers/scsi/csiostor/csio_lnode.c csio_handle_link_up(struct csio_hw *hw, uint8_t portid, uint32_t fcfi, uint32_t 874 drivers/scsi/csiostor/csio_lnode.c uint32_t vnpi) uint32_t 1035 drivers/scsi/csiostor/csio_lnode.c csio_handle_link_down(struct csio_hw *hw, uint8_t portid, uint32_t fcfi, uint32_t 1036 drivers/scsi/csiostor/csio_lnode.c uint32_t vnpi) uint32_t 1433 drivers/scsi/csiostor/csio_lnode.c csio_ln_mgmt_wr_handler(struct csio_hw *hw, void *wr, uint32_t len) uint32_t 1493 drivers/scsi/csiostor/csio_lnode.c uint32_t fcfi, rdev_flowid, vnpi; uint32_t 1681 drivers/scsi/csiostor/csio_lnode.c csio_ln_prep_ecwr(struct csio_ioreq *io_req, uint32_t wr_len, uint32_t 1682 drivers/scsi/csiostor/csio_lnode.c uint32_t immd_len, uint8_t sub_op, uint32_t sid, uint32_t 1683 drivers/scsi/csiostor/csio_lnode.c uint32_t did, uint32_t flow_id, uint8_t *fw_wr) uint32_t 1727 drivers/scsi/csiostor/csio_lnode.c uint32_t pld_len) uint32_t 1735 drivers/scsi/csiostor/csio_lnode.c uint32_t wr_size = 0; uint32_t 1737 drivers/scsi/csiostor/csio_lnode.c uint32_t wr_off = 0; uint32_t 1809 drivers/scsi/csiostor/csio_lnode.c uint32_t pld_len) uint32_t 58 drivers/scsi/csiostor/csio_lnode.h CSIO_LNE_NONE = (uint32_t)0, uint32_t 79 drivers/scsi/csiostor/csio_lnode.h uint32_t fka_adv; uint32_t 80 drivers/scsi/csiostor/csio_lnode.h uint32_t fcfi; uint32_t 107 drivers/scsi/csiostor/csio_lnode.h uint32_t n_link_up; /* Link down */ uint32_t 108 drivers/scsi/csiostor/csio_lnode.h uint32_t n_link_down; /* Link up */ uint32_t 109 drivers/scsi/csiostor/csio_lnode.h uint32_t n_err; /* error */ uint32_t 110 drivers/scsi/csiostor/csio_lnode.h uint32_t n_err_nomem; /* memory not available */ uint32_t 111 drivers/scsi/csiostor/csio_lnode.h uint32_t n_inval_parm; /* Invalid parameters */ uint32_t 112 drivers/scsi/csiostor/csio_lnode.h uint32_t n_evt_unexp; /* unexpected event */ uint32_t 113 drivers/scsi/csiostor/csio_lnode.h uint32_t n_evt_drop; /* dropped event */ uint32_t 114 drivers/scsi/csiostor/csio_lnode.h uint32_t n_rnode_match; /* matched rnode */ uint32_t 115 drivers/scsi/csiostor/csio_lnode.h uint32_t n_dev_loss_tmo; /* Device loss timeout */ uint32_t 116 drivers/scsi/csiostor/csio_lnode.h uint32_t n_fdmi_err; /* fdmi err */ uint32_t 117 drivers/scsi/csiostor/csio_lnode.h uint32_t n_evt_fw[PROTO_ERR_IMPL_LOGO + 1]; /* fw events */ uint32_t 119 drivers/scsi/csiostor/csio_lnode.h uint32_t n_rnode_alloc; /* rnode allocated */ uint32_t 120 drivers/scsi/csiostor/csio_lnode.h uint32_t n_rnode_free; /* rnode freed */ uint32_t 121 drivers/scsi/csiostor/csio_lnode.h uint32_t n_rnode_nomem; /* rnode alloc failure */ uint32_t 122 drivers/scsi/csiostor/csio_lnode.h uint32_t n_input_requests; /* Input Requests */ uint32_t 123 drivers/scsi/csiostor/csio_lnode.h uint32_t n_output_requests; /* Output Requests */ uint32_t 124 drivers/scsi/csiostor/csio_lnode.h uint32_t n_control_requests; /* Control Requests */ uint32_t 125 drivers/scsi/csiostor/csio_lnode.h uint32_t n_input_bytes; /* Input Bytes */ uint32_t 126 drivers/scsi/csiostor/csio_lnode.h uint32_t n_output_bytes; /* Output Bytes */ uint32_t 127 drivers/scsi/csiostor/csio_lnode.h uint32_t rsvd1; uint32_t 132 drivers/scsi/csiostor/csio_lnode.h uint32_t ra_tov; uint32_t 133 drivers/scsi/csiostor/csio_lnode.h uint32_t fcfi; uint32_t 134 drivers/scsi/csiostor/csio_lnode.h uint32_t log_level; /* Module level for debugging */ uint32_t 154 drivers/scsi/csiostor/csio_lnode.h uint32_t dev_num; /* Device number */ uint32_t 155 drivers/scsi/csiostor/csio_lnode.h uint32_t flags; /* Flags */ uint32_t 162 drivers/scsi/csiostor/csio_lnode.h uint32_t nport_id; uint32_t 166 drivers/scsi/csiostor/csio_lnode.h uint32_t fcf_flowid; /*fcf flowid */ uint32_t 167 drivers/scsi/csiostor/csio_lnode.h uint32_t vnp_flowid; uint32_t 176 drivers/scsi/csiostor/csio_lnode.h uint32_t num_vports; /* Total NPIV/children LNodes*/ uint32_t 184 drivers/scsi/csiostor/csio_lnode.h uint32_t num_reg_rnodes; /* Number of rnodes registered uint32_t 187 drivers/scsi/csiostor/csio_lnode.h uint32_t n_scsi_tgts; /* Number of scsi targets uint32_t 190 drivers/scsi/csiostor/csio_lnode.h uint32_t last_scan_ntgts;/* Number of scsi targets uint32_t 193 drivers/scsi/csiostor/csio_lnode.h uint32_t tgt_scan_tick; /* timer started after uint32_t 76 drivers/scsi/csiostor/csio_mb.c csio_mb_hello(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, uint32_t 77 drivers/scsi/csiostor/csio_mb.c uint32_t m_mbox, uint32_t a_mbox, enum csio_dev_master master, uint32_t 113 drivers/scsi/csiostor/csio_mb.c uint32_t value; uint32_t 140 drivers/scsi/csiostor/csio_mb.c csio_mb_bye(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, uint32_t 162 drivers/scsi/csiostor/csio_mb.c csio_mb_reset(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, uint32_t 193 drivers/scsi/csiostor/csio_mb.c csio_mb_params(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, uint32_t 198 drivers/scsi/csiostor/csio_mb.c uint32_t i; uint32_t 199 drivers/scsi/csiostor/csio_mb.c uint32_t temp_params = 0, temp_val = 0; uint32_t 245 drivers/scsi/csiostor/csio_mb.c uint32_t i; uint32_t 264 drivers/scsi/csiostor/csio_mb.c csio_mb_ldst(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, int reg) uint32_t 300 drivers/scsi/csiostor/csio_mb.c csio_mb_caps_config(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, uint32_t 342 drivers/scsi/csiostor/csio_mb.c csio_mb_port(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, uint32_t 343 drivers/scsi/csiostor/csio_mb.c u8 portid, bool wr, uint32_t fc, uint16_t fw_caps, uint32_t 413 drivers/scsi/csiostor/csio_mb.c csio_mb_initialize(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, uint32_t 441 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, struct csio_iq_params *iq_params, uint32_t 486 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, bool cascaded_req, uint32_t 492 drivers/scsi/csiostor/csio_mb.c uint32_t iq_start_stop = (iq_params->iq_start) ? uint32_t 572 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, struct csio_iq_params *iq_params, uint32_t 623 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, struct csio_iq_params *iq_params, uint32_t 659 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, struct csio_eq_params *eq_ofld_params, uint32_t 695 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, bool cascaded_req, uint32_t 701 drivers/scsi/csiostor/csio_mb.c uint32_t eq_start_stop = (eq_ofld_params->eqstart) ? uint32_t 756 drivers/scsi/csiostor/csio_mb.c void *priv, uint32_t mb_tmo, uint32_t 809 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, struct csio_eq_params *eq_ofld_params, uint32_t 839 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, uint8_t port_id, uint32_t sub_opcode, uint32_t 840 drivers/scsi/csiostor/csio_mb.c uint8_t cos, bool link_status, uint32_t fcfi, uint32_t 874 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, uint32_t 908 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, uint32_t fcfi, uint32_t vnpi, uint16_t iqid, uint32_t 950 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, uint32_t fcfi, uint32_t vnpi, uint32_t 979 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, uint32_t fcfi, uint32_t vnpi, uint32_t 1010 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, uint32_t portid, uint32_t fcfi, uint32_t 1028 drivers/scsi/csiostor/csio_mb.c uint32_t mb_tmo, uint32_t 1162 drivers/scsi/csiostor/csio_mb.c uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); uint32_t 1163 drivers/scsi/csiostor/csio_mb.c uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A); uint32_t 1190 drivers/scsi/csiostor/csio_mb.c uint32_t owner, ctl; uint32_t 1192 drivers/scsi/csiostor/csio_mb.c uint32_t ii; uint32_t 1196 drivers/scsi/csiostor/csio_mb.c uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); uint32_t 1197 drivers/scsi/csiostor/csio_mb.c uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A); uint32_t 1410 drivers/scsi/csiostor/csio_mb.c uint32_t link_status; uint32_t 1477 drivers/scsi/csiostor/csio_mb.c uint32_t ctl, cim_cause, pl_cause; uint32_t 1479 drivers/scsi/csiostor/csio_mb.c uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); uint32_t 1480 drivers/scsi/csiostor/csio_mb.c uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A); uint32_t 104 drivers/scsi/csiostor/csio_mb.h uint32_t n_req; /* number of mbox req */ uint32_t 105 drivers/scsi/csiostor/csio_mb.h uint32_t n_rsp; /* number of mbox rsp */ uint32_t 106 drivers/scsi/csiostor/csio_mb.h uint32_t n_activeq; /* number of mbox req active Q */ uint32_t 107 drivers/scsi/csiostor/csio_mb.h uint32_t n_cbfnq; /* number of mbox req cbfn Q */ uint32_t 108 drivers/scsi/csiostor/csio_mb.h uint32_t n_tmo; /* number of mbox timeout */ uint32_t 109 drivers/scsi/csiostor/csio_mb.h uint32_t n_cancel; /* number of mbox cancel */ uint32_t 110 drivers/scsi/csiostor/csio_mb.h uint32_t n_err; /* number of mbox error */ uint32_t 121 drivers/scsi/csiostor/csio_mb.h uint32_t tmo; /* Timeout */ uint32_t 131 drivers/scsi/csiostor/csio_mb.h uint32_t a_mbox; /* Async mbox num */ uint32_t 132 drivers/scsi/csiostor/csio_mb.h uint32_t intr_idx; /* Interrupt index */ uint32_t 138 drivers/scsi/csiostor/csio_mb.h uint32_t req_q_cnt; /* Outstanding mbox uint32_t 153 drivers/scsi/csiostor/csio_mb.h void csio_mb_hello(struct csio_hw *, struct csio_mb *, uint32_t, uint32_t 154 drivers/scsi/csiostor/csio_mb.h uint32_t, uint32_t, enum csio_dev_master, uint32_t 161 drivers/scsi/csiostor/csio_mb.h void csio_mb_bye(struct csio_hw *, struct csio_mb *, uint32_t, uint32_t 164 drivers/scsi/csiostor/csio_mb.h void csio_mb_reset(struct csio_hw *, struct csio_mb *, uint32_t, int, int, uint32_t 167 drivers/scsi/csiostor/csio_mb.h void csio_mb_params(struct csio_hw *, struct csio_mb *, uint32_t, unsigned int, uint32_t 174 drivers/scsi/csiostor/csio_mb.h void csio_mb_ldst(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, uint32_t 177 drivers/scsi/csiostor/csio_mb.h void csio_mb_caps_config(struct csio_hw *, struct csio_mb *, uint32_t, uint32_t 181 drivers/scsi/csiostor/csio_mb.h void csio_mb_port(struct csio_hw *, struct csio_mb *, uint32_t, uint32_t 182 drivers/scsi/csiostor/csio_mb.h uint8_t, bool, uint32_t, uint16_t, uint32_t 187 drivers/scsi/csiostor/csio_mb.h uint32_t *, uint32_t *); uint32_t 189 drivers/scsi/csiostor/csio_mb.h void csio_mb_initialize(struct csio_hw *, struct csio_mb *, uint32_t, uint32_t 193 drivers/scsi/csiostor/csio_mb.h uint32_t, struct csio_iq_params *, uint32_t 200 drivers/scsi/csiostor/csio_mb.h uint32_t, struct csio_iq_params *, uint32_t 204 drivers/scsi/csiostor/csio_mb.h uint32_t, struct csio_eq_params *, uint32_t 211 drivers/scsi/csiostor/csio_mb.h uint32_t , struct csio_eq_params *, uint32_t 215 drivers/scsi/csiostor/csio_mb.h uint32_t, uint32_t 219 drivers/scsi/csiostor/csio_mb.h uint32_t, uint8_t, uint32_t, uint8_t, bool, uint32_t, uint32_t 223 drivers/scsi/csiostor/csio_mb.h uint32_t, uint32_t , uint32_t , uint16_t, uint32_t 228 drivers/scsi/csiostor/csio_mb.h uint32_t, uint32_t , uint32_t , uint32_t 232 drivers/scsi/csiostor/csio_mb.h uint32_t , uint32_t, uint32_t , uint32_t 236 drivers/scsi/csiostor/csio_mb.h uint32_t, uint32_t, uint32_t, uint32_t 240 drivers/scsi/csiostor/csio_mb.h struct csio_mb *mbp, uint32_t mb_tmo, uint32_t 121 drivers/scsi/csiostor/csio_rnode.c csio_rn_lookup(struct csio_lnode *ln, uint32_t flowid) uint32_t 169 drivers/scsi/csiostor/csio_rnode.c csio_rnode_lookup_portid(struct csio_lnode *ln, uint32_t portid) uint32_t 185 drivers/scsi/csiostor/csio_rnode.c csio_rn_dup_flowid(struct csio_lnode *ln, uint32_t rdev_flowid, uint32_t 186 drivers/scsi/csiostor/csio_rnode.c uint32_t *vnp_flowid) uint32_t 258 drivers/scsi/csiostor/csio_rnode.c csio_get_rnode(struct csio_lnode *ln, uint32_t flowid) uint32_t 300 drivers/scsi/csiostor/csio_rnode.c csio_confirm_rnode(struct csio_lnode *ln, uint32_t rdev_flowid, uint32_t 305 drivers/scsi/csiostor/csio_rnode.c uint32_t vnp_flowid = 0; uint32_t 42 drivers/scsi/csiostor/csio_rnode.h CSIO_RNFE_NONE = (uint32_t)0, /* None */ uint32_t 61 drivers/scsi/csiostor/csio_rnode.h uint32_t n_err; /* error */ uint32_t 62 drivers/scsi/csiostor/csio_rnode.h uint32_t n_err_inval; /* invalid parameter */ uint32_t 63 drivers/scsi/csiostor/csio_rnode.h uint32_t n_err_nomem; /* error nomem */ uint32_t 64 drivers/scsi/csiostor/csio_rnode.h uint32_t n_evt_unexp; /* unexpected event */ uint32_t 65 drivers/scsi/csiostor/csio_rnode.h uint32_t n_evt_drop; /* unexpected event */ uint32_t 66 drivers/scsi/csiostor/csio_rnode.h uint32_t n_evt_fw[PROTO_ERR_IMPL_LOGO + 1]; /* fw events */ uint32_t 68 drivers/scsi/csiostor/csio_rnode.h uint32_t n_lun_rst; /* Number of resets of uint32_t 72 drivers/scsi/csiostor/csio_rnode.h uint32_t n_lun_rst_fail; /* Number of LUN reset uint32_t 75 drivers/scsi/csiostor/csio_rnode.h uint32_t n_tgt_rst; /* Number of target resets */ uint32_t 76 drivers/scsi/csiostor/csio_rnode.h uint32_t n_tgt_rst_fail; /* Number of target reset uint32_t 95 drivers/scsi/csiostor/csio_rnode.h uint32_t flowid; /* Firmware ID */ uint32_t 101 drivers/scsi/csiostor/csio_rnode.h uint32_t nport_id; uint32_t 105 drivers/scsi/csiostor/csio_rnode.h uint32_t role; /* Fabric/Target/ uint32_t 113 drivers/scsi/csiostor/csio_rnode.h uint32_t supp_classes; /* Supported FC classes */ uint32_t 114 drivers/scsi/csiostor/csio_rnode.h uint32_t maxframe_size; /* Max Frame size */ uint32_t 115 drivers/scsi/csiostor/csio_rnode.h uint32_t scsi_id; /* Transport given SCSI id */ uint32_t 128 drivers/scsi/csiostor/csio_rnode.h struct csio_rnode *csio_rnode_lookup_portid(struct csio_lnode *, uint32_t); uint32_t 130 drivers/scsi/csiostor/csio_rnode.h uint32_t, struct fcoe_rdev_entry *); uint32_t 59 drivers/scsi/csiostor/csio_scsi.c uint32_t csio_max_scan_tmo; uint32_t 60 drivers/scsi/csiostor/csio_scsi.c uint32_t csio_delta_scan_tmo = 5; uint32_t 201 drivers/scsi/csiostor/csio_scsi.c csio_scsi_init_cmd_wr(struct csio_ioreq *req, void *addr, uint32_t size) uint32_t 260 drivers/scsi/csiostor/csio_scsi.c uint32_t size = CSIO_SCSI_CMD_WR_SZ_16(scsim->proto_cmd_len); uint32_t 295 drivers/scsi/csiostor/csio_scsi.c uint32_t i = 0; uint32_t 296 drivers/scsi/csiostor/csio_scsi.c uint32_t xfer_len; uint32_t 360 drivers/scsi/csiostor/csio_scsi.c csio_scsi_init_read_wr(struct csio_ioreq *req, void *wrp, uint32_t size) uint32_t 413 drivers/scsi/csiostor/csio_scsi.c csio_scsi_init_write_wr(struct csio_ioreq *req, void *wrp, uint32_t size) uint32_t 482 drivers/scsi/csiostor/csio_scsi.c uint32_t size; uint32_t 519 drivers/scsi/csiostor/csio_scsi.c uint32_t size; uint32_t 561 drivers/scsi/csiostor/csio_scsi.c uint32_t ddp_pagesz = 4096; uint32_t 562 drivers/scsi/csiostor/csio_scsi.c uint32_t buf_off; uint32_t 564 drivers/scsi/csiostor/csio_scsi.c uint32_t alloc_len = 0; uint32_t 565 drivers/scsi/csiostor/csio_scsi.c uint32_t xfer_len = 0; uint32_t 566 drivers/scsi/csiostor/csio_scsi.c uint32_t sg_len = 0; uint32_t 567 drivers/scsi/csiostor/csio_scsi.c uint32_t i; uint32_t 646 drivers/scsi/csiostor/csio_scsi.c csio_scsi_init_abrt_cls_wr(struct csio_ioreq *req, void *addr, uint32_t size, uint32_t 678 drivers/scsi/csiostor/csio_scsi.c uint32_t size = ALIGN(sizeof(struct fw_scsi_abrt_cls_wr), 16); uint32_t 1102 drivers/scsi/csiostor/csio_scsi.c csio_scsi_cmpl_handler(struct csio_hw *hw, void *wr, uint32_t len, uint32_t 1233 drivers/scsi/csiostor/csio_scsi.c csio_scsi_abort_io_q(struct csio_scsim *scm, struct list_head *q, uint32_t tmo) uint32_t 1443 drivers/scsi/csiostor/csio_scsi.c uint32_t dbg_level = 0; uint32_t 1488 drivers/scsi/csiostor/csio_scsi.c static inline uint32_t uint32_t 1493 drivers/scsi/csiostor/csio_scsi.c uint32_t bytes_left; uint32_t 1494 drivers/scsi/csiostor/csio_scsi.c uint32_t bytes_copy; uint32_t 1495 drivers/scsi/csiostor/csio_scsi.c uint32_t buf_off = 0; uint32_t 1496 drivers/scsi/csiostor/csio_scsi.c uint32_t start_off = 0; uint32_t 1497 drivers/scsi/csiostor/csio_scsi.c uint32_t sg_off = 0; uint32_t 1525 drivers/scsi/csiostor/csio_scsi.c bytes_copy = min((uint32_t)(PAGE_SIZE - (sg_off & ~PAGE_MASK)), uint32_t 1566 drivers/scsi/csiostor/csio_scsi.c uint32_t host_status = DID_OK; uint32_t 1567 drivers/scsi/csiostor/csio_scsi.c uint32_t rsp_len = 0, sns_len = 0; uint32_t 1741 drivers/scsi/csiostor/csio_scsi.c uint32_t host_status = DID_OK; uint32_t 2321 drivers/scsi/csiostor/csio_scsi.c uint32_t unit_size = 0; uint32_t 57 drivers/scsi/csiostor/csio_scsi.h extern uint32_t csio_max_scan_tmo; uint32_t 58 drivers/scsi/csiostor/csio_scsi.h extern uint32_t csio_delta_scan_tmo; uint32_t 96 drivers/scsi/csiostor/csio_scsi.h uint32_t n_rn_nr_error; /* No. of remote-node-not- uint32_t 99 drivers/scsi/csiostor/csio_scsi.h uint32_t n_hw_nr_error; /* No. of hw-module-not- uint32_t 102 drivers/scsi/csiostor/csio_scsi.h uint32_t n_dmamap_error; /* No. of DMA map erros */ uint32_t 103 drivers/scsi/csiostor/csio_scsi.h uint32_t n_unsupp_sge_error; /* No. of too-many-SGes uint32_t 106 drivers/scsi/csiostor/csio_scsi.h uint32_t n_no_req_error; /* No. of Out-of-ioreqs error */ uint32_t 107 drivers/scsi/csiostor/csio_scsi.h uint32_t n_busy_error; /* No. of -EBUSY errors */ uint32_t 108 drivers/scsi/csiostor/csio_scsi.h uint32_t n_hosterror; /* No. of FW_HOSTERROR I/O */ uint32_t 109 drivers/scsi/csiostor/csio_scsi.h uint32_t n_rsperror; /* No. of response errors */ uint32_t 110 drivers/scsi/csiostor/csio_scsi.h uint32_t n_autosense; /* No. of auto sense replies */ uint32_t 111 drivers/scsi/csiostor/csio_scsi.h uint32_t n_ovflerror; /* No. of overflow errors */ uint32_t 112 drivers/scsi/csiostor/csio_scsi.h uint32_t n_unflerror; /* No. of underflow errors */ uint32_t 113 drivers/scsi/csiostor/csio_scsi.h uint32_t n_rdev_nr_error;/* No. of rdev not uint32_t 116 drivers/scsi/csiostor/csio_scsi.h uint32_t n_rdev_lost_error;/* No. of rdev lost errors */ uint32_t 117 drivers/scsi/csiostor/csio_scsi.h uint32_t n_rdev_logo_error;/* No. of rdev logo errors */ uint32_t 118 drivers/scsi/csiostor/csio_scsi.h uint32_t n_link_down_error;/* No. of link down errors */ uint32_t 119 drivers/scsi/csiostor/csio_scsi.h uint32_t n_no_xchg_error; /* No. no exchange error */ uint32_t 120 drivers/scsi/csiostor/csio_scsi.h uint32_t n_unknown_error;/* No. of unhandled errors */ uint32_t 121 drivers/scsi/csiostor/csio_scsi.h uint32_t n_aborted; /* No. of aborted I/Os */ uint32_t 122 drivers/scsi/csiostor/csio_scsi.h uint32_t n_abrt_timedout; /* No. of abort timedouts */ uint32_t 123 drivers/scsi/csiostor/csio_scsi.h uint32_t n_abrt_fail; /* No. of abort failures */ uint32_t 124 drivers/scsi/csiostor/csio_scsi.h uint32_t n_abrt_dups; /* No. of duplicate aborts */ uint32_t 125 drivers/scsi/csiostor/csio_scsi.h uint32_t n_abrt_race_comp; /* No. of aborts that raced uint32_t 128 drivers/scsi/csiostor/csio_scsi.h uint32_t n_abrt_busy_error;/* No. of abort failures uint32_t 131 drivers/scsi/csiostor/csio_scsi.h uint32_t n_closed; /* No. of closed I/Os */ uint32_t 132 drivers/scsi/csiostor/csio_scsi.h uint32_t n_cls_busy_error; /* No. of close failures uint32_t 135 drivers/scsi/csiostor/csio_scsi.h uint32_t n_active; /* No. of IOs in active_q */ uint32_t 136 drivers/scsi/csiostor/csio_scsi.h uint32_t n_tm_active; /* No. of TMs in active_q */ uint32_t 137 drivers/scsi/csiostor/csio_scsi.h uint32_t n_wcbfn; /* No. of I/Os in worker uint32_t 140 drivers/scsi/csiostor/csio_scsi.h uint32_t n_free_ioreq; /* No. of freelist entries */ uint32_t 141 drivers/scsi/csiostor/csio_scsi.h uint32_t n_free_ddp; /* No. of DDP freelist */ uint32_t 142 drivers/scsi/csiostor/csio_scsi.h uint32_t n_unaligned; /* No. of Unaligned SGls */ uint32_t 143 drivers/scsi/csiostor/csio_scsi.h uint32_t n_inval_cplop; /* No. invalid CPL op's in IQ */ uint32_t 144 drivers/scsi/csiostor/csio_scsi.h uint32_t n_inval_scsiop; /* No. invalid scsi op's in IQ*/ uint32_t 335 drivers/scsi/csiostor/csio_scsi.h struct csio_ioreq *csio_scsi_cmpl_handler(struct csio_hw *, void *, uint32_t, uint32_t 58 drivers/scsi/csiostor/csio_wr.c csio_get_flbuf_size(struct csio_hw *hw, struct csio_sge *sge, uint32_t reg) uint32_t 61 drivers/scsi/csiostor/csio_wr.c reg * sizeof(uint32_t)); uint32_t 65 drivers/scsi/csiostor/csio_wr.c static inline uint32_t uint32_t 72 drivers/scsi/csiostor/csio_wr.c static inline uint32_t uint32_t 186 drivers/scsi/csiostor/csio_wr.c csio_wr_alloc_q(struct csio_hw *hw, uint32_t qsize, uint32_t wrsize, uint32_t 187 drivers/scsi/csiostor/csio_wr.c uint16_t type, void *owner, uint32_t nflb, int sreg, uint32_t 194 drivers/scsi/csiostor/csio_wr.c uint32_t qsz; uint32_t 342 drivers/scsi/csiostor/csio_wr.c uint32_t iq_id; uint32_t 417 drivers/scsi/csiostor/csio_wr.c uint32_t vec, uint8_t portid, bool async, uint32_t 768 drivers/scsi/csiostor/csio_wr.c uint32_t i = 0; uint32_t 862 drivers/scsi/csiostor/csio_wr.c csio_wr_get(struct csio_hw *hw, int qidx, uint32_t size, uint32_t 872 drivers/scsi/csiostor/csio_wr.c uint32_t req_sz = ALIGN(size, CSIO_QCREDIT_SZ); uint32_t 910 drivers/scsi/csiostor/csio_wr.c wrp->size1 = (uint32_t)((uintptr_t)q->vwrap - (uintptr_t)cwr); uint32_t 951 drivers/scsi/csiostor/csio_wr.c uint32_t wr_off, uint32_t data_len) uint32_t 953 drivers/scsi/csiostor/csio_wr.c uint32_t nbytes; uint32_t 998 drivers/scsi/csiostor/csio_wr.c static inline uint32_t uint32_t 1042 drivers/scsi/csiostor/csio_wr.c void *wr, uint32_t len_to_qid, uint32_t 1044 drivers/scsi/csiostor/csio_wr.c uint32_t, struct csio_fl_dma_buf *, uint32_t 1052 drivers/scsi/csiostor/csio_wr.c uint32_t bufsz, len, lastlen = 0; uint32_t 1130 drivers/scsi/csiostor/csio_wr.c uint32_t, struct csio_fl_dma_buf *, uint32_t 1137 drivers/scsi/csiostor/csio_wr.c uint32_t wr_type, fw_qid, qid; uint32_t 1237 drivers/scsi/csiostor/csio_wr.c uint32_t avail = csio_wr_avail_qcredits(flq); uint32_t 1264 drivers/scsi/csiostor/csio_wr.c uint32_t, struct csio_fl_dma_buf *, uint32_t 1313 drivers/scsi/csiostor/csio_wr.c uint32_t clsz = L1_CACHE_BYTES; uint32_t 1314 drivers/scsi/csiostor/csio_wr.c uint32_t s_hps = PAGE_SHIFT - 10; uint32_t 1315 drivers/scsi/csiostor/csio_wr.c uint32_t stat_len = clsz > 64 ? 128 : 64; uint32_t 1458 drivers/scsi/csiostor/csio_wr.c uint32_t ingpad; uint32_t 1689 drivers/scsi/csiostor/csio_wr.c uint32_t j; uint32_t 158 drivers/scsi/csiostor/csio_wr.h uint32_t reserved6; uint32_t 209 drivers/scsi/csiostor/csio_wr.h uint32_t eqid; uint32_t 235 drivers/scsi/csiostor/csio_wr.h uint32_t len; /* Buffer size */ uint32_t 245 drivers/scsi/csiostor/csio_wr.h uint32_t nsge; /* Number of SG elements */ uint32_t 246 drivers/scsi/csiostor/csio_wr.h uint32_t tmo; /* Driver timeout */ uint32_t 247 drivers/scsi/csiostor/csio_wr.h uint32_t datadir; /* Data direction */ uint32_t 328 drivers/scsi/csiostor/csio_wr.h uint32_t size1; uint32_t 330 drivers/scsi/csiostor/csio_wr.h uint32_t size2; uint32_t 343 drivers/scsi/csiostor/csio_wr.h uint32_t totlen; /* Total length */ uint32_t 350 drivers/scsi/csiostor/csio_wr.h typedef void (*iq_handler_t)(struct csio_hw *, void *, uint32_t, uint32_t 380 drivers/scsi/csiostor/csio_wr.h uint32_t n_tot_reqs; /* Total no. of Requests */ uint32_t 381 drivers/scsi/csiostor/csio_wr.h uint32_t n_tot_rsps; /* Total no. of responses */ uint32_t 382 drivers/scsi/csiostor/csio_wr.h uint32_t n_qwrap; /* Queue wraps */ uint32_t 383 drivers/scsi/csiostor/csio_wr.h uint32_t n_eq_wr_split; /* Number of split EQ WRs */ uint32_t 384 drivers/scsi/csiostor/csio_wr.h uint32_t n_qentry; /* Queue entry */ uint32_t 385 drivers/scsi/csiostor/csio_wr.h uint32_t n_qempty; /* Queue empty */ uint32_t 386 drivers/scsi/csiostor/csio_wr.h uint32_t n_qfull; /* Queue fulls */ uint32_t 387 drivers/scsi/csiostor/csio_wr.h uint32_t n_rsp_unknown; /* Unknown response type */ uint32_t 388 drivers/scsi/csiostor/csio_wr.h uint32_t n_stray_comp; /* Stray completion intr */ uint32_t 389 drivers/scsi/csiostor/csio_wr.h uint32_t n_flq_refill; /* Number of FL refills */ uint32_t 398 drivers/scsi/csiostor/csio_wr.h uint32_t wr_sz; /* Size of all WRs in this q uint32_t 407 drivers/scsi/csiostor/csio_wr.h uint32_t credits; /* Size of queue in credits */ uint32_t 418 drivers/scsi/csiostor/csio_wr.h uint32_t portid; /* PCIE Channel */ uint32_t 419 drivers/scsi/csiostor/csio_wr.h uint32_t size; /* Size of queue in bytes */ uint32_t 424 drivers/scsi/csiostor/csio_wr.h uint32_t csio_fl_align; /* Calculated and cached uint32_t 427 drivers/scsi/csiostor/csio_wr.h uint32_t sge_control; /* padding, boundaries, uint32_t 430 drivers/scsi/csiostor/csio_wr.h uint32_t sge_host_page_size; /* Host page size */ uint32_t 431 drivers/scsi/csiostor/csio_wr.h uint32_t sge_fl_buf_size[CSIO_SGE_FL_SIZE_REGS]; uint32_t 444 drivers/scsi/csiostor/csio_wr.h uint32_t fw_iq_start; /* Start ID of IQ for this fn*/ uint32_t 445 drivers/scsi/csiostor/csio_wr.h uint32_t fw_eq_start; /* Start ID of EQ for this fn*/ uint32_t 483 drivers/scsi/csiostor/csio_wr.h int csio_wr_alloc_q(struct csio_hw *, uint32_t, uint32_t, uint32_t 484 drivers/scsi/csiostor/csio_wr.h uint16_t, void *, uint32_t, int, iq_handler_t); uint32_t 486 drivers/scsi/csiostor/csio_wr.h uint32_t, uint8_t, bool, uint32_t 493 drivers/scsi/csiostor/csio_wr.h int csio_wr_get(struct csio_hw *, int, uint32_t, uint32_t 495 drivers/scsi/csiostor/csio_wr.h void csio_wr_copy_to_wrp(void *, struct csio_wr_pair *, uint32_t, uint32_t); uint32_t 499 drivers/scsi/csiostor/csio_wr.h uint32_t, struct csio_fl_dma_buf *, uint32_t 504 drivers/scsi/csiostor/csio_wr.h uint32_t, struct csio_fl_dma_buf *, uint32_t 267 drivers/scsi/ips.c static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t); uint32_t 268 drivers/scsi/ips.c static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t); uint32_t 270 drivers/scsi/ips.c static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); uint32_t 271 drivers/scsi/ips.c static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); uint32_t 297 drivers/scsi/ips.c static uint32_t ips_statupd_copperhead(ips_ha_t *); uint32_t 298 drivers/scsi/ips.c static uint32_t ips_statupd_copperhead_memio(ips_ha_t *); uint32_t 299 drivers/scsi/ips.c static uint32_t ips_statupd_morpheus(ips_ha_t *); uint32_t 354 drivers/scsi/ips.c static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */ uint32_t 1827 drivers/scsi/ips.c uint32_t cmd_busaddr; uint32_t 1900 drivers/scsi/ips.c uint32_t cmd_busaddr; uint32_t 3248 drivers/scsi/ips.c uint32_t transfer_len; uint32_t 3301 drivers/scsi/ips.c (uint32_t) scb->dcdb.transfer_length; uint32_t 4071 drivers/scsi/ips.c cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE); uint32_t 4092 drivers/scsi/ips.c uint32_t cylinders; uint32_t 4367 drivers/scsi/ips.c uint32_t cmd_busaddr, sg_busaddr; uint32_t 4392 drivers/scsi/ips.c scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE); uint32_t 4522 drivers/scsi/ips.c uint32_t post; uint32_t 4523 drivers/scsi/ips.c uint32_t bits; uint32_t 4675 drivers/scsi/ips.c uint32_t Oimr; uint32_t 4886 drivers/scsi/ips.c uint32_t Post; uint32_t 4887 drivers/scsi/ips.c uint32_t Config; uint32_t 4888 drivers/scsi/ips.c uint32_t Isr; uint32_t 4889 drivers/scsi/ips.c uint32_t Oimr; uint32_t 4920 drivers/scsi/ips.c Isr = (uint32_t) IPS_BIT_I960_MSG0I; uint32_t 4940 drivers/scsi/ips.c Isr = (uint32_t) IPS_BIT_I960_MSG0I; uint32_t 4972 drivers/scsi/ips.c Isr = (uint32_t) IPS_BIT_I960_MSG1I; uint32_t 5137 drivers/scsi/ips.c uint32_t phys_status_start; uint32_t 5168 drivers/scsi/ips.c uint32_t phys_status_start; uint32_t 5195 drivers/scsi/ips.c static uint32_t uint32_t 5223 drivers/scsi/ips.c static uint32_t uint32_t 5250 drivers/scsi/ips.c static uint32_t uint32_t 5253 drivers/scsi/ips.c uint32_t val; uint32_t 5274 drivers/scsi/ips.c uint32_t TimeOut; uint32_t 5275 drivers/scsi/ips.c uint32_t val; uint32_t 5328 drivers/scsi/ips.c uint32_t TimeOut; uint32_t 5329 drivers/scsi/ips.c uint32_t val; uint32_t 5511 drivers/scsi/ips.c uint32_t Isr; uint32_t 6237 drivers/scsi/ips.c ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, uint32_t 6238 drivers/scsi/ips.c uint32_t offset) uint32_t 6328 drivers/scsi/ips.c ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, uint32_t 6329 drivers/scsi/ips.c uint32_t offset) uint32_t 6419 drivers/scsi/ips.c ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, uint32_t 6420 drivers/scsi/ips.c uint32_t offset) uint32_t 6468 drivers/scsi/ips.c ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, uint32_t 6469 drivers/scsi/ips.c uint32_t offset) uint32_t 6834 drivers/scsi/ips.c uint32_t io_addr; uint32_t 6835 drivers/scsi/ips.c uint32_t mem_addr; uint32_t 6836 drivers/scsi/ips.c uint32_t io_len; uint32_t 6837 drivers/scsi/ips.c uint32_t mem_len; uint32_t 6845 drivers/scsi/ips.c uint32_t IsDead; uint32_t 6884 drivers/scsi/ips.c uint32_t base; uint32_t 6885 drivers/scsi/ips.c uint32_t offs; uint32_t 6917 drivers/scsi/ips.c ha->host_num = (uint32_t) index; uint32_t 413 drivers/scsi/ips.h uint32_t lba; uint32_t 414 drivers/scsi/ips.h uint32_t sg_addr; uint32_t 418 drivers/scsi/ips.h uint32_t ccsar; uint32_t 419 drivers/scsi/ips.h uint32_t cccr; uint32_t 426 drivers/scsi/ips.h uint32_t reserved2; uint32_t 427 drivers/scsi/ips.h uint32_t buffer_addr; uint32_t 428 drivers/scsi/ips.h uint32_t reserved3; uint32_t 429 drivers/scsi/ips.h uint32_t ccsar; uint32_t 430 drivers/scsi/ips.h uint32_t cccr; uint32_t 438 drivers/scsi/ips.h uint32_t reserved3; uint32_t 439 drivers/scsi/ips.h uint32_t buffer_addr; uint32_t 440 drivers/scsi/ips.h uint32_t reserved4; uint32_t 466 drivers/scsi/ips.h uint32_t reserved2; uint32_t 467 drivers/scsi/ips.h uint32_t dcdb_address; uint32_t 471 drivers/scsi/ips.h uint32_t ccsar; uint32_t 472 drivers/scsi/ips.h uint32_t cccr; uint32_t 480 drivers/scsi/ips.h uint32_t reserved; uint32_t 481 drivers/scsi/ips.h uint32_t reserved2; uint32_t 482 drivers/scsi/ips.h uint32_t reserved3; uint32_t 483 drivers/scsi/ips.h uint32_t ccsar; uint32_t 484 drivers/scsi/ips.h uint32_t cccr; uint32_t 492 drivers/scsi/ips.h uint32_t reserved; uint32_t 493 drivers/scsi/ips.h uint32_t reserved2; uint32_t 494 drivers/scsi/ips.h uint32_t reserved3; uint32_t 495 drivers/scsi/ips.h uint32_t ccsar; uint32_t 496 drivers/scsi/ips.h uint32_t cccr; uint32_t 504 drivers/scsi/ips.h uint32_t reserved2; uint32_t 505 drivers/scsi/ips.h uint32_t reserved3; uint32_t 506 drivers/scsi/ips.h uint32_t reserved4; uint32_t 507 drivers/scsi/ips.h uint32_t ccsar; uint32_t 508 drivers/scsi/ips.h uint32_t cccr; uint32_t 516 drivers/scsi/ips.h uint32_t reserved2; uint32_t 517 drivers/scsi/ips.h uint32_t buffer_addr; uint32_t 518 drivers/scsi/ips.h uint32_t reserved3; uint32_t 519 drivers/scsi/ips.h uint32_t ccsar; uint32_t 520 drivers/scsi/ips.h uint32_t cccr; uint32_t 528 drivers/scsi/ips.h uint32_t reserved; uint32_t 529 drivers/scsi/ips.h uint32_t buffer_addr; uint32_t 530 drivers/scsi/ips.h uint32_t reserved2; uint32_t 531 drivers/scsi/ips.h uint32_t ccsar; uint32_t 532 drivers/scsi/ips.h uint32_t cccr; uint32_t 540 drivers/scsi/ips.h uint32_t count; uint32_t 541 drivers/scsi/ips.h uint32_t buffer_addr; uint32_t 542 drivers/scsi/ips.h uint32_t reserved2; uint32_t 566 drivers/scsi/ips.h uint32_t count; uint32_t 567 drivers/scsi/ips.h uint32_t buffer_addr; uint32_t 578 drivers/scsi/ips.h uint32_t count; uint32_t 579 drivers/scsi/ips.h uint32_t buffer_addr; uint32_t 580 drivers/scsi/ips.h uint32_t offset; uint32_t 605 drivers/scsi/ips.h uint32_t sector_count; uint32_t 618 drivers/scsi/ips.h uint32_t buffer_pointer; uint32_t 634 drivers/scsi/ips.h uint32_t transfer_length; uint32_t 635 drivers/scsi/ips.h uint32_t buffer_pointer; uint32_t 639 drivers/scsi/ips.h uint32_t reserved; uint32_t 652 drivers/scsi/ips.h volatile uint32_t value; uint32_t 660 drivers/scsi/ips.h volatile uint32_t hw_status_start; uint32_t 661 drivers/scsi/ips.h volatile uint32_t hw_status_tail; uint32_t 675 drivers/scsi/ips.h uint32_t ulDriveSize[IPS_MAX_LD]; uint32_t 694 drivers/scsi/ips.h uint32_t ulBlockCount; uint32_t 702 drivers/scsi/ips.h uint32_t ulStartSect; uint32_t 703 drivers/scsi/ips.h uint32_t ulNoOfSects; uint32_t 714 drivers/scsi/ips.h uint32_t ulLogDrvSize; uint32_t 725 drivers/scsi/ips.h uint32_t ulNvramSize; uint32_t 736 drivers/scsi/ips.h uint32_t UserOpt; uint32_t 747 drivers/scsi/ips.h uint32_t signature; uint32_t 775 drivers/scsi/ips.h uint32_t revision; uint32_t 787 drivers/scsi/ips.h uint32_t param[128]; uint32_t 815 drivers/scsi/ips.h uint32_t lba; uint32_t 816 drivers/scsi/ips.h uint32_t len; uint32_t 895 drivers/scsi/ips.h uint32_t NumberOfBlocks; uint32_t 926 drivers/scsi/ips.h uint32_t address; uint32_t 927 drivers/scsi/ips.h uint32_t length; uint32_t 931 drivers/scsi/ips.h uint32_t address_lo; uint32_t 932 drivers/scsi/ips.h uint32_t address_hi; uint32_t 933 drivers/scsi/ips.h uint32_t length; uint32_t 934 drivers/scsi/ips.h uint32_t reserved; uint32_t 953 drivers/scsi/ips.h uint32_t residue_len; uint32_t 997 drivers/scsi/ips.h int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t); uint32_t 998 drivers/scsi/ips.h int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t); uint32_t 1002 drivers/scsi/ips.h uint32_t (*statupd)(struct ips_ha *); uint32_t 1007 drivers/scsi/ips.h uint32_t dcdb_active[IPS_MAX_CHANNELS]; uint32_t 1008 drivers/scsi/ips.h uint32_t io_addr; /* Base I/O address */ uint32_t 1014 drivers/scsi/ips.h uint32_t max_xfer; /* Maximum Xfer size */ uint32_t 1015 drivers/scsi/ips.h uint32_t max_cmds; /* Max concurrent commands */ uint32_t 1016 drivers/scsi/ips.h uint32_t num_ioctl; /* Number of Ioctls */ uint32_t 1032 drivers/scsi/ips.h uint32_t ioctl_datasize; /* IOCTL data size */ uint32_t 1033 drivers/scsi/ips.h uint32_t cmd_in_progress; /* Current command in progress*/ uint32_t 1044 drivers/scsi/ips.h uint32_t mem_addr; /* Memory mapped address */ uint32_t 1045 drivers/scsi/ips.h uint32_t io_len; /* Size of IO Address */ uint32_t 1046 drivers/scsi/ips.h uint32_t mem_len; /* Size of memory address */ uint32_t 1071 drivers/scsi/ips.h uint32_t scb_busaddr; uint32_t 1072 drivers/scsi/ips.h uint32_t old_data_busaddr; // Obsolete, but kept for old utility compatibility uint32_t 1073 drivers/scsi/ips.h uint32_t timeout; uint32_t 1078 drivers/scsi/ips.h uint32_t data_len; uint32_t 1079 drivers/scsi/ips.h uint32_t sg_len; uint32_t 1080 drivers/scsi/ips.h uint32_t flags; uint32_t 1081 drivers/scsi/ips.h uint32_t op_code; uint32_t 1086 drivers/scsi/ips.h uint32_t sg_busaddr; uint32_t 1098 drivers/scsi/ips.h uint32_t scb_busaddr; uint32_t 1099 drivers/scsi/ips.h uint32_t data_busaddr; uint32_t 1100 drivers/scsi/ips.h uint32_t timeout; uint32_t 1104 drivers/scsi/ips.h uint32_t data_len; uint32_t 1105 drivers/scsi/ips.h uint32_t sg_len; uint32_t 1106 drivers/scsi/ips.h uint32_t flags; uint32_t 1107 drivers/scsi/ips.h uint32_t op_code; uint32_t 1119 drivers/scsi/ips.h uint32_t CoppCmd; uint32_t 1120 drivers/scsi/ips.h uint32_t PtBuffer; uint32_t 1122 drivers/scsi/ips.h uint32_t CmdBSize; uint32_t 1124 drivers/scsi/ips.h uint32_t TimeOut; uint32_t 314 drivers/scsi/isci/probe_roms.h uint32_t high; uint32_t 315 drivers/scsi/isci/probe_roms.h uint32_t low; uint32_t 318 drivers/scsi/isci/probe_roms.h uint32_t afe_tx_amp_control0; uint32_t 319 drivers/scsi/isci/probe_roms.h uint32_t afe_tx_amp_control1; uint32_t 320 drivers/scsi/isci/probe_roms.h uint32_t afe_tx_amp_control2; uint32_t 321 drivers/scsi/isci/probe_roms.h uint32_t afe_tx_amp_control3; uint32_t 545 drivers/scsi/iscsi_tcp.c uint32_t conn_idx) uint32_t 836 drivers/scsi/iscsi_tcp.c uint16_t qdepth, uint32_t initial_cmdsn) uint32_t 43 drivers/scsi/iscsi_tcp.h uint32_t sendpage_failures_cnt; uint32_t 44 drivers/scsi/iscsi_tcp.h uint32_t discontiguous_hdr_cnt; uint32_t 1886 drivers/scsi/libfc/fc_lport.c job->reply_len = sizeof(uint32_t); uint32_t 97 drivers/scsi/libiscsi.c uint32_t exp_cmdsn, uint32_t max_cmdsn) uint32_t 555 drivers/scsi/libiscsi.c uint32_t exp_cmdsn, uint32_t max_cmdsn) uint32_t 658 drivers/scsi/libiscsi.c char *data, uint32_t data_size) uint32_t 765 drivers/scsi/libiscsi.c char *data, uint32_t data_size) uint32_t 1130 drivers/scsi/libiscsi.c uint32_t itt; uint32_t 2732 drivers/scsi/libiscsi.c uint32_t initial_cmdsn, unsigned int id) uint32_t 2886 drivers/scsi/libiscsi.c uint32_t conn_idx) uint32_t 1091 drivers/scsi/libiscsi_tcp.c uint32_t conn_idx) uint32_t 93 drivers/scsi/lpfc/lpfc.h #define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr))) uint32_t 94 drivers/scsi/lpfc/lpfc.h #define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32))) uint32_t 141 drivers/scsi/lpfc/lpfc.h uint32_t buffer_tag; /* used for tagged queue ring */ uint32_t 154 drivers/scsi/lpfc/lpfc.h uint32_t max_count; uint32_t 155 drivers/scsi/lpfc/lpfc.h uint32_t current_count; uint32_t 163 drivers/scsi/lpfc/lpfc.h uint32_t tag; uint32_t 187 drivers/scsi/lpfc/lpfc.h uint32_t status; /* vpd status value */ uint32_t 188 drivers/scsi/lpfc/lpfc.h uint32_t length; /* number of bytes actually returned */ uint32_t 190 drivers/scsi/lpfc/lpfc.h uint32_t rsvd1; /* Revision numbers */ uint32_t 191 drivers/scsi/lpfc/lpfc.h uint32_t biuRev; uint32_t 192 drivers/scsi/lpfc/lpfc.h uint32_t smRev; uint32_t 193 drivers/scsi/lpfc/lpfc.h uint32_t smFwRev; uint32_t 194 drivers/scsi/lpfc/lpfc.h uint32_t endecRev; uint32_t 200 drivers/scsi/lpfc/lpfc.h uint32_t postKernRev; uint32_t 201 drivers/scsi/lpfc/lpfc.h uint32_t opFwRev; uint32_t 203 drivers/scsi/lpfc/lpfc.h uint32_t sli1FwRev; uint32_t 205 drivers/scsi/lpfc/lpfc.h uint32_t sli2FwRev; uint32_t 210 drivers/scsi/lpfc/lpfc.h uint32_t rsvd3 :19; /* Reserved */ uint32_t 211 drivers/scsi/lpfc/lpfc.h uint32_t cdss : 1; /* Configure Data Security SLI */ uint32_t 212 drivers/scsi/lpfc/lpfc.h uint32_t rsvd2 : 3; /* Reserved */ uint32_t 213 drivers/scsi/lpfc/lpfc.h uint32_t cbg : 1; /* Configure BlockGuard */ uint32_t 214 drivers/scsi/lpfc/lpfc.h uint32_t cmv : 1; /* Configure Max VPIs */ uint32_t 215 drivers/scsi/lpfc/lpfc.h uint32_t ccrp : 1; /* Config Command Ring Polling */ uint32_t 216 drivers/scsi/lpfc/lpfc.h uint32_t csah : 1; /* Configure Synchronous Abort Handling */ uint32_t 217 drivers/scsi/lpfc/lpfc.h uint32_t chbs : 1; /* Cofigure Host Backing store */ uint32_t 218 drivers/scsi/lpfc/lpfc.h uint32_t cinb : 1; /* Enable Interrupt Notification Block */ uint32_t 219 drivers/scsi/lpfc/lpfc.h uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ uint32_t 220 drivers/scsi/lpfc/lpfc.h uint32_t cmx : 1; /* Configure Max XRIs */ uint32_t 221 drivers/scsi/lpfc/lpfc.h uint32_t cmr : 1; /* Configure Max RPIs */ uint32_t 223 drivers/scsi/lpfc/lpfc.h uint32_t cmr : 1; /* Configure Max RPIs */ uint32_t 224 drivers/scsi/lpfc/lpfc.h uint32_t cmx : 1; /* Configure Max XRIs */ uint32_t 225 drivers/scsi/lpfc/lpfc.h uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ uint32_t 226 drivers/scsi/lpfc/lpfc.h uint32_t cinb : 1; /* Enable Interrupt Notification Block */ uint32_t 227 drivers/scsi/lpfc/lpfc.h uint32_t chbs : 1; /* Cofigure Host Backing store */ uint32_t 228 drivers/scsi/lpfc/lpfc.h uint32_t csah : 1; /* Configure Synchronous Abort Handling */ uint32_t 229 drivers/scsi/lpfc/lpfc.h uint32_t ccrp : 1; /* Config Command Ring Polling */ uint32_t 230 drivers/scsi/lpfc/lpfc.h uint32_t cmv : 1; /* Configure Max VPIs */ uint32_t 231 drivers/scsi/lpfc/lpfc.h uint32_t cbg : 1; /* Configure BlockGuard */ uint32_t 232 drivers/scsi/lpfc/lpfc.h uint32_t rsvd2 : 3; /* Reserved */ uint32_t 233 drivers/scsi/lpfc/lpfc.h uint32_t cdss : 1; /* Configure Data Security SLI */ uint32_t 234 drivers/scsi/lpfc/lpfc.h uint32_t rsvd3 :19; /* Reserved */ uint32_t 245 drivers/scsi/lpfc/lpfc.h uint32_t elsLogiCol; uint32_t 246 drivers/scsi/lpfc/lpfc.h uint32_t elsRetryExceeded; uint32_t 247 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitRetry; uint32_t 248 drivers/scsi/lpfc/lpfc.h uint32_t elsDelayRetry; uint32_t 249 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvDrop; uint32_t 250 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvFrame; uint32_t 251 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvRSCN; uint32_t 252 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvRNID; uint32_t 253 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvFARP; uint32_t 254 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvFARPR; uint32_t 255 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvFLOGI; uint32_t 256 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvPLOGI; uint32_t 257 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvADISC; uint32_t 258 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvPDISC; uint32_t 259 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvFAN; uint32_t 260 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvLOGO; uint32_t 261 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvPRLO; uint32_t 262 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvPRLI; uint32_t 263 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvLIRR; uint32_t 264 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvRLS; uint32_t 265 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvRPS; uint32_t 266 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvRPL; uint32_t 267 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvRRQ; uint32_t 268 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvRTV; uint32_t 269 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvECHO; uint32_t 270 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvLCB; uint32_t 271 drivers/scsi/lpfc/lpfc.h uint32_t elsRcvRDP; uint32_t 272 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitFLOGI; uint32_t 273 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitFDISC; uint32_t 274 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitPLOGI; uint32_t 275 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitPRLI; uint32_t 276 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitADISC; uint32_t 277 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitLOGO; uint32_t 278 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitSCR; uint32_t 279 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitRSCN; uint32_t 280 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitRNID; uint32_t 281 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitFARP; uint32_t 282 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitFARPR; uint32_t 283 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitACC; uint32_t 284 drivers/scsi/lpfc/lpfc.h uint32_t elsXmitLSRJT; uint32_t 286 drivers/scsi/lpfc/lpfc.h uint32_t frameRcvBcast; uint32_t 287 drivers/scsi/lpfc/lpfc.h uint32_t frameRcvMulti; uint32_t 288 drivers/scsi/lpfc/lpfc.h uint32_t strayXmitCmpl; uint32_t 289 drivers/scsi/lpfc/lpfc.h uint32_t frameXmitDelay; uint32_t 290 drivers/scsi/lpfc/lpfc.h uint32_t xriCmdCmpl; uint32_t 291 drivers/scsi/lpfc/lpfc.h uint32_t xriStatErr; uint32_t 292 drivers/scsi/lpfc/lpfc.h uint32_t LinkUp; uint32_t 293 drivers/scsi/lpfc/lpfc.h uint32_t LinkDown; uint32_t 294 drivers/scsi/lpfc/lpfc.h uint32_t LinkMultiEvent; uint32_t 295 drivers/scsi/lpfc/lpfc.h uint32_t NoRcvBuf; uint32_t 296 drivers/scsi/lpfc/lpfc.h uint32_t fcpCmd; uint32_t 297 drivers/scsi/lpfc/lpfc.h uint32_t fcpCmpl; uint32_t 298 drivers/scsi/lpfc/lpfc.h uint32_t fcpRspErr; uint32_t 299 drivers/scsi/lpfc/lpfc.h uint32_t fcpRemoteStop; uint32_t 300 drivers/scsi/lpfc/lpfc.h uint32_t fcpPortRjt; uint32_t 301 drivers/scsi/lpfc/lpfc.h uint32_t fcpPortBusy; uint32_t 302 drivers/scsi/lpfc/lpfc.h uint32_t fcpError; uint32_t 303 drivers/scsi/lpfc/lpfc.h uint32_t fcpLocalErr; uint32_t 364 drivers/scsi/lpfc/lpfc.h uint32_t fc_flag; /* FC flags */ uint32_t 392 drivers/scsi/lpfc/lpfc.h uint32_t ct_flags; uint32_t 412 drivers/scsi/lpfc/lpfc.h uint32_t fc_myDID; /* fibre channel S_ID */ uint32_t 413 drivers/scsi/lpfc/lpfc.h uint32_t fc_prevDID; /* previous fibre channel S_ID */ uint32_t 420 drivers/scsi/lpfc/lpfc.h uint32_t num_disc_nodes; /* in addition to hba_state */ uint32_t 421 drivers/scsi/lpfc/lpfc.h uint32_t gidft_inp; /* cnt of outstanding GID_FTs */ uint32_t 423 drivers/scsi/lpfc/lpfc.h uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */ uint32_t 424 drivers/scsi/lpfc/lpfc.h uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */ uint32_t 425 drivers/scsi/lpfc/lpfc.h uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */ uint32_t 434 drivers/scsi/lpfc/lpfc.h uint32_t fc_prli_sent; /* cntr for outstanding PRLIs */ uint32_t 437 drivers/scsi/lpfc/lpfc.h uint32_t work_port_events; /* Timeout to be handled */ uint32_t 459 drivers/scsi/lpfc/lpfc.h uint32_t cfg_scan_down; uint32_t 460 drivers/scsi/lpfc/lpfc.h uint32_t cfg_lun_queue_depth; uint32_t 461 drivers/scsi/lpfc/lpfc.h uint32_t cfg_nodev_tmo; uint32_t 462 drivers/scsi/lpfc/lpfc.h uint32_t cfg_devloss_tmo; uint32_t 463 drivers/scsi/lpfc/lpfc.h uint32_t cfg_restrict_login; uint32_t 464 drivers/scsi/lpfc/lpfc.h uint32_t cfg_peer_port_login; uint32_t 465 drivers/scsi/lpfc/lpfc.h uint32_t cfg_fcp_class; uint32_t 466 drivers/scsi/lpfc/lpfc.h uint32_t cfg_use_adisc; uint32_t 467 drivers/scsi/lpfc/lpfc.h uint32_t cfg_discovery_threads; uint32_t 468 drivers/scsi/lpfc/lpfc.h uint32_t cfg_log_verbose; uint32_t 469 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_fc4_type; uint32_t 470 drivers/scsi/lpfc/lpfc.h uint32_t cfg_max_luns; uint32_t 471 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_da_id; uint32_t 472 drivers/scsi/lpfc/lpfc.h uint32_t cfg_max_scsicmpl_time; uint32_t 473 drivers/scsi/lpfc/lpfc.h uint32_t cfg_tgt_queue_depth; uint32_t 474 drivers/scsi/lpfc/lpfc.h uint32_t cfg_first_burst_size; uint32_t 475 drivers/scsi/lpfc/lpfc.h uint32_t dev_loss_tmo_changed; uint32_t 494 drivers/scsi/lpfc/lpfc.h uint32_t vport_flag; uint32_t 500 drivers/scsi/lpfc/lpfc.h uint32_t fdmi_hba_mask; uint32_t 501 drivers/scsi/lpfc/lpfc.h uint32_t fdmi_port_mask; uint32_t 506 drivers/scsi/lpfc/lpfc.h uint32_t last_fcp_wqidx; uint32_t 507 drivers/scsi/lpfc/lpfc.h uint32_t rcv_flogi_cnt; /* How many unsol FLOGIs ACK'd. */ uint32_t 513 drivers/scsi/lpfc/lpfc.h uint32_t next_hbqPutIdx; /* Index to next HBQ slot to use */ uint32_t 514 drivers/scsi/lpfc/lpfc.h uint32_t hbqPutIdx; /* HBQ slot to use */ uint32_t 515 drivers/scsi/lpfc/lpfc.h uint32_t local_hbqGetIdx; /* Local copy of Get index from Port */ uint32_t 543 drivers/scsi/lpfc/lpfc.h uint32_t ctxt_id; uint32_t 544 drivers/scsi/lpfc/lpfc.h uint32_t SID; uint32_t 545 drivers/scsi/lpfc/lpfc.h uint32_t valid; uint32_t 586 drivers/scsi/lpfc/lpfc.h uint32_t state; uint32_t 594 drivers/scsi/lpfc/lpfc.h uint32_t numBuf; uint32_t 595 drivers/scsi/lpfc/lpfc.h uint32_t mbxTag; uint32_t 596 drivers/scsi/lpfc/lpfc.h uint32_t seqNum; uint32_t 610 drivers/scsi/lpfc/lpfc.h uint32_t fw_buffcount; /* Buffer size posted to FW */ uint32_t 615 drivers/scsi/lpfc/lpfc.h uint32_t fw_loglevel; /* Log level set */ uint32_t 646 drivers/scsi/lpfc/lpfc.h (struct lpfc_hba *, uint32_t, uint32_t 647 drivers/scsi/lpfc/lpfc.h struct lpfc_iocbq *, uint32_t); uint32_t 658 drivers/scsi/lpfc/lpfc.h (struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t); uint32_t 663 drivers/scsi/lpfc/lpfc.h uint32_t mask); uint32_t 667 drivers/scsi/lpfc/lpfc.h (struct lpfc_hba *, uint32_t, struct hbq_dmabuf *); uint32_t 671 drivers/scsi/lpfc/lpfc.h (struct lpfc_hba *, uint32_t); uint32_t 677 drivers/scsi/lpfc/lpfc.h (struct lpfc_hba *, uint32_t); uint32_t 679 drivers/scsi/lpfc/lpfc.h (struct lpfc_hba *, uint32_t); uint32_t 698 drivers/scsi/lpfc/lpfc.h uint32_t sli_rev; /* SLI2, SLI3, or SLI4 */ uint32_t 699 drivers/scsi/lpfc/lpfc.h uint32_t sli3_options; /* Mask of enabled SLI3 options */ uint32_t 708 drivers/scsi/lpfc/lpfc.h uint32_t iocb_cmd_size; uint32_t 709 drivers/scsi/lpfc/lpfc.h uint32_t iocb_rsp_size; uint32_t 713 drivers/scsi/lpfc/lpfc.h uint32_t link_flag; /* link state flags */ uint32_t 722 drivers/scsi/lpfc/lpfc.h uint32_t hba_flag; /* hba generic flags */ uint32_t 747 drivers/scsi/lpfc/lpfc.h uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/ uint32_t 751 drivers/scsi/lpfc/lpfc.h uint32_t *mbox_ext; uint32_t 753 drivers/scsi/lpfc/lpfc.h uint32_t ha_copy; uint32_t 763 drivers/scsi/lpfc/lpfc.h uint32_t fc_eventTag; /* event tag for link attention */ uint32_t 764 drivers/scsi/lpfc/lpfc.h uint32_t link_events; uint32_t 767 drivers/scsi/lpfc/lpfc.h uint32_t fc_pref_DID; /* preferred D_ID */ uint32_t 769 drivers/scsi/lpfc/lpfc.h uint32_t fc_edtovResol; /* E_D_TOV timer resolution */ uint32_t 770 drivers/scsi/lpfc/lpfc.h uint32_t fc_edtov; /* E_D_TOV timer value */ uint32_t 771 drivers/scsi/lpfc/lpfc.h uint32_t fc_arbtov; /* ARB_TOV timer value */ uint32_t 772 drivers/scsi/lpfc/lpfc.h uint32_t fc_ratov; /* R_A_TOV timer value */ uint32_t 773 drivers/scsi/lpfc/lpfc.h uint32_t fc_rttov; /* R_T_TOV timer value */ uint32_t 774 drivers/scsi/lpfc/lpfc.h uint32_t fc_altov; /* AL_TOV timer value */ uint32_t 775 drivers/scsi/lpfc/lpfc.h uint32_t fc_crtov; /* C_R_TOV timer value */ uint32_t 780 drivers/scsi/lpfc/lpfc.h uint32_t lmt; uint32_t 782 drivers/scsi/lpfc/lpfc.h uint32_t fc_topology; /* link topology, from LINK INIT */ uint32_t 783 drivers/scsi/lpfc/lpfc.h uint32_t fc_topology_changed; /* link topology, from LINK INIT */ uint32_t 788 drivers/scsi/lpfc/lpfc.h uint32_t nport_event_cnt; /* timestamp for nlplist entry */ uint32_t 792 drivers/scsi/lpfc/lpfc.h uint32_t RandomData[7]; uint32_t 803 drivers/scsi/lpfc/lpfc.h uint32_t cfg_ack0; uint32_t 804 drivers/scsi/lpfc/lpfc.h uint32_t cfg_xri_rebalancing; uint32_t 805 drivers/scsi/lpfc/lpfc.h uint32_t cfg_xpsgl; uint32_t 806 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_npiv; uint32_t 807 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_rrq; uint32_t 808 drivers/scsi/lpfc/lpfc.h uint32_t cfg_topology; uint32_t 809 drivers/scsi/lpfc/lpfc.h uint32_t cfg_link_speed; uint32_t 812 drivers/scsi/lpfc/lpfc.h uint32_t cfg_fcf_failover_policy; uint32_t 813 drivers/scsi/lpfc/lpfc.h uint32_t cfg_fcp_io_sched; uint32_t 814 drivers/scsi/lpfc/lpfc.h uint32_t cfg_ns_query; uint32_t 815 drivers/scsi/lpfc/lpfc.h uint32_t cfg_fcp2_no_tgt_reset; uint32_t 816 drivers/scsi/lpfc/lpfc.h uint32_t cfg_cr_delay; uint32_t 817 drivers/scsi/lpfc/lpfc.h uint32_t cfg_cr_count; uint32_t 818 drivers/scsi/lpfc/lpfc.h uint32_t cfg_multi_ring_support; uint32_t 819 drivers/scsi/lpfc/lpfc.h uint32_t cfg_multi_ring_rctl; uint32_t 820 drivers/scsi/lpfc/lpfc.h uint32_t cfg_multi_ring_type; uint32_t 821 drivers/scsi/lpfc/lpfc.h uint32_t cfg_poll; uint32_t 822 drivers/scsi/lpfc/lpfc.h uint32_t cfg_poll_tmo; uint32_t 823 drivers/scsi/lpfc/lpfc.h uint32_t cfg_task_mgmt_tmo; uint32_t 824 drivers/scsi/lpfc/lpfc.h uint32_t cfg_use_msi; uint32_t 825 drivers/scsi/lpfc/lpfc.h uint32_t cfg_auto_imax; uint32_t 826 drivers/scsi/lpfc/lpfc.h uint32_t cfg_fcp_imax; uint32_t 827 drivers/scsi/lpfc/lpfc.h uint32_t cfg_force_rscn; uint32_t 828 drivers/scsi/lpfc/lpfc.h uint32_t cfg_cq_poll_threshold; uint32_t 829 drivers/scsi/lpfc/lpfc.h uint32_t cfg_cq_max_proc_limit; uint32_t 830 drivers/scsi/lpfc/lpfc.h uint32_t cfg_fcp_cpu_map; uint32_t 831 drivers/scsi/lpfc/lpfc.h uint32_t cfg_fcp_mq_threshold; uint32_t 832 drivers/scsi/lpfc/lpfc.h uint32_t cfg_hdw_queue; uint32_t 833 drivers/scsi/lpfc/lpfc.h uint32_t cfg_irq_chann; uint32_t 834 drivers/scsi/lpfc/lpfc.h uint32_t cfg_suppress_rsp; uint32_t 835 drivers/scsi/lpfc/lpfc.h uint32_t cfg_nvme_oas; uint32_t 836 drivers/scsi/lpfc/lpfc.h uint32_t cfg_nvme_embed_cmd; uint32_t 837 drivers/scsi/lpfc/lpfc.h uint32_t cfg_nvmet_mrq_post; uint32_t 838 drivers/scsi/lpfc/lpfc.h uint32_t cfg_nvmet_mrq; uint32_t 839 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_nvmet; uint32_t 840 drivers/scsi/lpfc/lpfc.h uint32_t cfg_nvme_enable_fb; uint32_t 841 drivers/scsi/lpfc/lpfc.h uint32_t cfg_nvmet_fb_size; uint32_t 842 drivers/scsi/lpfc/lpfc.h uint32_t cfg_total_seg_cnt; uint32_t 843 drivers/scsi/lpfc/lpfc.h uint32_t cfg_sg_seg_cnt; uint32_t 844 drivers/scsi/lpfc/lpfc.h uint32_t cfg_nvme_seg_cnt; uint32_t 845 drivers/scsi/lpfc/lpfc.h uint32_t cfg_scsi_seg_cnt; uint32_t 846 drivers/scsi/lpfc/lpfc.h uint32_t cfg_sg_dma_buf_size; uint32_t 849 drivers/scsi/lpfc/lpfc.h uint32_t cfg_hba_queue_depth; uint32_t 850 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_hba_reset; uint32_t 851 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_hba_heartbeat; uint32_t 852 drivers/scsi/lpfc/lpfc.h uint32_t cfg_fof; uint32_t 853 drivers/scsi/lpfc/lpfc.h uint32_t cfg_EnableXLane; uint32_t 856 drivers/scsi/lpfc/lpfc.h uint32_t cfg_oas_lun_state; uint32_t 859 drivers/scsi/lpfc/lpfc.h uint32_t cfg_oas_lun_status; uint32_t 861 drivers/scsi/lpfc/lpfc.h uint32_t cfg_oas_flags; uint32_t 865 drivers/scsi/lpfc/lpfc.h uint32_t cfg_oas_priority; uint32_t 866 drivers/scsi/lpfc/lpfc.h uint32_t cfg_XLanePriority; uint32_t 867 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_bg; uint32_t 868 drivers/scsi/lpfc/lpfc.h uint32_t cfg_prot_mask; uint32_t 869 drivers/scsi/lpfc/lpfc.h uint32_t cfg_prot_guard; uint32_t 870 drivers/scsi/lpfc/lpfc.h uint32_t cfg_hostmem_hgp; uint32_t 871 drivers/scsi/lpfc/lpfc.h uint32_t cfg_log_verbose; uint32_t 872 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_fc4_type; uint32_t 873 drivers/scsi/lpfc/lpfc.h uint32_t cfg_aer_support; uint32_t 874 drivers/scsi/lpfc/lpfc.h uint32_t cfg_sriov_nr_virtfn; uint32_t 875 drivers/scsi/lpfc/lpfc.h uint32_t cfg_request_firmware_upgrade; uint32_t 876 drivers/scsi/lpfc/lpfc.h uint32_t cfg_iocb_cnt; uint32_t 877 drivers/scsi/lpfc/lpfc.h uint32_t cfg_suppress_link_up; uint32_t 878 drivers/scsi/lpfc/lpfc.h uint32_t cfg_rrq_xri_bitmap_sz; uint32_t 879 drivers/scsi/lpfc/lpfc.h uint32_t cfg_delay_discovery; uint32_t 880 drivers/scsi/lpfc/lpfc.h uint32_t cfg_sli_mode; uint32_t 884 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_dss; uint32_t 885 drivers/scsi/lpfc/lpfc.h uint32_t cfg_fdmi_on; uint32_t 888 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_SmartSAN; uint32_t 889 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_mds_diags; uint32_t 890 drivers/scsi/lpfc/lpfc.h uint32_t cfg_ras_fwlog_level; uint32_t 891 drivers/scsi/lpfc/lpfc.h uint32_t cfg_ras_fwlog_buffsize; uint32_t 892 drivers/scsi/lpfc/lpfc.h uint32_t cfg_ras_fwlog_func; uint32_t 893 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_bbcr; /* Enable BB Credit Recovery */ uint32_t 894 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_dpp; /* Enable Direct Packet Push */ uint32_t 898 drivers/scsi/lpfc/lpfc.h uint32_t cfg_enable_pbde; uint32_t 904 drivers/scsi/lpfc/lpfc.h uint32_t work_ha; /* Host Attention Bits for WT */ uint32_t 905 drivers/scsi/lpfc/lpfc.h uint32_t work_ha_mask; /* HA Bits owned by WT */ uint32_t 906 drivers/scsi/lpfc/lpfc.h uint32_t work_hs; /* HS stored in case of ERRAT */ uint32_t 907 drivers/scsi/lpfc/lpfc.h uint32_t work_status[2]; /* Extra status from SLIM */ uint32_t 912 drivers/scsi/lpfc/lpfc.h uint32_t border_sge_num; uint32_t 914 drivers/scsi/lpfc/lpfc.h uint32_t hbq_in_use; /* HBQs in use flag */ uint32_t 915 drivers/scsi/lpfc/lpfc.h uint32_t hbq_count; /* Count of configured HBQs */ uint32_t 947 drivers/scsi/lpfc/lpfc.h uint32_t __iomem *hbq_put; /* Address in SLIM to HBQ put ptrs */ uint32_t 948 drivers/scsi/lpfc/lpfc.h uint32_t *hbq_get; /* Host mem address of HBQ get ptrs */ uint32_t 970 drivers/scsi/lpfc/lpfc.h uint32_t eratt_poll_interval; uint32_t 981 drivers/scsi/lpfc/lpfc.h uint32_t total_scsi_bufs; uint32_t 983 drivers/scsi/lpfc/lpfc.h uint32_t total_iocbq_bufs; uint32_t 1005 drivers/scsi/lpfc/lpfc.h uint32_t intr_mode; uint32_t 1060 drivers/scsi/lpfc/lpfc.h uint32_t nvmeio_trc_size; uint32_t 1061 drivers/scsi/lpfc/lpfc.h uint32_t nvmeio_trc_output_idx; uint32_t 1064 drivers/scsi/lpfc/lpfc.h uint32_t lpfc_injerr_wgrd_cnt; uint32_t 1065 drivers/scsi/lpfc/lpfc.h uint32_t lpfc_injerr_wapp_cnt; uint32_t 1066 drivers/scsi/lpfc/lpfc.h uint32_t lpfc_injerr_wref_cnt; uint32_t 1067 drivers/scsi/lpfc/lpfc.h uint32_t lpfc_injerr_rgrd_cnt; uint32_t 1068 drivers/scsi/lpfc/lpfc.h uint32_t lpfc_injerr_rapp_cnt; uint32_t 1069 drivers/scsi/lpfc/lpfc.h uint32_t lpfc_injerr_rref_cnt; uint32_t 1070 drivers/scsi/lpfc/lpfc.h uint32_t lpfc_injerr_nportid; uint32_t 1112 drivers/scsi/lpfc/lpfc.h uint32_t buffer_tag_count; uint32_t 1120 drivers/scsi/lpfc/lpfc.h uint32_t bucket_base; uint32_t 1121 drivers/scsi/lpfc/lpfc.h uint32_t bucket_step; uint32_t 1126 drivers/scsi/lpfc/lpfc.h uint32_t fcoe_eventtag; uint32_t 1127 drivers/scsi/lpfc/lpfc.h uint32_t fcoe_eventtag_at_fcf_scan; uint32_t 1128 drivers/scsi/lpfc/lpfc.h uint32_t fcoe_cvl_eventtag; uint32_t 1129 drivers/scsi/lpfc/lpfc.h uint32_t fcoe_cvl_eventtag_attn; uint32_t 1143 drivers/scsi/lpfc/lpfc.h uint32_t ctx_idx; uint32_t 1150 drivers/scsi/lpfc/lpfc.h uint32_t iocb_cnt; uint32_t 1151 drivers/scsi/lpfc/lpfc.h uint32_t iocb_max; uint32_t 1259 drivers/scsi/lpfc/lpfc.h lpfc_readl(void __iomem *addr, uint32_t *data) uint32_t 1261 drivers/scsi/lpfc/lpfc.h uint32_t temp; uint32_t 807 drivers/scsi/lpfc/lpfc_attr.c uint32_t if_type; uint32_t 1213 drivers/scsi/lpfc/lpfc_attr.c lpfc_do_offline(struct lpfc_hba *phba, uint32_t type) uint32_t 1518 drivers/scsi/lpfc/lpfc_attr.c lpfc_sli4_pdev_reg_request(struct lpfc_hba *phba, uint32_t opcode) uint32_t 1522 drivers/scsi/lpfc/lpfc_attr.c uint32_t before_fc_flag; uint32_t 1523 drivers/scsi/lpfc/lpfc_attr.c uint32_t sriov_nr_virtfn; uint32_t 1524 drivers/scsi/lpfc/lpfc_attr.c uint32_t reg_val; uint32_t 1835 drivers/scsi/lpfc/lpfc_attr.c uint32_t *mxri, uint32_t *axri, uint32_t 1836 drivers/scsi/lpfc/lpfc_attr.c uint32_t *mrpi, uint32_t *arpi, uint32_t 1837 drivers/scsi/lpfc/lpfc_attr.c uint32_t *mvpi, uint32_t *avpi) uint32_t 1843 drivers/scsi/lpfc/lpfc_attr.c uint32_t max_vpi; uint32_t 1949 drivers/scsi/lpfc/lpfc_attr.c uint32_t cnt; uint32_t 1977 drivers/scsi/lpfc/lpfc_attr.c uint32_t cnt, acnt; uint32_t 2005 drivers/scsi/lpfc/lpfc_attr.c uint32_t cnt; uint32_t 2033 drivers/scsi/lpfc/lpfc_attr.c uint32_t cnt, acnt; uint32_t 2061 drivers/scsi/lpfc/lpfc_attr.c uint32_t cnt; uint32_t 2089 drivers/scsi/lpfc/lpfc_attr.c uint32_t cnt, acnt; uint32_t 2167 drivers/scsi/lpfc/lpfc_attr.c uint32_t creg_val; uint32_t 2168 drivers/scsi/lpfc/lpfc_attr.c uint32_t old_val; uint32_t 2778 drivers/scsi/lpfc/lpfc_attr.c u32 *fawwpn_key = (uint32_t *)&vport->fc_sparam.un.vendorVersion[0]; uint32_t 3286 drivers/scsi/lpfc/lpfc_attr.c uint32_t oas_state, uint8_t pri) uint32_t 3325 drivers/scsi/lpfc/lpfc_attr.c uint8_t tgt_wwpn[], uint32_t *lun_status, uint32_t 3326 drivers/scsi/lpfc/lpfc_attr.c uint32_t *lun_pri) uint32_t 3364 drivers/scsi/lpfc/lpfc_attr.c uint32_t oas_state, uint8_t pri) uint32_t 3443 drivers/scsi/lpfc/lpfc_attr.c uint32_t pri; uint32_t 4078 drivers/scsi/lpfc/lpfc_attr.c uint32_t prev_val; uint32_t 4520 drivers/scsi/lpfc/lpfc_attr.c uint32_t prev_val, if_type; uint32_t 5045 drivers/scsi/lpfc/lpfc_attr.c uint32_t usdelay; uint32_t 5077 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_fcp_imax = (uint32_t)val; uint32_t 5180 drivers/scsi/lpfc/lpfc_attr.c phba->cfg_cq_max_proc_limit = (uint32_t)val; uint32_t 6172 drivers/scsi/lpfc/lpfc_attr.c buf_off += sizeof(uint32_t)) uint32_t 6173 drivers/scsi/lpfc/lpfc_attr.c writel(*((uint32_t *)(buf + buf_off + LPFC_REG_WRITE_KEY_SIZE)), uint32_t 6205 drivers/scsi/lpfc/lpfc_attr.c uint32_t * tmp_ptr; uint32_t 6227 drivers/scsi/lpfc/lpfc_attr.c for (buf_off = 0; buf_off < count; buf_off += sizeof(uint32_t)) { uint32_t 6228 drivers/scsi/lpfc/lpfc_attr.c tmp_ptr = (uint32_t *)(buf + buf_off); uint32_t 6858 drivers/scsi/lpfc/lpfc_attr.c lpfc_set_rport_loss_tmo(struct fc_rport *rport, uint32_t timeout) uint32_t 6943 drivers/scsi/lpfc/lpfc_attr.c lpfc_hba_log_verbose_init(struct lpfc_hba *phba, uint32_t verbose) uint32_t 59 drivers/scsi/lpfc/lpfc_bsg.c uint32_t type_mask; uint32_t 60 drivers/scsi/lpfc/lpfc_bsg.c uint32_t req_id; uint32_t 61 drivers/scsi/lpfc/lpfc_bsg.c uint32_t reg_id; uint32_t 86 drivers/scsi/lpfc/lpfc_bsg.c uint32_t mbOffset; /* from app */ uint32_t 87 drivers/scsi/lpfc/lpfc_bsg.c uint32_t inExtWLen; /* from app */ uint32_t 88 drivers/scsi/lpfc/lpfc_bsg.c uint32_t outExtWLen; /* from app */ uint32_t 103 drivers/scsi/lpfc/lpfc_bsg.c uint32_t type; uint32_t 115 drivers/scsi/lpfc/lpfc_bsg.c uint32_t type; uint32_t 116 drivers/scsi/lpfc/lpfc_bsg.c uint32_t immed_dat; uint32_t 118 drivers/scsi/lpfc/lpfc_bsg.c uint32_t len; uint32_t 134 drivers/scsi/lpfc/lpfc_bsg.c uint32_t size; uint32_t 135 drivers/scsi/lpfc/lpfc_bsg.c uint32_t flag; uint32_t 396 drivers/scsi/lpfc/lpfc_bsg.c uint32_t timeout; uint32_t 404 drivers/scsi/lpfc/lpfc_bsg.c uint32_t creg_val; uint32_t 670 drivers/scsi/lpfc/lpfc_bsg.c uint32_t elscmd; uint32_t 671 drivers/scsi/lpfc/lpfc_bsg.c uint32_t cmdsize; uint32_t 676 drivers/scsi/lpfc/lpfc_bsg.c uint32_t creg_val; uint32_t 854 drivers/scsi/lpfc/lpfc_bsg.c lpfc_bsg_event_new(uint32_t ev_mask, int ev_reg_id, uint32_t ev_req_id) uint32_t 918 drivers/scsi/lpfc/lpfc_bsg.c uint32_t evt_req_id = 0; uint32_t 919 drivers/scsi/lpfc/lpfc_bsg.c uint32_t cmd; uint32_t 1179 drivers/scsi/lpfc/lpfc_bsg.c uint32_t sid; uint32_t 1215 drivers/scsi/lpfc/lpfc_bsg.c uint32_t ev_mask; uint32_t 1229 drivers/scsi/lpfc/lpfc_bsg.c ev_mask = ((uint32_t)(unsigned long)event_req->type_mask & uint32_t 1300 drivers/scsi/lpfc/lpfc_bsg.c uint32_t rc = 0; uint32_t 1481 drivers/scsi/lpfc/lpfc_bsg.c lpfc_issue_ct_rsp(struct lpfc_hba *phba, struct bsg_job *job, uint32_t tag, uint32_t 1491 drivers/scsi/lpfc/lpfc_bsg.c uint32_t creg_val; uint32_t 1637 drivers/scsi/lpfc/lpfc_bsg.c uint32_t tag = mgmt_resp->tag; uint32_t 1796 drivers/scsi/lpfc/lpfc_bsg.c uint32_t link_flags; uint32_t 1797 drivers/scsi/lpfc/lpfc_bsg.c uint32_t timeout; uint32_t 1914 drivers/scsi/lpfc/lpfc_bsg.c lpfc_sli4_bsg_set_link_diag_state(struct lpfc_hba *phba, uint32_t diag) uint32_t 1918 drivers/scsi/lpfc/lpfc_bsg.c uint32_t req_len, alloc_len; uint32_t 1978 drivers/scsi/lpfc/lpfc_bsg.c uint32_t link_no) uint32_t 1981 drivers/scsi/lpfc/lpfc_bsg.c uint32_t req_len, alloc_len; uint32_t 2065 drivers/scsi/lpfc/lpfc_bsg.c uint32_t link_flags, timeout, link_no; uint32_t 2322 drivers/scsi/lpfc/lpfc_bsg.c uint32_t timeout; uint32_t 2402 drivers/scsi/lpfc/lpfc_bsg.c uint32_t req_len, alloc_len; uint32_t 2405 drivers/scsi/lpfc/lpfc_bsg.c uint32_t shdr_status, shdr_add_status; uint32_t 2876 drivers/scsi/lpfc/lpfc_bsg.c struct ulp_bde64 *bpl, uint32_t size, uint32_t 2965 drivers/scsi/lpfc/lpfc_bsg.c uint32_t num_bde; uint32_t 2990 drivers/scsi/lpfc/lpfc_bsg.c num_bde = (uint32_t)rxbuffer->flag; uint32_t 3107 drivers/scsi/lpfc/lpfc_bsg.c uint32_t size; uint32_t 3108 drivers/scsi/lpfc/lpfc_bsg.c uint32_t full_size; uint32_t 3120 drivers/scsi/lpfc/lpfc_bsg.c uint32_t num_bde; uint32_t 3127 drivers/scsi/lpfc/lpfc_bsg.c uint32_t total_mem; uint32_t 3280 drivers/scsi/lpfc/lpfc_bsg.c num_bde = (uint32_t)txbuffer->flag; uint32_t 3459 drivers/scsi/lpfc/lpfc_bsg.c uint32_t size; uint32_t 3642 drivers/scsi/lpfc/lpfc_bsg.c uint32_t size; uint32_t 3799 drivers/scsi/lpfc/lpfc_bsg.c uint32_t index, struct lpfc_dmabuf *mbx_dmabuf, uint32_t 3909 drivers/scsi/lpfc/lpfc_bsg.c uint32_t ext_buf_cnt, ext_buf_index; uint32_t 4097 drivers/scsi/lpfc/lpfc_bsg.c uint32_t ext_buf_cnt; uint32_t 4260 drivers/scsi/lpfc/lpfc_bsg.c uint32_t subsys; uint32_t 4261 drivers/scsi/lpfc/lpfc_bsg.c uint32_t opcode; uint32_t 4411 drivers/scsi/lpfc/lpfc_bsg.c uint32_t size; uint32_t 4412 drivers/scsi/lpfc/lpfc_bsg.c uint32_t index; uint32_t 4484 drivers/scsi/lpfc/lpfc_bsg.c uint32_t size; uint32_t 4485 drivers/scsi/lpfc/lpfc_bsg.c uint32_t index; uint32_t 4737 drivers/scsi/lpfc/lpfc_bsg.c uint32_t transmit_length, receive_length, mode; uint32_t 4744 drivers/scsi/lpfc/lpfc_bsg.c uint32_t size; uint32_t 4769 drivers/scsi/lpfc/lpfc_bsg.c if ((mbox_req->inExtWLen > BSG_MBOX_SIZE/sizeof(uint32_t)) || uint32_t 4770 drivers/scsi/lpfc/lpfc_bsg.c (mbox_req->outExtWLen > BSG_MBOX_SIZE/sizeof(uint32_t))) { uint32_t 4841 drivers/scsi/lpfc/lpfc_bsg.c mbox_req->inExtWLen * sizeof(uint32_t); uint32_t 4843 drivers/scsi/lpfc/lpfc_bsg.c mbox_req->outExtWLen * sizeof(uint32_t); uint32_t 5586 drivers/scsi/lpfc/lpfc_bsg.c lwpd_ptr = (uint32_t *)(ras_fwlog->lwpd.virt); uint32_t 5843 drivers/scsi/lpfc/lpfc_bsg.c uint32_t msgcode; uint32_t 48 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 49 drivers/scsi/lpfc/lpfc_bsg.h uint32_t type_mask; uint32_t 50 drivers/scsi/lpfc/lpfc_bsg.h uint32_t ev_req_id; uint32_t 51 drivers/scsi/lpfc/lpfc_bsg.h uint32_t ev_reg_id; uint32_t 55 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 56 drivers/scsi/lpfc/lpfc_bsg.h uint32_t ev_reg_id; uint32_t 57 drivers/scsi/lpfc/lpfc_bsg.h uint32_t ev_req_id; uint32_t 61 drivers/scsi/lpfc/lpfc_bsg.h uint32_t immed_data; uint32_t 62 drivers/scsi/lpfc/lpfc_bsg.h uint32_t type; uint32_t 66 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 67 drivers/scsi/lpfc/lpfc_bsg.h uint32_t tag; uint32_t 76 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 77 drivers/scsi/lpfc/lpfc_bsg.h uint32_t type; uint32_t 78 drivers/scsi/lpfc/lpfc_bsg.h uint32_t timeout; uint32_t 79 drivers/scsi/lpfc/lpfc_bsg.h uint32_t physical_link; uint32_t 83 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 84 drivers/scsi/lpfc/lpfc_bsg.h uint32_t timeout; uint32_t 85 drivers/scsi/lpfc/lpfc_bsg.h uint32_t test_id; uint32_t 86 drivers/scsi/lpfc/lpfc_bsg.h uint32_t loops; uint32_t 87 drivers/scsi/lpfc/lpfc_bsg.h uint32_t test_version; uint32_t 88 drivers/scsi/lpfc/lpfc_bsg.h uint32_t error_action; uint32_t 92 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 96 drivers/scsi/lpfc/lpfc_bsg.h uint32_t mbox_status; uint32_t 97 drivers/scsi/lpfc/lpfc_bsg.h uint32_t shdr_status; uint32_t 98 drivers/scsi/lpfc/lpfc_bsg.h uint32_t shdr_add_status; uint32_t 105 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 113 drivers/scsi/lpfc/lpfc_bsg.h uint32_t a_Major; uint32_t 114 drivers/scsi/lpfc/lpfc_bsg.h uint32_t a_Minor; uint32_t 125 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 126 drivers/scsi/lpfc/lpfc_bsg.h uint32_t mbOffset; uint32_t 127 drivers/scsi/lpfc/lpfc_bsg.h uint32_t inExtWLen; uint32_t 128 drivers/scsi/lpfc/lpfc_bsg.h uint32_t outExtWLen; uint32_t 129 drivers/scsi/lpfc/lpfc_bsg.h uint32_t extMboxTag; uint32_t 130 drivers/scsi/lpfc/lpfc_bsg.h uint32_t extSeqNum; uint32_t 135 drivers/scsi/lpfc/lpfc_bsg.h uint32_t cmd; uint32_t 136 drivers/scsi/lpfc/lpfc_bsg.h uint32_t xri; uint32_t 140 drivers/scsi/lpfc/lpfc_bsg.h uint32_t xri; /* return the xri of the iocb exchange */ uint32_t 197 drivers/scsi/lpfc/lpfc_bsg.h uint32_t pa_lo; uint32_t 198 drivers/scsi/lpfc/lpfc_bsg.h uint32_t pa_hi; uint32_t 199 drivers/scsi/lpfc/lpfc_bsg.h uint32_t buf_len; uint32_t 206 drivers/scsi/lpfc/lpfc_bsg.h uint32_t buf_len; uint32_t 210 drivers/scsi/lpfc/lpfc_bsg.h uint32_t pa_lo; uint32_t 211 drivers/scsi/lpfc/lpfc_bsg.h uint32_t pa_hi; uint32_t 215 drivers/scsi/lpfc/lpfc_bsg.h uint32_t word1; uint32_t 222 drivers/scsi/lpfc/lpfc_bsg.h uint32_t payload_length; uint32_t 223 drivers/scsi/lpfc/lpfc_bsg.h uint32_t tag_lo; uint32_t 224 drivers/scsi/lpfc/lpfc_bsg.h uint32_t tag_hi; uint32_t 225 drivers/scsi/lpfc/lpfc_bsg.h uint32_t reserved5; uint32_t 232 drivers/scsi/lpfc/lpfc_bsg.h uint32_t padding; uint32_t 233 drivers/scsi/lpfc/lpfc_bsg.h uint32_t word64; uint32_t 250 drivers/scsi/lpfc/lpfc_bsg.h uint32_t word6; uint32_t 266 drivers/scsi/lpfc/lpfc_bsg.h uint32_t timeout; uint32_t 267 drivers/scsi/lpfc/lpfc_bsg.h uint32_t request_length; uint32_t 268 drivers/scsi/lpfc/lpfc_bsg.h uint32_t word9; uint32_t 272 drivers/scsi/lpfc/lpfc_bsg.h uint32_t word10; uint32_t 276 drivers/scsi/lpfc/lpfc_bsg.h uint32_t rd_offset; uint32_t 277 drivers/scsi/lpfc/lpfc_bsg.h uint32_t obj_name[26]; uint32_t 278 drivers/scsi/lpfc/lpfc_bsg.h uint32_t hbd_count; uint32_t 284 drivers/scsi/lpfc/lpfc_bsg.h uint32_t word0; uint32_t 300 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 307 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 311 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 312 drivers/scsi/lpfc/lpfc_bsg.h uint32_t read_size; uint32_t 313 drivers/scsi/lpfc/lpfc_bsg.h uint32_t read_offset; uint32_t 317 drivers/scsi/lpfc/lpfc_bsg.h uint32_t offset; uint32_t 318 drivers/scsi/lpfc/lpfc_bsg.h uint32_t wrap_count; uint32_t 322 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 334 drivers/scsi/lpfc/lpfc_bsg.h uint32_t log_buff_sz; uint32_t 338 drivers/scsi/lpfc/lpfc_bsg.h uint32_t word0; uint32_t 368 drivers/scsi/lpfc/lpfc_bsg.h uint32_t reserved3; uint32_t 372 drivers/scsi/lpfc/lpfc_bsg.h uint32_t command; uint32_t 42 drivers/scsi/lpfc/lpfc_compat.h uint32_t __iomem *dest32; uint32_t 43 drivers/scsi/lpfc/lpfc_compat.h uint32_t *src32; uint32_t 47 drivers/scsi/lpfc/lpfc_compat.h dest32 = (uint32_t __iomem *) dest; uint32_t 48 drivers/scsi/lpfc/lpfc_compat.h src32 = (uint32_t *) src; uint32_t 64 drivers/scsi/lpfc/lpfc_compat.h uint32_t *dest32; uint32_t 65 drivers/scsi/lpfc/lpfc_compat.h uint32_t __iomem *src32; uint32_t 69 drivers/scsi/lpfc/lpfc_compat.h dest32 = (uint32_t *) dest; uint32_t 70 drivers/scsi/lpfc/lpfc_compat.h src32 = (uint32_t __iomem *) src; uint32_t 88 drivers/scsi/lpfc/lpfc_compat.h __iowrite32_copy(dest, src, bytes / sizeof(uint32_t)); uint32_t 35 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_config_async(struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t); uint32_t 46 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_reg_rpi(struct lpfc_hba *, uint16_t, uint32_t, uint8_t *, uint32_t 48 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_set_var(struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t, uint32_t); uint32_t 49 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_unreg_login(struct lpfc_hba *, uint16_t, uint32_t, LPFC_MBOXQ_t *); uint32_t 50 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_unreg_did(struct lpfc_hba *, uint16_t, uint32_t, LPFC_MBOXQ_t *); uint32_t 57 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_init_link(struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t, uint32_t); uint32_t 65 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_vport *lpfc_find_vport_by_did(struct lpfc_hba *, uint32_t); uint32_t 106 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_nodelist *lpfc_nlp_init(struct lpfc_vport *vport, uint32_t did); uint32_t 110 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_nodelist *lpfc_setup_disc_node(struct lpfc_vport *, uint32_t); uint32_t 121 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_workq_post_event(struct lpfc_hba *, void *, void *, uint32_t); uint32_t 124 drivers/scsi/lpfc/lpfc_crtn.h uint32_t); uint32_t 128 drivers/scsi/lpfc/lpfc_crtn.h struct serv_parm *, uint32_t, int); uint32_t 138 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_issue_els_plogi(struct lpfc_vport *, uint32_t, uint8_t); uint32_t 143 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_issue_els_scr(struct lpfc_vport *, uint32_t, uint8_t); uint32_t 148 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_els_rsp_acc(struct lpfc_vport *, uint32_t, struct lpfc_iocbq *, uint32_t 150 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_els_rsp_reject(struct lpfc_vport *, uint32_t, struct lpfc_iocbq *, uint32_t 163 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_rscn_payload_check(struct lpfc_vport *, uint32_t); uint32_t 172 drivers/scsi/lpfc/lpfc_crtn.h uint32_t, uint32_t); uint32_t 181 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_ns_cmd(struct lpfc_vport *, int, uint8_t, uint32_t); uint32_t 182 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_fdmi_cmd(struct lpfc_vport *, struct lpfc_nodelist *, int, uint32_t); uint32_t 192 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_hba_init(struct lpfc_hba *, uint32_t *); uint32_t 247 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_config_hbq(struct lpfc_hba *, uint32_t, struct lpfc_hbq_init *, uint32_t 248 drivers/scsi/lpfc/lpfc_crtn.h uint32_t , LPFC_MBOXQ_t *); uint32_t 292 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_sli_ring *, uint32_t); uint32_t 298 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_sli_cancel_iocbs(struct lpfc_hba *, struct list_head *, uint32_t, uint32_t 299 drivers/scsi/lpfc/lpfc_crtn.h uint32_t); uint32_t 303 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_sli_brdready(struct lpfc_hba *, uint32_t); uint32_t 312 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_sli_issue_mbox(struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t); uint32_t 317 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_sli_ring *, uint32_t); uint32_t 323 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_sli_issue_iocb(struct lpfc_hba *, uint32_t, uint32_t 324 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_iocbq *, uint32_t); uint32_t 330 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_sli_pcimem_bcopy(void *, void *, uint32_t); uint32_t 331 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_sli_bemem_bcopy(void *, void *, uint32_t); uint32_t 342 drivers/scsi/lpfc/lpfc_crtn.h uint32_t lpfc_sli_get_buffer_tag(struct lpfc_hba *); uint32_t 344 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_sli_ring *, uint32_t ); uint32_t 347 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_sli_hbqbuf_add_hbqs(struct lpfc_hba *, uint32_t); uint32_t 362 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_nodelist *lpfc_findnode_did(struct lpfc_vport *, uint32_t); uint32_t 367 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_sli_issue_mbox_wait(struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t); uint32_t 369 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_sli_issue_iocb_wait(struct lpfc_hba *, uint32_t, uint32_t 371 drivers/scsi/lpfc/lpfc_crtn.h uint32_t); uint32_t 426 drivers/scsi/lpfc/lpfc_crtn.h extern void lpfc_debugfs_disc_trc(struct lpfc_vport *, int, char *, uint32_t, uint32_t 427 drivers/scsi/lpfc/lpfc_crtn.h uint32_t, uint32_t); uint32_t 428 drivers/scsi/lpfc/lpfc_crtn.h extern void lpfc_debugfs_slow_ring_trc(struct lpfc_hba *, char *, uint32_t, uint32_t 429 drivers/scsi/lpfc/lpfc_crtn.h uint32_t, uint32_t); uint32_t 431 drivers/scsi/lpfc/lpfc_crtn.h uint16_t data1, uint16_t data2, uint32_t data3); uint32_t 461 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_parse_fcoe_conf(struct lpfc_hba *, uint8_t *, uint32_t); uint32_t 480 drivers/scsi/lpfc/lpfc_crtn.h int __lpfc_sli_issue_iocb(struct lpfc_hba *, uint32_t, uint32_t 481 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_iocbq *, uint32_t); uint32_t 482 drivers/scsi/lpfc/lpfc_crtn.h uint32_t lpfc_drain_txq(struct lpfc_hba *); uint32_t 492 drivers/scsi/lpfc/lpfc_crtn.h uint32_t); uint32_t 495 drivers/scsi/lpfc/lpfc_crtn.h struct lpfc_dmabuf *, uint32_t); uint32_t 497 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_wr_object(struct lpfc_hba *, struct list_head *, uint32_t, uint32_t *); uint32_t 507 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_hba_init_link_fc_topology(struct lpfc_hba *, uint32_t, uint32_t); uint32_t 523 drivers/scsi/lpfc/lpfc_crtn.h uint32_t lpfc_sli_port_speed_get(struct lpfc_hba *); uint32_t 530 drivers/scsi/lpfc/lpfc_crtn.h uint64_t, uint32_t, bool); uint32_t 543 drivers/scsi/lpfc/lpfc_crtn.h uint32_t *, uint32_t *); uint32_t 550 drivers/scsi/lpfc/lpfc_crtn.h int lpfc_sli4_ras_fwlog_init(struct lpfc_hba *phba, uint32_t fwlog_level, uint32_t 551 drivers/scsi/lpfc/lpfc_crtn.h uint32_t fwlog_enable); uint32_t 570 drivers/scsi/lpfc/lpfc_crtn.h void lpfc_nvmet_unsol_fcp_event(struct lpfc_hba *phba, uint32_t idx, uint32_t 82 drivers/scsi/lpfc/lpfc_ct.c struct lpfc_dmabuf *mp, uint32_t size) uint32_t 98 drivers/scsi/lpfc/lpfc_ct.c struct lpfc_dmabuf *mp, uint32_t size) uint32_t 112 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 219 drivers/scsi/lpfc/lpfc_ct.c uint32_t size, int *entries) uint32_t 320 drivers/scsi/lpfc/lpfc_ct.c struct lpfc_nodelist *ndlp, uint32_t usr_flg, uint32_t num_entry, uint32_t 321 drivers/scsi/lpfc/lpfc_ct.c uint32_t tmo, uint8_t retry) uint32_t 413 drivers/scsi/lpfc/lpfc_ct.c uint32_t rsp_size, uint8_t retry) uint32_t 444 drivers/scsi/lpfc/lpfc_ct.c lpfc_find_vport_by_did(struct lpfc_hba *phba, uint32_t did) { uint32_t 460 drivers/scsi/lpfc/lpfc_ct.c lpfc_prep_node_fc4type(struct lpfc_vport *vport, uint32_t Did, uint8_t fc4_type) uint32_t 548 drivers/scsi/lpfc/lpfc_ct.c lpfc_ns_rsp_audit_did(struct lpfc_vport *vport, uint32_t Did, uint8_t fc4_type) uint32_t 593 drivers/scsi/lpfc/lpfc_ct.c uint32_t Size) uint32_t 598 drivers/scsi/lpfc/lpfc_ct.c uint32_t *ctptr = (uint32_t *) & Response->un.gid.PortType; uint32_t 599 drivers/scsi/lpfc/lpfc_ct.c uint32_t Did, CTentry; uint32_t 619 drivers/scsi/lpfc/lpfc_ct.c ctptr = (uint32_t *) mlast->virt; uint32_t 624 drivers/scsi/lpfc/lpfc_ct.c while (Cnt >= sizeof(uint32_t)) { uint32_t 632 drivers/scsi/lpfc/lpfc_ct.c Cnt -= sizeof(uint32_t); uint32_t 773 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) (irsp->un.genreq64.bdl.bdeSize)); uint32_t 784 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->ReasonCode, uint32_t 785 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->Explanation, uint32_t 790 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->CommandResponse.bits.CmdRsp, uint32_t 791 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->ReasonCode, uint32_t 792 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->Explanation); uint32_t 799 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->ReasonCode, uint32_t 800 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->Explanation, uint32_t 805 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->CommandResponse.bits.CmdRsp, uint32_t 806 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->ReasonCode, uint32_t 807 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->Explanation); uint32_t 817 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->ReasonCode, uint32_t 818 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->Explanation, uint32_t 823 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->CommandResponse.bits.CmdRsp, uint32_t 824 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->ReasonCode, uint32_t 825 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) CTrsp->Explanation); uint32_t 970 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)(irsp->un.genreq64.bdl.bdeSize)); uint32_t 981 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->ReasonCode, uint32_t 982 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->Explanation, uint32_t 988 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->CommandResponse.bits.CmdRsp, uint32_t 989 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->ReasonCode, uint32_t 990 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->Explanation); uint32_t 997 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->ReasonCode, uint32_t 998 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->Explanation, uint32_t 1004 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->CommandResponse.bits.CmdRsp, uint32_t 1005 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->ReasonCode, uint32_t 1006 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->Explanation); uint32_t 1014 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->ReasonCode, uint32_t 1015 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->Explanation, uint32_t 1021 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->CommandResponse.bits.CmdRsp, uint32_t 1022 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->ReasonCode, uint32_t 1023 drivers/scsi/lpfc/lpfc_ct.c (uint32_t)CTrsp->Explanation); uint32_t 1194 drivers/scsi/lpfc/lpfc_ct.c uint32_t fc4_data_0, fc4_data_1; uint32_t 1277 drivers/scsi/lpfc/lpfc_ct.c uint32_t latt; uint32_t 1510 drivers/scsi/lpfc/lpfc_ct.c static uint32_t uint32_t 1515 drivers/scsi/lpfc/lpfc_ct.c uint32_t cnt = 0; uint32_t 1539 drivers/scsi/lpfc/lpfc_ct.c uint32_t type; uint32_t 1545 drivers/scsi/lpfc/lpfc_ct.c type = (uint32_t)CtReq->un.gid.Fc4Type; uint32_t 1560 drivers/scsi/lpfc/lpfc_ct.c uint8_t retry, uint32_t context) uint32_t 1569 drivers/scsi/lpfc/lpfc_ct.c uint32_t *ptr; uint32_t 1570 drivers/scsi/lpfc/lpfc_ct.c uint32_t rsp_size = 1024; uint32_t 1711 drivers/scsi/lpfc/lpfc_ct.c ptr = (uint32_t *)CtReq; uint32_t 1794 drivers/scsi/lpfc/lpfc_ct.c ptr = (uint32_t *)CtReq; uint32_t 1859 drivers/scsi/lpfc/lpfc_ct.c uint32_t latt, cmd, err; uint32_t 2057 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2074 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2099 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2121 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2142 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2165 drivers/scsi/lpfc/lpfc_ct.c uint32_t i, j, incr, size; uint32_t 2195 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2217 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2242 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2262 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2285 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2290 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2301 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2320 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2326 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2337 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2343 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2354 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2373 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2394 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2400 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2411 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2434 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2460 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2502 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2514 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2572 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2584 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2589 drivers/scsi/lpfc/lpfc_ct.c ae->un.AttrInt = (((uint32_t) hsp->cmn.bbRcvSizeMsb & 0x0F) << 8) | uint32_t 2590 drivers/scsi/lpfc/lpfc_ct.c (uint32_t) hsp->cmn.bbRcvSizeLsb; uint32_t 2592 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2604 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2625 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2646 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2664 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2682 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2701 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2708 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2719 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2723 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2734 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2752 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2776 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2781 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2792 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2797 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2808 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2812 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2823 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2844 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2865 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2887 drivers/scsi/lpfc/lpfc_ct.c uint32_t len, size; uint32_t 2907 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2916 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2927 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2931 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 2942 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 2946 drivers/scsi/lpfc/lpfc_ct.c size = FOURBYTES + sizeof(uint32_t); uint32_t 3016 drivers/scsi/lpfc/lpfc_ct.c int cmdcode, uint32_t new_mask) uint32_t 3022 drivers/scsi/lpfc/lpfc_ct.c uint32_t bit_pos; uint32_t 3023 drivers/scsi/lpfc/lpfc_ct.c uint32_t size; uint32_t 3024 drivers/scsi/lpfc/lpfc_ct.c uint32_t rsp_size; uint32_t 3025 drivers/scsi/lpfc/lpfc_ct.c uint32_t mask; uint32_t 3261 drivers/scsi/lpfc/lpfc_ct.c uint32_t tmo_posted; uint32_t 3303 drivers/scsi/lpfc/lpfc_ct.c uint32_t b1, b2, b3, b4, i, rev; uint32_t 3305 drivers/scsi/lpfc/lpfc_ct.c uint32_t *ptr, str[4]; uint32_t 3349 drivers/scsi/lpfc/lpfc_ct.c ptr = (uint32_t*)fwname; uint32_t 151 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t ms; uint32_t 217 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t ms; uint32_t 286 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t phys, raw_index, getidx; uint32_t 669 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t *ptr; uint32_t 683 drivers/scsi/lpfc/lpfc_debugfs.c ptr = (uint32_t *)&buffer[0]; uint32_t 698 drivers/scsi/lpfc/lpfc_debugfs.c i -= (8 * sizeof(uint32_t)); uint32_t 699 drivers/scsi/lpfc/lpfc_debugfs.c off += (8 * sizeof(uint32_t)); uint32_t 728 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t word0, word1, word2, word3; uint32_t 729 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t *ptr; uint32_t 738 drivers/scsi/lpfc/lpfc_debugfs.c ptr = (uint32_t *)phba->slim2p.virt; uint32_t 746 drivers/scsi/lpfc/lpfc_debugfs.c i -= (8 * sizeof(uint32_t)); uint32_t 747 drivers/scsi/lpfc/lpfc_debugfs.c off += (8 * sizeof(uint32_t)); uint32_t 751 drivers/scsi/lpfc/lpfc_debugfs.c ptr = (uint32_t *)phba->pcb; uint32_t 759 drivers/scsi/lpfc/lpfc_debugfs.c i -= (8 * sizeof(uint32_t)); uint32_t 760 drivers/scsi/lpfc/lpfc_debugfs.c off += (8 * sizeof(uint32_t)); uint32_t 1624 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t tot_xmt; uint32_t 1625 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t tot_rcv; uint32_t 1626 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t tot_cmpl; uint32_t 1711 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t data1, uint32_t data2, uint32_t data3) uint32_t 1752 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t data1, uint32_t data2, uint32_t data3) uint32_t 1790 drivers/scsi/lpfc/lpfc_debugfs.c uint16_t data1, uint16_t data2, uint32_t data3) uint32_t 2231 drivers/scsi/lpfc/lpfc_debugfs.c phba->lpfc_injerr_wgrd_cnt = (uint32_t)tmp; uint32_t 2233 drivers/scsi/lpfc/lpfc_debugfs.c phba->lpfc_injerr_wapp_cnt = (uint32_t)tmp; uint32_t 2235 drivers/scsi/lpfc/lpfc_debugfs.c phba->lpfc_injerr_wref_cnt = (uint32_t)tmp; uint32_t 2237 drivers/scsi/lpfc/lpfc_debugfs.c phba->lpfc_injerr_rgrd_cnt = (uint32_t)tmp; uint32_t 2239 drivers/scsi/lpfc/lpfc_debugfs.c phba->lpfc_injerr_rapp_cnt = (uint32_t)tmp; uint32_t 2241 drivers/scsi/lpfc/lpfc_debugfs.c phba->lpfc_injerr_rref_cnt = (uint32_t)tmp; uint32_t 2245 drivers/scsi/lpfc/lpfc_debugfs.c phba->lpfc_injerr_nportid = (uint32_t)(tmp & Mask_DID); uint32_t 2791 drivers/scsi/lpfc/lpfc_debugfs.c phba->nvmeio_trc_size = (uint32_t)sz; uint32_t 2804 drivers/scsi/lpfc/lpfc_debugfs.c phba->nvmeio_trc_size = (uint32_t)sz; uint32_t 3102 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t u32val; uint32_t 3168 drivers/scsi/lpfc/lpfc_debugfs.c offset += sizeof(uint32_t); uint32_t 3174 drivers/scsi/lpfc/lpfc_debugfs.c index -= sizeof(uint32_t); uint32_t 3178 drivers/scsi/lpfc/lpfc_debugfs.c else if (!(index % (8 * sizeof(uint32_t)))) { uint32_t 3179 drivers/scsi/lpfc/lpfc_debugfs.c offset_label += (8 * sizeof(uint32_t)); uint32_t 3220 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t where, value, count; uint32_t 3221 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t u32val; uint32_t 3246 drivers/scsi/lpfc/lpfc_debugfs.c if (where % sizeof(uint32_t)) uint32_t 3252 drivers/scsi/lpfc/lpfc_debugfs.c (count != sizeof(uint32_t))) uint32_t 3266 drivers/scsi/lpfc/lpfc_debugfs.c if (count == sizeof(uint32_t)) { uint32_t 3267 drivers/scsi/lpfc/lpfc_debugfs.c if (where > LPFC_PCI_CFG_SIZE - sizeof(uint32_t)) uint32_t 3269 drivers/scsi/lpfc/lpfc_debugfs.c if (where % sizeof(uint32_t)) uint32_t 3285 drivers/scsi/lpfc/lpfc_debugfs.c (count != sizeof(uint32_t))) uint32_t 3337 drivers/scsi/lpfc/lpfc_debugfs.c if (count == sizeof(uint32_t)) { uint32_t 3338 drivers/scsi/lpfc/lpfc_debugfs.c if (where > LPFC_PCI_CFG_SIZE - sizeof(uint32_t)) uint32_t 3340 drivers/scsi/lpfc/lpfc_debugfs.c if (where % sizeof(uint32_t)) uint32_t 3398 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t if_type; uint32_t 3400 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t u32val; uint32_t 3472 drivers/scsi/lpfc/lpfc_debugfs.c offset_run += sizeof(uint32_t); uint32_t 3481 drivers/scsi/lpfc/lpfc_debugfs.c (acc_range * sizeof(uint32_t))) { uint32_t 3487 drivers/scsi/lpfc/lpfc_debugfs.c index -= sizeof(uint32_t); uint32_t 3491 drivers/scsi/lpfc/lpfc_debugfs.c else if (!(index % (8 * sizeof(uint32_t)))) { uint32_t 3492 drivers/scsi/lpfc/lpfc_debugfs.c offset_label += (8 * sizeof(uint32_t)); uint32_t 3507 drivers/scsi/lpfc/lpfc_debugfs.c (acc_range * sizeof(uint32_t))) uint32_t 3545 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t bar_num, bar_size, offset, value, acc_range; uint32_t 3548 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t if_type; uint32_t 3549 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t u32val; uint32_t 3603 drivers/scsi/lpfc/lpfc_debugfs.c if (offset % sizeof(uint32_t)) uint32_t 3613 drivers/scsi/lpfc/lpfc_debugfs.c if (offset > bar_size - sizeof(uint32_t)) uint32_t 3618 drivers/scsi/lpfc/lpfc_debugfs.c if (offset + acc_range * sizeof(uint32_t) > bar_size) uint32_t 4006 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t index) uint32_t 4009 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t *pentry; uint32_t 4024 drivers/scsi/lpfc/lpfc_debugfs.c offset += sizeof(uint32_t); uint32_t 4025 drivers/scsi/lpfc/lpfc_debugfs.c esize -= sizeof(uint32_t); uint32_t 4026 drivers/scsi/lpfc/lpfc_debugfs.c if (esize > 0 && !(offset % (4 * sizeof(uint32_t)))) uint32_t 4057 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t last_index, index, count; uint32_t 4135 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t qidx, quetp, queid, index, count, offset, value; uint32_t 4136 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t *pentry; uint32_t 4338 drivers/scsi/lpfc/lpfc_debugfs.c if (offset > pque->entry_size/sizeof(uint32_t) - 1) uint32_t 4373 drivers/scsi/lpfc/lpfc_debugfs.c int len, uint32_t drbregid) uint32_t 4435 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t drb_reg_id, i; uint32_t 4491 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t drb_reg_id, value, reg_val = 0; uint32_t 4583 drivers/scsi/lpfc/lpfc_debugfs.c int len, uint32_t ctlregid) uint32_t 4653 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t ctl_reg_id, i; uint32_t 4706 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t ctl_reg_id, value, reg_val = 0; uint32_t 4806 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t mbx_dump_map, mbx_dump_cnt, mbx_word_cnt, mbx_mbox_cmd; uint32_t 4891 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t mbx_dump_map, mbx_dump_cnt, mbx_word_cnt, mbx_mbox_cmd; uint32_t 5165 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t ext_map; uint32_t 5213 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t ext_map; uint32_t 5474 drivers/scsi/lpfc/lpfc_debugfs.c struct lpfc_dmabuf *dmabuf, uint32_t ext_buf) uint32_t 5477 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t *mbx_mbox_cmd, *mbx_dump_map, *mbx_dump_cnt, *mbx_word_cnt; uint32_t 5480 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t do_dump = 0; uint32_t 5481 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t *pword; uint32_t 5482 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t i; uint32_t 5535 drivers/scsi/lpfc/lpfc_debugfs.c pword = (uint32_t *)dmabuf->virt; uint32_t 5546 drivers/scsi/lpfc/lpfc_debugfs.c "%08x ", (uint32_t)*pword); uint32_t 5573 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t *mbx_dump_map, *mbx_dump_cnt, *mbx_word_cnt, *mbx_mbox_cmd; uint32_t 5576 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t *pword; uint32_t 5578 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t i, j; uint32_t 5601 drivers/scsi/lpfc/lpfc_debugfs.c pword = (uint32_t *)pmbox; uint32_t 5614 drivers/scsi/lpfc/lpfc_debugfs.c ((uint32_t)*pword) & 0xffffffff); uint32_t 5674 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t num, i; uint32_t 203 drivers/scsi/lpfc/lpfc_debugfs.h #define SIZE_U32 sizeof(uint32_t) uint32_t 222 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t data1; uint32_t 223 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t data2; uint32_t 224 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t data3; uint32_t 225 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t seq_cnt; uint32_t 233 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t data3; uint32_t 237 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t last_rd; uint32_t 242 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t opcode; uint32_t 273 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t data[LPFC_IDIAG_CMD_DATA_SIZE]; uint32_t 277 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t active; uint32_t 333 drivers/scsi/lpfc/lpfc_debugfs.h lpfc_debug_dump_qe(struct lpfc_queue *q, uint32_t idx) uint32_t 337 drivers/scsi/lpfc/lpfc_debugfs.h uint32_t *pword; uint32_t 346 drivers/scsi/lpfc/lpfc_debugfs.h qe_word_cnt = esize / sizeof(uint32_t); uint32_t 366 drivers/scsi/lpfc/lpfc_debugfs.h ((uint32_t)*pword) & 0xffffffff); uint32_t 83 drivers/scsi/lpfc/lpfc_disc.h uint32_t nlp_flag; /* entry flags */ uint32_t 84 drivers/scsi/lpfc/lpfc_disc.h uint32_t nlp_DID; /* FC D_ID of entry */ uint32_t 85 drivers/scsi/lpfc/lpfc_disc.h uint32_t nlp_last_elscmd; /* Last ELS cmd sent */ uint32_t 133 drivers/scsi/lpfc/lpfc_disc.h uint32_t cmd_qdepth; uint32_t 137 drivers/scsi/lpfc/lpfc_disc.h uint32_t fc4_prli_sent; uint32_t 138 drivers/scsi/lpfc/lpfc_disc.h uint32_t upcall_flags; uint32_t 141 drivers/scsi/lpfc/lpfc_disc.h uint32_t nvme_fb_size; /* NVME target's supported byte cnt */ uint32_t 143 drivers/scsi/lpfc/lpfc_disc.h uint32_t nlp_defer_did; uint32_t 150 drivers/scsi/lpfc/lpfc_disc.h uint32_t nlp_DID; /* FC D_ID of entry */ uint32_t 88 drivers/scsi/lpfc/lpfc_els.c uint32_t ha_copy; uint32_t 155 drivers/scsi/lpfc/lpfc_els.c struct lpfc_nodelist *ndlp, uint32_t did, uint32_t 156 drivers/scsi/lpfc/lpfc_els.c uint32_t elscmd) uint32_t 1114 drivers/scsi/lpfc/lpfc_els.c sp = prsp->virt + sizeof(uint32_t); uint32_t 1223 drivers/scsi/lpfc/lpfc_els.c uint32_t *pcmd; uint32_t 1224 drivers/scsi/lpfc/lpfc_els.c uint32_t cmd; uint32_t 1226 drivers/scsi/lpfc/lpfc_els.c pcmd = (uint32_t *)(((struct lpfc_dmabuf *)cmdiocb->context2)->virt); uint32_t 1276 drivers/scsi/lpfc/lpfc_els.c uint32_t tmo, did; uint32_t 1279 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(uint32_t) + sizeof(struct serv_parm)); uint32_t 1290 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_FLOGI; uint32_t 1291 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 1596 drivers/scsi/lpfc/lpfc_els.c lpfc_plogi_confirm_nport(struct lpfc_hba *phba, uint32_t *prsp, uint32_t 1606 drivers/scsi/lpfc/lpfc_els.c uint32_t rc, keepDID = 0, keep_nlp_flag = 0; uint32_t 1607 drivers/scsi/lpfc/lpfc_els.c uint32_t keep_new_nlp_flag = 0; uint32_t 1621 drivers/scsi/lpfc/lpfc_els.c sp = (struct serv_parm *) ((uint8_t *) prsp + sizeof(uint32_t)); uint32_t 2121 drivers/scsi/lpfc/lpfc_els.c lpfc_issue_els_plogi(struct lpfc_vport *vport, uint32_t did, uint8_t retry) uint32_t 2158 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(uint32_t) + sizeof(struct serv_parm)); uint32_t 2172 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_PLOGI; uint32_t 2173 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 2372 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(uint32_t) + sizeof(PRLI)); uint32_t 2376 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(uint32_t) + sizeof(struct lpfc_nvme_prli)); uint32_t 2413 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *)(pcmd)) = ELS_CMD_PRLI; uint32_t 2414 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 2443 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *)(pcmd)) = ELS_CMD_NVMEPRLI; uint32_t 2444 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 2750 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(uint32_t) + sizeof(ADISC)); uint32_t 2759 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ADISC; uint32_t 2760 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 2811 drivers/scsi/lpfc/lpfc_els.c uint32_t skip_recovery = 0; uint32_t 2961 drivers/scsi/lpfc/lpfc_els.c cmdsize = (2 * sizeof(uint32_t)) + sizeof(struct lpfc_name); uint32_t 2968 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_LOGO; uint32_t 2969 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 2972 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = be32_to_cpu(vport->fc_myDID); uint32_t 2973 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 3065 drivers/scsi/lpfc/lpfc_els.c lpfc_issue_els_scr(struct lpfc_vport *vport, uint32_t nportid, uint8_t retry) uint32_t 3073 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(uint32_t) + sizeof(SCR)); uint32_t 3100 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_SCR; uint32_t 3101 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 3161 drivers/scsi/lpfc/lpfc_els.c uint32_t nportid; uint32_t 3264 drivers/scsi/lpfc/lpfc_els.c lpfc_issue_els_farpr(struct lpfc_vport *vport, uint32_t nportid, uint8_t retry) uint32_t 3270 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp; uint32_t 3275 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(uint32_t) + sizeof(FARP)); uint32_t 3301 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_FARPR; uint32_t 3302 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 3307 drivers/scsi/lpfc/lpfc_els.c lp = (uint32_t *) pcmd; uint32_t 3457 drivers/scsi/lpfc/lpfc_els.c uint32_t cmd, retry; uint32_t 3533 drivers/scsi/lpfc/lpfc_els.c uint32_t control; uint32_t 3602 drivers/scsi/lpfc/lpfc_els.c uint32_t *elscmd; uint32_t 3606 drivers/scsi/lpfc/lpfc_els.c uint32_t cmd = 0; uint32_t 3607 drivers/scsi/lpfc/lpfc_els.c uint32_t did; uint32_t 3616 drivers/scsi/lpfc/lpfc_els.c elscmd = (uint32_t *) (pcmd->virt); uint32_t 3633 drivers/scsi/lpfc/lpfc_els.c *(((uint32_t *) irsp) + 7), irsp->un.ulpWord[4], ndlp->nlp_DID); uint32_t 4300 drivers/scsi/lpfc/lpfc_els.c uint32_t ls_rjt = 0; uint32_t 4312 drivers/scsi/lpfc/lpfc_els.c (*((uint32_t *) (pcmd)) == ELS_CMD_LS_RJT)) { uint32_t 4493 drivers/scsi/lpfc/lpfc_els.c lpfc_els_rsp_acc(struct lpfc_vport *vport, uint32_t flag, uint32_t 4512 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(uint32_t); uint32_t 4526 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 4527 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 4535 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(struct serv_parm) + sizeof(uint32_t)); uint32_t 4549 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 4550 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 4597 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(uint32_t) + sizeof(PRLO); uint32_t 4609 drivers/scsi/lpfc/lpfc_els.c sizeof(uint32_t) + sizeof(PRLO)); uint32_t 4610 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_PRLO_ACC; uint32_t 4664 drivers/scsi/lpfc/lpfc_els.c lpfc_els_rsp_reject(struct lpfc_vport *vport, uint32_t rejectError, uint32_t 4676 drivers/scsi/lpfc/lpfc_els.c cmdsize = 2 * sizeof(uint32_t); uint32_t 4688 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_LS_RJT; uint32_t 4689 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 4690 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = rejectError; uint32_t 4749 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(uint32_t) + sizeof(ADISC); uint32_t 4769 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 4770 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 4833 drivers/scsi/lpfc/lpfc_els.c uint32_t prli_fc4_req, *req_payload; uint32_t 4842 drivers/scsi/lpfc/lpfc_els.c req_payload = (((uint32_t *)req_buf->virt) + 1); uint32_t 4849 drivers/scsi/lpfc/lpfc_els.c prli_fc4_req, *((uint32_t *)req_payload)); uint32_t 4852 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(uint32_t) + sizeof(PRLI); uint32_t 4855 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(uint32_t) + sizeof(struct lpfc_nvme_prli); uint32_t 4881 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *)(pcmd)) = elsrspcmd; uint32_t 4882 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 4998 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(uint32_t) + sizeof(uint32_t) uint32_t 5018 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 5019 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 5081 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 5148 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 5149 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 5150 drivers/scsi/lpfc/lpfc_els.c memcpy(pcmd, data, cmdsize - sizeof(uint32_t)); uint32_t 5284 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5286 drivers/scsi/lpfc/lpfc_els.c uint32_t word0) uint32_t 5296 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5361 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5365 drivers/scsi/lpfc/lpfc_els.c uint32_t type; uint32_t 5390 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5394 drivers/scsi/lpfc/lpfc_els.c uint32_t bbCredit; uint32_t 5415 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5419 drivers/scsi/lpfc/lpfc_els.c uint32_t flags = 0; uint32_t 5443 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5448 drivers/scsi/lpfc/lpfc_els.c uint32_t flags = 0; uint32_t 5472 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5477 drivers/scsi/lpfc/lpfc_els.c uint32_t flags = 0; uint32_t 5501 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5506 drivers/scsi/lpfc/lpfc_els.c uint32_t flags = 0; uint32_t 5531 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5536 drivers/scsi/lpfc/lpfc_els.c uint32_t flags = 0; uint32_t 5560 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5574 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5591 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5660 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5677 drivers/scsi/lpfc/lpfc_els.c static uint32_t uint32_t 5713 drivers/scsi/lpfc/lpfc_els.c uint32_t cmdsize, len; uint32_t 5744 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 5808 drivers/scsi/lpfc/lpfc_els.c cmdsize = 2 * sizeof(uint32_t); uint32_t 5820 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_LS_RJT; uint32_t 5821 drivers/scsi/lpfc/lpfc_els.c stat = (struct ls_rjt *)(pcmd + sizeof(uint32_t)); uint32_t 5972 drivers/scsi/lpfc/lpfc_els.c uint32_t cmdsize, shdr_status, shdr_add_status; uint32_t 6020 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *)(pcmd)) = ELS_CMD_ACC; uint32_t 6049 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *)(pcmd)) = ELS_CMD_LS_RJT; uint32_t 6050 drivers/scsi/lpfc/lpfc_els.c stat = (struct ls_rjt *)(pcmd + sizeof(uint32_t)); uint32_t 6068 drivers/scsi/lpfc/lpfc_els.c uint32_t beacon_state) uint32_t 6073 drivers/scsi/lpfc/lpfc_els.c uint32_t len; uint32_t 6275 drivers/scsi/lpfc/lpfc_els.c lpfc_rscn_payload_check(struct lpfc_vport *vport, uint32_t did) uint32_t 6279 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp; uint32_t 6280 drivers/scsi/lpfc/lpfc_els.c uint32_t payload_len, i; uint32_t 6305 drivers/scsi/lpfc/lpfc_els.c payload_len -= sizeof(uint32_t); /* take off word 0 */ uint32_t 6308 drivers/scsi/lpfc/lpfc_els.c payload_len -= sizeof(uint32_t); uint32_t 6406 drivers/scsi/lpfc/lpfc_els.c uint32_t *payload_ptr; uint32_t 6407 drivers/scsi/lpfc/lpfc_els.c uint32_t payload_len; uint32_t 6411 drivers/scsi/lpfc/lpfc_els.c payload_ptr = (uint32_t *) pcmd->virt; uint32_t 6464 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp, *datap; uint32_t 6465 drivers/scsi/lpfc/lpfc_els.c uint32_t payload_len, length, nportid, *cmd; uint32_t 6471 drivers/scsi/lpfc/lpfc_els.c lp = (uint32_t *) pcmd->virt; uint32_t 6474 drivers/scsi/lpfc/lpfc_els.c payload_len -= sizeof(uint32_t); /* take off word 0 */ uint32_t 6484 drivers/scsi/lpfc/lpfc_els.c for (i = 0; i < payload_len/sizeof(uint32_t); i++) uint32_t 6527 drivers/scsi/lpfc/lpfc_els.c i -= sizeof(uint32_t); uint32_t 6771 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp = (uint32_t *) pcmd->virt; uint32_t 6775 drivers/scsi/lpfc/lpfc_els.c uint32_t cmd, did; uint32_t 6777 drivers/scsi/lpfc/lpfc_els.c uint32_t fc_flag = 0; uint32_t 6778 drivers/scsi/lpfc/lpfc_els.c uint32_t port_state = 0; uint32_t 6932 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp; uint32_t 6937 drivers/scsi/lpfc/lpfc_els.c lp = (uint32_t *) pcmd->virt; uint32_t 6980 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 7069 drivers/scsi/lpfc/lpfc_els.c uint32_t cmdsize; uint32_t 7084 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(struct RLS_RSP) + sizeof(uint32_t); uint32_t 7102 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 7103 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* Skip past command */ uint32_t 7157 drivers/scsi/lpfc/lpfc_els.c uint32_t cmdsize; uint32_t 7172 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(RPS_RSP) + sizeof(uint32_t); uint32_t 7189 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 7190 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* Skip past command */ uint32_t 7312 drivers/scsi/lpfc/lpfc_els.c uint32_t cmdsize; uint32_t 7320 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(struct RTV_RSP) + sizeof(uint32_t); uint32_t 7329 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 7330 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* Skip past command */ uint32_t 7392 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp; uint32_t 7405 drivers/scsi/lpfc/lpfc_els.c lp = (uint32_t *) pcmd->virt; uint32_t 7462 drivers/scsi/lpfc/lpfc_els.c uint32_t did, struct lpfc_node_rrq *rrq) uint32_t 7478 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(uint32_t) + sizeof(struct RRQ)); uint32_t 7487 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_RRQ; uint32_t 7488 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 7580 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_ACC; uint32_t 7592 drivers/scsi/lpfc/lpfc_els.c memcpy(pcmd, &rpl_rsp, cmdsize - sizeof(uint32_t)); uint32_t 7632 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp; uint32_t 7633 drivers/scsi/lpfc/lpfc_els.c uint32_t maxsize; uint32_t 7652 drivers/scsi/lpfc/lpfc_els.c lp = (uint32_t *) pcmd->virt; uint32_t 7659 drivers/scsi/lpfc/lpfc_els.c ((maxsize * sizeof(uint32_t)) >= sizeof(RPL_RSP)))) { uint32_t 7660 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(uint32_t) + sizeof(RPL_RSP); uint32_t 7662 drivers/scsi/lpfc/lpfc_els.c cmdsize = sizeof(uint32_t) + maxsize * sizeof(uint32_t); uint32_t 7698 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp; uint32_t 7701 drivers/scsi/lpfc/lpfc_els.c uint32_t cnt, did; uint32_t 7706 drivers/scsi/lpfc/lpfc_els.c lp = (uint32_t *) pcmd->virt; uint32_t 7771 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp; uint32_t 7773 drivers/scsi/lpfc/lpfc_els.c uint32_t did; uint32_t 7778 drivers/scsi/lpfc/lpfc_els.c lp = (uint32_t *) pcmd->virt; uint32_t 7814 drivers/scsi/lpfc/lpfc_els.c uint32_t *lp; uint32_t 7818 drivers/scsi/lpfc/lpfc_els.c lp = (uint32_t *)((struct lpfc_dmabuf *)cmdiocb->context2)->virt; uint32_t 7860 drivers/scsi/lpfc/lpfc_els.c uint32_t tmo_posted; uint32_t 7892 drivers/scsi/lpfc/lpfc_els.c uint32_t els_command = 0; uint32_t 7893 drivers/scsi/lpfc/lpfc_els.c uint32_t timeout; uint32_t 7894 drivers/scsi/lpfc/lpfc_els.c uint32_t remote_ID = 0xffffffff; uint32_t 7898 drivers/scsi/lpfc/lpfc_els.c timeout = (uint32_t)(phba->fc_ratov << 1); uint32_t 7930 drivers/scsi/lpfc/lpfc_els.c els_command = *(uint32_t *) (pcmd->virt); uint32_t 8175 drivers/scsi/lpfc/lpfc_els.c uint32_t *pcmd; uint32_t 8188 drivers/scsi/lpfc/lpfc_els.c pcmd = (uint32_t *) (((struct lpfc_dmabuf *) uint32_t 8234 drivers/scsi/lpfc/lpfc_els.c uint32_t *payload) uint32_t 8323 drivers/scsi/lpfc/lpfc_els.c uint32_t *payload; uint32_t 8324 drivers/scsi/lpfc/lpfc_els.c uint32_t cmd, did, newnode; uint32_t 9128 drivers/scsi/lpfc/lpfc_els.c uint32_t link_state; uint32_t 9283 drivers/scsi/lpfc/lpfc_els.c sp = prsp->virt + sizeof(uint32_t); uint32_t 9382 drivers/scsi/lpfc/lpfc_els.c cmdsize = (sizeof(uint32_t) + sizeof(struct serv_parm)); uint32_t 9406 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_FDISC; uint32_t 9407 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* CSP Word 1 */ uint32_t 9418 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* CSP Word 2 */ uint32_t 9419 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* CSP Word 3 */ uint32_t 9420 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* CSP Word 4 */ uint32_t 9421 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* Port Name */ uint32_t 9423 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* Node Name */ uint32_t 9424 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); /* Node Name */ uint32_t 9525 drivers/scsi/lpfc/lpfc_els.c cmdsize = 2 * sizeof(uint32_t) + sizeof(struct lpfc_name); uint32_t 9532 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = ELS_CMD_LOGO; uint32_t 9533 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 9536 drivers/scsi/lpfc/lpfc_els.c *((uint32_t *) (pcmd)) = be32_to_cpu(vport->fc_myDID); uint32_t 9537 drivers/scsi/lpfc/lpfc_els.c pcmd += sizeof(uint32_t); uint32_t 9575 drivers/scsi/lpfc/lpfc_els.c uint32_t tmo_posted; uint32_t 349 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t nlp_did) uint32_t 457 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t evt_data_size; uint32_t 524 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t nlp_did; uint32_t 616 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t ha_copy, status, control, work_port_events; uint32_t 781 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t evt) uint32_t 1082 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t control; uint32_t 1272 drivers/scsi/lpfc/lpfc_hbadisc.c static uint32_t uint32_t 1303 drivers/scsi/lpfc/lpfc_hbadisc.c static uint32_t uint32_t 1334 drivers/scsi/lpfc/lpfc_hbadisc.c static uint32_t uint32_t 1458 drivers/scsi/lpfc/lpfc_hbadisc.c struct fcf_record *new_fcf_record, uint32_t addr_mode, uint32_t 1459 drivers/scsi/lpfc/lpfc_hbadisc.c uint16_t vlan_id, uint32_t flag) uint32_t 1554 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t *boot_flag, uint32_t *addr_mode, uint32_t 1806 drivers/scsi/lpfc/lpfc_hbadisc.c lpfc_sli4_new_fcf_random_select(struct lpfc_hba *phba, uint32_t fcf_cnt) uint32_t 1808 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t rand_num; uint32_t 1840 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t shdr_status, shdr_add_status, if_type; uint32_t 2230 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t boot_flag, addr_mode; uint32_t 2606 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t boot_flag, addr_mode; uint32_t 2712 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t boot_flag, addr_mode; uint32_t 3063 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t ed_tov; uint32_t 3129 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t fc_flags = 0; uint32_t 3191 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t wd1; uint32_t 3192 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t wd2; uint32_t 3193 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t wd3; uint32_t 3194 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t wd4; uint32_t 3355 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t control; uint32_t 3739 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t byte_count = 0; uint32_t 4478 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t did) uint32_t 4500 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t did, flag; uint32_t 4504 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t defer_did = 0; uint32_t 4633 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t tmo; uint32_t 4765 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t i; uint32_t 5268 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t did) uint32_t 5323 drivers/scsi/lpfc/lpfc_hbadisc.c __lpfc_findnode_did(struct lpfc_vport *vport, uint32_t did) uint32_t 5326 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t data1; uint32_t 5330 drivers/scsi/lpfc/lpfc_hbadisc.c data1 = (((uint32_t)ndlp->nlp_state << 24) | uint32_t 5331 drivers/scsi/lpfc/lpfc_hbadisc.c ((uint32_t)ndlp->nlp_xri << 16) | uint32_t 5332 drivers/scsi/lpfc/lpfc_hbadisc.c ((uint32_t)ndlp->nlp_type << 8) | uint32_t 5333 drivers/scsi/lpfc/lpfc_hbadisc.c ((uint32_t)ndlp->nlp_usg_map & 0xff)); uint32_t 5351 drivers/scsi/lpfc/lpfc_hbadisc.c lpfc_findnode_did(struct lpfc_vport *vport, uint32_t did) uint32_t 5368 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t data1; uint32_t 5376 drivers/scsi/lpfc/lpfc_hbadisc.c data1 = (((uint32_t)ndlp->nlp_state << 24) | uint32_t 5377 drivers/scsi/lpfc/lpfc_hbadisc.c ((uint32_t)ndlp->nlp_xri << 16) | uint32_t 5378 drivers/scsi/lpfc/lpfc_hbadisc.c ((uint32_t)ndlp->nlp_type << 8) | uint32_t 5379 drivers/scsi/lpfc/lpfc_hbadisc.c ((uint32_t)ndlp->nlp_rpi & 0xff)); uint32_t 5399 drivers/scsi/lpfc/lpfc_hbadisc.c lpfc_setup_disc_node(struct lpfc_vport *vport, uint32_t did) uint32_t 5503 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t alpa, index; uint32_t 5598 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t num_sent; uint32_t 5599 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t clear_la_pending; uint32_t 5787 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t tmo_posted; uint32_t 6219 drivers/scsi/lpfc/lpfc_hbadisc.c lpfc_nlp_init(struct lpfc_vport *vport, uint32_t did) uint32_t 6779 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t record_count; uint32_t 6790 drivers/scsi/lpfc/lpfc_hbadisc.c record_count = conn_hdr->length * sizeof(uint32_t)/ uint32_t 6894 drivers/scsi/lpfc/lpfc_hbadisc.c lpfc_get_rec_conf23(uint8_t *buff, uint32_t size, uint8_t rec_type) uint32_t 6896 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t offset = 0, rec_length; uint32_t 6899 drivers/scsi/lpfc/lpfc_hbadisc.c (size < sizeof(uint32_t))) uint32_t 6908 drivers/scsi/lpfc/lpfc_hbadisc.c while ((offset + rec_length * sizeof(uint32_t) + sizeof(uint32_t)) uint32_t 6916 drivers/scsi/lpfc/lpfc_hbadisc.c offset += rec_length * sizeof(uint32_t) + sizeof(uint32_t); uint32_t 6934 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t size) uint32_t 6936 drivers/scsi/lpfc/lpfc_hbadisc.c uint32_t offset = 0; uint32_t 6943 drivers/scsi/lpfc/lpfc_hbadisc.c if (size < 2*sizeof(uint32_t)) uint32_t 80 drivers/scsi/lpfc/lpfc_hw.h uint32_t Revision:8; uint32_t 81 drivers/scsi/lpfc/lpfc_hw.h uint32_t InId:24; uint32_t 83 drivers/scsi/lpfc/lpfc_hw.h uint32_t word; uint32_t 89 drivers/scsi/lpfc/lpfc_hw.h uint32_t CmdRsp:16; uint32_t 90 drivers/scsi/lpfc/lpfc_hw.h uint32_t Size:16; uint32_t 92 drivers/scsi/lpfc/lpfc_hw.h uint32_t word; uint32_t 115 drivers/scsi/lpfc/lpfc_hw.h uint32_t PortID; uint32_t 134 drivers/scsi/lpfc/lpfc_hw.h uint32_t PortId; /* For RFT_ID requests */ uint32_t 137 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd0:16; uint32_t 138 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:7; uint32_t 139 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpReg:1; /* Type 8 */ uint32_t 140 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:2; uint32_t 141 drivers/scsi/lpfc/lpfc_hw.h uint32_t ipReg:1; /* Type 5 */ uint32_t 142 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:5; uint32_t 144 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd0:16; uint32_t 145 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpReg:1; /* Type 8 */ uint32_t 146 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:7; uint32_t 147 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:5; uint32_t 148 drivers/scsi/lpfc/lpfc_hw.h uint32_t ipReg:1; /* Type 5 */ uint32_t 149 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:2; uint32_t 152 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd[7]; uint32_t 155 drivers/scsi/lpfc/lpfc_hw.h uint32_t PortId; /* For RNN_ID requests */ uint32_t 164 drivers/scsi/lpfc/lpfc_hw.h uint32_t port_id; uint32_t 167 drivers/scsi/lpfc/lpfc_hw.h uint32_t PortId; uint32_t 172 drivers/scsi/lpfc/lpfc_hw.h uint32_t PortId; uint32_t 178 drivers/scsi/lpfc/lpfc_hw.h uint32_t PortId; uint32_t 181 drivers/scsi/lpfc/lpfc_hw.h uint32_t fc4_types[8]; uint32_t 185 drivers/scsi/lpfc/lpfc_hw.h uint32_t PortId; uint32_t 440 drivers/scsi/lpfc/lpfc_hw.h uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ uint32_t 443 drivers/scsi/lpfc/lpfc_hw.h uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ uint32_t 526 drivers/scsi/lpfc/lpfc_hw.h uint32_t vid; uint32_t 528 drivers/scsi/lpfc/lpfc_hw.h uint32_t flags; uint32_t 538 drivers/scsi/lpfc/lpfc_hw.h uint32_t word0; uint32_t 557 drivers/scsi/lpfc/lpfc_hw.h uint32_t word1; uint32_t 660 drivers/scsi/lpfc/lpfc_hw.h uint32_t lsRjtError; uint32_t 711 drivers/scsi/lpfc/lpfc_hw.h uint32_t nPortId32; /* Access nPortId as a word */ uint32_t 762 drivers/scsi/lpfc/lpfc_hw.h uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ uint32_t 764 drivers/scsi/lpfc/lpfc_hw.h uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ uint32_t 834 drivers/scsi/lpfc/lpfc_hw.h uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ uint32_t 836 drivers/scsi/lpfc/lpfc_hw.h uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ uint32_t 838 drivers/scsi/lpfc/lpfc_hw.h uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ uint32_t 842 drivers/scsi/lpfc/lpfc_hw.h uint32_t hardAL_PA; uint32_t 845 drivers/scsi/lpfc/lpfc_hw.h uint32_t DID; uint32_t 849 drivers/scsi/lpfc/lpfc_hw.h uint32_t Mflags:8; uint32_t 850 drivers/scsi/lpfc/lpfc_hw.h uint32_t Odid:24; uint32_t 860 drivers/scsi/lpfc/lpfc_hw.h uint32_t Rflags:8; uint32_t 861 drivers/scsi/lpfc/lpfc_hw.h uint32_t Rdid:24; uint32_t 873 drivers/scsi/lpfc/lpfc_hw.h uint32_t Fdid; uint32_t 892 drivers/scsi/lpfc/lpfc_hw.h uint32_t unitType; uint32_t 896 drivers/scsi/lpfc/lpfc_hw.h uint32_t physPort; uint32_t 897 drivers/scsi/lpfc/lpfc_hw.h uint32_t attachedNodes; uint32_t 924 drivers/scsi/lpfc/lpfc_hw.h uint32_t portNum; uint32_t 932 drivers/scsi/lpfc/lpfc_hw.h uint32_t linkFailureCnt; uint32_t 933 drivers/scsi/lpfc/lpfc_hw.h uint32_t lossSyncCnt; uint32_t 934 drivers/scsi/lpfc/lpfc_hw.h uint32_t lossSignalCnt; uint32_t 935 drivers/scsi/lpfc/lpfc_hw.h uint32_t primSeqErrCnt; uint32_t 936 drivers/scsi/lpfc/lpfc_hw.h uint32_t invalidXmitWord; uint32_t 937 drivers/scsi/lpfc/lpfc_hw.h uint32_t crcCnt; uint32_t 941 drivers/scsi/lpfc/lpfc_hw.h uint32_t rls; uint32_t 951 drivers/scsi/lpfc/lpfc_hw.h uint32_t linkFailureCnt; uint32_t 952 drivers/scsi/lpfc/lpfc_hw.h uint32_t lossSyncCnt; uint32_t 953 drivers/scsi/lpfc/lpfc_hw.h uint32_t lossSignalCnt; uint32_t 954 drivers/scsi/lpfc/lpfc_hw.h uint32_t primSeqErrCnt; uint32_t 955 drivers/scsi/lpfc/lpfc_hw.h uint32_t invalidXmitWord; uint32_t 956 drivers/scsi/lpfc/lpfc_hw.h uint32_t crcCnt; uint32_t 960 drivers/scsi/lpfc/lpfc_hw.h uint32_t rrq; uint32_t 967 drivers/scsi/lpfc/lpfc_hw.h uint32_t rrq_exchg; uint32_t 980 drivers/scsi/lpfc/lpfc_hw.h uint32_t ratov; uint32_t 981 drivers/scsi/lpfc/lpfc_hw.h uint32_t edtov; uint32_t 982 drivers/scsi/lpfc/lpfc_hw.h uint32_t qtov; uint32_t 1002 drivers/scsi/lpfc/lpfc_hw.h uint32_t maxsize; uint32_t 1003 drivers/scsi/lpfc/lpfc_hw.h uint32_t index; uint32_t 1007 drivers/scsi/lpfc/lpfc_hw.h uint32_t portNum; uint32_t 1008 drivers/scsi/lpfc/lpfc_hw.h uint32_t portID; uint32_t 1013 drivers/scsi/lpfc/lpfc_hw.h uint32_t listLen; uint32_t 1014 drivers/scsi/lpfc/lpfc_hw.h uint32_t index; uint32_t 1021 drivers/scsi/lpfc/lpfc_hw.h uint32_t word; uint32_t 1073 drivers/scsi/lpfc/lpfc_hw.h uint32_t lcb_command; /* ELS command opcode (0x81) */ uint32_t 1093 drivers/scsi/lpfc/lpfc_hw.h uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ uint32_t 1138 drivers/scsi/lpfc/lpfc_hw.h uint32_t link_failure_cnt; uint32_t 1139 drivers/scsi/lpfc/lpfc_hw.h uint32_t loss_of_synch_cnt; uint32_t 1140 drivers/scsi/lpfc/lpfc_hw.h uint32_t loss_of_signal_cnt; uint32_t 1141 drivers/scsi/lpfc/lpfc_hw.h uint32_t primitive_seq_proto_err; uint32_t 1142 drivers/scsi/lpfc/lpfc_hw.h uint32_t invalid_trans_word; uint32_t 1143 drivers/scsi/lpfc/lpfc_hw.h uint32_t invalid_crc_cnt; uint32_t 1149 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; /* 0001 0003h */ uint32_t 1150 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; /* set to size of payload struct */ uint32_t 1156 drivers/scsi/lpfc/lpfc_hw.h uint32_t CorrectedBlocks; uint32_t 1157 drivers/scsi/lpfc/lpfc_hw.h uint32_t UncorrectableBlocks; uint32_t 1162 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; uint32_t 1163 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; uint32_t 1169 drivers/scsi/lpfc/lpfc_hw.h uint32_t port_type; /* bits 31-30 only */ uint32_t 1174 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; /* 0001 0002h */ uint32_t 1175 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; /* set to size of payload struct */ uint32_t 1211 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; /* 00010001h */ uint32_t 1212 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; /* set to size of payload struct */ uint32_t 1219 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; /* 0000 0003h, big endian */ uint32_t 1220 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; /* size of RDP_N_PORT_ID struct */ uint32_t 1221 drivers/scsi/lpfc/lpfc_hw.h uint32_t nport_id : 12; uint32_t 1222 drivers/scsi/lpfc/lpfc_hw.h uint32_t reserved : 8; uint32_t 1227 drivers/scsi/lpfc/lpfc_hw.h uint32_t els_req; /* Request payload word 0 value.*/ uint32_t 1232 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; /* Descriptor tag 1 */ uint32_t 1233 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; /* set to size of payload struct. */ uint32_t 1249 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; uint32_t 1250 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; /* set to size of sfp_info struct */ uint32_t 1256 drivers/scsi/lpfc/lpfc_hw.h uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ uint32_t 1257 drivers/scsi/lpfc/lpfc_hw.h uint32_t attached_port_bbc; uint32_t 1258 drivers/scsi/lpfc/lpfc_hw.h uint32_t rtt; /* Round trip time */ uint32_t 1262 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; uint32_t 1263 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; uint32_t 1286 drivers/scsi/lpfc/lpfc_hw.h uint32_t function_flags; uint32_t 1290 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; uint32_t 1291 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; uint32_t 1306 drivers/scsi/lpfc/lpfc_hw.h uint32_t tag; uint32_t 1307 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; uint32_t 1312 drivers/scsi/lpfc/lpfc_hw.h uint32_t rdp_command; /* ELS command opcode (0x18)*/ uint32_t 1313 drivers/scsi/lpfc/lpfc_hw.h uint32_t rdp_des_length; /* RDP Payload Word 1 */ uint32_t 1319 drivers/scsi/lpfc/lpfc_hw.h uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ uint32_t 1320 drivers/scsi/lpfc/lpfc_hw.h uint32_t length; /* FC Word 1 */ uint32_t 1347 drivers/scsi/lpfc/lpfc_hw.h uint32_t EntryCnt; uint32_t 1348 drivers/scsi/lpfc/lpfc_hw.h uint32_t pe; /* Variable-length array */ uint32_t 1356 drivers/scsi/lpfc/lpfc_hw.h uint32_t AttrType:16; uint32_t 1357 drivers/scsi/lpfc/lpfc_hw.h uint32_t AttrLen:16; uint32_t 1358 drivers/scsi/lpfc/lpfc_hw.h uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */ uint32_t 1365 drivers/scsi/lpfc/lpfc_hw.h uint32_t AttrInt; uint32_t 1378 drivers/scsi/lpfc/lpfc_hw.h uint32_t EntryCnt; /* Number of HBA attribute entries */ uint32_t 1660 drivers/scsi/lpfc/lpfc_hw.h uint32_t hostAtt; /* See definitions for Host Attention uint32_t 1662 drivers/scsi/lpfc/lpfc_hw.h uint32_t chipAtt; /* See definitions for Chip Attention uint32_t 1664 drivers/scsi/lpfc/lpfc_hw.h uint32_t hostStatus; /* See definitions for Host Status register */ uint32_t 1665 drivers/scsi/lpfc/lpfc_hw.h uint32_t hostControl; /* See definitions for Host Control register */ uint32_t 1666 drivers/scsi/lpfc/lpfc_hw.h uint32_t buiConfig; /* See definitions for BIU configuration uint32_t 2005 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeAddress; uint32_t 2007 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeReserved:4; uint32_t 2008 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeAddrHigh:4; uint32_t 2009 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeSize:24; uint32_t 2011 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeSize:24; uint32_t 2012 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeAddrHigh:4; uint32_t 2013 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeReserved:4; uint32_t 2019 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeFlags:8; /* BDL Flags */ uint32_t 2020 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ uint32_t 2022 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ uint32_t 2023 drivers/scsi/lpfc/lpfc_hw.h uint32_t bdeFlags:8; /* BDL Flags */ uint32_t 2026 drivers/scsi/lpfc/lpfc_hw.h uint32_t addrLow; /* Address 0:31 */ uint32_t 2027 drivers/scsi/lpfc/lpfc_hw.h uint32_t addrHigh; /* Address 32:63 */ uint32_t 2028 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ uint32_t 2059 drivers/scsi/lpfc/lpfc_hw.h uint32_t word0; uint32_t 2066 drivers/scsi/lpfc/lpfc_hw.h uint32_t reftag; /* Reference Tag Value */ uint32_t 2067 drivers/scsi/lpfc/lpfc_hw.h uint32_t reftagtr; /* Reference Tag Translation Value */ uint32_t 2071 drivers/scsi/lpfc/lpfc_hw.h uint32_t word0; uint32_t 2078 drivers/scsi/lpfc/lpfc_hw.h uint32_t word1; uint32_t 2091 drivers/scsi/lpfc/lpfc_hw.h uint32_t word2; uint32_t 2122 drivers/scsi/lpfc/lpfc_hw.h uint32_t word0; uint32_t 2129 drivers/scsi/lpfc/lpfc_hw.h uint32_t addrHigh; uint32_t 2130 drivers/scsi/lpfc/lpfc_hw.h uint32_t addrLow; uint32_t 2137 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:25; uint32_t 2138 drivers/scsi/lpfc/lpfc_hw.h uint32_t acknowledgment:1; uint32_t 2139 drivers/scsi/lpfc/lpfc_hw.h uint32_t version:1; uint32_t 2140 drivers/scsi/lpfc/lpfc_hw.h uint32_t erase_or_prog:1; uint32_t 2141 drivers/scsi/lpfc/lpfc_hw.h uint32_t update_flash:1; uint32_t 2142 drivers/scsi/lpfc/lpfc_hw.h uint32_t update_ram:1; uint32_t 2143 drivers/scsi/lpfc/lpfc_hw.h uint32_t method:1; uint32_t 2144 drivers/scsi/lpfc/lpfc_hw.h uint32_t load_cmplt:1; uint32_t 2146 drivers/scsi/lpfc/lpfc_hw.h uint32_t load_cmplt:1; uint32_t 2147 drivers/scsi/lpfc/lpfc_hw.h uint32_t method:1; uint32_t 2148 drivers/scsi/lpfc/lpfc_hw.h uint32_t update_ram:1; uint32_t 2149 drivers/scsi/lpfc/lpfc_hw.h uint32_t update_flash:1; uint32_t 2150 drivers/scsi/lpfc/lpfc_hw.h uint32_t erase_or_prog:1; uint32_t 2151 drivers/scsi/lpfc/lpfc_hw.h uint32_t version:1; uint32_t 2152 drivers/scsi/lpfc/lpfc_hw.h uint32_t acknowledgment:1; uint32_t 2153 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:25; uint32_t 2156 drivers/scsi/lpfc/lpfc_hw.h uint32_t dl_to_adr_low; uint32_t 2157 drivers/scsi/lpfc/lpfc_hw.h uint32_t dl_to_adr_high; uint32_t 2158 drivers/scsi/lpfc/lpfc_hw.h uint32_t dl_len; uint32_t 2160 drivers/scsi/lpfc/lpfc_hw.h uint32_t dl_from_mbx_offset; uint32_t 2170 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1[3]; /* Read as all one's */ uint32_t 2171 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; /* Read as all zero's */ uint32_t 2172 drivers/scsi/lpfc/lpfc_hw.h uint32_t portname[2]; /* N_PORT name */ uint32_t 2173 drivers/scsi/lpfc/lpfc_hw.h uint32_t nodename[2]; /* NODE name */ uint32_t 2176 drivers/scsi/lpfc/lpfc_hw.h uint32_t pref_DID:24; uint32_t 2177 drivers/scsi/lpfc/lpfc_hw.h uint32_t hardAL_PA:8; uint32_t 2179 drivers/scsi/lpfc/lpfc_hw.h uint32_t hardAL_PA:8; uint32_t 2180 drivers/scsi/lpfc/lpfc_hw.h uint32_t pref_DID:24; uint32_t 2183 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3[21]; /* Read as all one's */ uint32_t 2189 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1[3]; /* Must be all one's */ uint32_t 2190 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; /* Must be all zero's */ uint32_t 2191 drivers/scsi/lpfc/lpfc_hw.h uint32_t portname[2]; /* N_PORT name */ uint32_t 2192 drivers/scsi/lpfc/lpfc_hw.h uint32_t nodename[2]; /* NODE name */ uint32_t 2195 drivers/scsi/lpfc/lpfc_hw.h uint32_t pref_DID:24; uint32_t 2196 drivers/scsi/lpfc/lpfc_hw.h uint32_t hardAL_PA:8; uint32_t 2198 drivers/scsi/lpfc/lpfc_hw.h uint32_t hardAL_PA:8; uint32_t 2199 drivers/scsi/lpfc/lpfc_hw.h uint32_t pref_DID:24; uint32_t 2202 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3[21]; /* Must be all one's */ uint32_t 2209 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 2224 drivers/scsi/lpfc/lpfc_hw.h uint32_t word1; uint32_t 2229 drivers/scsi/lpfc/lpfc_hw.h uint32_t offset; uint32_t 2237 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:24; uint32_t 2238 drivers/scsi/lpfc/lpfc_hw.h uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ uint32_t 2240 drivers/scsi/lpfc/lpfc_hw.h uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ uint32_t 2241 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:24; uint32_t 2266 drivers/scsi/lpfc/lpfc_hw.h uint32_t link_speed; uint32_t 2284 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 2291 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr:1; uint32_t 2292 drivers/scsi/lpfc/lpfc_hw.h uint32_t ci:1; uint32_t 2293 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr_delay:6; uint32_t 2294 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr_count:8; uint32_t 2295 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:8; uint32_t 2296 drivers/scsi/lpfc/lpfc_hw.h uint32_t MaxBBC:8; uint32_t 2298 drivers/scsi/lpfc/lpfc_hw.h uint32_t MaxBBC:8; uint32_t 2299 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:8; uint32_t 2300 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr_count:8; uint32_t 2301 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr_delay:6; uint32_t 2302 drivers/scsi/lpfc/lpfc_hw.h uint32_t ci:1; uint32_t 2303 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr:1; uint32_t 2306 drivers/scsi/lpfc/lpfc_hw.h uint32_t myId; uint32_t 2307 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; uint32_t 2308 drivers/scsi/lpfc/lpfc_hw.h uint32_t edtov; uint32_t 2309 drivers/scsi/lpfc/lpfc_hw.h uint32_t arbtov; uint32_t 2310 drivers/scsi/lpfc/lpfc_hw.h uint32_t ratov; uint32_t 2311 drivers/scsi/lpfc/lpfc_hw.h uint32_t rttov; uint32_t 2312 drivers/scsi/lpfc/lpfc_hw.h uint32_t altov; uint32_t 2313 drivers/scsi/lpfc/lpfc_hw.h uint32_t crtov; uint32_t 2316 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4:19; uint32_t 2317 drivers/scsi/lpfc/lpfc_hw.h uint32_t cscn:1; uint32_t 2318 drivers/scsi/lpfc/lpfc_hw.h uint32_t bbscn:4; uint32_t 2319 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:8; uint32_t 2321 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:8; uint32_t 2322 drivers/scsi/lpfc/lpfc_hw.h uint32_t bbscn:4; uint32_t 2323 drivers/scsi/lpfc/lpfc_hw.h uint32_t cscn:1; uint32_t 2324 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4:19; uint32_t 2328 drivers/scsi/lpfc/lpfc_hw.h uint32_t rrq_enable:1; uint32_t 2329 drivers/scsi/lpfc/lpfc_hw.h uint32_t rrq_immed:1; uint32_t 2330 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5:29; uint32_t 2331 drivers/scsi/lpfc/lpfc_hw.h uint32_t ack0_enable:1; uint32_t 2333 drivers/scsi/lpfc/lpfc_hw.h uint32_t ack0_enable:1; uint32_t 2334 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5:29; uint32_t 2335 drivers/scsi/lpfc/lpfc_hw.h uint32_t rrq_immed:1; uint32_t 2336 drivers/scsi/lpfc/lpfc_hw.h uint32_t rrq_enable:1; uint32_t 2359 drivers/scsi/lpfc/lpfc_hw.h uint32_t unused1:24; uint32_t 2360 drivers/scsi/lpfc/lpfc_hw.h uint32_t numRing:8; uint32_t 2362 drivers/scsi/lpfc/lpfc_hw.h uint32_t numRing:8; uint32_t 2363 drivers/scsi/lpfc/lpfc_hw.h uint32_t unused1:24; uint32_t 2367 drivers/scsi/lpfc/lpfc_hw.h uint32_t hbainit; uint32_t 2374 drivers/scsi/lpfc/lpfc_hw.h uint32_t unused2:6; uint32_t 2375 drivers/scsi/lpfc/lpfc_hw.h uint32_t recvSeq:1; uint32_t 2376 drivers/scsi/lpfc/lpfc_hw.h uint32_t recvNotify:1; uint32_t 2377 drivers/scsi/lpfc/lpfc_hw.h uint32_t numMask:8; uint32_t 2378 drivers/scsi/lpfc/lpfc_hw.h uint32_t profile:8; uint32_t 2379 drivers/scsi/lpfc/lpfc_hw.h uint32_t unused1:4; uint32_t 2380 drivers/scsi/lpfc/lpfc_hw.h uint32_t ring:4; uint32_t 2382 drivers/scsi/lpfc/lpfc_hw.h uint32_t ring:4; uint32_t 2383 drivers/scsi/lpfc/lpfc_hw.h uint32_t unused1:4; uint32_t 2384 drivers/scsi/lpfc/lpfc_hw.h uint32_t profile:8; uint32_t 2385 drivers/scsi/lpfc/lpfc_hw.h uint32_t numMask:8; uint32_t 2386 drivers/scsi/lpfc/lpfc_hw.h uint32_t recvNotify:1; uint32_t 2387 drivers/scsi/lpfc/lpfc_hw.h uint32_t recvSeq:1; uint32_t 2388 drivers/scsi/lpfc/lpfc_hw.h uint32_t unused2:6; uint32_t 2405 drivers/scsi/lpfc/lpfc_hw.h uint32_t ring_no; uint32_t 2412 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr:1; uint32_t 2413 drivers/scsi/lpfc/lpfc_hw.h uint32_t ci:1; uint32_t 2414 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr_delay:6; uint32_t 2415 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr_count:8; uint32_t 2416 drivers/scsi/lpfc/lpfc_hw.h uint32_t InitBBC:8; uint32_t 2417 drivers/scsi/lpfc/lpfc_hw.h uint32_t MaxBBC:8; uint32_t 2419 drivers/scsi/lpfc/lpfc_hw.h uint32_t MaxBBC:8; uint32_t 2420 drivers/scsi/lpfc/lpfc_hw.h uint32_t InitBBC:8; uint32_t 2421 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr_count:8; uint32_t 2422 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr_delay:6; uint32_t 2423 drivers/scsi/lpfc/lpfc_hw.h uint32_t ci:1; uint32_t 2424 drivers/scsi/lpfc/lpfc_hw.h uint32_t cr:1; uint32_t 2428 drivers/scsi/lpfc/lpfc_hw.h uint32_t topology:8; uint32_t 2429 drivers/scsi/lpfc/lpfc_hw.h uint32_t myDid:24; uint32_t 2431 drivers/scsi/lpfc/lpfc_hw.h uint32_t myDid:24; uint32_t 2432 drivers/scsi/lpfc/lpfc_hw.h uint32_t topology:8; uint32_t 2437 drivers/scsi/lpfc/lpfc_hw.h uint32_t AR:1; uint32_t 2438 drivers/scsi/lpfc/lpfc_hw.h uint32_t IR:1; uint32_t 2439 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:29; uint32_t 2440 drivers/scsi/lpfc/lpfc_hw.h uint32_t ack0:1; uint32_t 2442 drivers/scsi/lpfc/lpfc_hw.h uint32_t ack0:1; uint32_t 2443 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:29; uint32_t 2444 drivers/scsi/lpfc/lpfc_hw.h uint32_t IR:1; uint32_t 2445 drivers/scsi/lpfc/lpfc_hw.h uint32_t AR:1; uint32_t 2448 drivers/scsi/lpfc/lpfc_hw.h uint32_t edtov; uint32_t 2449 drivers/scsi/lpfc/lpfc_hw.h uint32_t arbtov; uint32_t 2450 drivers/scsi/lpfc/lpfc_hw.h uint32_t ratov; uint32_t 2451 drivers/scsi/lpfc/lpfc_hw.h uint32_t rttov; uint32_t 2452 drivers/scsi/lpfc/lpfc_hw.h uint32_t altov; uint32_t 2453 drivers/scsi/lpfc/lpfc_hw.h uint32_t lmt; uint32_t 2465 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; uint32_t 2466 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3; uint32_t 2467 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_xri; uint32_t 2468 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_iocb; uint32_t 2469 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_rpi; uint32_t 2470 drivers/scsi/lpfc/lpfc_hw.h uint32_t avail_xri; uint32_t 2471 drivers/scsi/lpfc/lpfc_hw.h uint32_t avail_iocb; uint32_t 2472 drivers/scsi/lpfc/lpfc_hw.h uint32_t avail_rpi; uint32_t 2473 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_vpi; uint32_t 2474 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4; uint32_t 2475 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5; uint32_t 2476 drivers/scsi/lpfc/lpfc_hw.h uint32_t avail_vpi; uint32_t 2483 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:7; uint32_t 2484 drivers/scsi/lpfc/lpfc_hw.h uint32_t recvNotify:1; uint32_t 2485 drivers/scsi/lpfc/lpfc_hw.h uint32_t numMask:8; uint32_t 2486 drivers/scsi/lpfc/lpfc_hw.h uint32_t profile:8; uint32_t 2487 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:4; uint32_t 2488 drivers/scsi/lpfc/lpfc_hw.h uint32_t ring:4; uint32_t 2490 drivers/scsi/lpfc/lpfc_hw.h uint32_t ring:4; uint32_t 2491 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:4; uint32_t 2492 drivers/scsi/lpfc/lpfc_hw.h uint32_t profile:8; uint32_t 2493 drivers/scsi/lpfc/lpfc_hw.h uint32_t numMask:8; uint32_t 2494 drivers/scsi/lpfc/lpfc_hw.h uint32_t recvNotify:1; uint32_t 2495 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:7; uint32_t 2533 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 2534 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; uint32_t 2553 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:31; uint32_t 2554 drivers/scsi/lpfc/lpfc_hw.h uint32_t clrCounters:1; uint32_t 2558 drivers/scsi/lpfc/lpfc_hw.h uint32_t clrCounters:1; uint32_t 2559 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:31; uint32_t 2564 drivers/scsi/lpfc/lpfc_hw.h uint32_t xmitByteCnt; uint32_t 2565 drivers/scsi/lpfc/lpfc_hw.h uint32_t rcvByteCnt; uint32_t 2566 drivers/scsi/lpfc/lpfc_hw.h uint32_t xmitFrameCnt; uint32_t 2567 drivers/scsi/lpfc/lpfc_hw.h uint32_t rcvFrameCnt; uint32_t 2568 drivers/scsi/lpfc/lpfc_hw.h uint32_t xmitSeqCnt; uint32_t 2569 drivers/scsi/lpfc/lpfc_hw.h uint32_t rcvSeqCnt; uint32_t 2570 drivers/scsi/lpfc/lpfc_hw.h uint32_t totalOrigExchanges; uint32_t 2571 drivers/scsi/lpfc/lpfc_hw.h uint32_t totalRespExchanges; uint32_t 2572 drivers/scsi/lpfc/lpfc_hw.h uint32_t rcvPbsyCnt; uint32_t 2573 drivers/scsi/lpfc/lpfc_hw.h uint32_t rcvFbsyCnt; uint32_t 2583 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:8; uint32_t 2584 drivers/scsi/lpfc/lpfc_hw.h uint32_t DID:24; uint32_t 2588 drivers/scsi/lpfc/lpfc_hw.h uint32_t DID:24; uint32_t 2589 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:8; uint32_t 2607 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:8; uint32_t 2608 drivers/scsi/lpfc/lpfc_hw.h uint32_t DID:24; uint32_t 2609 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:8; uint32_t 2610 drivers/scsi/lpfc/lpfc_hw.h uint32_t SID:24; uint32_t 2611 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4; uint32_t 2617 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd6:30; uint32_t 2618 drivers/scsi/lpfc/lpfc_hw.h uint32_t si:1; uint32_t 2619 drivers/scsi/lpfc/lpfc_hw.h uint32_t exchOrig:1; uint32_t 2625 drivers/scsi/lpfc/lpfc_hw.h uint32_t DID:24; uint32_t 2626 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:8; uint32_t 2627 drivers/scsi/lpfc/lpfc_hw.h uint32_t SID:24; uint32_t 2628 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:8; uint32_t 2629 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4; uint32_t 2635 drivers/scsi/lpfc/lpfc_hw.h uint32_t exchOrig:1; uint32_t 2636 drivers/scsi/lpfc/lpfc_hw.h uint32_t si:1; uint32_t 2637 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd6:30; uint32_t 2645 drivers/scsi/lpfc/lpfc_hw.h uint32_t cv:1; uint32_t 2646 drivers/scsi/lpfc/lpfc_hw.h uint32_t rr:1; uint32_t 2647 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:2; uint32_t 2648 drivers/scsi/lpfc/lpfc_hw.h uint32_t v3req:1; uint32_t 2649 drivers/scsi/lpfc/lpfc_hw.h uint32_t v3rsp:1; uint32_t 2650 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:25; uint32_t 2651 drivers/scsi/lpfc/lpfc_hw.h uint32_t rv:1; uint32_t 2653 drivers/scsi/lpfc/lpfc_hw.h uint32_t rv:1; uint32_t 2654 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:25; uint32_t 2655 drivers/scsi/lpfc/lpfc_hw.h uint32_t v3rsp:1; uint32_t 2656 drivers/scsi/lpfc/lpfc_hw.h uint32_t v3req:1; uint32_t 2657 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:2; uint32_t 2658 drivers/scsi/lpfc/lpfc_hw.h uint32_t rr:1; uint32_t 2659 drivers/scsi/lpfc/lpfc_hw.h uint32_t cv:1; uint32_t 2662 drivers/scsi/lpfc/lpfc_hw.h uint32_t biuRev; uint32_t 2663 drivers/scsi/lpfc/lpfc_hw.h uint32_t smRev; uint32_t 2665 drivers/scsi/lpfc/lpfc_hw.h uint32_t smFwRev; uint32_t 2687 drivers/scsi/lpfc/lpfc_hw.h uint32_t endecRev; uint32_t 2700 drivers/scsi/lpfc/lpfc_hw.h uint32_t postKernRev; uint32_t 2701 drivers/scsi/lpfc/lpfc_hw.h uint32_t opFwRev; uint32_t 2703 drivers/scsi/lpfc/lpfc_hw.h uint32_t sli1FwRev; uint32_t 2705 drivers/scsi/lpfc/lpfc_hw.h uint32_t sli2FwRev; uint32_t 2707 drivers/scsi/lpfc/lpfc_hw.h uint32_t sli3Feat; uint32_t 2708 drivers/scsi/lpfc/lpfc_hw.h uint32_t RandomData[6]; uint32_t 2714 drivers/scsi/lpfc/lpfc_hw.h uint32_t word0; uint32_t 2744 drivers/scsi/lpfc/lpfc_hw.h uint32_t linkFailureCnt; uint32_t 2745 drivers/scsi/lpfc/lpfc_hw.h uint32_t lossSyncCnt; uint32_t 2746 drivers/scsi/lpfc/lpfc_hw.h uint32_t lossSignalCnt; uint32_t 2747 drivers/scsi/lpfc/lpfc_hw.h uint32_t primSeqErrCnt; uint32_t 2748 drivers/scsi/lpfc/lpfc_hw.h uint32_t invalidXmitWord; uint32_t 2749 drivers/scsi/lpfc/lpfc_hw.h uint32_t crcCnt; uint32_t 2750 drivers/scsi/lpfc/lpfc_hw.h uint32_t primSeqTimeout; uint32_t 2751 drivers/scsi/lpfc/lpfc_hw.h uint32_t elasticOverrun; uint32_t 2752 drivers/scsi/lpfc/lpfc_hw.h uint32_t arbTimeout; uint32_t 2753 drivers/scsi/lpfc/lpfc_hw.h uint32_t advRecBufCredit; uint32_t 2754 drivers/scsi/lpfc/lpfc_hw.h uint32_t curRecBufCredit; uint32_t 2755 drivers/scsi/lpfc/lpfc_hw.h uint32_t advTransBufCredit; uint32_t 2756 drivers/scsi/lpfc/lpfc_hw.h uint32_t curTransBufCredit; uint32_t 2757 drivers/scsi/lpfc/lpfc_hw.h uint32_t recEofCount; uint32_t 2758 drivers/scsi/lpfc/lpfc_hw.h uint32_t recEofdtiCount; uint32_t 2759 drivers/scsi/lpfc/lpfc_hw.h uint32_t recEofniCount; uint32_t 2760 drivers/scsi/lpfc/lpfc_hw.h uint32_t recSofcount; uint32_t 2761 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 2762 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; uint32_t 2763 drivers/scsi/lpfc/lpfc_hw.h uint32_t recDrpXriCount; uint32_t 2764 drivers/scsi/lpfc/lpfc_hw.h uint32_t fecCorrBlkCount; uint32_t 2765 drivers/scsi/lpfc/lpfc_hw.h uint32_t fecUncorrBlkCount; uint32_t 2775 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:8; uint32_t 2776 drivers/scsi/lpfc/lpfc_hw.h uint32_t did:24; uint32_t 2780 drivers/scsi/lpfc/lpfc_hw.h uint32_t did:24; uint32_t 2781 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:8; uint32_t 2812 drivers/scsi/lpfc/lpfc_hw.h uint32_t word; uint32_t 2821 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; uint32_t 2822 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3; uint32_t 2823 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4; uint32_t 2824 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5; uint32_t 2830 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; uint32_t 2831 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3; uint32_t 2832 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4; uint32_t 2833 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5; uint32_t 2842 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 2843 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:7; uint32_t 2844 drivers/scsi/lpfc/lpfc_hw.h uint32_t upd:1; uint32_t 2845 drivers/scsi/lpfc/lpfc_hw.h uint32_t sid:24; uint32_t 2846 drivers/scsi/lpfc/lpfc_hw.h uint32_t wwn[2]; uint32_t 2847 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5; uint32_t 2851 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 2852 drivers/scsi/lpfc/lpfc_hw.h uint32_t sid:24; uint32_t 2853 drivers/scsi/lpfc/lpfc_hw.h uint32_t upd:1; uint32_t 2854 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:7; uint32_t 2855 drivers/scsi/lpfc/lpfc_hw.h uint32_t wwn[2]; uint32_t 2856 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5; uint32_t 2864 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 2872 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3; uint32_t 2873 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4; uint32_t 2874 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5; uint32_t 2887 drivers/scsi/lpfc/lpfc_hw.h uint32_t did; uint32_t 2888 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; uint32_t 2889 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3; uint32_t 2890 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4; uint32_t 2891 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5; uint32_t 2903 drivers/scsi/lpfc/lpfc_hw.h uint32_t eventTag; /* Event tag */ uint32_t 2904 drivers/scsi/lpfc/lpfc_hw.h uint32_t word2; uint32_t 2924 drivers/scsi/lpfc/lpfc_hw.h uint32_t word3; uint32_t 2943 drivers/scsi/lpfc/lpfc_hw.h uint32_t word7; uint32_t 2962 drivers/scsi/lpfc/lpfc_hw.h uint32_t word8; uint32_t 2997 drivers/scsi/lpfc/lpfc_hw.h uint32_t eventTag; /* Event tag */ uint32_t 2998 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 3005 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd:25; uint32_t 3006 drivers/scsi/lpfc/lpfc_hw.h uint32_t ra:1; uint32_t 3007 drivers/scsi/lpfc/lpfc_hw.h uint32_t co:1; uint32_t 3008 drivers/scsi/lpfc/lpfc_hw.h uint32_t cv:1; uint32_t 3009 drivers/scsi/lpfc/lpfc_hw.h uint32_t type:4; uint32_t 3010 drivers/scsi/lpfc/lpfc_hw.h uint32_t entry_index:16; uint32_t 3011 drivers/scsi/lpfc/lpfc_hw.h uint32_t region_id:16; uint32_t 3013 drivers/scsi/lpfc/lpfc_hw.h uint32_t type:4; uint32_t 3014 drivers/scsi/lpfc/lpfc_hw.h uint32_t cv:1; uint32_t 3015 drivers/scsi/lpfc/lpfc_hw.h uint32_t co:1; uint32_t 3016 drivers/scsi/lpfc/lpfc_hw.h uint32_t ra:1; uint32_t 3017 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd:25; uint32_t 3018 drivers/scsi/lpfc/lpfc_hw.h uint32_t region_id:16; uint32_t 3019 drivers/scsi/lpfc/lpfc_hw.h uint32_t entry_index:16; uint32_t 3022 drivers/scsi/lpfc/lpfc_hw.h uint32_t sli4_length; uint32_t 3023 drivers/scsi/lpfc/lpfc_hw.h uint32_t word_cnt; uint32_t 3024 drivers/scsi/lpfc/lpfc_hw.h uint32_t resp_offset; uint32_t 3057 drivers/scsi/lpfc/lpfc_hw.h uint32_t signature; uint32_t 3058 drivers/scsi/lpfc/lpfc_hw.h uint32_t rev; uint32_t 3060 drivers/scsi/lpfc/lpfc_hw.h uint32_t resvd[66]; uint32_t 3068 drivers/scsi/lpfc/lpfc_hw.h uint32_t ver:4; /* Major Version */ uint32_t 3069 drivers/scsi/lpfc/lpfc_hw.h uint32_t rev:4; /* Revision */ uint32_t 3070 drivers/scsi/lpfc/lpfc_hw.h uint32_t lev:2; /* Level */ uint32_t 3071 drivers/scsi/lpfc/lpfc_hw.h uint32_t dist:2; /* Dist Type */ uint32_t 3072 drivers/scsi/lpfc/lpfc_hw.h uint32_t num:4; /* number after dist type */ uint32_t 3074 drivers/scsi/lpfc/lpfc_hw.h uint32_t num:4; /* number after dist type */ uint32_t 3075 drivers/scsi/lpfc/lpfc_hw.h uint32_t dist:2; /* Dist Type */ uint32_t 3076 drivers/scsi/lpfc/lpfc_hw.h uint32_t lev:2; /* Level */ uint32_t 3077 drivers/scsi/lpfc/lpfc_hw.h uint32_t rev:4; /* Revision */ uint32_t 3078 drivers/scsi/lpfc/lpfc_hw.h uint32_t ver:4; /* Major Version */ uint32_t 3088 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:16; uint32_t 3089 drivers/scsi/lpfc/lpfc_hw.h uint32_t type:8; uint32_t 3090 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd:1; uint32_t 3091 drivers/scsi/lpfc/lpfc_hw.h uint32_t ra:1; uint32_t 3092 drivers/scsi/lpfc/lpfc_hw.h uint32_t co:1; uint32_t 3093 drivers/scsi/lpfc/lpfc_hw.h uint32_t cv:1; uint32_t 3094 drivers/scsi/lpfc/lpfc_hw.h uint32_t req:4; uint32_t 3095 drivers/scsi/lpfc/lpfc_hw.h uint32_t entry_length:16; uint32_t 3096 drivers/scsi/lpfc/lpfc_hw.h uint32_t region_id:16; uint32_t 3098 drivers/scsi/lpfc/lpfc_hw.h uint32_t req:4; uint32_t 3099 drivers/scsi/lpfc/lpfc_hw.h uint32_t cv:1; uint32_t 3100 drivers/scsi/lpfc/lpfc_hw.h uint32_t co:1; uint32_t 3101 drivers/scsi/lpfc/lpfc_hw.h uint32_t ra:1; uint32_t 3102 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd:1; uint32_t 3103 drivers/scsi/lpfc/lpfc_hw.h uint32_t type:8; uint32_t 3104 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:16; uint32_t 3105 drivers/scsi/lpfc/lpfc_hw.h uint32_t region_id:16; uint32_t 3106 drivers/scsi/lpfc/lpfc_hw.h uint32_t entry_length:16; uint32_t 3109 drivers/scsi/lpfc/lpfc_hw.h uint32_t resp_info; uint32_t 3110 drivers/scsi/lpfc/lpfc_hw.h uint32_t byte_cnt; uint32_t 3111 drivers/scsi/lpfc/lpfc_hw.h uint32_t data_offset; uint32_t 3133 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 :7; uint32_t 3134 drivers/scsi/lpfc/lpfc_hw.h uint32_t recvNotify :1; /* Receive Notification */ uint32_t 3135 drivers/scsi/lpfc/lpfc_hw.h uint32_t numMask :8; /* # Mask Entries */ uint32_t 3136 drivers/scsi/lpfc/lpfc_hw.h uint32_t profile :8; /* Selection Profile */ uint32_t 3137 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2 :8; uint32_t 3139 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2 :8; uint32_t 3140 drivers/scsi/lpfc/lpfc_hw.h uint32_t profile :8; /* Selection Profile */ uint32_t 3141 drivers/scsi/lpfc/lpfc_hw.h uint32_t numMask :8; /* # Mask Entries */ uint32_t 3142 drivers/scsi/lpfc/lpfc_hw.h uint32_t recvNotify :1; /* Receive Notification */ uint32_t 3143 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 :7; uint32_t 3147 drivers/scsi/lpfc/lpfc_hw.h uint32_t hbqId :16; uint32_t 3148 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3 :12; uint32_t 3149 drivers/scsi/lpfc/lpfc_hw.h uint32_t ringMask :4; uint32_t 3151 drivers/scsi/lpfc/lpfc_hw.h uint32_t ringMask :4; uint32_t 3152 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3 :12; uint32_t 3153 drivers/scsi/lpfc/lpfc_hw.h uint32_t hbqId :16; uint32_t 3157 drivers/scsi/lpfc/lpfc_hw.h uint32_t entry_count :16; uint32_t 3158 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4 :8; uint32_t 3159 drivers/scsi/lpfc/lpfc_hw.h uint32_t headerLen :8; uint32_t 3161 drivers/scsi/lpfc/lpfc_hw.h uint32_t headerLen :8; uint32_t 3162 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4 :8; uint32_t 3163 drivers/scsi/lpfc/lpfc_hw.h uint32_t entry_count :16; uint32_t 3166 drivers/scsi/lpfc/lpfc_hw.h uint32_t hbqaddrLow; uint32_t 3167 drivers/scsi/lpfc/lpfc_hw.h uint32_t hbqaddrHigh; uint32_t 3170 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5 :31; uint32_t 3171 drivers/scsi/lpfc/lpfc_hw.h uint32_t logEntry :1; uint32_t 3173 drivers/scsi/lpfc/lpfc_hw.h uint32_t logEntry :1; uint32_t 3174 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5 :31; uint32_t 3177 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd6; /* w7 */ uint32_t 3178 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd7; /* w8 */ uint32_t 3179 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd8; /* w9 */ uint32_t 3185 drivers/scsi/lpfc/lpfc_hw.h uint32_t allprofiles[12]; uint32_t 3189 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenoff :16; uint32_t 3190 drivers/scsi/lpfc/lpfc_hw.h uint32_t maxlen :16; uint32_t 3192 drivers/scsi/lpfc/lpfc_hw.h uint32_t maxlen :16; uint32_t 3193 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenoff :16; uint32_t 3196 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 :28; uint32_t 3197 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenbcnt :4; uint32_t 3199 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenbcnt :4; uint32_t 3200 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 :28; uint32_t 3202 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd[10]; uint32_t 3207 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenoff :16; uint32_t 3208 drivers/scsi/lpfc/lpfc_hw.h uint32_t maxlen :16; uint32_t 3210 drivers/scsi/lpfc/lpfc_hw.h uint32_t maxlen :16; uint32_t 3211 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenoff :16; uint32_t 3214 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmdcodeoff :28; uint32_t 3215 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 :12; uint32_t 3216 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenbcnt :4; uint32_t 3218 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenbcnt :4; uint32_t 3219 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 :12; uint32_t 3220 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmdcodeoff :28; uint32_t 3222 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmdmatch[8]; uint32_t 3224 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd[2]; uint32_t 3229 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenoff :16; uint32_t 3230 drivers/scsi/lpfc/lpfc_hw.h uint32_t maxlen :16; uint32_t 3232 drivers/scsi/lpfc/lpfc_hw.h uint32_t maxlen :16; uint32_t 3233 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenoff :16; uint32_t 3236 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmdcodeoff :28; uint32_t 3237 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 :12; uint32_t 3238 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenbcnt :4; uint32_t 3240 drivers/scsi/lpfc/lpfc_hw.h uint32_t seqlenbcnt :4; uint32_t 3241 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 :12; uint32_t 3242 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmdcodeoff :28; uint32_t 3244 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmdmatch[8]; uint32_t 3246 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd[2]; uint32_t 3258 drivers/scsi/lpfc/lpfc_hw.h uint32_t cBE : 1; uint32_t 3259 drivers/scsi/lpfc/lpfc_hw.h uint32_t cET : 1; uint32_t 3260 drivers/scsi/lpfc/lpfc_hw.h uint32_t cHpcb : 1; uint32_t 3261 drivers/scsi/lpfc/lpfc_hw.h uint32_t cMA : 1; uint32_t 3262 drivers/scsi/lpfc/lpfc_hw.h uint32_t sli_mode : 4; uint32_t 3263 drivers/scsi/lpfc/lpfc_hw.h uint32_t pcbLen : 24; /* bit 23:0 of memory based port uint32_t 3266 drivers/scsi/lpfc/lpfc_hw.h uint32_t pcbLen : 24; /* bit 23:0 of memory based port uint32_t 3268 drivers/scsi/lpfc/lpfc_hw.h uint32_t sli_mode : 4; uint32_t 3269 drivers/scsi/lpfc/lpfc_hw.h uint32_t cMA : 1; uint32_t 3270 drivers/scsi/lpfc/lpfc_hw.h uint32_t cHpcb : 1; uint32_t 3271 drivers/scsi/lpfc/lpfc_hw.h uint32_t cET : 1; uint32_t 3272 drivers/scsi/lpfc/lpfc_hw.h uint32_t cBE : 1; uint32_t 3275 drivers/scsi/lpfc/lpfc_hw.h uint32_t pcbLow; /* bit 31:0 of memory based port config block */ uint32_t 3276 drivers/scsi/lpfc/lpfc_hw.h uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ uint32_t 3277 drivers/scsi/lpfc/lpfc_hw.h uint32_t hbainit[5]; uint32_t 3279 drivers/scsi/lpfc/lpfc_hw.h uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ uint32_t 3280 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ uint32_t 3282 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ uint32_t 3283 drivers/scsi/lpfc/lpfc_hw.h uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ uint32_t 3287 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 : 19; /* Reserved */ uint32_t 3288 drivers/scsi/lpfc/lpfc_hw.h uint32_t cdss : 1; /* Configure Data Security SLI */ uint32_t 3289 drivers/scsi/lpfc/lpfc_hw.h uint32_t casabt : 1; /* Configure async abts status notice */ uint32_t 3290 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2 : 2; /* Reserved */ uint32_t 3291 drivers/scsi/lpfc/lpfc_hw.h uint32_t cbg : 1; /* Configure BlockGuard */ uint32_t 3292 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmv : 1; /* Configure Max VPIs */ uint32_t 3293 drivers/scsi/lpfc/lpfc_hw.h uint32_t ccrp : 1; /* Config Command Ring Polling */ uint32_t 3294 drivers/scsi/lpfc/lpfc_hw.h uint32_t csah : 1; /* Configure Synchronous Abort Handling */ uint32_t 3295 drivers/scsi/lpfc/lpfc_hw.h uint32_t chbs : 1; /* Cofigure Host Backing store */ uint32_t 3296 drivers/scsi/lpfc/lpfc_hw.h uint32_t cinb : 1; /* Enable Interrupt Notification Block */ uint32_t 3297 drivers/scsi/lpfc/lpfc_hw.h uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ uint32_t 3298 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmx : 1; /* Configure Max XRIs */ uint32_t 3299 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmr : 1; /* Configure Max RPIs */ uint32_t 3301 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmr : 1; /* Configure Max RPIs */ uint32_t 3302 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmx : 1; /* Configure Max XRIs */ uint32_t 3303 drivers/scsi/lpfc/lpfc_hw.h uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ uint32_t 3304 drivers/scsi/lpfc/lpfc_hw.h uint32_t cinb : 1; /* Enable Interrupt Notification Block */ uint32_t 3305 drivers/scsi/lpfc/lpfc_hw.h uint32_t chbs : 1; /* Cofigure Host Backing store */ uint32_t 3306 drivers/scsi/lpfc/lpfc_hw.h uint32_t csah : 1; /* Configure Synchronous Abort Handling */ uint32_t 3307 drivers/scsi/lpfc/lpfc_hw.h uint32_t ccrp : 1; /* Config Command Ring Polling */ uint32_t 3308 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmv : 1; /* Configure Max VPIs */ uint32_t 3309 drivers/scsi/lpfc/lpfc_hw.h uint32_t cbg : 1; /* Configure BlockGuard */ uint32_t 3310 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2 : 2; /* Reserved */ uint32_t 3311 drivers/scsi/lpfc/lpfc_hw.h uint32_t casabt : 1; /* Configure async abts status notice */ uint32_t 3312 drivers/scsi/lpfc/lpfc_hw.h uint32_t cdss : 1; /* Configure Data Security SLI */ uint32_t 3313 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1 : 19; /* Reserved */ uint32_t 3316 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3 : 19; /* Reserved */ uint32_t 3317 drivers/scsi/lpfc/lpfc_hw.h uint32_t gdss : 1; /* Configure Data Security SLI */ uint32_t 3318 drivers/scsi/lpfc/lpfc_hw.h uint32_t gasabt : 1; /* Grant async abts status notice */ uint32_t 3319 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4 : 2; /* Reserved */ uint32_t 3320 drivers/scsi/lpfc/lpfc_hw.h uint32_t gbg : 1; /* Grant BlockGuard */ uint32_t 3321 drivers/scsi/lpfc/lpfc_hw.h uint32_t gmv : 1; /* Grant Max VPIs */ uint32_t 3322 drivers/scsi/lpfc/lpfc_hw.h uint32_t gcrp : 1; /* Grant Command Ring Polling */ uint32_t 3323 drivers/scsi/lpfc/lpfc_hw.h uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ uint32_t 3324 drivers/scsi/lpfc/lpfc_hw.h uint32_t ghbs : 1; /* Grant Host Backing Store */ uint32_t 3325 drivers/scsi/lpfc/lpfc_hw.h uint32_t ginb : 1; /* Grant Interrupt Notification Block */ uint32_t 3326 drivers/scsi/lpfc/lpfc_hw.h uint32_t gerbm : 1; /* Grant ERBM Request */ uint32_t 3327 drivers/scsi/lpfc/lpfc_hw.h uint32_t gmx : 1; /* Grant Max XRIs */ uint32_t 3328 drivers/scsi/lpfc/lpfc_hw.h uint32_t gmr : 1; /* Grant Max RPIs */ uint32_t 3330 drivers/scsi/lpfc/lpfc_hw.h uint32_t gmr : 1; /* Grant Max RPIs */ uint32_t 3331 drivers/scsi/lpfc/lpfc_hw.h uint32_t gmx : 1; /* Grant Max XRIs */ uint32_t 3332 drivers/scsi/lpfc/lpfc_hw.h uint32_t gerbm : 1; /* Grant ERBM Request */ uint32_t 3333 drivers/scsi/lpfc/lpfc_hw.h uint32_t ginb : 1; /* Grant Interrupt Notification Block */ uint32_t 3334 drivers/scsi/lpfc/lpfc_hw.h uint32_t ghbs : 1; /* Grant Host Backing Store */ uint32_t 3335 drivers/scsi/lpfc/lpfc_hw.h uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ uint32_t 3336 drivers/scsi/lpfc/lpfc_hw.h uint32_t gcrp : 1; /* Grant Command Ring Polling */ uint32_t 3337 drivers/scsi/lpfc/lpfc_hw.h uint32_t gmv : 1; /* Grant Max VPIs */ uint32_t 3338 drivers/scsi/lpfc/lpfc_hw.h uint32_t gbg : 1; /* Grant BlockGuard */ uint32_t 3339 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4 : 2; /* Reserved */ uint32_t 3340 drivers/scsi/lpfc/lpfc_hw.h uint32_t gasabt : 1; /* Grant async abts status notice */ uint32_t 3341 drivers/scsi/lpfc/lpfc_hw.h uint32_t gdss : 1; /* Configure Data Security SLI */ uint32_t 3342 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3 : 19; /* Reserved */ uint32_t 3346 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_rpi : 16; /* Max RPIs Port should configure */ uint32_t 3347 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_xri : 16; /* Max XRIs Port should configure */ uint32_t 3349 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_xri : 16; /* Max XRIs Port should configure */ uint32_t 3350 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_rpi : 16; /* Max RPIs Port should configure */ uint32_t 3354 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ uint32_t 3355 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ uint32_t 3357 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ uint32_t 3358 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ uint32_t 3361 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd6; /* Reserved */ uint32_t 3364 drivers/scsi/lpfc/lpfc_hw.h uint32_t fips_rev : 3; /* FIPS Spec Revision */ uint32_t 3365 drivers/scsi/lpfc/lpfc_hw.h uint32_t fips_level : 4; /* FIPS Level */ uint32_t 3366 drivers/scsi/lpfc/lpfc_hw.h uint32_t sec_err : 9; /* security crypto error */ uint32_t 3367 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_vpi : 16; /* Max number of virt N-Ports */ uint32_t 3369 drivers/scsi/lpfc/lpfc_hw.h uint32_t max_vpi : 16; /* Max number of virt N-Ports */ uint32_t 3370 drivers/scsi/lpfc/lpfc_hw.h uint32_t sec_err : 9; /* security crypto error */ uint32_t 3371 drivers/scsi/lpfc/lpfc_hw.h uint32_t fips_level : 4; /* FIPS Level */ uint32_t 3372 drivers/scsi/lpfc/lpfc_hw.h uint32_t fips_rev : 3; /* FIPS Spec Revision */ uint32_t 3380 drivers/scsi/lpfc/lpfc_hw.h uint32_t dfltMsgNum:8; /* Default message number */ uint32_t 3381 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:11; /* Reserved */ uint32_t 3382 drivers/scsi/lpfc/lpfc_hw.h uint32_t NID:5; /* Number of secondary attention IDs */ uint32_t 3383 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:5; /* Reserved */ uint32_t 3384 drivers/scsi/lpfc/lpfc_hw.h uint32_t dfltPresent:1; /* Default message number present */ uint32_t 3385 drivers/scsi/lpfc/lpfc_hw.h uint32_t addFlag:1; /* Add association flag */ uint32_t 3386 drivers/scsi/lpfc/lpfc_hw.h uint32_t reportFlag:1; /* Report association flag */ uint32_t 3388 drivers/scsi/lpfc/lpfc_hw.h uint32_t reportFlag:1; /* Report association flag */ uint32_t 3389 drivers/scsi/lpfc/lpfc_hw.h uint32_t addFlag:1; /* Add association flag */ uint32_t 3390 drivers/scsi/lpfc/lpfc_hw.h uint32_t dfltPresent:1; /* Default message number present */ uint32_t 3391 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:5; /* Reserved */ uint32_t 3392 drivers/scsi/lpfc/lpfc_hw.h uint32_t NID:5; /* Number of secondary attention IDs */ uint32_t 3393 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1:11; /* Reserved */ uint32_t 3394 drivers/scsi/lpfc/lpfc_hw.h uint32_t dfltMsgNum:8; /* Default message number */ uint32_t 3396 drivers/scsi/lpfc/lpfc_hw.h uint32_t attentionConditions[2]; uint32_t 3400 drivers/scsi/lpfc/lpfc_hw.h uint32_t autoClearHA[2]; uint32_t 3402 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:16; uint32_t 3403 drivers/scsi/lpfc/lpfc_hw.h uint32_t autoClearID:16; uint32_t 3405 drivers/scsi/lpfc/lpfc_hw.h uint32_t autoClearID:16; uint32_t 3406 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:16; uint32_t 3408 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd4; uint32_t 3417 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmdEntries; uint32_t 3418 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmdAddrLow; uint32_t 3419 drivers/scsi/lpfc/lpfc_hw.h uint32_t cmdAddrHigh; uint32_t 3421 drivers/scsi/lpfc/lpfc_hw.h uint32_t rspEntries; uint32_t 3422 drivers/scsi/lpfc/lpfc_hw.h uint32_t rspAddrLow; uint32_t 3423 drivers/scsi/lpfc/lpfc_hw.h uint32_t rspAddrHigh; uint32_t 3428 drivers/scsi/lpfc/lpfc_hw.h uint32_t type:8; uint32_t 3430 drivers/scsi/lpfc/lpfc_hw.h uint32_t feature:8; uint32_t 3432 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd:12; uint32_t 3433 drivers/scsi/lpfc/lpfc_hw.h uint32_t maxRing:4; uint32_t 3435 drivers/scsi/lpfc/lpfc_hw.h uint32_t maxRing:4; uint32_t 3436 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd:12; uint32_t 3437 drivers/scsi/lpfc/lpfc_hw.h uint32_t feature:8; uint32_t 3439 drivers/scsi/lpfc/lpfc_hw.h uint32_t type:8; uint32_t 3443 drivers/scsi/lpfc/lpfc_hw.h uint32_t mailBoxSize; uint32_t 3444 drivers/scsi/lpfc/lpfc_hw.h uint32_t mbAddrLow; uint32_t 3445 drivers/scsi/lpfc/lpfc_hw.h uint32_t mbAddrHigh; uint32_t 3447 drivers/scsi/lpfc/lpfc_hw.h uint32_t hgpAddrLow; uint32_t 3448 drivers/scsi/lpfc/lpfc_hw.h uint32_t hgpAddrHigh; uint32_t 3450 drivers/scsi/lpfc/lpfc_hw.h uint32_t pgpAddrLow; uint32_t 3451 drivers/scsi/lpfc/lpfc_hw.h uint32_t pgpAddrHigh; uint32_t 3458 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd0:27; uint32_t 3459 drivers/scsi/lpfc/lpfc_hw.h uint32_t discardFarp:1; uint32_t 3460 drivers/scsi/lpfc/lpfc_hw.h uint32_t IPEnable:1; uint32_t 3461 drivers/scsi/lpfc/lpfc_hw.h uint32_t nodeName:1; uint32_t 3462 drivers/scsi/lpfc/lpfc_hw.h uint32_t portName:1; uint32_t 3463 drivers/scsi/lpfc/lpfc_hw.h uint32_t filterEnable:1; uint32_t 3465 drivers/scsi/lpfc/lpfc_hw.h uint32_t filterEnable:1; uint32_t 3466 drivers/scsi/lpfc/lpfc_hw.h uint32_t portName:1; uint32_t 3467 drivers/scsi/lpfc/lpfc_hw.h uint32_t nodeName:1; uint32_t 3468 drivers/scsi/lpfc/lpfc_hw.h uint32_t IPEnable:1; uint32_t 3469 drivers/scsi/lpfc/lpfc_hw.h uint32_t discardFarp:1; uint32_t 3470 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd:27; uint32_t 3475 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 3476 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2; uint32_t 3477 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3; uint32_t 3478 drivers/scsi/lpfc/lpfc_hw.h uint32_t IPAddress; uint32_t 3485 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd:30; uint32_t 3486 drivers/scsi/lpfc/lpfc_hw.h uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ uint32_t 3488 drivers/scsi/lpfc/lpfc_hw.h uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ uint32_t 3489 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd:30; uint32_t 3495 drivers/scsi/lpfc/lpfc_hw.h #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) uint32_t 3498 drivers/scsi/lpfc/lpfc_hw.h #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) uint32_t 3504 drivers/scsi/lpfc/lpfc_hw.h uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ uint32_t 3561 drivers/scsi/lpfc/lpfc_hw.h uint32_t unused1[16]; uint32_t 3568 drivers/scsi/lpfc/lpfc_hw.h uint32_t reserved[8]; uint32_t 3569 drivers/scsi/lpfc/lpfc_hw.h uint32_t hbq_put[16]; uint32_t 3574 drivers/scsi/lpfc/lpfc_hw.h uint32_t hbq_get[16]; uint32_t 3725 drivers/scsi/lpfc/lpfc_hw.h uint32_t reserved; uint32_t 3730 drivers/scsi/lpfc/lpfc_hw.h uint32_t reserved[4]; uint32_t 3737 drivers/scsi/lpfc/lpfc_hw.h uint32_t xrsqRo; /* Starting Relative Offset */ uint32_t 3747 drivers/scsi/lpfc/lpfc_hw.h uint32_t word4Rsvd:7; uint32_t 3748 drivers/scsi/lpfc/lpfc_hw.h uint32_t fl:1; uint32_t 3749 drivers/scsi/lpfc/lpfc_hw.h uint32_t myID:24; uint32_t 3750 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3751 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3753 drivers/scsi/lpfc/lpfc_hw.h uint32_t myID:24; uint32_t 3754 drivers/scsi/lpfc/lpfc_hw.h uint32_t fl:1; uint32_t 3755 drivers/scsi/lpfc/lpfc_hw.h uint32_t word4Rsvd:7; uint32_t 3756 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3757 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3764 drivers/scsi/lpfc/lpfc_hw.h uint32_t parmRo; uint32_t 3767 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3768 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3770 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3771 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3777 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd[3]; uint32_t 3778 drivers/scsi/lpfc/lpfc_hw.h uint32_t abortType; uint32_t 3781 drivers/scsi/lpfc/lpfc_hw.h uint32_t parm; uint32_t 3793 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd[3]; uint32_t 3794 drivers/scsi/lpfc/lpfc_hw.h uint32_t abortType; uint32_t 3795 drivers/scsi/lpfc/lpfc_hw.h uint32_t parm; uint32_t 3796 drivers/scsi/lpfc/lpfc_hw.h uint32_t iotag32; uint32_t 3801 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd[4]; uint32_t 3802 drivers/scsi/lpfc/lpfc_hw.h uint32_t parmRo; uint32_t 3804 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3805 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3807 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3808 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3816 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpi_parm; uint32_t 3817 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ uint32_t 3823 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpt_Offset; uint32_t 3824 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpt_Length; /* transfer ready for IWRITE */ uint32_t 3832 drivers/scsi/lpfc/lpfc_hw.h uint32_t xrsqRo; /* Starting Relative Offset */ uint32_t 3842 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 3843 drivers/scsi/lpfc/lpfc_hw.h uint32_t xrsqRo; /* Starting Relative Offset */ uint32_t 3851 drivers/scsi/lpfc/lpfc_hw.h uint32_t word4Rsvd:7; uint32_t 3852 drivers/scsi/lpfc/lpfc_hw.h uint32_t fl:1; uint32_t 3853 drivers/scsi/lpfc/lpfc_hw.h uint32_t myID:24; uint32_t 3854 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3855 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3857 drivers/scsi/lpfc/lpfc_hw.h uint32_t myID:24; uint32_t 3858 drivers/scsi/lpfc/lpfc_hw.h uint32_t fl:1; uint32_t 3859 drivers/scsi/lpfc/lpfc_hw.h uint32_t word4Rsvd:7; uint32_t 3860 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3861 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3868 drivers/scsi/lpfc/lpfc_hw.h uint32_t xrsqRo; /* Starting Relative Offset */ uint32_t 3875 drivers/scsi/lpfc/lpfc_hw.h uint32_t rcvd1; uint32_t 3876 drivers/scsi/lpfc/lpfc_hw.h uint32_t parmRo; uint32_t 3879 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3880 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3882 drivers/scsi/lpfc/lpfc_hw.h uint32_t remoteID:24; uint32_t 3883 drivers/scsi/lpfc/lpfc_hw.h uint32_t word5Rsvd:8; uint32_t 3890 drivers/scsi/lpfc/lpfc_hw.h uint32_t hbq_1; uint32_t 3891 drivers/scsi/lpfc/lpfc_hw.h uint32_t parmRo; uint32_t 3893 drivers/scsi/lpfc/lpfc_hw.h uint32_t rctl:8; uint32_t 3894 drivers/scsi/lpfc/lpfc_hw.h uint32_t type:8; uint32_t 3895 drivers/scsi/lpfc/lpfc_hw.h uint32_t dfctl:8; uint32_t 3896 drivers/scsi/lpfc/lpfc_hw.h uint32_t ls:1; uint32_t 3897 drivers/scsi/lpfc/lpfc_hw.h uint32_t fs:1; uint32_t 3898 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:3; uint32_t 3899 drivers/scsi/lpfc/lpfc_hw.h uint32_t si:1; uint32_t 3900 drivers/scsi/lpfc/lpfc_hw.h uint32_t bc:1; uint32_t 3901 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:1; uint32_t 3903 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd3:1; uint32_t 3904 drivers/scsi/lpfc/lpfc_hw.h uint32_t bc:1; uint32_t 3905 drivers/scsi/lpfc/lpfc_hw.h uint32_t si:1; uint32_t 3906 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd2:3; uint32_t 3907 drivers/scsi/lpfc/lpfc_hw.h uint32_t fs:1; uint32_t 3908 drivers/scsi/lpfc/lpfc_hw.h uint32_t ls:1; uint32_t 3909 drivers/scsi/lpfc/lpfc_hw.h uint32_t dfctl:8; uint32_t 3910 drivers/scsi/lpfc/lpfc_hw.h uint32_t type:8; uint32_t 3911 drivers/scsi/lpfc/lpfc_hw.h uint32_t rctl:8; uint32_t 3918 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpi_parm; uint32_t 3919 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ uint32_t 3925 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpt_Offset; uint32_t 3926 drivers/scsi/lpfc/lpfc_hw.h uint32_t fcpt_Length; /* transfer ready for IWRITE */ uint32_t 3931 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd[4]; uint32_t 3932 drivers/scsi/lpfc/lpfc_hw.h uint32_t param; uint32_t 3962 drivers/scsi/lpfc/lpfc_hw.h uint32_t word10Rsvd; uint32_t 3963 drivers/scsi/lpfc/lpfc_hw.h uint32_t acc_len; /* accumulated length */ uint32_t 3970 drivers/scsi/lpfc/lpfc_hw.h uint32_t buffer_tag; uint32_t 3976 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd; uint32_t 3977 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd1; uint32_t 3981 drivers/scsi/lpfc/lpfc_hw.h uint32_t iotag64_low; uint32_t 3982 drivers/scsi/lpfc/lpfc_hw.h uint32_t iotag64_high; uint32_t 3983 drivers/scsi/lpfc/lpfc_hw.h uint32_t ebde_count; uint32_t 3984 drivers/scsi/lpfc/lpfc_hw.h uint32_t rsvd; uint32_t 3989 drivers/scsi/lpfc/lpfc_hw.h uint32_t filler[6]; /* word 8-13 in IOCB */ uint32_t 3990 drivers/scsi/lpfc/lpfc_hw.h uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ uint32_t 4010 drivers/scsi/lpfc/lpfc_hw.h uint32_t bgstat; /* word 15 - BlockGuard Status */ uint32_t 4013 drivers/scsi/lpfc/lpfc_hw.h static inline uint32_t uint32_t 4014 drivers/scsi/lpfc/lpfc_hw.h lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) uint32_t 4020 drivers/scsi/lpfc/lpfc_hw.h static inline uint32_t uint32_t 4021 drivers/scsi/lpfc/lpfc_hw.h lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) uint32_t 4027 drivers/scsi/lpfc/lpfc_hw.h static inline uint32_t uint32_t 4028 drivers/scsi/lpfc/lpfc_hw.h lpfc_bgs_get_bg_prof(uint32_t bgstat) uint32_t 4034 drivers/scsi/lpfc/lpfc_hw.h static inline uint32_t uint32_t 4035 drivers/scsi/lpfc/lpfc_hw.h lpfc_bgs_get_invalid_prof(uint32_t bgstat) uint32_t 4041 drivers/scsi/lpfc/lpfc_hw.h static inline uint32_t uint32_t 4042 drivers/scsi/lpfc/lpfc_hw.h lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) uint32_t 4048 drivers/scsi/lpfc/lpfc_hw.h static inline uint32_t uint32_t 4049 drivers/scsi/lpfc/lpfc_hw.h lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) uint32_t 4055 drivers/scsi/lpfc/lpfc_hw.h static inline uint32_t uint32_t 4056 drivers/scsi/lpfc/lpfc_hw.h lpfc_bgs_get_reftag_err(uint32_t bgstat) uint32_t 4062 drivers/scsi/lpfc/lpfc_hw.h static inline uint32_t uint32_t 4063 drivers/scsi/lpfc/lpfc_hw.h lpfc_bgs_get_apptag_err(uint32_t bgstat) uint32_t 4069 drivers/scsi/lpfc/lpfc_hw.h static inline uint32_t uint32_t 4070 drivers/scsi/lpfc/lpfc_hw.h lpfc_bgs_get_guard_err(uint32_t bgstat) uint32_t 4078 drivers/scsi/lpfc/lpfc_hw.h uint32_t io_tag64_low; uint32_t 4079 drivers/scsi/lpfc/lpfc_hw.h uint32_t io_tag64_high; uint32_t 4091 drivers/scsi/lpfc/lpfc_hw.h uint32_t reserved4; uint32_t 4123 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ uint32_t 4152 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpTimeout:8; uint32_t 4153 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpXS:1; uint32_t 4154 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpFCP2Rcvy:1; uint32_t 4155 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpPU:2; uint32_t 4156 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpIr:1; uint32_t 4157 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpClass:3; uint32_t 4158 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpCommand:8; uint32_t 4159 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpStatus:4; uint32_t 4160 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpBdeCount:2; uint32_t 4161 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpLe:1; uint32_t 4162 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpOwner:1; /* Low order bit word 7 */ uint32_t 4164 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpOwner:1; /* Low order bit word 7 */ uint32_t 4165 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpLe:1; uint32_t 4166 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpBdeCount:2; uint32_t 4167 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpStatus:4; uint32_t 4168 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpCommand:8; uint32_t 4169 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpClass:3; uint32_t 4170 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpIr:1; uint32_t 4171 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpPU:2; uint32_t 4172 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpFCP2Rcvy:1; uint32_t 4173 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpXS:1; uint32_t 4174 drivers/scsi/lpfc/lpfc_hw.h uint32_t ulpTimeout:8; uint32_t 4183 drivers/scsi/lpfc/lpfc_hw.h uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ uint32_t 4237 drivers/scsi/lpfc/lpfc_hw.h sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) uint32_t 4245 drivers/scsi/lpfc/lpfc_hw.h uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; uint32_t 61 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addr_lo; uint32_t 62 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addr_hi; uint32_t 66 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 229 drivers/scsi/lpfc/lpfc_hw4.h uint32_t w; uint32_t 232 drivers/scsi/lpfc/lpfc_hw4.h uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED uint32_t 234 drivers/scsi/lpfc/lpfc_hw4.h uint32_t bdeSize:24; /* Size of buffer (in bytes) */ uint32_t 236 drivers/scsi/lpfc/lpfc_hw4.h uint32_t bdeSize:24; /* Size of buffer (in bytes) */ uint32_t 237 drivers/scsi/lpfc/lpfc_hw4.h uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED uint32_t 249 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addrLow; uint32_t 250 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addrHigh; uint32_t 257 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 277 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0_rsvd; /* Word0 must be reserved */ uint32_t 278 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 284 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 291 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 302 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 303 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5_rsvd; /* Word5 must be reserved */ uint32_t 308 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 325 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved0; uint32_t 326 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved1; uint32_t 327 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved2; uint32_t 328 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 377 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 390 drivers/scsi/lpfc/lpfc_hw4.h uint32_t total_data_placed; uint32_t 391 drivers/scsi/lpfc/lpfc_hw4.h uint32_t parameter; uint32_t 407 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 430 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved0; uint32_t 431 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved1; uint32_t 432 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 439 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 449 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 453 drivers/scsi/lpfc/lpfc_hw4.h uint32_t parameter; uint32_t 454 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 461 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 487 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 498 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 502 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 515 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 545 drivers/scsi/lpfc/lpfc_hw4.h uint32_t address_hi; uint32_t 546 drivers/scsi/lpfc/lpfc_hw4.h uint32_t address_lo; uint32_t 551 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addr_hi; uint32_t 552 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addr_lo; uint32_t 553 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 560 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 567 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 890 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 897 drivers/scsi/lpfc/lpfc_hw4.h uint32_t payload_length; uint32_t 898 drivers/scsi/lpfc/lpfc_hw4.h uint32_t tag_lo; uint32_t 899 drivers/scsi/lpfc/lpfc_hw4.h uint32_t tag_hi; uint32_t 900 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved5; uint32_t 905 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 918 drivers/scsi/lpfc/lpfc_hw4.h uint32_t timeout; uint32_t 919 drivers/scsi/lpfc/lpfc_hw4.h uint32_t request_length; uint32_t 920 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word9; uint32_t 937 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 947 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 954 drivers/scsi/lpfc/lpfc_hw4.h uint32_t response_length; uint32_t 955 drivers/scsi/lpfc/lpfc_hw4.h uint32_t actual_response_length; uint32_t 1051 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1063 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 1072 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 1076 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved3; uint32_t 1080 drivers/scsi/lpfc/lpfc_hw4.h uint32_t eq_id; uint32_t 1081 drivers/scsi/lpfc/lpfc_hw4.h uint32_t phase; uint32_t 1082 drivers/scsi/lpfc/lpfc_hw4.h uint32_t delay_multi; uint32_t 1087 drivers/scsi/lpfc/lpfc_hw4.h uint32_t sgl_pg0_addr_lo; uint32_t 1088 drivers/scsi/lpfc/lpfc_hw4.h uint32_t sgl_pg0_addr_hi; uint32_t 1089 drivers/scsi/lpfc/lpfc_hw4.h uint32_t sgl_pg1_addr_lo; uint32_t 1090 drivers/scsi/lpfc/lpfc_hw4.h uint32_t sgl_pg1_addr_hi; uint32_t 1095 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1108 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1113 drivers/scsi/lpfc/lpfc_hw4.h uint32_t pa_lo; uint32_t 1114 drivers/scsi/lpfc/lpfc_hw4.h uint32_t pa_hi; uint32_t 1115 drivers/scsi/lpfc/lpfc_hw4.h uint32_t length; uint32_t 1132 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1140 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1152 drivers/scsi/lpfc/lpfc_hw4.h uint32_t num_eq; uint32_t 1156 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1165 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1171 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1178 drivers/scsi/lpfc/lpfc_hw4.h uint32_t context[2]; uint32_t 1187 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 1202 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 1214 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1221 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1238 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 1245 drivers/scsi/lpfc/lpfc_hw4.h uint32_t lpfc_cq_context_count; /* Version 2 Only */ uint32_t 1246 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved1; uint32_t 1253 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1264 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1276 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1283 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 1305 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 1315 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 1322 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 1329 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 1336 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 1343 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 1350 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word8; uint32_t 1357 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word9; uint32_t 1364 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 1374 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1389 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1395 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1401 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved0; uint32_t 1402 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved1; uint32_t 1403 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved2; uint32_t 1404 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved3; uint32_t 1411 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1422 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word9; uint32_t 1431 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; /* Word 0 is the same as in v0 */ uint32_t 1432 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 1454 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 1458 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1462 drivers/scsi/lpfc/lpfc_hw4.h uint32_t doorbell_offset; uint32_t 1463 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 1475 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1482 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 1486 drivers/scsi/lpfc/lpfc_hw4.h uint32_t doorbell_offset; uint32_t 1487 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 1494 drivers/scsi/lpfc/lpfc_hw4.h uint32_t dpp_offset; uint32_t 1503 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1509 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1518 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1541 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 1548 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 1558 drivers/scsi/lpfc/lpfc_hw4.h uint32_t buffer_size; /* Version 1 Only */ uint32_t 1565 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1582 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1589 drivers/scsi/lpfc/lpfc_hw4.h uint32_t doorbell_offset; uint32_t 1590 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 1605 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1634 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1641 drivers/scsi/lpfc/lpfc_hw4.h uint32_t doorbell_offset; uint32_t 1642 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 1657 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1663 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1669 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1680 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 1684 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved2; uint32_t 1685 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved3; uint32_t 1692 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1700 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1712 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1719 drivers/scsi/lpfc/lpfc_hw4.h uint32_t async_evt_bmap; uint32_t 1751 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1766 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1772 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1789 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 1795 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 1809 drivers/scsi/lpfc/lpfc_hw4.h uint32_t config_number; uint32_t 1811 drivers/scsi/lpfc/lpfc_hw4.h uint32_t asic_revision; uint32_t 1812 drivers/scsi/lpfc/lpfc_hw4.h uint32_t physical_port; uint32_t 1813 drivers/scsi/lpfc/lpfc_hw4.h uint32_t function_mode; uint32_t 1817 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ulp0_mode; uint32_t 1820 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ulp0_nap_words[12]; uint32_t 1821 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ulp1_mode; uint32_t 1822 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ulp1_nap_words[12]; uint32_t 1823 drivers/scsi/lpfc/lpfc_hw4.h uint32_t function_capabilities; uint32_t 1824 drivers/scsi/lpfc/lpfc_hw4.h uint32_t cqid_base; uint32_t 1825 drivers/scsi/lpfc/lpfc_hw4.h uint32_t cqid_tot; uint32_t 1826 drivers/scsi/lpfc/lpfc_hw4.h uint32_t eqid_base; uint32_t 1827 drivers/scsi/lpfc/lpfc_hw4.h uint32_t eqid_tot; uint32_t 1828 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ulp0_nap2_words[2]; uint32_t 1829 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ulp1_nap2_words[2]; uint32_t 1835 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 1853 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; /* RESERVED */ uint32_t 1857 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 1870 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1887 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1896 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1912 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1921 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1928 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 1935 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 1944 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 1970 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 1979 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 1997 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 2004 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 2016 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 2023 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rpi_paddr_lo; uint32_t 2024 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rpi_paddr_hi; uint32_t 2028 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addr_hi; uint32_t 2029 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addr_lo; uint32_t 2031 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2050 drivers/scsi/lpfc/lpfc_hw4.h uint32_t sge_len; uint32_t 2071 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ref_tag; uint32_t 2072 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ref_tag_tran; uint32_t 2074 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2093 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 2125 drivers/scsi/lpfc/lpfc_hw4.h uint32_t max_rcv_size; uint32_t 2126 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fka_adv_period; uint32_t 2127 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fip_priority; uint32_t 2128 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 2141 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 2156 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 2169 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 2182 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 2201 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word8; uint32_t 2209 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word137; uint32_t 2222 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word138; uint32_t 2241 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 2247 drivers/scsi/lpfc/lpfc_hw4.h uint32_t eventag; uint32_t 2250 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word11; uint32_t 2258 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 2267 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 2278 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 2282 drivers/scsi/lpfc/lpfc_hw4.h uint32_t resvd; uint32_t 2283 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word12; uint32_t 2329 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2345 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2352 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 2359 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 2368 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2378 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2385 drivers/scsi/lpfc/lpfc_hw4.h uint32_t wwn[2]; uint32_t 2387 drivers/scsi/lpfc/lpfc_hw4.h uint32_t e_d_tov; uint32_t 2388 drivers/scsi/lpfc/lpfc_hw4.h uint32_t r_a_tov; uint32_t 2389 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 2402 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2412 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1_rsvd; uint32_t 2413 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2417 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3_rsvd; uint32_t 2418 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 2434 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5_rsvd; uint32_t 2435 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 2439 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 2452 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word8; uint32_t 2468 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1_rsvd; uint32_t 2469 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2476 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2487 drivers/scsi/lpfc/lpfc_hw4.h uint32_t event_tag; uint32_t 2492 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2499 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2506 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 2513 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 2526 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 2539 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 2552 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 2565 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word8; uint32_t 2581 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2588 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2595 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 2602 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 2615 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 2628 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 2641 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 2654 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word8; uint32_t 2715 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word9; uint32_t 2725 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 2726 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word11; uint32_t 2727 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word12; uint32_t 2728 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word13; uint32_t 2729 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word14; uint32_t 2730 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word15; uint32_t 2731 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word16; uint32_t 2735 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1_rsv; uint32_t 2736 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2743 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2758 drivers/scsi/lpfc/lpfc_hw4.h uint32_t first_hw_rev; uint32_t 2760 drivers/scsi/lpfc/lpfc_hw4.h uint32_t second_hw_rev; uint32_t 2761 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4_rsvd; uint32_t 2762 drivers/scsi/lpfc/lpfc_hw4.h uint32_t third_hw_rev; uint32_t 2763 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 2776 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7_rsvd; uint32_t 2777 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fw_id_rev; uint32_t 2779 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ulp_fw_id_rev; uint32_t 2781 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word18_47_rsvd[30]; uint32_t 2782 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word48; uint32_t 2786 drivers/scsi/lpfc/lpfc_hw4.h uint32_t vpd_paddr_low; uint32_t 2787 drivers/scsi/lpfc/lpfc_hw4.h uint32_t vpd_paddr_high; uint32_t 2788 drivers/scsi/lpfc/lpfc_hw4.h uint32_t avail_vpd_len; uint32_t 2789 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_52_63[12]; uint32_t 2793 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2797 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2815 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_3; uint32_t 2816 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 2820 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_5; uint32_t 2821 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 2828 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_7; uint32_t 2829 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word8; uint32_t 2839 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word9; uint32_t 2843 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_10; uint32_t 2844 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_11; uint32_t 2845 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word12; uint32_t 2852 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word13; uint32_t 2859 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word14; uint32_t 2866 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word15; uint32_t 2873 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word16; uint32_t 2877 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word17; uint32_t 2884 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word18; uint32_t 2894 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2898 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2932 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 2966 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 2979 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 2989 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 3002 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 3015 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd[27]; uint32_t 3022 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 3029 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 3036 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 3040 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addr_lo; uint32_t 3041 drivers/scsi/lpfc/lpfc_hw4.h uint32_t addr_hi; uint32_t 3042 drivers/scsi/lpfc/lpfc_hw4.h uint32_t return_len; uint32_t 3238 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 3251 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 3267 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 3283 drivers/scsi/lpfc/lpfc_hw4.h uint32_t sge_supp_len; uint32_t 3285 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 3295 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 3302 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 3309 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word8; uint32_t 3319 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word9; uint32_t 3326 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 3333 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word11; uint32_t 3343 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word12; uint32_t 3350 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_13_63[51]; uint32_t 3356 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 3360 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 3379 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 3383 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 3384 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 3394 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 3395 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 3399 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 3400 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word8; uint32_t 3413 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word9; uint32_t 3414 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 3418 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word11; uint32_t 3422 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word12; uint32_t 3441 drivers/scsi/lpfc/lpfc_hw4.h uint32_t sge_supp_len; uint32_t 3442 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word14; uint32_t 3452 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word15; uint32_t 3453 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word16; uint32_t 3454 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word17; uint32_t 3455 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word18; uint32_t 3456 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word19; uint32_t 3487 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word20; uint32_t 3492 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word21; /* RESERVED */ uint32_t 3493 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word22; /* RESERVED */ uint32_t 3494 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word23; /* RESERVED */ uint32_t 3496 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word24; uint32_t 3505 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word25; uint32_t 3514 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word26; /* Chain SGE initial value LOW */ uint32_t 3515 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word27; /* Chain SGE initial value HIGH */ uint32_t 3523 drivers/scsi/lpfc/lpfc_hw4.h uint32_t feature; uint32_t 3524 drivers/scsi/lpfc/lpfc_hw4.h uint32_t param_len; uint32_t 3525 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 3535 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 3549 drivers/scsi/lpfc/lpfc_hw4.h uint32_t param_id; uint32_t 3550 drivers/scsi/lpfc/lpfc_hw4.h uint32_t param_len; uint32_t 3556 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 3560 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 3561 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 3571 drivers/scsi/lpfc/lpfc_hw4.h uint32_t desc[LPFC_RSRC_DESC_WSIZE]; uint32_t 3575 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 3583 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 3587 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved; uint32_t 3588 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 3598 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 3605 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 3616 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 3623 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 3630 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 3637 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 3644 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 3651 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 3652 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 3653 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word8; uint32_t 3654 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word9; uint32_t 3655 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 3656 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word11; uint32_t 3657 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word12; uint32_t 3658 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word13; uint32_t 3675 drivers/scsi/lpfc/lpfc_hw4.h uint32_t bw_min; uint32_t 3676 drivers/scsi/lpfc/lpfc_hw4.h uint32_t bw_max; uint32_t 3677 drivers/scsi/lpfc/lpfc_hw4.h uint32_t iops_min; uint32_t 3678 drivers/scsi/lpfc/lpfc_hw4.h uint32_t iops_max; uint32_t 3679 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved[4]; uint32_t 3684 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrc_desc_count; uint32_t 3698 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrc_desc_count; uint32_t 3709 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 3724 drivers/scsi/lpfc/lpfc_hw4.h uint32_t version_string[8]; uint32_t 3725 drivers/scsi/lpfc/lpfc_hw4.h uint32_t manufacturer_name[8]; uint32_t 3726 drivers/scsi/lpfc/lpfc_hw4.h uint32_t supported_modes; uint32_t 3727 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word17; uint32_t 3734 drivers/scsi/lpfc/lpfc_hw4.h uint32_t mbx_da_struct_ver; uint32_t 3735 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ep_fw_da_struct_ver; uint32_t 3736 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ncsi_ver_str[3]; uint32_t 3737 drivers/scsi/lpfc/lpfc_hw4.h uint32_t dflt_ext_timeout; uint32_t 3738 drivers/scsi/lpfc/lpfc_hw4.h uint32_t model_number[8]; uint32_t 3739 drivers/scsi/lpfc/lpfc_hw4.h uint32_t description[16]; uint32_t 3740 drivers/scsi/lpfc/lpfc_hw4.h uint32_t serial_number[8]; uint32_t 3741 drivers/scsi/lpfc/lpfc_hw4.h uint32_t ip_ver_str[8]; uint32_t 3742 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fw_ver_str[8]; uint32_t 3743 drivers/scsi/lpfc/lpfc_hw4.h uint32_t bios_ver_str[8]; uint32_t 3744 drivers/scsi/lpfc/lpfc_hw4.h uint32_t redboot_ver_str[8]; uint32_t 3745 drivers/scsi/lpfc/lpfc_hw4.h uint32_t driver_ver_str[8]; uint32_t 3746 drivers/scsi/lpfc/lpfc_hw4.h uint32_t flash_fw_ver_str[8]; uint32_t 3747 drivers/scsi/lpfc/lpfc_hw4.h uint32_t functionality; uint32_t 3748 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word105; uint32_t 3758 drivers/scsi/lpfc/lpfc_hw4.h uint32_t gen_guid1_12[3]; uint32_t 3759 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word109; uint32_t 3769 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word110; uint32_t 3776 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word111; uint32_t 3792 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fw_post_status; uint32_t 3793 drivers/scsi/lpfc/lpfc_hw4.h uint32_t hba_mtu[8]; uint32_t 3794 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word121; uint32_t 3795 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved1[3]; uint32_t 3796 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word125; uint32_t 3803 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word126; uint32_t 3810 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word127; uint32_t 3823 drivers/scsi/lpfc/lpfc_hw4.h uint32_t unique_id[2]; uint32_t 3824 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word130; uint32_t 3828 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved2[4]; uint32_t 3840 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 3846 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 3880 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 3890 drivers/scsi/lpfc/lpfc_hw4.h uint32_t write_offset; uint32_t 3891 drivers/scsi/lpfc/lpfc_hw4.h uint32_t object_name[26]; uint32_t 3892 drivers/scsi/lpfc/lpfc_hw4.h uint32_t bde_count; uint32_t 3896 drivers/scsi/lpfc/lpfc_hw4.h uint32_t actual_write_length; uint32_t 3897 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 3912 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 3920 drivers/scsi/lpfc/lpfc_hw4.h uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; uint32_t 3981 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 3988 drivers/scsi/lpfc/lpfc_hw4.h uint32_t mcqe_tag0; uint32_t 3989 drivers/scsi/lpfc/lpfc_hw4.h uint32_t mcqe_tag1; uint32_t 3990 drivers/scsi/lpfc/lpfc_hw4.h uint32_t trailer; uint32_t 4021 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 4053 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 4064 drivers/scsi/lpfc/lpfc_hw4.h uint32_t event_tag; uint32_t 4065 drivers/scsi/lpfc/lpfc_hw4.h uint32_t trailer; uint32_t 4071 drivers/scsi/lpfc/lpfc_hw4.h uint32_t index; uint32_t 4072 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 4079 drivers/scsi/lpfc/lpfc_hw4.h uint32_t event_tag; uint32_t 4080 drivers/scsi/lpfc/lpfc_hw4.h uint32_t trailer; uint32_t 4089 drivers/scsi/lpfc/lpfc_hw4.h uint32_t tlv_ttl; uint32_t 4090 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved; uint32_t 4091 drivers/scsi/lpfc/lpfc_hw4.h uint32_t event_tag; uint32_t 4092 drivers/scsi/lpfc/lpfc_hw4.h uint32_t trailer; uint32_t 4096 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 4103 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 4107 drivers/scsi/lpfc/lpfc_hw4.h uint32_t event_tag; uint32_t 4108 drivers/scsi/lpfc/lpfc_hw4.h uint32_t trailer; uint32_t 4114 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 4181 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 4197 drivers/scsi/lpfc/lpfc_hw4.h uint32_t event_tag; uint32_t 4198 drivers/scsi/lpfc/lpfc_hw4.h uint32_t trailer; uint32_t 4205 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word0; uint32_t 4218 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 4253 drivers/scsi/lpfc/lpfc_hw4.h uint32_t event_data1; uint32_t 4254 drivers/scsi/lpfc/lpfc_hw4.h uint32_t event_data2; uint32_t 4255 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved; uint32_t 4256 drivers/scsi/lpfc/lpfc_hw4.h uint32_t trailer; uint32_t 4283 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word6; uint32_t 4290 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word7; uint32_t 4330 drivers/scsi/lpfc/lpfc_hw4.h uint32_t abort_tag; /* word 8 in WQE */ uint32_t 4331 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word9; uint32_t 4347 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word10; uint32_t 4404 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word11; uint32_t 4437 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 4454 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 4455 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 4456 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 4458 drivers/scsi/lpfc/lpfc_hw4.h uint32_t payload[4]; uint32_t 4463 drivers/scsi/lpfc/lpfc_hw4.h uint32_t payload_len; uint32_t 4464 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 4476 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word12; uint32_t 4483 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word13; uint32_t 4487 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word14; uint32_t 4488 drivers/scsi/lpfc/lpfc_hw4.h uint32_t max_response_payload_len; uint32_t 4493 drivers/scsi/lpfc/lpfc_hw4.h uint32_t response_payload_len; uint32_t 4494 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 4503 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word12; uint32_t 4507 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_13_15[3]; uint32_t 4511 drivers/scsi/lpfc/lpfc_hw4.h uint32_t payload0; uint32_t 4529 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 4536 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 4543 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd3; uint32_t 4544 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd4; uint32_t 4547 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word12; uint32_t 4551 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_13_15[3]; uint32_t 4555 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 4581 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd3; uint32_t 4582 drivers/scsi/lpfc/lpfc_hw4.h uint32_t relative_offset; uint32_t 4585 drivers/scsi/lpfc/lpfc_hw4.h uint32_t xmit_len; uint32_t 4586 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_12_15[3]; uint32_t 4590 drivers/scsi/lpfc/lpfc_hw4.h uint32_t seq_payload_len; uint32_t 4591 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd4; uint32_t 4594 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_12_15[4]; uint32_t 4599 drivers/scsi/lpfc/lpfc_hw4.h uint32_t request_payload_len; uint32_t 4600 drivers/scsi/lpfc/lpfc_hw4.h uint32_t relative_offset; uint32_t 4603 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_12_14[3]; uint32_t 4604 drivers/scsi/lpfc/lpfc_hw4.h uint32_t max_response_payload_len; uint32_t 4612 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word1; uint32_t 4626 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word_rsvd2; uint32_t 4627 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word_rsvd3; uint32_t 4629 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word4; uint32_t 4648 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word5; uint32_t 4656 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd[5]; /* words 0-4 */ uint32_t 4659 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_12_15[4]; /* word 12-15 */ uint32_t 4666 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd[3]; uint32_t 4667 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 4674 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd4; uint32_t 4675 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd5; uint32_t 4677 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_12_15[4]; /* word 12-15 */ uint32_t 4682 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 4689 drivers/scsi/lpfc/lpfc_hw4.h uint32_t total_xfer_len; uint32_t 4690 drivers/scsi/lpfc/lpfc_hw4.h uint32_t initial_xfer_len; uint32_t 4692 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd12; uint32_t 4698 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 4705 drivers/scsi/lpfc/lpfc_hw4.h uint32_t total_xfer_len; /* word 4 */ uint32_t 4706 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd5; /* word 5 */ uint32_t 4708 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd12; uint32_t 4714 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word3; uint32_t 4721 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd4; /* word 4 */ uint32_t 4722 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsrvd5; /* word 5 */ uint32_t 4724 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_12_15[4]; /* word 12-15 */ uint32_t 4729 drivers/scsi/lpfc/lpfc_hw4.h uint32_t response_len; uint32_t 4730 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_4_5[2]; uint32_t 4732 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_12_15[4]; /* word 12-15 */ uint32_t 4737 drivers/scsi/lpfc/lpfc_hw4.h uint32_t payload_offset_len; uint32_t 4738 drivers/scsi/lpfc/lpfc_hw4.h uint32_t relative_offset; uint32_t 4739 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved; uint32_t 4741 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fcp_data_len; /* word 12 */ uint32_t 4742 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_13_15[3]; /* word 13-15 */ uint32_t 4747 drivers/scsi/lpfc/lpfc_hw4.h uint32_t payload_offset_len; uint32_t 4748 drivers/scsi/lpfc/lpfc_hw4.h uint32_t relative_offset; uint32_t 4749 drivers/scsi/lpfc/lpfc_hw4.h uint32_t reserved; uint32_t 4751 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fcp_data_len; /* word 12 */ uint32_t 4752 drivers/scsi/lpfc/lpfc_hw4.h uint32_t rsvd_13_15[3]; /* word 13-15 */ uint32_t 4760 drivers/scsi/lpfc/lpfc_hw4.h uint32_t frame_len; /* word 3 */ uint32_t 4761 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fc_hdr_wd0; /* word 4 */ uint32_t 4762 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fc_hdr_wd1; /* word 5 */ uint32_t 4764 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fc_hdr_wd2; /* word 12 */ uint32_t 4765 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fc_hdr_wd3; /* word 13 */ uint32_t 4766 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fc_hdr_wd4; /* word 14 */ uint32_t 4767 drivers/scsi/lpfc/lpfc_hw4.h uint32_t fc_hdr_wd5; /* word 15 */ uint32_t 4771 drivers/scsi/lpfc/lpfc_hw4.h uint32_t words[16]; uint32_t 4791 drivers/scsi/lpfc/lpfc_hw4.h uint32_t words[32]; uint32_t 4814 drivers/scsi/lpfc/lpfc_hw4.h uint32_t size; uint32_t 4815 drivers/scsi/lpfc/lpfc_hw4.h uint32_t magic_number; uint32_t 4816 drivers/scsi/lpfc/lpfc_hw4.h uint32_t word2; uint32_t 72 drivers/scsi/lpfc/lpfc_init.c static uint32_t lpfc_present_cpu; uint32_t 94 drivers/scsi/lpfc/lpfc_init.c static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t); uint32_t 142 drivers/scsi/lpfc/lpfc_init.c uint32_t *ptext = (uint32_t *) licensed; uint32_t 144 drivers/scsi/lpfc/lpfc_init.c for (i = 0; i < 56; i += sizeof (uint32_t), ptext++) uint32_t 176 drivers/scsi/lpfc/lpfc_init.c phba->sli3_options &= (uint32_t)LPFC_SLI3_BG_ENABLED; uint32_t 211 drivers/scsi/lpfc/lpfc_init.c memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t)); uint32_t 308 drivers/scsi/lpfc/lpfc_init.c uint32_t prog_id_word; uint32_t 418 drivers/scsi/lpfc/lpfc_init.c uint32_t status, timeout; uint32_t 689 drivers/scsi/lpfc/lpfc_init.c lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag) uint32_t 710 drivers/scsi/lpfc/lpfc_init.c lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology, uint32_t 711 drivers/scsi/lpfc/lpfc_init.c uint32_t flag) uint32_t 794 drivers/scsi/lpfc/lpfc_init.c lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag) uint32_t 1152 drivers/scsi/lpfc/lpfc_init.c uint32_t tmo_posted; uint32_t 1244 drivers/scsi/lpfc/lpfc_init.c uint32_t usdelay; uint32_t 1548 drivers/scsi/lpfc/lpfc_init.c uint32_t old_host_status = phba->work_hs; uint32_t 1645 drivers/scsi/lpfc/lpfc_init.c uint32_t event_data; uint32_t 1714 drivers/scsi/lpfc/lpfc_init.c temp_event_data.data = (uint32_t)temperature; uint32_t 1773 drivers/scsi/lpfc/lpfc_init.c uint32_t intr_mode; uint32_t 1828 drivers/scsi/lpfc/lpfc_init.c uint32_t event_data; uint32_t 1830 drivers/scsi/lpfc/lpfc_init.c uint32_t if_type; uint32_t 1832 drivers/scsi/lpfc/lpfc_init.c uint32_t reg_err1, reg_err2; uint32_t 1833 drivers/scsi/lpfc/lpfc_init.c uint32_t uerrlo_reg, uemasklo_reg; uint32_t 1834 drivers/scsi/lpfc/lpfc_init.c uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2; uint32_t 2035 drivers/scsi/lpfc/lpfc_init.c volatile uint32_t control; uint32_t 2138 drivers/scsi/lpfc/lpfc_init.c (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2], uint32_t 2139 drivers/scsi/lpfc/lpfc_init.c (uint32_t) vpd[3]); uint32_t 2671 drivers/scsi/lpfc/lpfc_init.c lpfc_sha_init(uint32_t * HashResultPointer) uint32_t 2691 drivers/scsi/lpfc/lpfc_init.c lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer) uint32_t 2694 drivers/scsi/lpfc/lpfc_init.c uint32_t TEMP; uint32_t 2695 drivers/scsi/lpfc/lpfc_init.c uint32_t A, B, C, D, E; uint32_t 2748 drivers/scsi/lpfc/lpfc_init.c lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking) uint32_t 2761 drivers/scsi/lpfc/lpfc_init.c lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit) uint32_t 2764 drivers/scsi/lpfc/lpfc_init.c uint32_t *HashWorking; uint32_t 2765 drivers/scsi/lpfc/lpfc_init.c uint32_t *pwwnn = (uint32_t *) phba->wwnn; uint32_t 2767 drivers/scsi/lpfc/lpfc_init.c HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL); uint32_t 4531 drivers/scsi/lpfc/lpfc_init.c (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) | uint32_t 4532 drivers/scsi/lpfc/lpfc_init.c (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb; uint32_t 4729 drivers/scsi/lpfc/lpfc_init.c uint32_t uint32_t 4732 drivers/scsi/lpfc/lpfc_init.c uint32_t link_speed; uint32_t 4781 drivers/scsi/lpfc/lpfc_init.c static uint32_t uint32_t 4782 drivers/scsi/lpfc/lpfc_init.c lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code, uint32_t 4785 drivers/scsi/lpfc/lpfc_init.c uint32_t port_speed; uint32_t 5307 drivers/scsi/lpfc/lpfc_init.c temp_event_data.data = (uint32_t)acqe_sli->event_data1; uint32_t 5324 drivers/scsi/lpfc/lpfc_init.c temp_event_data.data = (uint32_t)acqe_sli->event_data1; uint32_t 5963 drivers/scsi/lpfc/lpfc_init.c static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode) uint32_t 7621 drivers/scsi/lpfc/lpfc_init.c uint32_t old_mask; uint32_t 7622 drivers/scsi/lpfc/lpfc_init.c uint32_t old_guard; uint32_t 7859 drivers/scsi/lpfc/lpfc_init.c uint32_t if_type; uint32_t 7991 drivers/scsi/lpfc/lpfc_init.c lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type) uint32_t 8079 drivers/scsi/lpfc/lpfc_init.c lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba, uint32_t if_type) uint32_t 8126 drivers/scsi/lpfc/lpfc_init.c lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf) uint32_t 8166 drivers/scsi/lpfc/lpfc_init.c uint32_t bmbx_size; uint32_t 8169 drivers/scsi/lpfc/lpfc_init.c uint32_t pa_addr; uint32_t 8213 drivers/scsi/lpfc/lpfc_init.c pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff); uint32_t 8214 drivers/scsi/lpfc/lpfc_init.c dma_address->addr_hi = (uint32_t) ((pa_addr << 2) | uint32_t 8217 drivers/scsi/lpfc/lpfc_init.c pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff); uint32_t 8218 drivers/scsi/lpfc/lpfc_init.c dma_address->addr_lo = (uint32_t) ((pa_addr << 2) | uint32_t 8266 drivers/scsi/lpfc/lpfc_init.c uint32_t shdr_status, shdr_add_status; uint32_t 8271 drivers/scsi/lpfc/lpfc_init.c uint32_t if_type, qmin; uint32_t 8566 drivers/scsi/lpfc/lpfc_init.c uint32_t if_type, rc = 0; uint32_t 8567 drivers/scsi/lpfc/lpfc_init.c uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0, uint32_t 9118 drivers/scsi/lpfc/lpfc_init.c uint32_t idx; uint32_t 9240 drivers/scsi/lpfc/lpfc_init.c int qidx, uint32_t qtype) uint32_t 9258 drivers/scsi/lpfc/lpfc_init.c qidx, (uint32_t)rc); uint32_t 9276 drivers/scsi/lpfc/lpfc_init.c qidx, (uint32_t)rc); uint32_t 9355 drivers/scsi/lpfc/lpfc_init.c uint32_t shdr_status, shdr_add_status; uint32_t 9361 drivers/scsi/lpfc/lpfc_init.c uint32_t length, usdelay; uint32_t 9443 drivers/scsi/lpfc/lpfc_init.c cpup->eq, (uint32_t)rc); uint32_t 9475 drivers/scsi/lpfc/lpfc_init.c qidx, (uint32_t)rc); uint32_t 9502 drivers/scsi/lpfc/lpfc_init.c (uint32_t)rc); uint32_t 9522 drivers/scsi/lpfc/lpfc_init.c (uint32_t)rc); uint32_t 9533 drivers/scsi/lpfc/lpfc_init.c "rc = 0x%x\n", (uint32_t)rc); uint32_t 9561 drivers/scsi/lpfc/lpfc_init.c (uint32_t)rc); uint32_t 9585 drivers/scsi/lpfc/lpfc_init.c "rc = 0x%x\n", (uint32_t)rc); uint32_t 9619 drivers/scsi/lpfc/lpfc_init.c (uint32_t)rc); uint32_t 9633 drivers/scsi/lpfc/lpfc_init.c (uint32_t)rc); uint32_t 9660 drivers/scsi/lpfc/lpfc_init.c "rc = 0x%x\n", (uint32_t)rc); uint32_t 9972 drivers/scsi/lpfc/lpfc_init.c uint32_t rc = 0, if_type; uint32_t 9973 drivers/scsi/lpfc/lpfc_init.c uint32_t shdr_status, shdr_add_status; uint32_t 9974 drivers/scsi/lpfc/lpfc_init.c uint32_t rdy_chk; uint32_t 9975 drivers/scsi/lpfc/lpfc_init.c uint32_t port_reset = 0; uint32_t 10106 drivers/scsi/lpfc/lpfc_init.c uint32_t if_type; uint32_t 10318 drivers/scsi/lpfc/lpfc_init.c uint32_t if_type; uint32_t 10499 drivers/scsi/lpfc/lpfc_init.c static uint32_t uint32_t 10500 drivers/scsi/lpfc/lpfc_init.c lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode) uint32_t 10502 drivers/scsi/lpfc/lpfc_init.c uint32_t intr_mode = LPFC_INTR_ERROR; uint32_t 11279 drivers/scsi/lpfc/lpfc_init.c static uint32_t uint32_t 11280 drivers/scsi/lpfc/lpfc_init.c lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode) uint32_t 11282 drivers/scsi/lpfc/lpfc_init.c uint32_t intr_mode = LPFC_INTR_ERROR; uint32_t 11596 drivers/scsi/lpfc/lpfc_init.c uint32_t mbox_tmo; uint32_t 11668 drivers/scsi/lpfc/lpfc_init.c uint32_t mbox_tmo; uint32_t 11876 drivers/scsi/lpfc/lpfc_init.c uint32_t cfg_mode, intr_mode; uint32_t 12187 drivers/scsi/lpfc/lpfc_init.c uint32_t intr_mode; uint32_t 12380 drivers/scsi/lpfc/lpfc_init.c uint32_t intr_mode; uint32_t 12493 drivers/scsi/lpfc/lpfc_init.c lpfc_log_write_firmware_error(struct lpfc_hba *phba, uint32_t offset, uint32_t 12494 drivers/scsi/lpfc/lpfc_init.c uint32_t magic_number, uint32_t ftype, uint32_t fid, uint32_t fsize, uint32_t 12532 drivers/scsi/lpfc/lpfc_init.c uint32_t offset = 0, temp_offset = 0; uint32_t 12533 drivers/scsi/lpfc/lpfc_init.c uint32_t magic_number, ftype, fid, fsize; uint32_t 12677 drivers/scsi/lpfc/lpfc_init.c uint32_t cfg_mode, intr_mode; uint32_t 12994 drivers/scsi/lpfc/lpfc_init.c uint32_t intr_mode; uint32_t 13186 drivers/scsi/lpfc/lpfc_init.c uint32_t intr_mode; uint32_t 58 drivers/scsi/lpfc/lpfc_logmsg.h { uint32_t log_verbose = (phba)->pport ? \ uint32_t 78 drivers/scsi/lpfc/lpfc_mbox.c mb->un.varDmp.word_cnt = DMP_RSP_SIZE/sizeof(uint32_t); uint32_t 151 drivers/scsi/lpfc/lpfc_mbox.c mb->un.varDmp.word_cnt = (DMP_RSP_SIZE / sizeof (uint32_t)); uint32_t 231 drivers/scsi/lpfc/lpfc_mbox.c uint32_t ring) uint32_t 411 drivers/scsi/lpfc/lpfc_mbox.c uint32_t attentionConditions[2]; uint32_t 488 drivers/scsi/lpfc/lpfc_mbox.c LPFC_MBOXQ_t * pmb, uint32_t topology, uint32_t linkspeed) uint32_t 655 drivers/scsi/lpfc/lpfc_mbox.c lpfc_unreg_did(struct lpfc_hba * phba, uint16_t vpi, uint32_t did, uint32_t 750 drivers/scsi/lpfc/lpfc_mbox.c lpfc_reg_rpi(struct lpfc_hba *phba, uint16_t vpi, uint32_t did, uint32_t 814 drivers/scsi/lpfc/lpfc_mbox.c lpfc_unreg_login(struct lpfc_hba *phba, uint16_t vpi, uint32_t rpi, uint32_t 961 drivers/scsi/lpfc/lpfc_mbox.c uint32_t offset; uint32_t 962 drivers/scsi/lpfc/lpfc_mbox.c uint32_t iocbCnt = 0; uint32_t 1139 drivers/scsi/lpfc/lpfc_mbox.c lpfc_config_hbq(struct lpfc_hba *phba, uint32_t id, uint32_t 1141 drivers/scsi/lpfc/lpfc_mbox.c uint32_t hbq_entry_index, LPFC_MBOXQ_t *pmb) uint32_t 1276 drivers/scsi/lpfc/lpfc_mbox.c uint32_t bar_low, bar_high; uint32_t 1280 drivers/scsi/lpfc/lpfc_mbox.c uint32_t pgp_offset; uint32_t 1433 drivers/scsi/lpfc/lpfc_mbox.c uint32_t hbainit[5]; uint32_t 1687 drivers/scsi/lpfc/lpfc_mbox.c lpfc_sli4_mbx_sge_set(struct lpfcMboxq *mbox, uint32_t sgentry, uint32_t 1688 drivers/scsi/lpfc/lpfc_mbox.c dma_addr_t phyaddr, uint32_t length) uint32_t 1708 drivers/scsi/lpfc/lpfc_mbox.c lpfc_sli4_mbx_sge_get(struct lpfcMboxq *mbox, uint32_t sgentry, uint32_t 1733 drivers/scsi/lpfc/lpfc_mbox.c uint32_t sgecount, sgentry; uint32_t 1779 drivers/scsi/lpfc/lpfc_mbox.c uint8_t subsystem, uint8_t opcode, uint32_t length, bool emb) uint32_t 1783 drivers/scsi/lpfc/lpfc_mbox.c uint32_t alloc_len; uint32_t 1784 drivers/scsi/lpfc/lpfc_mbox.c uint32_t resid_len; uint32_t 1785 drivers/scsi/lpfc/lpfc_mbox.c uint32_t pagen, pcount; uint32_t 1916 drivers/scsi/lpfc/lpfc_mbox.c sizeof(uint32_t)); uint32_t 2031 drivers/scsi/lpfc/lpfc_mbox.c uint32_t alloc_len, req_len; uint32_t 2038 drivers/scsi/lpfc/lpfc_mbox.c sizeof(union lpfc_sli4_cfg_shdr) + 2 * sizeof(uint32_t); uint32_t 2064 drivers/scsi/lpfc/lpfc_mbox.c lpfc_sli_pcimem_bcopy(bytep, bytep, sizeof(uint32_t)); uint32_t 61 drivers/scsi/lpfc/lpfc_nl.h uint32_t event_type; uint32_t 62 drivers/scsi/lpfc/lpfc_nl.h uint32_t payload_length; /* RSCN data length in bytes */ uint32_t 63 drivers/scsi/lpfc/lpfc_nl.h uint32_t rscn_payload[]; uint32_t 68 drivers/scsi/lpfc/lpfc_nl.h uint32_t event_type; uint32_t 69 drivers/scsi/lpfc/lpfc_nl.h uint32_t subcategory; uint32_t 84 drivers/scsi/lpfc/lpfc_nl.h uint32_t command; uint32_t 85 drivers/scsi/lpfc/lpfc_nl.h uint32_t reason_code; uint32_t 86 drivers/scsi/lpfc/lpfc_nl.h uint32_t explanation; uint32_t 97 drivers/scsi/lpfc/lpfc_nl.h uint32_t event_type; uint32_t 98 drivers/scsi/lpfc/lpfc_nl.h uint32_t subcategory; uint32_t 111 drivers/scsi/lpfc/lpfc_nl.h uint32_t lun; uint32_t 112 drivers/scsi/lpfc/lpfc_nl.h uint32_t opcode; uint32_t 113 drivers/scsi/lpfc/lpfc_nl.h uint32_t fcpiparam; uint32_t 119 drivers/scsi/lpfc/lpfc_nl.h uint32_t event_type; uint32_t 120 drivers/scsi/lpfc/lpfc_nl.h uint32_t subcategory; uint32_t 121 drivers/scsi/lpfc/lpfc_nl.h uint32_t lun; uint32_t 138 drivers/scsi/lpfc/lpfc_nl.h uint32_t oldval; uint32_t 139 drivers/scsi/lpfc/lpfc_nl.h uint32_t newval; uint32_t 156 drivers/scsi/lpfc/lpfc_nl.h uint32_t event_type; uint32_t 157 drivers/scsi/lpfc/lpfc_nl.h uint32_t subcategory; uint32_t 166 drivers/scsi/lpfc/lpfc_nl.h uint32_t event_type; uint32_t 167 drivers/scsi/lpfc/lpfc_nl.h uint32_t subcategory; uint32_t 177 drivers/scsi/lpfc/lpfc_nl.h uint32_t event_type; uint32_t 178 drivers/scsi/lpfc/lpfc_nl.h uint32_t event_code; uint32_t 179 drivers/scsi/lpfc/lpfc_nl.h uint32_t data; uint32_t 76 drivers/scsi/lpfc/lpfc_nportdisc.c struct serv_parm *sp, uint32_t class, int flogi) uint32_t 174 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t *lp; uint32_t 188 drivers/scsi/lpfc/lpfc_nportdisc.c lp = (uint32_t *) prsp->virt; uint32_t 189 drivers/scsi/lpfc/lpfc_nportdisc.c ptr = (void *)((uint8_t *)lp + sizeof(uint32_t)); uint32_t 290 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t *lp; uint32_t 293 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t ed_tov; uint32_t 296 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t vid, flag; uint32_t 301 drivers/scsi/lpfc/lpfc_nportdisc.c lp = (uint32_t *) pcmd->virt; uint32_t 302 drivers/scsi/lpfc/lpfc_nportdisc.c sp = (struct serv_parm *) ((uint8_t *) lp + sizeof (uint32_t)); uint32_t 539 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t cmd; uint32_t 568 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t *lp; uint32_t 569 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t cmd; uint32_t 572 drivers/scsi/lpfc/lpfc_nportdisc.c lp = (uint32_t *) pcmd->virt; uint32_t 647 drivers/scsi/lpfc/lpfc_nportdisc.c struct lpfc_iocbq *cmdiocb, uint32_t els_cmd) uint32_t 738 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 744 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t *payload; uint32_t 745 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t cmd; uint32_t 779 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t *lp; uint32_t 785 drivers/scsi/lpfc/lpfc_nportdisc.c lp = (uint32_t *) pcmd->virt; uint32_t 786 drivers/scsi/lpfc/lpfc_nportdisc.c npr = (PRLI *) ((uint8_t *) lp + sizeof (uint32_t)); uint32_t 842 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 929 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 931 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 953 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 955 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 974 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 976 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 988 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 990 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 996 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 998 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1011 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1013 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1018 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1020 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1025 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1028 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1033 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1035 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1041 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t *lp = (uint32_t *) pcmd->virt; uint32_t 1084 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1086 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1098 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1100 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1114 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1116 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1143 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1147 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1153 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t *lp; uint32_t 1154 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t vid, flag; uint32_t 1157 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t ed_tov; uint32_t 1180 drivers/scsi/lpfc/lpfc_nportdisc.c lp = (uint32_t *) prsp->virt; uint32_t 1181 drivers/scsi/lpfc/lpfc_nportdisc.c sp = (struct serv_parm *) ((uint8_t *) lp + sizeof (uint32_t)); uint32_t 1350 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1352 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1357 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1359 drivers/scsi/lpfc/lpfc_nportdisc.c struct lpfc_nodelist *ndlp, void *arg, uint32_t evt) uint32_t 1376 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1378 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1396 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1400 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1423 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1425 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1453 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1455 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1464 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1466 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1480 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1483 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1493 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1495 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1506 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1509 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1563 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1565 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1583 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1587 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1610 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1614 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1622 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1626 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1661 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1665 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1716 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1720 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1728 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1732 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1741 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1745 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1751 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t did = mb->un.varWords[1]; uint32_t 1853 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1857 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1872 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1876 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 1903 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1905 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1915 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1917 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1927 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1929 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1940 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1942 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1955 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1957 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 1965 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 1967 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2139 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2141 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2176 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2180 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 2203 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2205 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2217 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2219 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2231 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2233 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2245 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2247 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2259 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2261 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2273 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2275 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2288 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2290 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2304 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2307 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2317 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2319 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2327 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2329 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2341 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2343 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2351 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2353 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2361 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2363 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2371 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2375 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 2390 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2392 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2400 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2402 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2412 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2414 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2422 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2425 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2433 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2435 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2449 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2453 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t evt) uint32_t 2467 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2469 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2493 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2495 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2523 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2525 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2533 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2535 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2561 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2563 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2590 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2592 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2611 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2613 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2629 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2631 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2645 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2647 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2663 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2666 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2688 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2690 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2704 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t uint32_t 2706 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2781 drivers/scsi/lpfc/lpfc_nportdisc.c static uint32_t (*lpfc_disc_action[NLP_STE_MAX_STATE * NLP_EVT_MAX_EVENT]) uint32_t 2782 drivers/scsi/lpfc/lpfc_nportdisc.c (struct lpfc_vport *, struct lpfc_nodelist *, void *, uint32_t) = { uint32_t 2913 drivers/scsi/lpfc/lpfc_nportdisc.c void *arg, uint32_t evt) uint32_t 2915 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t cur_state, rc; uint32_t 2916 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t(*func) (struct lpfc_vport *, struct lpfc_nodelist *, void *, uint32_t 2917 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t); uint32_t 2918 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t got_ndlp = 0; uint32_t 2919 drivers/scsi/lpfc/lpfc_nportdisc.c uint32_t data1; uint32_t 2926 drivers/scsi/lpfc/lpfc_nportdisc.c data1 = (((uint32_t)ndlp->nlp_fc4_type << 16) | uint32_t 2927 drivers/scsi/lpfc/lpfc_nportdisc.c ((uint32_t)ndlp->nlp_type)); uint32_t 2944 drivers/scsi/lpfc/lpfc_nportdisc.c data1 = (((uint32_t)ndlp->nlp_fc4_type << 16) | uint32_t 2945 drivers/scsi/lpfc/lpfc_nportdisc.c ((uint32_t)ndlp->nlp_type)); uint32_t 365 drivers/scsi/lpfc/lpfc_nvme.c uint32_t status; uint32_t 425 drivers/scsi/lpfc/lpfc_nvme.c struct lpfc_nodelist *ndlp, uint32_t num_entry, uint32_t 426 drivers/scsi/lpfc/lpfc_nvme.c uint32_t tmo, uint8_t retry) uint32_t 774 drivers/scsi/lpfc/lpfc_nvme.c uint32_t *wptr, *dptr; uint32_t 814 drivers/scsi/lpfc/lpfc_nvme.c dptr = (uint32_t *)nCmd->cmdaddr; /* payload ptr */ uint32_t 972 drivers/scsi/lpfc/lpfc_nvme.c uint32_t code, status, idx; uint32_t 974 drivers/scsi/lpfc/lpfc_nvme.c uint32_t *ptr; uint32_t 1053 drivers/scsi/lpfc/lpfc_nvme.c ptr = (uint32_t *)&ep->cqe.result.u64; uint32_t 1056 drivers/scsi/lpfc/lpfc_nvme.c *ptr = (uint32_t)data; uint32_t 1148 drivers/scsi/lpfc/lpfc_nvme.c uint32_t cpu; uint32_t 1207 drivers/scsi/lpfc/lpfc_nvme.c uint32_t req_len; uint32_t 1221 drivers/scsi/lpfc/lpfc_nvme.c sizeof(uint32_t) * 5); uint32_t 1244 drivers/scsi/lpfc/lpfc_nvme.c sizeof(uint32_t) * 5); uint32_t 1257 drivers/scsi/lpfc/lpfc_nvme.c sizeof(uint32_t) * 8); uint32_t 1319 drivers/scsi/lpfc/lpfc_nvme.c uint32_t num_bde = 0; uint32_t 1320 drivers/scsi/lpfc/lpfc_nvme.c uint32_t dma_len = 0; uint32_t 1321 drivers/scsi/lpfc/lpfc_nvme.c uint32_t dma_offset = 0; uint32_t 1455 drivers/scsi/lpfc/lpfc_nvme.c memset(&wqe->words[13], 0, (sizeof(uint32_t) * 3)); uint32_t 41 drivers/scsi/lpfc/lpfc_nvme.h uint32_t index; /* WQ index to use */ uint32_t 42 drivers/scsi/lpfc/lpfc_nvme.h uint32_t qidx; /* queue index passed to create */ uint32_t 43 drivers/scsi/lpfc/lpfc_nvme.h uint32_t cpu_id; /* current cpu id at time of create */ uint32_t 67 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t, uint16_t); uint32_t 70 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t, uint16_t); uint32_t 73 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t, uint16_t); uint32_t 307 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t status, result; uint32_t 377 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t size, oxid, sid; uint32_t 716 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t status, result, op, start_clean, logerr; uint32_t 718 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t id; uint32_t 1207 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t rc; uint32_t 1681 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t sid; uint32_t 1913 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t qidx; uint32_t 1958 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t *payload; uint32_t 1959 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t size, oxid, sid, rc; uint32_t 1975 drivers/scsi/lpfc/lpfc_nvmet.c payload = (uint32_t *)(nvmebuf->dbuf.virt); uint32_t 2048 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t *payload, qno; uint32_t 2049 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t rc; uint32_t 2072 drivers/scsi/lpfc/lpfc_nvmet.c payload = (uint32_t *)(nvmebuf->dbuf.virt); uint32_t 2230 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t idx, uint32_t 2240 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t size, oxid, sid, qno; uint32_t 2427 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t idx, uint32_t 2598 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t *txrdy; uint32_t 2669 drivers/scsi/lpfc/lpfc_nvmet.c sizeof(uint32_t) * 5); uint32_t 2758 drivers/scsi/lpfc/lpfc_nvmet.c sizeof(uint32_t) * 9); uint32_t 2837 drivers/scsi/lpfc/lpfc_nvmet.c sizeof(uint32_t) * 8); uint32_t 2953 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t result; uint32_t 3023 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t result; uint32_t 3103 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t result; uint32_t 3143 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t sid, uint16_t xri) uint32_t 3238 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t sid, uint16_t xri) uint32_t 3392 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t sid, uint16_t xri) uint32_t 3457 drivers/scsi/lpfc/lpfc_nvmet.c uint32_t sid, uint16_t xri) uint32_t 117 drivers/scsi/lpfc/lpfc_nvmet.h uint32_t *txrdy; uint32_t 118 drivers/scsi/lpfc/lpfc_nvmet.h uint32_t sid; uint32_t 119 drivers/scsi/lpfc/lpfc_nvmet.h uint32_t offset; uint32_t 206 drivers/scsi/lpfc/lpfc_scsi.c uint32_t evt_posted; uint32_t 639 drivers/scsi/lpfc/lpfc_scsi.c uint32_t cpu, idx; uint32_t 845 drivers/scsi/lpfc/lpfc_scsi.c uint32_t num_bde = 0; uint32_t 985 drivers/scsi/lpfc/lpfc_scsi.c uint32_t *reftag, uint16_t *apptag, uint32_t new_guard) uint32_t 992 drivers/scsi/lpfc/lpfc_scsi.c uint32_t op = scsi_get_prot_op(sc); uint32_t 993 drivers/scsi/lpfc/lpfc_scsi.c uint32_t blksize; uint32_t 994 drivers/scsi/lpfc/lpfc_scsi.c uint32_t numblks; uint32_t 1571 drivers/scsi/lpfc/lpfc_scsi.c uint32_t rc; uint32_t 1573 drivers/scsi/lpfc/lpfc_scsi.c uint32_t checking = 1; uint32_t 1574 drivers/scsi/lpfc/lpfc_scsi.c uint32_t reftag; uint32_t 1582 drivers/scsi/lpfc/lpfc_scsi.c reftag = (uint32_t)scsi_get_lba(sc); /* Truncate LBA */ uint32_t 1720 drivers/scsi/lpfc/lpfc_scsi.c uint32_t rc; uint32_t 1722 drivers/scsi/lpfc/lpfc_scsi.c uint32_t checking = 1; uint32_t 1723 drivers/scsi/lpfc/lpfc_scsi.c uint32_t reftag; uint32_t 1743 drivers/scsi/lpfc/lpfc_scsi.c reftag = (uint32_t)scsi_get_lba(sc); /* Truncate LBA */ uint32_t 1954 drivers/scsi/lpfc/lpfc_scsi.c uint32_t reftag; uint32_t 1957 drivers/scsi/lpfc/lpfc_scsi.c uint32_t rc; uint32_t 1959 drivers/scsi/lpfc/lpfc_scsi.c uint32_t checking = 1; uint32_t 1960 drivers/scsi/lpfc/lpfc_scsi.c uint32_t dma_len; uint32_t 1961 drivers/scsi/lpfc/lpfc_scsi.c uint32_t dma_offset = 0; uint32_t 1971 drivers/scsi/lpfc/lpfc_scsi.c reftag = (uint32_t)scsi_get_lba(sc); /* Truncate LBA */ uint32_t 2142 drivers/scsi/lpfc/lpfc_scsi.c uint32_t reftag; uint32_t 2144 drivers/scsi/lpfc/lpfc_scsi.c uint32_t dma_len; uint32_t 2146 drivers/scsi/lpfc/lpfc_scsi.c uint32_t rc; uint32_t 2148 drivers/scsi/lpfc/lpfc_scsi.c uint32_t checking = 1; uint32_t 2149 drivers/scsi/lpfc/lpfc_scsi.c uint32_t dma_offset = 0; uint32_t 2169 drivers/scsi/lpfc/lpfc_scsi.c reftag = (uint32_t)scsi_get_lba(sc); /* Truncate LBA */ uint32_t 2525 drivers/scsi/lpfc/lpfc_scsi.c uint32_t num_bde = 0; uint32_t 2720 drivers/scsi/lpfc/lpfc_scsi.c uint32_t start_ref_tag, ref_tag; uint32_t 2761 drivers/scsi/lpfc/lpfc_scsi.c start_ref_tag = (uint32_t)scsi_get_lba(cmd); /* Truncate LBA */ uint32_t 2902 drivers/scsi/lpfc/lpfc_scsi.c uint32_t bghm = bgf->bghm; uint32_t 2903 drivers/scsi/lpfc/lpfc_scsi.c uint32_t bgstat = bgf->bgstat; uint32_t 3053 drivers/scsi/lpfc/lpfc_scsi.c uint32_t num_bde = 0; uint32_t 3054 drivers/scsi/lpfc/lpfc_scsi.c uint32_t dma_len; uint32_t 3055 drivers/scsi/lpfc/lpfc_scsi.c uint32_t dma_offset = 0; uint32_t 3210 drivers/scsi/lpfc/lpfc_scsi.c memset(bde, 0, (sizeof(uint32_t) * 3)); uint32_t 3263 drivers/scsi/lpfc/lpfc_scsi.c uint32_t num_sge = 0; uint32_t 3489 drivers/scsi/lpfc/lpfc_scsi.c uint32_t resp_info = fcprsp->rspStatus2; uint32_t 3490 drivers/scsi/lpfc/lpfc_scsi.c uint32_t scsi_status = fcprsp->rspStatus3; uint32_t 3491 drivers/scsi/lpfc/lpfc_scsi.c uint32_t fcpi_parm = rsp_iocb->iocb.un.fcpi.fcpi_parm; uint32_t 3612 drivers/scsi/lpfc/lpfc_scsi.c uint32_t fcpi_parm = rsp_iocb->iocb.un.fcpi.fcpi_parm; uint32_t 3613 drivers/scsi/lpfc/lpfc_scsi.c uint32_t resp_info = fcprsp->rspStatus2; uint32_t 3614 drivers/scsi/lpfc/lpfc_scsi.c uint32_t scsi_status = fcprsp->rspStatus3; uint32_t 3615 drivers/scsi/lpfc/lpfc_scsi.c uint32_t *lp; uint32_t 3616 drivers/scsi/lpfc/lpfc_scsi.c uint32_t host_status = DID_OK; uint32_t 3617 drivers/scsi/lpfc/lpfc_scsi.c uint32_t rsplen = 0; uint32_t 3618 drivers/scsi/lpfc/lpfc_scsi.c uint32_t fcpDl; uint32_t 3619 drivers/scsi/lpfc/lpfc_scsi.c uint32_t logit = LOG_FCP | LOG_FCP_ERROR; uint32_t 3658 drivers/scsi/lpfc/lpfc_scsi.c uint32_t snslen = be32_to_cpu(fcprsp->rspSnsLen); uint32_t 3666 drivers/scsi/lpfc/lpfc_scsi.c lp = (uint32_t *)cmnd->sense_buffer; uint32_t 3807 drivers/scsi/lpfc/lpfc_scsi.c uint32_t logit = LOG_FCP; uint32_t 4000 drivers/scsi/lpfc/lpfc_scsi.c uint32_t *lp = (uint32_t *)cmd->sense_buffer; uint32_t 4063 drivers/scsi/lpfc/lpfc_scsi.c i += sizeof(uint32_t), j++) { uint32_t 4064 drivers/scsi/lpfc/lpfc_scsi.c ((uint32_t *)data)[j] = cpu_to_be32(((uint32_t *)fcp_cmnd)[j]); uint32_t 4091 drivers/scsi/lpfc/lpfc_scsi.c uint32_t fcpdl; uint32_t 4654 drivers/scsi/lpfc/lpfc_scsi.c (uint32_t) uint32_t 4948 drivers/scsi/lpfc/lpfc_scsi.c uint32_t rsp_info; uint32_t 4949 drivers/scsi/lpfc/lpfc_scsi.c uint32_t rsp_len; uint32_t 5502 drivers/scsi/lpfc/lpfc_scsi.c uint32_t total = 0; uint32_t 5503 drivers/scsi/lpfc/lpfc_scsi.c uint32_t num_to_alloc = 0; uint32_t 5505 drivers/scsi/lpfc/lpfc_scsi.c uint32_t sdev_cnt; uint32_t 5675 drivers/scsi/lpfc/lpfc_scsi.c uint32_t pri, bool atomic_create) uint32_t 5804 drivers/scsi/lpfc/lpfc_scsi.c uint32_t *found_lun_status, uint32_t 5805 drivers/scsi/lpfc/lpfc_scsi.c uint32_t *found_lun_pri) uint32_t 62 drivers/scsi/lpfc/lpfc_scsi.h uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ uint32_t 63 drivers/scsi/lpfc/lpfc_scsi.h uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ uint32_t 74 drivers/scsi/lpfc/lpfc_scsi.h uint32_t rspResId; /* Residual xfer if residual count field set in uint32_t 77 drivers/scsi/lpfc/lpfc_scsi.h uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ uint32_t 79 drivers/scsi/lpfc/lpfc_scsi.h uint32_t rspRspLen; /* Length of FCP response data in fcpRspInfo */ uint32_t 95 drivers/scsi/lpfc/lpfc_scsi.h uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ uint32_t 125 drivers/scsi/lpfc/lpfc_scsi.h uint32_t fcpDl; /* Total transfer length */ uint32_t 130 drivers/scsi/lpfc/lpfc_scsi.h uint32_t cmd_count; uint32_t 72 drivers/scsi/lpfc/lpfc_sli.c uint32_t); uint32_t 74 drivers/scsi/lpfc/lpfc_sli.c uint8_t *, uint32_t *); uint32_t 112 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli4_pcimem_bcopy(void *srcp, void *destp, uint32_t cnt) uint32_t 142 drivers/scsi/lpfc/lpfc_sli.c uint32_t host_index; uint32_t 143 drivers/scsi/lpfc/lpfc_sli.c uint32_t idx; uint32_t 144 drivers/scsi/lpfc/lpfc_sli.c uint32_t i = 0; uint32_t 176 drivers/scsi/lpfc/lpfc_sli.c for (i = 0; i < q->entry_size; i += sizeof(uint32_t)) uint32_t 177 drivers/scsi/lpfc/lpfc_sli.c __raw_writel(*((uint32_t *)(tmp + i)), uint32_t 232 drivers/scsi/lpfc/lpfc_sli.c static uint32_t uint32_t 233 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli4_wq_release(struct lpfc_queue *q, uint32_t index) uint32_t 235 drivers/scsi/lpfc/lpfc_sli.c uint32_t released = 0; uint32_t 262 drivers/scsi/lpfc/lpfc_sli.c static uint32_t uint32_t 301 drivers/scsi/lpfc/lpfc_sli.c static uint32_t uint32_t 397 drivers/scsi/lpfc/lpfc_sli.c uint32_t count, bool arm) uint32_t 435 drivers/scsi/lpfc/lpfc_sli.c uint32_t count, bool arm) uint32_t 473 drivers/scsi/lpfc/lpfc_sli.c uint32_t count = 0; uint32_t 591 drivers/scsi/lpfc/lpfc_sli.c uint32_t count, bool arm) uint32_t 624 drivers/scsi/lpfc/lpfc_sli.c uint32_t count, bool arm) uint32_t 717 drivers/scsi/lpfc/lpfc_sli.c static uint32_t uint32_t 931 drivers/scsi/lpfc/lpfc_sli.c lpfc_get_active_rrq(struct lpfc_vport *vport, uint16_t xri, uint32_t did) uint32_t 1389 drivers/scsi/lpfc/lpfc_sli.c uint32_t ulpstatus, uint32_t ulpWord4) uint32_t 1647 drivers/scsi/lpfc/lpfc_sli.c uint32_t max_cmd_idx = pring->sli.sli3.numCiocb; uint32_t 1791 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) &nextiocb->iocb) + 4), uint32_t 1792 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) &nextiocb->iocb) + 6), uint32_t 1793 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) &nextiocb->iocb) + 7)); uint32_t 1930 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_next_hbq_slot(struct lpfc_hba *phba, uint32_t hbqno) uint32_t 1941 drivers/scsi/lpfc/lpfc_sli.c uint32_t raw_index = phba->hbq_get[hbqno]; uint32_t 1942 drivers/scsi/lpfc/lpfc_sli.c uint32_t getidx = le32_to_cpu(raw_index); uint32_t 2014 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_hbq_to_firmware(struct lpfc_hba *phba, uint32_t hbqno, uint32_t 2033 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_hbq_to_firmware_s3(struct lpfc_hba *phba, uint32_t hbqno, uint32_t 2073 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_hbq_to_firmware_s4(struct lpfc_hba *phba, uint32_t hbqno, uint32_t 2128 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_hbqbuf_fill_hbqs(struct lpfc_hba *phba, uint32_t hbqno, uint32_t count) uint32_t 2130 drivers/scsi/lpfc/lpfc_sli.c uint32_t i, posted = 0; uint32_t 2187 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_hbqbuf_add_hbqs(struct lpfc_hba *phba, uint32_t qno) uint32_t 2206 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_hbqbuf_init_hbqs(struct lpfc_hba *phba, uint32_t qno) uint32_t 2268 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_hbqbuf_find(struct lpfc_hba *phba, uint32_t tag) uint32_t 2272 drivers/scsi/lpfc/lpfc_sli.c uint32_t hbqno; uint32_t 2305 drivers/scsi/lpfc/lpfc_sli.c uint32_t hbqno; uint32_t 2657 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)pmbox->mbxCommand, uint32_t 2665 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)pmbox->mbxCommand, uint32_t 2728 drivers/scsi/lpfc/lpfc_sli.c *((uint32_t *) pmbox), uint32_t 2762 drivers/scsi/lpfc/lpfc_sli.c uint32_t tag) uint32_t 2788 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_iocbq *saveq, uint32_t fch_r_ctl, uint32_t 2789 drivers/scsi/lpfc/lpfc_sli.c uint32_t fch_type) uint32_t 2842 drivers/scsi/lpfc/lpfc_sli.c uint32_t Rctl, Type; uint32_t 3042 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) &prspiocb->iocb) + 7)); uint32_t 3294 drivers/scsi/lpfc/lpfc_sli.c uint32_t eratt = 0; uint32_t 3348 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_sli_ring *pring, uint32_t mask) uint32_t 3355 drivers/scsi/lpfc/lpfc_sli.c uint32_t status; uint32_t 3356 drivers/scsi/lpfc/lpfc_sli.c uint32_t portRspPut, portRspMax; uint32_t 3360 drivers/scsi/lpfc/lpfc_sli.c uint32_t rsp_cmpl = 0; uint32_t 3395 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_pcimem_bcopy((uint32_t *) entry, uint32_t 3396 drivers/scsi/lpfc/lpfc_sli.c (uint32_t *) &rspiocbq.iocb, uint32_t 3429 drivers/scsi/lpfc/lpfc_sli.c *(uint32_t *)&irsp->un1, uint32_t 3430 drivers/scsi/lpfc/lpfc_sli.c *((uint32_t *)&irsp->un1 + 1)); uint32_t 3554 drivers/scsi/lpfc/lpfc_sli.c uint32_t free_saveq; uint32_t 3609 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 6), uint32_t 3610 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 7), uint32_t 3611 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 8), uint32_t 3612 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 9), uint32_t 3613 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 10), uint32_t 3614 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 11), uint32_t 3615 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 12), uint32_t 3616 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 13), uint32_t 3617 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 14), uint32_t 3618 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 15)); uint32_t 3715 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_sli_ring *pring, uint32_t mask) uint32_t 3733 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_sli_ring *pring, uint32_t mask) uint32_t 3739 drivers/scsi/lpfc/lpfc_sli.c uint32_t portRspPut, portRspMax; uint32_t 3741 drivers/scsi/lpfc/lpfc_sli.c uint32_t status; uint32_t 3807 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 4), uint32_t 3808 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 6), uint32_t 3809 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *) irsp) + 7)); uint32_t 3869 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_sli_ring *pring, uint32_t mask) uint32_t 3981 drivers/scsi/lpfc/lpfc_sli.c uint32_t i; uint32_t 4012 drivers/scsi/lpfc/lpfc_sli.c uint32_t i; uint32_t 4089 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_brdready_s3(struct lpfc_hba *phba, uint32_t mask) uint32_t 4091 drivers/scsi/lpfc/lpfc_sli.c uint32_t status; uint32_t 4155 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_brdready_s4(struct lpfc_hba *phba, uint32_t mask) uint32_t 4157 drivers/scsi/lpfc/lpfc_sli.c uint32_t status; uint32_t 4188 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_brdready(struct lpfc_hba *phba, uint32_t mask) uint32_t 4204 drivers/scsi/lpfc/lpfc_sli.c uint32_t __iomem *resp_buf; uint32_t 4205 drivers/scsi/lpfc/lpfc_sli.c uint32_t __iomem *mbox_buf; uint32_t 4206 drivers/scsi/lpfc/lpfc_sli.c volatile uint32_t mbox; uint32_t 4207 drivers/scsi/lpfc/lpfc_sli.c uint32_t hc_copy, ha_copy, resp_data; uint32_t 4316 drivers/scsi/lpfc/lpfc_sli.c uint32_t status; uint32_t 4317 drivers/scsi/lpfc/lpfc_sli.c uint32_t ha_copy; uint32_t 4548 drivers/scsi/lpfc/lpfc_sli.c volatile uint32_t word0; uint32_t 4550 drivers/scsi/lpfc/lpfc_sli.c uint32_t hba_aer_enabled; uint32_t 4573 drivers/scsi/lpfc/lpfc_sli.c writel(*(uint32_t *) mb, to_slim); uint32_t 4581 drivers/scsi/lpfc/lpfc_sli.c to_slim = phba->MBslimaddr + sizeof (uint32_t); uint32_t 4582 drivers/scsi/lpfc/lpfc_sli.c writel(*(uint32_t *) mb, to_slim); uint32_t 4620 drivers/scsi/lpfc/lpfc_sli.c uint32_t hba_aer_enabled; uint32_t 4683 drivers/scsi/lpfc/lpfc_sli.c uint32_t status, i = 0; uint32_t 4828 drivers/scsi/lpfc/lpfc_sli.c uint32_t hbqno; uint32_t 4829 drivers/scsi/lpfc/lpfc_sli.c uint32_t hbq_entry_index; uint32_t 4920 drivers/scsi/lpfc/lpfc_sli.c uint32_t resetcount = 0, rc = 0, done = 0; uint32_t 5063 drivers/scsi/lpfc/lpfc_sli.c uint32_t rc; uint32_t 5206 drivers/scsi/lpfc/lpfc_sli.c uint32_t data_length; uint32_t 5290 drivers/scsi/lpfc/lpfc_sli.c uint8_t *vpd, uint32_t *vpd_size) uint32_t 5293 drivers/scsi/lpfc/lpfc_sli.c uint32_t dma_size; uint32_t 5368 drivers/scsi/lpfc/lpfc_sli.c uint32_t alloclen, reqlen; uint32_t 5369 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 5451 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 5606 drivers/scsi/lpfc/lpfc_sli.c uint32_t length; uint32_t 5607 drivers/scsi/lpfc/lpfc_sli.c uint32_t mbox_tmo; uint32_t 5752 drivers/scsi/lpfc/lpfc_sli.c uint32_t req_len; uint32_t 5753 drivers/scsi/lpfc/lpfc_sli.c uint32_t emb_len; uint32_t 5754 drivers/scsi/lpfc/lpfc_sli.c uint32_t alloc_len, mbox_tmo; uint32_t 5764 drivers/scsi/lpfc/lpfc_sli.c sizeof(uint32_t); uint32_t 5774 drivers/scsi/lpfc/lpfc_sli.c sizeof(uint32_t); uint32_t 5824 drivers/scsi/lpfc/lpfc_sli.c uint32_t length; uint32_t 6048 drivers/scsi/lpfc/lpfc_sli.c uint32_t length, mbox_tmo = 0; uint32_t 6155 drivers/scsi/lpfc/lpfc_sli.c uint32_t feature) uint32_t 6157 drivers/scsi/lpfc/lpfc_sli.c uint32_t len; uint32_t 6231 drivers/scsi/lpfc/lpfc_sli.c sizeof(uint32_t) * 2, uint32_t 6253 drivers/scsi/lpfc/lpfc_sli.c uint32_t fwlog_buff_count) uint32_t 6264 drivers/scsi/lpfc/lpfc_sli.c sizeof(uint32_t) * 2, uint32_t 6318 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 6361 drivers/scsi/lpfc/lpfc_sli.c uint32_t fwlog_level, uint32_t 6362 drivers/scsi/lpfc/lpfc_sli.c uint32_t fwlog_enable) uint32_t 6368 drivers/scsi/lpfc/lpfc_sli.c uint32_t len = 0, fwlog_buffsize, fwlog_entry_count; uint32_t 6763 drivers/scsi/lpfc/lpfc_sli.c uint32_t req_len, emb_len; uint32_t 6764 drivers/scsi/lpfc/lpfc_sli.c uint32_t alloc_len, mbox_tmo; uint32_t 6810 drivers/scsi/lpfc/lpfc_sli.c sizeof(uint32_t); uint32_t 6821 drivers/scsi/lpfc/lpfc_sli.c sizeof(uint32_t); uint32_t 7076 drivers/scsi/lpfc/lpfc_sli.c uint32_t len; uint32_t 7165 drivers/scsi/lpfc/lpfc_sli.c uint32_t vpd_size; uint32_t 7166 drivers/scsi/lpfc/lpfc_sli.c uint32_t ftr_rsp = 0; uint32_t 7793 drivers/scsi/lpfc/lpfc_sli.c uint32_t tmo_posted; uint32_t 7818 drivers/scsi/lpfc/lpfc_sli.c uint32_t idx; uint32_t 7867 drivers/scsi/lpfc/lpfc_sli.c uint32_t eqidx; uint32_t 8009 drivers/scsi/lpfc/lpfc_sli.c uint32_t flag) uint32_t 8013 drivers/scsi/lpfc/lpfc_sli.c uint32_t status, evtctr; uint32_t 8014 drivers/scsi/lpfc/lpfc_sli.c uint32_t ha_copy, hc_copy; uint32_t 8018 drivers/scsi/lpfc/lpfc_sli.c uint32_t word0, ldata; uint32_t 8145 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)mbx->mbxCommand, uint32_t 8152 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)mbx->mbxCommand, uint32_t 8196 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)mbx->mbxCommand, uint32_t 8203 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)mbx->mbxCommand, uint32_t 8217 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *)mbx) + pmbox->mbox_offset_word) uint32_t 8233 drivers/scsi/lpfc/lpfc_sli.c *(((uint32_t *)mbx) + pmbox->mbox_offset_word) uint32_t 8249 drivers/scsi/lpfc/lpfc_sli.c to_slim = phba->MBslimaddr + sizeof (uint32_t); uint32_t 8251 drivers/scsi/lpfc/lpfc_sli.c MAILBOX_CMD_SIZE - sizeof (uint32_t)); uint32_t 8254 drivers/scsi/lpfc/lpfc_sli.c ldata = *((uint32_t *)mbx); uint32_t 8285 drivers/scsi/lpfc/lpfc_sli.c word0 = *((uint32_t *)phba->mbox); uint32_t 8331 drivers/scsi/lpfc/lpfc_sli.c word0 = *((uint32_t *)phba->mbox); uint32_t 8335 drivers/scsi/lpfc/lpfc_sli.c uint32_t slimword0; uint32_t 8504 drivers/scsi/lpfc/lpfc_sli.c uint32_t db_ready; uint32_t 8545 drivers/scsi/lpfc/lpfc_sli.c uint32_t mcqe_status; uint32_t 8546 drivers/scsi/lpfc/lpfc_sli.c uint32_t mbx_cmnd; uint32_t 8669 drivers/scsi/lpfc/lpfc_sli.c uint32_t flag) uint32_t 8807 drivers/scsi/lpfc/lpfc_sli.c uint32_t mbx_cmnd; uint32_t 8926 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_issue_mbox(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmbox, uint32_t flag) uint32_t 9047 drivers/scsi/lpfc/lpfc_sli.c __lpfc_sli_issue_iocb_s3(struct lpfc_hba *phba, uint32_t ring_number, uint32_t 9048 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_iocbq *piocb, uint32_t flag) uint32_t 9187 drivers/scsi/lpfc/lpfc_sli.c uint32_t offset = 0; /* accumulated offset in the sg request list */ uint32_t 9284 drivers/scsi/lpfc/lpfc_sli.c uint32_t xmit_len = 0, total_len = 0; uint32_t 9286 drivers/scsi/lpfc/lpfc_sli.c uint32_t fip; uint32_t 9287 drivers/scsi/lpfc/lpfc_sli.c uint32_t abort_tag; uint32_t 9294 drivers/scsi/lpfc/lpfc_sli.c uint32_t els_id = LPFC_ELS_ID_DEFAULT; uint32_t 9298 drivers/scsi/lpfc/lpfc_sli.c uint32_t *pcmd; uint32_t 9299 drivers/scsi/lpfc/lpfc_sli.c uint32_t if_type; uint32_t 9318 drivers/scsi/lpfc/lpfc_sli.c abort_tag = (uint32_t) iocbq->iotag; uint32_t 9379 drivers/scsi/lpfc/lpfc_sli.c pcmd = (uint32_t *) (((struct lpfc_dmabuf *) uint32_t 9498 drivers/scsi/lpfc/lpfc_sli.c uint32_t *ptr; uint32_t 9562 drivers/scsi/lpfc/lpfc_sli.c uint32_t *ptr; uint32_t 9619 drivers/scsi/lpfc/lpfc_sli.c uint32_t *ptr; uint32_t 9718 drivers/scsi/lpfc/lpfc_sli.c pcmd = (uint32_t *) (((struct lpfc_dmabuf *) uint32_t 9881 drivers/scsi/lpfc/lpfc_sli.c __lpfc_sli_issue_iocb_s4(struct lpfc_hba *phba, uint32_t ring_number, uint32_t 9882 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_iocbq *piocb, uint32_t flag) uint32_t 9974 drivers/scsi/lpfc/lpfc_sli.c __lpfc_sli_issue_iocb(struct lpfc_hba *phba, uint32_t ring_number, uint32_t 9975 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_iocbq *piocb, uint32_t flag) uint32_t 10062 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_issue_iocb(struct lpfc_hba *phba, uint32_t ring_number, uint32_t 10063 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_iocbq *piocb, uint32_t flag) uint32_t 10201 drivers/scsi/lpfc/lpfc_sli.c uint32_t ext_status = 0; uint32_t 10251 drivers/scsi/lpfc/lpfc_sli.c uint32_t *iocb_w; uint32_t 10259 drivers/scsi/lpfc/lpfc_sli.c temp_event_data.data = (uint32_t) icmd->ulpContext; uint32_t 10266 drivers/scsi/lpfc/lpfc_sli.c (uint32_t) icmd->ulpContext); uint32_t 10272 drivers/scsi/lpfc/lpfc_sli.c (uint32_t) icmd->ulpContext); uint32_t 10285 drivers/scsi/lpfc/lpfc_sli.c iocb_w = (uint32_t *) icmd; uint32_t 10834 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_pcimem_bcopy(void *srcp, void *destp, uint32_t cnt) uint32_t 10836 drivers/scsi/lpfc/lpfc_sli.c uint32_t *src = srcp; uint32_t 10837 drivers/scsi/lpfc/lpfc_sli.c uint32_t *dest = destp; uint32_t 10838 drivers/scsi/lpfc/lpfc_sli.c uint32_t ldata; uint32_t 10841 drivers/scsi/lpfc/lpfc_sli.c for (i = 0; i < (int)cnt; i += sizeof (uint32_t)) { uint32_t 10862 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_bemem_bcopy(void *srcp, void *destp, uint32_t cnt) uint32_t 10864 drivers/scsi/lpfc/lpfc_sli.c uint32_t *src = srcp; uint32_t 10865 drivers/scsi/lpfc/lpfc_sli.c uint32_t *dest = destp; uint32_t 10866 drivers/scsi/lpfc/lpfc_sli.c uint32_t ldata; uint32_t 10869 drivers/scsi/lpfc/lpfc_sli.c for (i = 0; i < (int)cnt; i += sizeof(uint32_t)) { uint32_t 10912 drivers/scsi/lpfc/lpfc_sli.c uint32_t uint32_t 10943 drivers/scsi/lpfc/lpfc_sli.c uint32_t tag) uint32_t 11778 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_iocbq *piocbq, uint32_t flag) uint32_t 11828 drivers/scsi/lpfc/lpfc_sli.c uint32_t ring_number, uint32_t 11831 drivers/scsi/lpfc/lpfc_sli.c uint32_t timeout) uint32_t 11836 drivers/scsi/lpfc/lpfc_sli.c uint32_t creg_val; uint32_t 11974 drivers/scsi/lpfc/lpfc_sli.c uint32_t timeout) uint32_t 12091 drivers/scsi/lpfc/lpfc_sli.c uint32_t ha_copy; uint32_t 12144 drivers/scsi/lpfc/lpfc_sli.c uint32_t uerr_sta_hi, uerr_sta_lo; uint32_t 12145 drivers/scsi/lpfc/lpfc_sli.c uint32_t if_type, portsmphr; uint32_t 12235 drivers/scsi/lpfc/lpfc_sli.c uint32_t ha_copy; uint32_t 12340 drivers/scsi/lpfc/lpfc_sli.c uint32_t ha_copy, hc_copy; uint32_t 12341 drivers/scsi/lpfc/lpfc_sli.c uint32_t work_ha_copy; uint32_t 12344 drivers/scsi/lpfc/lpfc_sli.c uint32_t control; uint32_t 12451 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)phba->sli.slistat.sli_intr); uint32_t 12458 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)((unsigned long) uint32_t 12471 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)((unsigned long) uint32_t 12503 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_pcimem_bcopy(mbox, pmbox, sizeof(uint32_t)); uint32_t 12542 drivers/scsi/lpfc/lpfc_sli.c (uint32_t)pmbox->mbxStatus, uint32_t 12640 drivers/scsi/lpfc/lpfc_sli.c uint32_t ha_copy; uint32_t 12731 drivers/scsi/lpfc/lpfc_sli.c uint32_t hc_copy; uint32_t 12873 drivers/scsi/lpfc/lpfc_sli.c uint32_t status, max_response; uint32_t 13084 drivers/scsi/lpfc/lpfc_sli.c uint32_t mcqe_status; uint32_t 13384 drivers/scsi/lpfc/lpfc_sli.c uint32_t status, rq_id; uint32_t 13880 drivers/scsi/lpfc/lpfc_sli.c uint32_t status, rq_id; uint32_t 13882 drivers/scsi/lpfc/lpfc_sli.c uint32_t fctl, idx; uint32_t 14047 drivers/scsi/lpfc/lpfc_sli.c uint32_t qidx = eq->hdwq; uint32_t 14221 drivers/scsi/lpfc/lpfc_sli.c uint32_t icnt; uint32_t 14513 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli4_queue_alloc(struct lpfc_hba *phba, uint32_t page_size, uint32_t 14514 drivers/scsi/lpfc/lpfc_sli.c uint32_t entry_size, uint32_t entry_count, int cpu) uint32_t 14518 drivers/scsi/lpfc/lpfc_sli.c uint32_t hw_page_size = phba->sli4_hba.pc_sli4_params.if_page_sz; uint32_t 14636 drivers/scsi/lpfc/lpfc_sli.c lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq, uint32_t 14637 drivers/scsi/lpfc/lpfc_sli.c uint32_t numq, uint32_t usdelay) uint32_t 14643 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 14644 drivers/scsi/lpfc/lpfc_sli.c uint32_t dmult; uint32_t 14749 drivers/scsi/lpfc/lpfc_sli.c lpfc_eq_create(struct lpfc_hba *phba, struct lpfc_queue *eq, uint32_t imax) uint32_t 14755 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 14758 drivers/scsi/lpfc/lpfc_sli.c uint32_t hw_page_size = phba->sli4_hba.pc_sli4_params.if_page_sz; uint32_t 14882 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_queue *eq, uint32_t type, uint32_t subtype) uint32_t 14888 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 15027 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_sli4_hdw_queue *hdwq, uint32_t type, uint32_t 15028 drivers/scsi/lpfc/lpfc_sli.c uint32_t subtype) uint32_t 15037 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 15039 drivers/scsi/lpfc/lpfc_sli.c uint32_t hw_page_size = phba->sli4_hba.pc_sli4_params.if_page_sz; uint32_t 15336 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_queue *cq, uint32_t subtype) uint32_t 15343 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 15345 drivers/scsi/lpfc/lpfc_sli.c uint32_t hw_page_size = phba->sli4_hba.pc_sli4_params.if_page_sz; uint32_t 15491 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_queue *cq, uint32_t subtype) uint32_t 15497 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 15499 drivers/scsi/lpfc/lpfc_sli.c uint32_t hw_page_size = phba->sli4_hba.pc_sli4_params.if_page_sz; uint32_t 15502 drivers/scsi/lpfc/lpfc_sli.c uint32_t db_offset; uint32_t 15505 drivers/scsi/lpfc/lpfc_sli.c uint32_t dpp_offset; uint32_t 15758 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_queue *drq, struct lpfc_queue *cq, uint32_t subtype) uint32_t 15764 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 15766 drivers/scsi/lpfc/lpfc_sli.c uint32_t hw_page_size = phba->sli4_hba.pc_sli4_params.if_page_sz; uint32_t 15768 drivers/scsi/lpfc/lpfc_sli.c uint32_t db_offset; uint32_t 16048 drivers/scsi/lpfc/lpfc_sli.c uint32_t subtype) uint32_t 16056 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 16058 drivers/scsi/lpfc/lpfc_sli.c uint32_t hw_page_size = phba->sli4_hba.pc_sli4_params.if_page_sz; uint32_t 16232 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 16289 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 16343 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 16397 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 16453 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 16537 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 16538 drivers/scsi/lpfc/lpfc_sli.c uint32_t mbox_tmo; uint32_t 16704 drivers/scsi/lpfc/lpfc_sli.c uint32_t reqlen, alloclen, pg_pairs; uint32_t 16705 drivers/scsi/lpfc/lpfc_sli.c uint32_t mbox_tmo; uint32_t 16708 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 16712 drivers/scsi/lpfc/lpfc_sli.c sizeof(union lpfc_sli4_cfg_shdr) + sizeof(uint32_t); uint32_t 16807 drivers/scsi/lpfc/lpfc_sli.c uint32_t reqlen, alloclen, pg_pairs; uint32_t 16808 drivers/scsi/lpfc/lpfc_sli.c uint32_t mbox_tmo; uint32_t 16811 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 16817 drivers/scsi/lpfc/lpfc_sli.c sizeof(union lpfc_sli4_cfg_shdr) + sizeof(uint32_t); uint32_t 17043 drivers/scsi/lpfc/lpfc_sli.c uint32_t *header = (uint32_t *) fc_hdr; uint32_t 17122 drivers/scsi/lpfc/lpfc_sli.c static uint32_t uint32_t 17146 drivers/scsi/lpfc/lpfc_sli.c uint16_t fcfi, uint32_t did) uint32_t 17518 drivers/scsi/lpfc/lpfc_sli.c uint32_t sid, fctl; uint32_t 17667 drivers/scsi/lpfc/lpfc_sli.c uint32_t fctl; uint32_t 17712 drivers/scsi/lpfc/lpfc_sli.c uint32_t fctl; uint32_t 17761 drivers/scsi/lpfc/lpfc_sli.c uint32_t sid; uint32_t 17762 drivers/scsi/lpfc/lpfc_sli.c uint32_t len, tot_len; uint32_t 17931 drivers/scsi/lpfc/lpfc_sli.c uint32_t frame_len; uint32_t 17982 drivers/scsi/lpfc/lpfc_sli.c wqe->send_frame.fc_hdr_wd0 = be32_to_cpu(*((uint32_t *)fc_hdr)); uint32_t 17983 drivers/scsi/lpfc/lpfc_sli.c wqe->send_frame.fc_hdr_wd1 = be32_to_cpu(*((uint32_t *)fc_hdr + 1)); uint32_t 17984 drivers/scsi/lpfc/lpfc_sli.c wqe->send_frame.fc_hdr_wd2 = be32_to_cpu(*((uint32_t *)fc_hdr + 2)); uint32_t 17985 drivers/scsi/lpfc/lpfc_sli.c wqe->send_frame.fc_hdr_wd3 = be32_to_cpu(*((uint32_t *)fc_hdr + 3)); uint32_t 17986 drivers/scsi/lpfc/lpfc_sli.c wqe->send_frame.fc_hdr_wd4 = be32_to_cpu(*((uint32_t *)fc_hdr + 4)); uint32_t 17987 drivers/scsi/lpfc/lpfc_sli.c wqe->send_frame.fc_hdr_wd5 = be32_to_cpu(*((uint32_t *)fc_hdr + 5)); uint32_t 18028 drivers/scsi/lpfc/lpfc_sli.c uint32_t fcfi; uint32_t 18029 drivers/scsi/lpfc/lpfc_sli.c uint32_t did; uint32_t 18138 drivers/scsi/lpfc/lpfc_sli.c uint32_t rc = 0; uint32_t 18192 drivers/scsi/lpfc/lpfc_sli.c uint32_t rc = 0; uint32_t 18193 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 18451 drivers/scsi/lpfc/lpfc_sli.c uint32_t mbox_tmo; uint32_t 18486 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 18521 drivers/scsi/lpfc/lpfc_sli.c uint32_t alloc_len, req_len; uint32_t 18522 drivers/scsi/lpfc/lpfc_sli.c uint32_t fcfindex; uint32_t 18532 drivers/scsi/lpfc/lpfc_sli.c sizeof(uint32_t); uint32_t 18559 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_pcimem_bcopy(&fcfindex, bytep, sizeof(uint32_t)); uint32_t 18566 drivers/scsi/lpfc/lpfc_sli.c bytep += sizeof(uint32_t); uint32_t 19023 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status; uint32_t 19126 drivers/scsi/lpfc/lpfc_sli.c uint32_t link_state; uint32_t 19150 drivers/scsi/lpfc/lpfc_sli.c static uint32_t uint32_t 19155 drivers/scsi/lpfc/lpfc_sli.c uint32_t offset = 0; uint32_t 19208 drivers/scsi/lpfc/lpfc_sli.c static uint32_t uint32_t 19214 drivers/scsi/lpfc/lpfc_sli.c uint32_t data_length = 0; uint32_t 19263 drivers/scsi/lpfc/lpfc_sli.c uint32_t if_type, data_size, sub_tlv_len, tlv_offset; uint32_t 19264 drivers/scsi/lpfc/lpfc_sli.c uint32_t offset = 0; uint32_t 19370 drivers/scsi/lpfc/lpfc_sli.c uint32_t size, uint32_t *offset) uint32_t 19375 drivers/scsi/lpfc/lpfc_sli.c uint32_t shdr_status, shdr_add_status, shdr_change_status; uint32_t 19376 drivers/scsi/lpfc/lpfc_sli.c uint32_t mbox_tmo; uint32_t 19378 drivers/scsi/lpfc/lpfc_sli.c uint32_t written = 0; uint32_t 19596 drivers/scsi/lpfc/lpfc_sli.c uint32_t uint32_t 19606 drivers/scsi/lpfc/lpfc_sli.c uint32_t txq_cnt = 0; uint32_t 19716 drivers/scsi/lpfc/lpfc_sli.c uint32_t offset = 0; /* accumulated offset in the sg request list */ uint32_t 19718 drivers/scsi/lpfc/lpfc_sli.c uint32_t cmd; uint32_t 19828 drivers/scsi/lpfc/lpfc_sli.c uint32_t ret = 0; uint32_t 75 drivers/scsi/lpfc/lpfc_sli.h uint32_t iocb_flag; uint32_t 104 drivers/scsi/lpfc/lpfc_sli.h uint32_t drvrTimeout; /* driver timeout in seconds */ uint32_t 202 drivers/scsi/lpfc/lpfc_sli.h uint32_t local_getidx; /* last available cmd index (from cmdGetInx) */ uint32_t 203 drivers/scsi/lpfc/lpfc_sli.h uint32_t next_cmdidx; /* next_cmd index */ uint32_t 204 drivers/scsi/lpfc/lpfc_sli.h uint32_t rspidx; /* current index in response ring */ uint32_t 205 drivers/scsi/lpfc/lpfc_sli.h uint32_t cmdidx; /* current index in command ring */ uint32_t 210 drivers/scsi/lpfc/lpfc_sli.h uint32_t *cmdringaddr; /* virtual address for cmd rings */ uint32_t 211 drivers/scsi/lpfc/lpfc_sli.h uint32_t *rspringaddr; /* virtual address for rsp rings */ uint32_t 232 drivers/scsi/lpfc/lpfc_sli.h uint32_t fast_iotag; /* max fastlookup based iotag */ uint32_t 233 drivers/scsi/lpfc/lpfc_sli.h uint32_t iotag_ctr; /* keeps track of the next iotag to use */ uint32_t 234 drivers/scsi/lpfc/lpfc_sli.h uint32_t iotag_max; /* max iotag value to use */ uint32_t 241 drivers/scsi/lpfc/lpfc_sli.h uint32_t missbufcnt; /* keep track of buffers to post */ uint32_t 251 drivers/scsi/lpfc/lpfc_sli.h uint32_t num_mask; /* number of mask entries in prt array */ uint32_t 268 drivers/scsi/lpfc/lpfc_sli.h uint32_t rn; /* Receive buffer notification */ uint32_t 269 drivers/scsi/lpfc/lpfc_sli.h uint32_t entry_count; /* max # of entries in HBQ */ uint32_t 270 drivers/scsi/lpfc/lpfc_sli.h uint32_t headerLen; /* 0 if not profile 4 or 5 */ uint32_t 271 drivers/scsi/lpfc/lpfc_sli.h uint32_t logEntry; /* Set to 1 if this HBQ used for LogEntry */ uint32_t 272 drivers/scsi/lpfc/lpfc_sli.h uint32_t profile; /* Selection profile 0=all, 7=logentry */ uint32_t 273 drivers/scsi/lpfc/lpfc_sli.h uint32_t ring_mask; /* Binds HBQ to a ring e.g. Ring0=b0001, uint32_t 275 drivers/scsi/lpfc/lpfc_sli.h uint32_t hbq_index; /* index of this hbq in ring .HBQs[] */ uint32_t 277 drivers/scsi/lpfc/lpfc_sli.h uint32_t seqlenoff; uint32_t 278 drivers/scsi/lpfc/lpfc_sli.h uint32_t maxlen; uint32_t 279 drivers/scsi/lpfc/lpfc_sli.h uint32_t seqlenbcnt; uint32_t 280 drivers/scsi/lpfc/lpfc_sli.h uint32_t cmdcodeoff; uint32_t 281 drivers/scsi/lpfc/lpfc_sli.h uint32_t cmdmatch[8]; uint32_t 282 drivers/scsi/lpfc/lpfc_sli.h uint32_t mask_count; /* number of mask entries in prt array */ uint32_t 286 drivers/scsi/lpfc/lpfc_sli.h uint32_t buffer_count; /* number of buffers allocated */ uint32_t 287 drivers/scsi/lpfc/lpfc_sli.h uint32_t init_count; /* number to allocate when initialized */ uint32_t 288 drivers/scsi/lpfc/lpfc_sli.h uint32_t add_count; /* number to allocate when starved */ uint32_t 298 drivers/scsi/lpfc/lpfc_sli.h uint32_t err_attn_event; /* Error Attn event counters */ uint32_t 299 drivers/scsi/lpfc/lpfc_sli.h uint32_t link_event; /* Link event counters */ uint32_t 300 drivers/scsi/lpfc/lpfc_sli.h uint32_t mbox_event; /* Mailbox event counters */ uint32_t 301 drivers/scsi/lpfc/lpfc_sli.h uint32_t mbox_busy; /* Mailbox cmd busy */ uint32_t 306 drivers/scsi/lpfc/lpfc_sli.h uint32_t link_failure_count; uint32_t 307 drivers/scsi/lpfc/lpfc_sli.h uint32_t loss_of_sync_count; uint32_t 308 drivers/scsi/lpfc/lpfc_sli.h uint32_t loss_of_signal_count; uint32_t 309 drivers/scsi/lpfc/lpfc_sli.h uint32_t prim_seq_protocol_err_count; uint32_t 310 drivers/scsi/lpfc/lpfc_sli.h uint32_t invalid_tx_word_count; uint32_t 311 drivers/scsi/lpfc/lpfc_sli.h uint32_t invalid_crc_count; uint32_t 312 drivers/scsi/lpfc/lpfc_sli.h uint32_t error_frames; uint32_t 313 drivers/scsi/lpfc/lpfc_sli.h uint32_t link_events; uint32_t 318 drivers/scsi/lpfc/lpfc_sli.h uint32_t num_rings; uint32_t 319 drivers/scsi/lpfc/lpfc_sli.h uint32_t sli_flag; uint32_t 386 drivers/scsi/lpfc/lpfc_sli.h uint32_t timeout; uint32_t 395 drivers/scsi/lpfc/lpfc_sli.h uint32_t result; /* From IOCB Word 4. */ uint32_t 397 drivers/scsi/lpfc/lpfc_sli.h uint32_t seg_cnt; /* Number of scatter-gather segments returned by uint32_t 410 drivers/scsi/lpfc/lpfc_sli.h uint32_t prot_seg_cnt; /* seg_cnt's counterpart for uint32_t 430 drivers/scsi/lpfc/lpfc_sli.h uint32_t prot_data; uint32_t 431 drivers/scsi/lpfc/lpfc_sli.h uint32_t prot_data_type; uint32_t 161 drivers/scsi/lpfc/lpfc_sli4.h uint32_t entry_count; /* Number of entries to support on the queue */ uint32_t 162 drivers/scsi/lpfc/lpfc_sli4.h uint32_t entry_size; /* Size of each queue entry. */ uint32_t 163 drivers/scsi/lpfc/lpfc_sli4.h uint32_t entry_cnt_per_pg; uint32_t 164 drivers/scsi/lpfc/lpfc_sli4.h uint32_t notify_interval; /* Queue Notification Interval uint32_t 180 drivers/scsi/lpfc/lpfc_sli4.h uint32_t max_proc_limit; /* Queue Processing Limit uint32_t 195 drivers/scsi/lpfc/lpfc_sli4.h uint32_t queue_claimed; /* indicates queue is being processed */ uint32_t 196 drivers/scsi/lpfc/lpfc_sli4.h uint32_t queue_id; /* Queue ID assigned by the hardware */ uint32_t 197 drivers/scsi/lpfc/lpfc_sli4.h uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */ uint32_t 198 drivers/scsi/lpfc/lpfc_sli4.h uint32_t host_index; /* The host's index for putting or getting */ uint32_t 199 drivers/scsi/lpfc/lpfc_sli4.h uint32_t hba_index; /* The last known hba index for get or put */ uint32_t 200 drivers/scsi/lpfc/lpfc_sli4.h uint32_t q_mode; uint32_t 226 drivers/scsi/lpfc/lpfc_sli4.h uint32_t q_cnt_1; uint32_t 227 drivers/scsi/lpfc/lpfc_sli4.h uint32_t q_cnt_2; uint32_t 228 drivers/scsi/lpfc/lpfc_sli4.h uint32_t q_cnt_3; uint32_t 265 drivers/scsi/lpfc/lpfc_sli4.h uint32_t speed; uint32_t 271 drivers/scsi/lpfc/lpfc_sli4.h uint32_t logical_speed; uint32_t 280 drivers/scsi/lpfc/lpfc_sli4.h uint32_t priority; uint32_t 282 drivers/scsi/lpfc/lpfc_sli4.h uint32_t addr_mode; uint32_t 283 drivers/scsi/lpfc/lpfc_sli4.h uint32_t flag; uint32_t 293 drivers/scsi/lpfc/lpfc_sli4.h uint32_t priority; uint32_t 309 drivers/scsi/lpfc/lpfc_sli4.h uint32_t fcf_flag; uint32_t 323 drivers/scsi/lpfc/lpfc_sli4.h uint32_t addr_mode; uint32_t 324 drivers/scsi/lpfc/lpfc_sli4.h uint32_t eligible_fcf_cnt; uint32_t 329 drivers/scsi/lpfc/lpfc_sli4.h uint32_t current_fcf_scan_pri; uint32_t 407 drivers/scsi/lpfc/lpfc_sli4.h uint32_t bmbx_size; uint32_t 468 drivers/scsi/lpfc/lpfc_sli4.h uint32_t idx; uint32_t 476 drivers/scsi/lpfc/lpfc_sli4.h uint32_t word0; uint32_t 490 drivers/scsi/lpfc/lpfc_sli4.h uint32_t supported; uint32_t 491 drivers/scsi/lpfc/lpfc_sli4.h uint32_t if_type; uint32_t 492 drivers/scsi/lpfc/lpfc_sli4.h uint32_t sli_rev; uint32_t 493 drivers/scsi/lpfc/lpfc_sli4.h uint32_t sli_family; uint32_t 494 drivers/scsi/lpfc/lpfc_sli4.h uint32_t featurelevel_1; uint32_t 495 drivers/scsi/lpfc/lpfc_sli4.h uint32_t featurelevel_2; uint32_t 496 drivers/scsi/lpfc/lpfc_sli4.h uint32_t proto_types; uint32_t 502 drivers/scsi/lpfc/lpfc_sli4.h uint32_t sge_supp_len; uint32_t 503 drivers/scsi/lpfc/lpfc_sli4.h uint32_t if_page_sz; uint32_t 504 drivers/scsi/lpfc/lpfc_sli4.h uint32_t rq_db_window; uint32_t 505 drivers/scsi/lpfc/lpfc_sli4.h uint32_t loopbk_scope; uint32_t 506 drivers/scsi/lpfc/lpfc_sli4.h uint32_t oas_supported; uint32_t 507 drivers/scsi/lpfc/lpfc_sli4.h uint32_t eq_pages_max; uint32_t 508 drivers/scsi/lpfc/lpfc_sli4.h uint32_t eqe_size; uint32_t 509 drivers/scsi/lpfc/lpfc_sli4.h uint32_t cq_pages_max; uint32_t 510 drivers/scsi/lpfc/lpfc_sli4.h uint32_t cqe_size; uint32_t 511 drivers/scsi/lpfc/lpfc_sli4.h uint32_t mq_pages_max; uint32_t 512 drivers/scsi/lpfc/lpfc_sli4.h uint32_t mqe_size; uint32_t 513 drivers/scsi/lpfc/lpfc_sli4.h uint32_t mq_elem_cnt; uint32_t 514 drivers/scsi/lpfc/lpfc_sli4.h uint32_t wq_pages_max; uint32_t 515 drivers/scsi/lpfc/lpfc_sli4.h uint32_t wqe_size; uint32_t 516 drivers/scsi/lpfc/lpfc_sli4.h uint32_t rq_pages_max; uint32_t 517 drivers/scsi/lpfc/lpfc_sli4.h uint32_t rqe_size; uint32_t 518 drivers/scsi/lpfc/lpfc_sli4.h uint32_t hdr_pages_max; uint32_t 519 drivers/scsi/lpfc/lpfc_sli4.h uint32_t hdr_size; uint32_t 520 drivers/scsi/lpfc/lpfc_sli4.h uint32_t hdr_pp_align; uint32_t 521 drivers/scsi/lpfc/lpfc_sli4.h uint32_t sgl_pages_max; uint32_t 522 drivers/scsi/lpfc/lpfc_sli4.h uint32_t sgl_pp_align; uint32_t 543 drivers/scsi/lpfc/lpfc_sli4.h uint32_t pf_number; uint32_t 544 drivers/scsi/lpfc/lpfc_sli4.h uint32_t vf_number; uint32_t 638 drivers/scsi/lpfc/lpfc_sli4.h uint32_t alloc_xri_get; uint32_t 639 drivers/scsi/lpfc/lpfc_sli4.h uint32_t alloc_xri_put; uint32_t 640 drivers/scsi/lpfc/lpfc_sli4.h uint32_t free_xri; uint32_t 641 drivers/scsi/lpfc/lpfc_sli4.h uint32_t wq_access; uint32_t 642 drivers/scsi/lpfc/lpfc_sli4.h uint32_t alloc_pvt_pool; uint32_t 643 drivers/scsi/lpfc/lpfc_sli4.h uint32_t mv_from_pvt_pool; uint32_t 644 drivers/scsi/lpfc/lpfc_sli4.h uint32_t mv_to_pub_pool; uint32_t 645 drivers/scsi/lpfc/lpfc_sli4.h uint32_t mv_to_pvt_pool; uint32_t 646 drivers/scsi/lpfc/lpfc_sli4.h uint32_t free_pub_pool; uint32_t 647 drivers/scsi/lpfc/lpfc_sli4.h uint32_t free_pvt_pool; uint32_t 653 drivers/scsi/lpfc/lpfc_sli4.h uint32_t icnt; uint32_t 671 drivers/scsi/lpfc/lpfc_sli4.h uint32_t total_io_bufs; uint32_t 672 drivers/scsi/lpfc/lpfc_sli4.h uint32_t get_io_bufs; uint32_t 673 drivers/scsi/lpfc/lpfc_sli4.h uint32_t put_io_bufs; uint32_t 674 drivers/scsi/lpfc/lpfc_sli4.h uint32_t empty_io_bufs; uint32_t 675 drivers/scsi/lpfc/lpfc_sli4.h uint32_t abts_scsi_io_bufs; uint32_t 676 drivers/scsi/lpfc/lpfc_sli4.h uint32_t abts_nvme_io_bufs; uint32_t 690 drivers/scsi/lpfc/lpfc_sli4.h uint32_t cpucheck_rcv_io[LPFC_CHECK_CPU_CNT]; uint32_t 691 drivers/scsi/lpfc/lpfc_sli4.h uint32_t cpucheck_xmt_io[LPFC_CHECK_CPU_CNT]; uint32_t 692 drivers/scsi/lpfc/lpfc_sli4.h uint32_t cpucheck_cmpl_io[LPFC_CHECK_CPU_CNT]; uint32_t 789 drivers/scsi/lpfc/lpfc_sli4.h uint32_t ue_mask_lo; uint32_t 790 drivers/scsi/lpfc/lpfc_sli4.h uint32_t ue_mask_hi; uint32_t 791 drivers/scsi/lpfc/lpfc_sli4.h uint32_t ue_to_sr; uint32_t 792 drivers/scsi/lpfc/lpfc_sli4.h uint32_t ue_to_rp; uint32_t 800 drivers/scsi/lpfc/lpfc_sli4.h uint32_t count, bool arm); uint32_t 802 drivers/scsi/lpfc/lpfc_sli4.h uint32_t count, bool arm); uint32_t 825 drivers/scsi/lpfc/lpfc_sli4.h uint32_t fw_func_mode; /* FW function protocol mode */ uint32_t 826 drivers/scsi/lpfc/lpfc_sli4.h uint32_t ulp0_mode; /* ULP0 protocol mode */ uint32_t 827 drivers/scsi/lpfc/lpfc_sli4.h uint32_t ulp1_mode; /* ULP1 protocol mode */ uint32_t 848 drivers/scsi/lpfc/lpfc_sli4.h uint32_t intr_enable; uint32_t 897 drivers/scsi/lpfc/lpfc_sli4.h uint32_t pport_name_sta; uint32_t 903 drivers/scsi/lpfc/lpfc_sli4.h uint32_t physical_port; uint32_t 911 drivers/scsi/lpfc/lpfc_sli4.h uint32_t conf_trunk; uint32_t 967 drivers/scsi/lpfc/lpfc_sli4.h uint32_t len; uint32_t 969 drivers/scsi/lpfc/lpfc_sli4.h uint32_t page_count; uint32_t 970 drivers/scsi/lpfc/lpfc_sli4.h uint32_t start_rpi; uint32_t 1010 drivers/scsi/lpfc/lpfc_sli4.h uint8_t, uint32_t, bool); uint32_t 1012 drivers/scsi/lpfc/lpfc_sli4.h void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t); uint32_t 1013 drivers/scsi/lpfc/lpfc_sli4.h void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t, uint32_t 1020 drivers/scsi/lpfc/lpfc_sli4.h uint32_t page_size, uint32_t 1021 drivers/scsi/lpfc/lpfc_sli4.h uint32_t entry_size, uint32_t 1022 drivers/scsi/lpfc/lpfc_sli4.h uint32_t entry_count, int cpu); uint32_t 1024 drivers/scsi/lpfc/lpfc_sli4.h int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t); uint32_t 1025 drivers/scsi/lpfc/lpfc_sli4.h void lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq, uint32_t 1026 drivers/scsi/lpfc/lpfc_sli4.h uint32_t numq, uint32_t usdelay); uint32_t 1028 drivers/scsi/lpfc/lpfc_sli4.h struct lpfc_queue *, uint32_t, uint32_t); uint32_t 1030 drivers/scsi/lpfc/lpfc_sli4.h struct lpfc_sli4_hdw_queue *hdwq, uint32_t type, uint32_t 1031 drivers/scsi/lpfc/lpfc_sli4.h uint32_t subtype); uint32_t 1033 drivers/scsi/lpfc/lpfc_sli4.h struct lpfc_queue *, uint32_t); uint32_t 1035 drivers/scsi/lpfc/lpfc_sli4.h struct lpfc_queue *, uint32_t); uint32_t 1037 drivers/scsi/lpfc/lpfc_sli4.h struct lpfc_queue *, struct lpfc_queue *, uint32_t); uint32_t 1040 drivers/scsi/lpfc/lpfc_sli4.h uint32_t subtype); uint32_t 1091 drivers/scsi/lpfc/lpfc_sli4.h uint32_t count, bool arm); uint32_t 1093 drivers/scsi/lpfc/lpfc_sli4.h uint32_t count, bool arm); uint32_t 1096 drivers/scsi/lpfc/lpfc_sli4.h uint32_t count, bool arm); uint32_t 1098 drivers/scsi/lpfc/lpfc_sli4.h uint32_t count, bool arm); uint32_t 244 drivers/scsi/lpfc/lpfc_vport.c uint32_t wait_flags = 0; uint32_t 33 drivers/scsi/lpfc/lpfc_vport.h uint32_t api_versions; uint32_t 58 drivers/scsi/lpfc/lpfc_vport.h uint32_t vports_max; uint32_t 59 drivers/scsi/lpfc/lpfc_vport.h uint32_t vports_inuse; uint32_t 60 drivers/scsi/lpfc/lpfc_vport.h uint32_t rpi_max; uint32_t 61 drivers/scsi/lpfc/lpfc_vport.h uint32_t rpi_inuse; uint32_t 67 drivers/scsi/lpfc/lpfc_vport.h uint32_t api_version; uint32_t 69 drivers/scsi/lpfc/lpfc_vport.h uint32_t options; uint32_t 108 drivers/scsi/lpfc/lpfc_vport.h uint32_t cmd; uint32_t 161 drivers/scsi/megaraid/mbox_defs.h uint32_t lba; uint32_t 162 drivers/scsi/megaraid/mbox_defs.h uint32_t xferaddr; uint32_t 186 drivers/scsi/megaraid/mbox_defs.h uint32_t xferaddr_lo; uint32_t 187 drivers/scsi/megaraid/mbox_defs.h uint32_t xferaddr_hi; uint32_t 242 drivers/scsi/megaraid/mbox_defs.h uint32_t dataxferaddr; uint32_t 243 drivers/scsi/megaraid/mbox_defs.h uint32_t dataxferlen; uint32_t 248 drivers/scsi/megaraid/mbox_defs.h uint32_t dataxferaddr_lo; uint32_t 249 drivers/scsi/megaraid/mbox_defs.h uint32_t dataxferaddr_hi; uint32_t 298 drivers/scsi/megaraid/mbox_defs.h uint32_t dataxferaddr; uint32_t 299 drivers/scsi/megaraid/mbox_defs.h uint32_t dataxferlen; uint32_t 330 drivers/scsi/megaraid/mbox_defs.h uint32_t data_size; uint32_t 331 drivers/scsi/megaraid/mbox_defs.h uint32_t config_signature; uint32_t 339 drivers/scsi/megaraid/mbox_defs.h uint32_t signature; uint32_t 386 drivers/scsi/megaraid/mbox_defs.h uint32_t global_counter; uint32_t 449 drivers/scsi/megaraid/mbox_defs.h uint32_t data_size; uint32_t 465 drivers/scsi/megaraid/mbox_defs.h uint32_t ldrv_size[MAX_LOGICAL_DRIVES_40LD]; uint32_t 536 drivers/scsi/megaraid/mbox_defs.h uint32_t size[MAX_LOGICAL_DRIVES_8LD]; uint32_t 600 drivers/scsi/megaraid/mbox_defs.h uint32_t start_blk; uint32_t 601 drivers/scsi/megaraid/mbox_defs.h uint32_t num_blks; uint32_t 612 drivers/scsi/megaraid/mbox_defs.h uint32_t start_blk; uint32_t 613 drivers/scsi/megaraid/mbox_defs.h uint32_t num_blks; uint32_t 692 drivers/scsi/megaraid/mbox_defs.h uint32_t size; uint32_t 770 drivers/scsi/megaraid/mbox_defs.h uint32_t length; uint32_t 779 drivers/scsi/megaraid/mbox_defs.h uint32_t address; uint32_t 780 drivers/scsi/megaraid/mbox_defs.h uint32_t length; uint32_t 70 drivers/scsi/megaraid/mega_common.h uint32_t state; uint32_t 71 drivers/scsi/megaraid/mega_common.h uint32_t dma_direction; uint32_t 72 drivers/scsi/megaraid/mega_common.h uint32_t dma_type; uint32_t 75 drivers/scsi/megaraid/mega_common.h uint32_t status; uint32_t 173 drivers/scsi/megaraid/mega_common.h uint32_t unique_id; uint32_t 121 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t opcode; uint32_t 122 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t adapno; uint32_t 124 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t xferlen; uint32_t 125 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t data_dir; uint32_t 131 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t user_data_len; uint32_t 134 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t pad_for_64bit_align; uint32_t 190 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t unique_id; uint32_t 191 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t host_no; uint32_t 222 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t uid; uint32_t 240 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t buf_size; uint32_t 273 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t unique_id; uint32_t 274 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t drvr_type; uint32_t 281 drivers/scsi/megaraid/megaraid_ioctl.h int(*issue_uioc)(unsigned long, uioc_t *, uint32_t); uint32_t 284 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t quiescent; uint32_t 299 drivers/scsi/megaraid/megaraid_ioctl.h int mraid_mm_unregister_adp(uint32_t); uint32_t 300 drivers/scsi/megaraid/megaraid_ioctl.h uint32_t mraid_mm_adapter_app_handle(uint32_t); uint32_t 129 drivers/scsi/megaraid/megaraid_mbox.c static int megaraid_mbox_mm_handler(unsigned long, uioc_t *, uint32_t); uint32_t 702 drivers/scsi/megaraid/megaraid_mbox.c uint32_t magic64; uint32_t 1632 drivers/scsi/megaraid/megaraid_mbox.c mbox64->xferaddr_lo = (uint32_t )ccb->pthru_dma_h; uint32_t 1670 drivers/scsi/megaraid/megaraid_mbox.c mbox->numsectors = (uint32_t)scp->cmnd[4]; uint32_t 1672 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[1] << 16) | uint32_t 1673 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[2] << 8) | uint32_t 1674 drivers/scsi/megaraid/megaraid_mbox.c (uint32_t)scp->cmnd[3]; uint32_t 1684 drivers/scsi/megaraid/megaraid_mbox.c (uint32_t)scp->cmnd[8] | uint32_t 1685 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[7] << 8); uint32_t 1687 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[2] << 24) | uint32_t 1688 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[3] << 16) | uint32_t 1689 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[4] << 8) | uint32_t 1690 drivers/scsi/megaraid/megaraid_mbox.c (uint32_t)scp->cmnd[5]; uint32_t 1698 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[2] << 24) | uint32_t 1699 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[3] << 16) | uint32_t 1700 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[4] << 8) | uint32_t 1701 drivers/scsi/megaraid/megaraid_mbox.c (uint32_t)scp->cmnd[5]; uint32_t 1704 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[6] << 24) | uint32_t 1705 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[7] << 16) | uint32_t 1706 drivers/scsi/megaraid/megaraid_mbox.c ((uint32_t)scp->cmnd[8] << 8) | uint32_t 1707 drivers/scsi/megaraid/megaraid_mbox.c (uint32_t)scp->cmnd[9]; uint32_t 1722 drivers/scsi/megaraid/megaraid_mbox.c mbox64->xferaddr_lo = (uint32_t )ccb->sgl_dma_h; uint32_t 1830 drivers/scsi/megaraid/megaraid_mbox.c mbox64->xferaddr_lo = (uint32_t)ccb->epthru_dma_h; uint32_t 1839 drivers/scsi/megaraid/megaraid_mbox.c mbox64->xferaddr_lo = (uint32_t)ccb->pthru_dma_h; uint32_t 2042 drivers/scsi/megaraid/megaraid_mbox.c uint32_t dword; uint32_t 2906 drivers/scsi/megaraid/megaraid_mbox.c mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h; uint32_t 2939 drivers/scsi/megaraid/megaraid_mbox.c mbox->xferaddr = (uint32_t)pinfo_dma_h; uint32_t 3010 drivers/scsi/megaraid/megaraid_mbox.c mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h; uint32_t 3048 drivers/scsi/megaraid/megaraid_mbox.c mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h; uint32_t 3140 drivers/scsi/megaraid/megaraid_mbox.c mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h; uint32_t 3180 drivers/scsi/megaraid/megaraid_mbox.c mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h; uint32_t 3241 drivers/scsi/megaraid/megaraid_mbox.c uint32_t dword; uint32_t 3510 drivers/scsi/megaraid/megaraid_mbox.c megaraid_mbox_mm_handler(unsigned long drvr_data, uioc_t *kioc, uint32_t action) uint32_t 3913 drivers/scsi/megaraid/megaraid_mbox.c mbox->xferaddr = (uint32_t)raid_dev->sysfs_buffer_dma; uint32_t 3988 drivers/scsi/megaraid/megaraid_mbox.c uint32_t app_hndl; uint32_t 4020 drivers/scsi/megaraid/megaraid_mbox.c uint32_t app_hndl = 0; uint32_t 204 drivers/scsi/megaraid/megaraid_mbox.h uint32_t last_disp; uint32_t 61 drivers/scsi/megaraid/megaraid_mm.c static uint32_t drvr_ver = 0x02200207; uint32_t 247 drivers/scsi/megaraid/megaraid_mm.c uint32_t adapno; uint32_t 322 drivers/scsi/megaraid/megaraid_mm.c if (copy_to_user(kmimd.data, &drvr_ver, sizeof(uint32_t))) uint32_t 332 drivers/scsi/megaraid/megaraid_mm.c sizeof(uint32_t))) uint32_t 363 drivers/scsi/megaraid/megaraid_mm.c uint32_t adapno; uint32_t 460 drivers/scsi/megaraid/megaraid_mm.c mbox->xferaddr = (uint32_t)kioc->buf_paddr; uint32_t 480 drivers/scsi/megaraid/megaraid_mm.c mbox->xferaddr = (uint32_t)kioc->pthru32_h; uint32_t 733 drivers/scsi/megaraid/megaraid_mm.c uint32_t adapno; uint32_t 908 drivers/scsi/megaraid/megaraid_mm.c uint32_t rval; uint32_t 1035 drivers/scsi/megaraid/megaraid_mm.c uint32_t uint32_t 1036 drivers/scsi/megaraid/megaraid_mm.c mraid_mm_adapter_app_handle(uint32_t unique_id) uint32_t 1118 drivers/scsi/megaraid/megaraid_mm.c mraid_mm_unregister_adp(uint32_t unique_id) uint32_t 62 drivers/scsi/megaraid/megaraid_mm.h uint32_t inlen; uint32_t 63 drivers/scsi/megaraid/megaraid_mm.h uint32_t outlen; uint32_t 78 drivers/scsi/megaraid/megaraid_mm.h uint32_t length; uint32_t 365 drivers/scsi/megaraid/megaraid_sas_base.c format_timestamp(uint32_t timestamp) uint32_t 88 drivers/scsi/megaraid/megaraid_sas_fp.c u64 mega_div64_32(uint64_t dividend, uint32_t divisor) uint32_t 105 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t ioc_number; uint32_t 106 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t port_number; uint32_t 107 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t max_data_size; uint32_t 129 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t device:5; uint32_t 130 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t function:3; uint32_t 131 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t bus:24; uint32_t 133 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t word; uint32_t 135 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t segment_id; uint32_t 169 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t adapter_type; uint32_t 170 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t port_number; uint32_t 171 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t pci_id; uint32_t 172 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t hw_rev; uint32_t 173 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t subsystem_device; uint32_t 174 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t subsystem_vendor; uint32_t 175 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t rsvd0; uint32_t 176 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t firmware_version; uint32_t 177 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t bios_version; uint32_t 200 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t event_types[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; uint32_t 210 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t event_types[4]; uint32_t 221 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t event; uint32_t 222 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t context; uint32_t 255 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t timeout; uint32_t 260 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t max_reply_bytes; uint32_t 261 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t data_in_size; uint32_t 262 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t data_out_size; uint32_t 263 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t max_sense_bytes; uint32_t 264 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t data_sge_offset; uint32_t 271 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t timeout; uint32_t 272 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t reply_frame_buf_ptr; uint32_t 273 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t data_in_buf_ptr; uint32_t 274 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t data_out_buf_ptr; uint32_t 275 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t sense_data_ptr; uint32_t 276 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t max_reply_bytes; uint32_t 277 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t data_in_size; uint32_t 278 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t data_out_size; uint32_t 279 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t max_sense_bytes; uint32_t 280 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t data_sge_offset; uint32_t 301 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t id; uint32_t 302 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t bus; uint32_t 339 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t diagnostic_flags; uint32_t 340 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t product_specific[MPT3_PRODUCT_SPECIFIC_DWORDS]; uint32_t 341 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t requested_buffer_size; uint32_t 342 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t unique_id; uint32_t 355 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t unique_id; uint32_t 379 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t diagnostic_flags; uint32_t 380 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t product_specific[MPT3_PRODUCT_SPECIFIC_DWORDS]; uint32_t 381 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t total_buffer_size; uint32_t 382 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t driver_added_buffer_size; uint32_t 383 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t unique_id; uint32_t 397 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t unique_id; uint32_t 418 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t starting_offset; uint32_t 419 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t bytes_to_read; uint32_t 420 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t unique_id; uint32_t 421 drivers/scsi/mpt3sas/mpt3sas_ctl.h uint32_t diagnostic_data[1]; uint32_t 86 drivers/scsi/mpt3sas/mpt3sas_trigger_diag.h uint32_t MasterData; uint32_t 113 drivers/scsi/mpt3sas/mpt3sas_trigger_diag.h uint32_t ValidEntries; uint32_t 146 drivers/scsi/mpt3sas/mpt3sas_trigger_diag.h uint32_t ValidEntries; uint32_t 161 drivers/scsi/mpt3sas/mpt3sas_trigger_diag.h uint32_t IocLogInfo; uint32_t 176 drivers/scsi/mpt3sas/mpt3sas_trigger_diag.h uint32_t ValidEntries; uint32_t 186 drivers/scsi/mpt3sas/mpt3sas_trigger_diag.h uint32_t trigger_type; uint32_t 238 drivers/scsi/pm8001/pm8001_sas.c uint32_t *qp = (uint32_t *)(((char *) uint32_t 58 drivers/scsi/qedf/qedf.h uint32_t req_len; uint32_t 65 drivers/scsi/qedf/qedf.h uint32_t resp_len; uint32_t 181 drivers/scsi/qedf/qedf.h uint32_t rx_buf_off; uint32_t 182 drivers/scsi/qedf/qedf.h uint32_t tx_buf_off; uint32_t 183 drivers/scsi/qedf/qedf.h uint32_t rx_id; uint32_t 184 drivers/scsi/qedf/qedf.h uint32_t task_retry_identifier; uint32_t 247 drivers/scsi/qedf/qedf.h uint32_t cq_num_entries; uint32_t 283 drivers/scsi/qedf/qedf.h uint32_t port_id; /* Remote port fabric ID */ uint32_t 396 drivers/scsi/qedf/qedf.h uint32_t grcdump_size; uint32_t 107 drivers/scsi/qedf/qedf_dbg.c qedf_alloc_grc_dump_buf(u8 **buf, uint32_t len) uint32_t 126 drivers/scsi/qedf/qedf_dbg.c u8 **buf, uint32_t *grcsize) uint32_t 105 drivers/scsi/qedf/qedf_dbg.h extern int qedf_alloc_grc_dump_buf(uint8_t **buf, uint32_t len); uint32_t 109 drivers/scsi/qedf/qedf_dbg.h uint32_t *grcsize); uint32_t 158 drivers/scsi/qedf/qedf_debugfs.c uint32_t val; uint32_t 10 drivers/scsi/qedf/qedf_els.c void *data, uint32_t data_len, uint32_t 12 drivers/scsi/qedf/qedf_els.c struct qedf_els_cb_arg *cb_arg, uint32_t timer_msec) uint32_t 21 drivers/scsi/qedf/qedf_els.c uint32_t did, sid; uint32_t 226 drivers/scsi/qedf/qedf_els.c uint32_t sid; uint32_t 227 drivers/scsi/qedf/qedf_els.c uint32_t r_a_tov; uint32_t 492 drivers/scsi/qedf/qedf_els.c uint32_t r_a_tov = lport->r_a_tov; uint32_t 984 drivers/scsi/qedf/qedf_els.c uint32_t sid; uint32_t 985 drivers/scsi/qedf/qedf_els.c uint32_t r_a_tov; uint32_t 312 drivers/scsi/qedf/qedf_io.c uint32_t free_sqes; uint32_t 1938 drivers/scsi/qedf/qedf_io.c uint32_t r_ctl; uint32_t 239 drivers/scsi/qedi/qedi_iscsi.c u16 qdepth, uint32_t initial_cmdsn) uint32_t 291 drivers/scsi/qedi/qedi_iscsi.c qedi_conn_create(struct iscsi_cls_session *cls_session, uint32_t cid) uint32_t 679 drivers/scsi/qedi/qedi_iscsi.c conn->dataout_pdus_cnt = (uint32_t)iscsi_stats.iscsi_tx_data_pdu_cnt; uint32_t 680 drivers/scsi/qedi/qedi_iscsi.c conn->datain_pdus_cnt = (uint32_t)iscsi_stats.iscsi_rx_data_pdu_cnt; uint32_t 681 drivers/scsi/qedi/qedi_iscsi.c conn->r2t_pdus_cnt = (uint32_t)iscsi_stats.iscsi_rx_r2t_pdu_cnt; uint32_t 424 drivers/scsi/qla1280.c static uint16_t qla1280_get_nvram_word(struct scsi_qla_host *, uint32_t); uint32_t 425 drivers/scsi/qla1280.c static uint16_t qla1280_nvram_request(struct scsi_qla_host *, uint32_t); uint32_t 1298 drivers/scsi/qla1280.c uint32_t residual_length = le32_to_cpu(sts->residual_length); uint32_t 2310 drivers/scsi/qla1280.c qla1280_get_nvram_word(struct scsi_qla_host *ha, uint32_t address) uint32_t 2312 drivers/scsi/qla1280.c uint32_t nv_cmd; uint32_t 2341 drivers/scsi/qla1280.c qla1280_nvram_request(struct scsi_qla_host *ha, uint32_t nv_cmd) uint32_t 3237 drivers/scsi/qla1280.c uint32_t timer; uint32_t 3346 drivers/scsi/qla1280.c uint32_t index; uint32_t 3603 drivers/scsi/qla1280.c uint32_t handle = le32_to_cpu(pkt->handle); uint32_t 3698 drivers/scsi/qla1280.c uint32_t handle = le32_to_cpu(pkt->handle); uint32_t 618 drivers/scsi/qla1280.h uint32_t handle; /* System handle. */ uint32_t 996 drivers/scsi/qla1280.h uint32_t no_sync:1; uint32_t 997 drivers/scsi/qla1280.h uint32_t no_wide:1; uint32_t 998 drivers/scsi/qla1280.h uint32_t no_ppr:1; uint32_t 999 drivers/scsi/qla1280.h uint32_t no_nvram:1; uint32_t 1052 drivers/scsi/qla1280.h uint32_t online:1; /* 0 */ uint32_t 1053 drivers/scsi/qla1280.h uint32_t reset_marker:1; /* 1 */ uint32_t 1054 drivers/scsi/qla1280.h uint32_t disable_host_adapter:1; /* 2 */ uint32_t 1055 drivers/scsi/qla1280.h uint32_t reset_active:1; /* 3 */ uint32_t 1056 drivers/scsi/qla1280.h uint32_t abort_isp_active:1; /* 4 */ uint32_t 1057 drivers/scsi/qla1280.h uint32_t disable_risc_code_load:1; /* 5 */ uint32_t 160 drivers/scsi/qla2xxx/qla_attr.c uint32_t faddr; uint32_t 208 drivers/scsi/qla2xxx/qla_attr.c uint32_t *iter; uint32_t 209 drivers/scsi/qla2xxx/qla_attr.c uint32_t chksum; uint32_t 211 drivers/scsi/qla2xxx/qla_attr.c iter = (uint32_t *)buf; uint32_t 337 drivers/scsi/qla2xxx/qla_attr.c uint32_t start = 0; uint32_t 338 drivers/scsi/qla2xxx/qla_attr.c uint32_t size = ha->optrom_size; uint32_t 521 drivers/scsi/qla2xxx/qla_attr.c uint32_t faddr; uint32_t 673 drivers/scsi/qla2xxx/qla_attr.c uint32_t idc_control; uint32_t 714 drivers/scsi/qla2xxx/qla_attr.c uint32_t idc_control; uint32_t 1062 drivers/scsi/qla2xxx/qla_attr.c uint32_t sn; uint32_t 1412 drivers/scsi/qla2xxx/qla_attr.c (uint32_t)ha->cs84xx->op_fw_version); uint32_t 1543 drivers/scsi/qla2xxx/qla_attr.c uint32_t pstate; uint32_t 1604 drivers/scsi/qla2xxx/qla_attr.c uint32_t size; uint32_t 2433 drivers/scsi/qla2xxx/qla_attr.c uint32_t port_type; uint32_t 2504 drivers/scsi/qla2xxx/qla_attr.c uint32_t port_id = ~0U; uint32_t 2519 drivers/scsi/qla2xxx/qla_attr.c qla2x00_set_rport_loss_tmo(struct fc_rport *rport, uint32_t timeout) uint32_t 68 drivers/scsi/qla2xxx/qla_bsg.c uint32_t *bcode_val_ptr, bcode_val; uint32_t 73 drivers/scsi/qla2xxx/qla_bsg.c bcode_val_ptr = (uint32_t *)pri_cfg; uint32_t 74 drivers/scsi/qla2xxx/qla_bsg.c bcode_val = (uint32_t)(*bcode_val_ptr); uint32_t 124 drivers/scsi/qla2xxx/qla_bsg.c uint32_t len; uint32_t 125 drivers/scsi/qla2xxx/qla_bsg.c uint32_t oper; uint32_t 722 drivers/scsi/qla2xxx/qla_bsg.c uint32_t req_data_len; uint32_t 725 drivers/scsi/qla2xxx/qla_bsg.c uint32_t rsp_data_len; uint32_t 799 drivers/scsi/qla2xxx/qla_bsg.c (le32_to_cpu(*(uint32_t *)req_data) == ELS_OPCODE_BYTE && uint32_t 956 drivers/scsi/qla2xxx/qla_bsg.c uint32_t flag; uint32_t 995 drivers/scsi/qla2xxx/qla_bsg.c uint32_t sg_cnt; uint32_t 996 drivers/scsi/qla2xxx/qla_bsg.c uint32_t data_len; uint32_t 998 drivers/scsi/qla2xxx/qla_bsg.c uint32_t flag; uint32_t 999 drivers/scsi/qla2xxx/qla_bsg.c uint32_t fw_ver; uint32_t 1046 drivers/scsi/qla2xxx/qla_bsg.c fw_ver = get_unaligned_le32((uint32_t *)fw_buf + 2); uint32_t 1106 drivers/scsi/qla2xxx/qla_bsg.c uint32_t sg_cnt; uint32_t 1107 drivers/scsi/qla2xxx/qla_bsg.c uint32_t data_len = 0; uint32_t 1108 drivers/scsi/qla2xxx/qla_bsg.c uint32_t dma_direction = DMA_NONE; uint32_t 1383 drivers/scsi/qla2xxx/qla_bsg.c uint32_t start = 0; uint32_t 1532 drivers/scsi/qla2xxx/qla_bsg.c uint32_t count; uint32_t 1775 drivers/scsi/qla2xxx/qla_bsg.c uint32_t rval = EXT_STATUS_OK; uint32_t 1779 drivers/scsi/qla2xxx/qla_bsg.c uint32_t tot_dsds; uint32_t 1781 drivers/scsi/qla2xxx/qla_bsg.c uint32_t req_data_len; uint32_t 1782 drivers/scsi/qla2xxx/qla_bsg.c uint32_t rsp_data_len; uint32_t 2302 drivers/scsi/qla2xxx/qla_bsg.c uint32_t *cmd = bsg_request->rqst_data.h_vendor.vendor_cmd; uint32_t 83 drivers/scsi/qla2xxx/qla_bsg.h uint32_t start_addr; uint32_t 86 drivers/scsi/qla2xxx/qla_bsg.h uint32_t id; uint32_t 92 drivers/scsi/qla2xxx/qla_bsg.h uint32_t param0; uint32_t 93 drivers/scsi/qla2xxx/qla_bsg.h uint32_t param1; uint32_t 97 drivers/scsi/qla2xxx/qla_bsg.h uint32_t type; uint32_t 106 drivers/scsi/qla2xxx/qla_bsg.h uint32_t context; uint32_t 153 drivers/scsi/qla2xxx/qla_bsg.h uint32_t len; /* bytes in payload following this struct */ uint32_t 206 drivers/scsi/qla2xxx/qla_bsg.h uint32_t count; uint32_t 238 drivers/scsi/qla2xxx/qla_bsg.h uint32_t addr; uint32_t 239 drivers/scsi/qla2xxx/qla_bsg.h uint32_t val; uint32_t 244 drivers/scsi/qla2xxx/qla_bsg.h uint32_t outage_duration; uint32_t 275 drivers/scsi/qla2xxx/qla_bsg.h uint32_t buf[16]; uint32_t 77 drivers/scsi/qla2xxx/qla_dbg.c static uint32_t ql_dbg_offset = 0x800; uint32_t 111 drivers/scsi/qla2xxx/qla_dbg.c qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, uint32_t 112 drivers/scsi/qla2xxx/qla_dbg.c uint32_t ram_dwords, void **nxt) uint32_t 116 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *chunk = (void *)ha->gid_list; uint32_t 117 drivers/scsi/qla2xxx/qla_dbg.c uint32_t dwords = qla2x00_gid_list_size(ha) / 4; uint32_t 118 drivers/scsi/qla2xxx/qla_dbg.c uint32_t stat; uint32_t 190 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, uint32_t 191 drivers/scsi/qla2xxx/qla_dbg.c uint32_t ram_dwords, void **nxt) uint32_t 196 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *chunk = (void *)ha->gid_list; uint32_t 197 drivers/scsi/qla2xxx/qla_dbg.c uint32_t dwords = qla2x00_gid_list_size(ha) / 4; uint32_t 198 drivers/scsi/qla2xxx/qla_dbg.c uint32_t stat; uint32_t 266 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, uint32_t 267 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cram_size, void **nxt) uint32_t 287 drivers/scsi/qla2xxx/qla_dbg.c static uint32_t * uint32_t 288 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, uint32_t 289 drivers/scsi/qla2xxx/qla_dbg.c uint32_t count, uint32_t *buf) uint32_t 291 drivers/scsi/qla2xxx/qla_dbg.c uint32_t __iomem *dmp_reg; uint32_t 316 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt; uint32_t 369 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, uint32_t 370 drivers/scsi/qla2xxx/qla_dbg.c uint32_t ram_words, void **nxt) uint32_t 373 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt, stat, timer, words, idx; uint32_t 453 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, uint32_t 473 drivers/scsi/qla2xxx/qla_dbg.c qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) uint32_t 475 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt; uint32_t 476 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *iter_reg; uint32_t 500 drivers/scsi/qla2xxx/qla_dbg.c qla25xx_copy_exlogin(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) uint32_t 522 drivers/scsi/qla2xxx/qla_dbg.c qla81xx_copy_exchoffld(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) uint32_t 545 drivers/scsi/qla2xxx/qla_dbg.c uint32_t **last_chain) uint32_t 549 drivers/scsi/qla2xxx/qla_dbg.c uint32_t num_queues; uint32_t 592 drivers/scsi/qla2xxx/qla_dbg.c qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) uint32_t 663 drivers/scsi/qla2xxx/qla_dbg.c qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) uint32_t 665 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt, que_idx; uint32_t 726 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt; uint32_t 896 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt, timer; uint32_t 1095 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt; uint32_t 1098 drivers/scsi/qla2xxx/qla_dbg.c uint32_t __iomem *dmp_reg; uint32_t 1099 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *iter_reg; uint32_t 1105 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *last_chain = NULL; uint32_t 1354 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt; uint32_t 1357 drivers/scsi/qla2xxx/qla_dbg.c uint32_t __iomem *dmp_reg; uint32_t 1358 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *iter_reg; uint32_t 1363 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *last_chain = NULL; uint32_t 1680 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt; uint32_t 1683 drivers/scsi/qla2xxx/qla_dbg.c uint32_t __iomem *dmp_reg; uint32_t 1684 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *iter_reg; uint32_t 1689 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *last_chain = NULL; uint32_t 2008 drivers/scsi/qla2xxx/qla_dbg.c uint32_t cnt; uint32_t 2011 drivers/scsi/qla2xxx/qla_dbg.c uint32_t __iomem *dmp_reg; uint32_t 2012 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *iter_reg; uint32_t 2017 drivers/scsi/qla2xxx/qla_dbg.c uint32_t *last_chain = NULL; uint32_t 2773 drivers/scsi/qla2xxx/qla_dbg.c ql_log_qp(uint32_t level, struct qla_qpair *qpair, int32_t id, uint32_t 2831 drivers/scsi/qla2xxx/qla_dbg.c ql_dbg_qp(uint32_t level, struct qla_qpair *qpair, int32_t id, uint32_t 59 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_status; uint32_t 60 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_reg[32]; uint32_t 61 drivers/scsi/qla2xxx/qla_dbg.h uint32_t shadow_reg[7]; uint32_t 63 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_gp_reg[128]; uint32_t 64 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_0_reg[16]; uint32_t 65 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_1_reg[16]; uint32_t 66 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_gp_reg[128]; uint32_t 67 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_0_reg[16]; uint32_t 68 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_1_reg[16]; uint32_t 69 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_2_reg[16]; uint32_t 70 drivers/scsi/qla2xxx/qla_dbg.h uint32_t cmd_dma_reg[16]; uint32_t 71 drivers/scsi/qla2xxx/qla_dbg.h uint32_t req0_dma_reg[15]; uint32_t 72 drivers/scsi/qla2xxx/qla_dbg.h uint32_t resp0_dma_reg[15]; uint32_t 73 drivers/scsi/qla2xxx/qla_dbg.h uint32_t req1_dma_reg[15]; uint32_t 74 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt0_dma_reg[32]; uint32_t 75 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt1_dma_reg[32]; uint32_t 76 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt2_dma_reg[32]; uint32_t 77 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt3_dma_reg[32]; uint32_t 78 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt4_dma_reg[32]; uint32_t 79 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt_data_dma_reg[16]; uint32_t 80 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rcvt0_data_dma_reg[32]; uint32_t 81 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rcvt1_data_dma_reg[32]; uint32_t 82 drivers/scsi/qla2xxx/qla_dbg.h uint32_t risc_gp_reg[128]; uint32_t 83 drivers/scsi/qla2xxx/qla_dbg.h uint32_t lmc_reg[112]; uint32_t 84 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fpm_hdw_reg[192]; uint32_t 85 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fb_hdw_reg[176]; uint32_t 86 drivers/scsi/qla2xxx/qla_dbg.h uint32_t code_ram[0x2000]; uint32_t 87 drivers/scsi/qla2xxx/qla_dbg.h uint32_t ext_mem[1]; uint32_t 91 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_status; uint32_t 92 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_risc_reg[32]; uint32_t 93 drivers/scsi/qla2xxx/qla_dbg.h uint32_t pcie_regs[4]; uint32_t 94 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_reg[32]; uint32_t 95 drivers/scsi/qla2xxx/qla_dbg.h uint32_t shadow_reg[11]; uint32_t 96 drivers/scsi/qla2xxx/qla_dbg.h uint32_t risc_io_reg; uint32_t 98 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_gp_reg[128]; uint32_t 99 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_0_reg[48]; uint32_t 100 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_1_reg[16]; uint32_t 101 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_gp_reg[128]; uint32_t 102 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_0_reg[32]; uint32_t 103 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_1_reg[16]; uint32_t 104 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_2_reg[16]; uint32_t 105 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_gp_reg[128]; uint32_t 106 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_0_reg[32]; uint32_t 107 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_1_reg[16]; uint32_t 108 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_2_reg[16]; uint32_t 109 drivers/scsi/qla2xxx/qla_dbg.h uint32_t cmd_dma_reg[16]; uint32_t 110 drivers/scsi/qla2xxx/qla_dbg.h uint32_t req0_dma_reg[15]; uint32_t 111 drivers/scsi/qla2xxx/qla_dbg.h uint32_t resp0_dma_reg[15]; uint32_t 112 drivers/scsi/qla2xxx/qla_dbg.h uint32_t req1_dma_reg[15]; uint32_t 113 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt0_dma_reg[32]; uint32_t 114 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt1_dma_reg[32]; uint32_t 115 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt2_dma_reg[32]; uint32_t 116 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt3_dma_reg[32]; uint32_t 117 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt4_dma_reg[32]; uint32_t 118 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt_data_dma_reg[16]; uint32_t 119 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rcvt0_data_dma_reg[32]; uint32_t 120 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rcvt1_data_dma_reg[32]; uint32_t 121 drivers/scsi/qla2xxx/qla_dbg.h uint32_t risc_gp_reg[128]; uint32_t 122 drivers/scsi/qla2xxx/qla_dbg.h uint32_t lmc_reg[128]; uint32_t 123 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fpm_hdw_reg[192]; uint32_t 124 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fb_hdw_reg[192]; uint32_t 125 drivers/scsi/qla2xxx/qla_dbg.h uint32_t code_ram[0x2000]; uint32_t 126 drivers/scsi/qla2xxx/qla_dbg.h uint32_t ext_mem[1]; uint32_t 130 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_status; uint32_t 131 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_risc_reg[32]; uint32_t 132 drivers/scsi/qla2xxx/qla_dbg.h uint32_t pcie_regs[4]; uint32_t 133 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_reg[32]; uint32_t 134 drivers/scsi/qla2xxx/qla_dbg.h uint32_t shadow_reg[11]; uint32_t 135 drivers/scsi/qla2xxx/qla_dbg.h uint32_t risc_io_reg; uint32_t 137 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_gp_reg[128]; uint32_t 138 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_0_reg[48]; uint32_t 139 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_1_reg[16]; uint32_t 140 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_gp_reg[128]; uint32_t 141 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_0_reg[32]; uint32_t 142 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_1_reg[16]; uint32_t 143 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_2_reg[16]; uint32_t 144 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_gp_reg[128]; uint32_t 145 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_0_reg[32]; uint32_t 146 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_1_reg[16]; uint32_t 147 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_2_reg[16]; uint32_t 148 drivers/scsi/qla2xxx/qla_dbg.h uint32_t cmd_dma_reg[16]; uint32_t 149 drivers/scsi/qla2xxx/qla_dbg.h uint32_t req0_dma_reg[15]; uint32_t 150 drivers/scsi/qla2xxx/qla_dbg.h uint32_t resp0_dma_reg[15]; uint32_t 151 drivers/scsi/qla2xxx/qla_dbg.h uint32_t req1_dma_reg[15]; uint32_t 152 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt0_dma_reg[32]; uint32_t 153 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt1_dma_reg[32]; uint32_t 154 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt2_dma_reg[32]; uint32_t 155 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt3_dma_reg[32]; uint32_t 156 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt4_dma_reg[32]; uint32_t 157 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt_data_dma_reg[16]; uint32_t 158 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rcvt0_data_dma_reg[32]; uint32_t 159 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rcvt1_data_dma_reg[32]; uint32_t 160 drivers/scsi/qla2xxx/qla_dbg.h uint32_t risc_gp_reg[128]; uint32_t 161 drivers/scsi/qla2xxx/qla_dbg.h uint32_t lmc_reg[128]; uint32_t 162 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fpm_hdw_reg[224]; uint32_t 163 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fb_hdw_reg[208]; uint32_t 164 drivers/scsi/qla2xxx/qla_dbg.h uint32_t code_ram[0x2000]; uint32_t 165 drivers/scsi/qla2xxx/qla_dbg.h uint32_t ext_mem[1]; uint32_t 169 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_status; uint32_t 170 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_risc_reg[48]; uint32_t 171 drivers/scsi/qla2xxx/qla_dbg.h uint32_t pcie_regs[4]; uint32_t 172 drivers/scsi/qla2xxx/qla_dbg.h uint32_t host_reg[32]; uint32_t 173 drivers/scsi/qla2xxx/qla_dbg.h uint32_t shadow_reg[11]; uint32_t 174 drivers/scsi/qla2xxx/qla_dbg.h uint32_t risc_io_reg; uint32_t 176 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_gp_reg[256]; uint32_t 177 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_0_reg[48]; uint32_t 178 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_1_reg[16]; uint32_t 179 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xseq_2_reg[16]; uint32_t 180 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_gp_reg[256]; uint32_t 181 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_0_reg[32]; uint32_t 182 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_1_reg[16]; uint32_t 183 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_2_reg[16]; uint32_t 184 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rseq_3_reg[16]; uint32_t 185 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_gp_reg[256]; uint32_t 186 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_0_reg[32]; uint32_t 187 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_1_reg[16]; uint32_t 188 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_2_reg[16]; uint32_t 189 drivers/scsi/qla2xxx/qla_dbg.h uint32_t aseq_3_reg[16]; uint32_t 190 drivers/scsi/qla2xxx/qla_dbg.h uint32_t cmd_dma_reg[64]; uint32_t 191 drivers/scsi/qla2xxx/qla_dbg.h uint32_t req0_dma_reg[15]; uint32_t 192 drivers/scsi/qla2xxx/qla_dbg.h uint32_t resp0_dma_reg[15]; uint32_t 193 drivers/scsi/qla2xxx/qla_dbg.h uint32_t req1_dma_reg[15]; uint32_t 194 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt0_dma_reg[32]; uint32_t 195 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt1_dma_reg[32]; uint32_t 196 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt2_dma_reg[32]; uint32_t 197 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt3_dma_reg[32]; uint32_t 198 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt4_dma_reg[32]; uint32_t 199 drivers/scsi/qla2xxx/qla_dbg.h uint32_t xmt_data_dma_reg[16]; uint32_t 200 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rcvt0_data_dma_reg[32]; uint32_t 201 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rcvt1_data_dma_reg[32]; uint32_t 202 drivers/scsi/qla2xxx/qla_dbg.h uint32_t risc_gp_reg[128]; uint32_t 203 drivers/scsi/qla2xxx/qla_dbg.h uint32_t lmc_reg[128]; uint32_t 204 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fpm_hdw_reg[256]; uint32_t 205 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rq0_array_reg[256]; uint32_t 206 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rq1_array_reg[256]; uint32_t 207 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rp0_array_reg[256]; uint32_t 208 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rp1_array_reg[256]; uint32_t 209 drivers/scsi/qla2xxx/qla_dbg.h uint32_t queue_control_reg[16]; uint32_t 210 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fb_hdw_reg[432]; uint32_t 211 drivers/scsi/qla2xxx/qla_dbg.h uint32_t at0_array_reg[128]; uint32_t 212 drivers/scsi/qla2xxx/qla_dbg.h uint32_t code_ram[0x2400]; uint32_t 213 drivers/scsi/qla2xxx/qla_dbg.h uint32_t ext_mem[1]; uint32_t 226 drivers/scsi/qla2xxx/qla_dbg.h uint32_t type; uint32_t 227 drivers/scsi/qla2xxx/qla_dbg.h uint32_t chain_size; uint32_t 229 drivers/scsi/qla2xxx/qla_dbg.h uint32_t size; uint32_t 230 drivers/scsi/qla2xxx/qla_dbg.h uint32_t addr_l; uint32_t 231 drivers/scsi/qla2xxx/qla_dbg.h uint32_t addr_h; uint32_t 232 drivers/scsi/qla2xxx/qla_dbg.h uint32_t eregs[8]; uint32_t 237 drivers/scsi/qla2xxx/qla_dbg.h uint32_t type; uint32_t 238 drivers/scsi/qla2xxx/qla_dbg.h uint32_t chain_size; uint32_t 240 drivers/scsi/qla2xxx/qla_dbg.h uint32_t size; uint32_t 245 drivers/scsi/qla2xxx/qla_dbg.h uint32_t type; uint32_t 246 drivers/scsi/qla2xxx/qla_dbg.h uint32_t chain_size; uint32_t 248 drivers/scsi/qla2xxx/qla_dbg.h uint32_t count; uint32_t 249 drivers/scsi/qla2xxx/qla_dbg.h uint32_t qregs[4 * QLA_MQ_SIZE]; uint32_t 253 drivers/scsi/qla2xxx/qla_dbg.h uint32_t queue; uint32_t 257 drivers/scsi/qla2xxx/qla_dbg.h uint32_t number; uint32_t 258 drivers/scsi/qla2xxx/qla_dbg.h uint32_t size; uint32_t 262 drivers/scsi/qla2xxx/qla_dbg.h uint32_t type; uint32_t 263 drivers/scsi/qla2xxx/qla_dbg.h uint32_t chain_size; uint32_t 276 drivers/scsi/qla2xxx/qla_dbg.h uint32_t version; uint32_t 278 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fw_major_version; uint32_t 279 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fw_minor_version; uint32_t 280 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fw_subminor_version; uint32_t 281 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fw_attributes; uint32_t 283 drivers/scsi/qla2xxx/qla_dbg.h uint32_t vendor; uint32_t 284 drivers/scsi/qla2xxx/qla_dbg.h uint32_t device; uint32_t 285 drivers/scsi/qla2xxx/qla_dbg.h uint32_t subsystem_vendor; uint32_t 286 drivers/scsi/qla2xxx/qla_dbg.h uint32_t subsystem_device; uint32_t 288 drivers/scsi/qla2xxx/qla_dbg.h uint32_t fixed_size; uint32_t 289 drivers/scsi/qla2xxx/qla_dbg.h uint32_t mem_size; uint32_t 290 drivers/scsi/qla2xxx/qla_dbg.h uint32_t req_q_size; uint32_t 291 drivers/scsi/qla2xxx/qla_dbg.h uint32_t rsp_q_size; uint32_t 293 drivers/scsi/qla2xxx/qla_dbg.h uint32_t eft_size; uint32_t 294 drivers/scsi/qla2xxx/qla_dbg.h uint32_t eft_addr_l; uint32_t 295 drivers/scsi/qla2xxx/qla_dbg.h uint32_t eft_addr_h; uint32_t 297 drivers/scsi/qla2xxx/qla_dbg.h uint32_t header_size; uint32_t 328 drivers/scsi/qla2xxx/qla_dbg.h ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...); uint32_t 337 drivers/scsi/qla2xxx/qla_dbg.h ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...); uint32_t 370 drivers/scsi/qla2xxx/qla_dbg.h extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *, uint32_t 371 drivers/scsi/qla2xxx/qla_dbg.h uint32_t, void **); uint32_t 372 drivers/scsi/qla2xxx/qla_dbg.h extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *, uint32_t 373 drivers/scsi/qla2xxx/qla_dbg.h uint32_t, void **); uint32_t 117 drivers/scsi/qla2xxx/qla_def.h #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) uint32_t 119 drivers/scsi/qla2xxx/qla_def.h #define LSD(x) ((uint32_t)((uint64_t)(x))) uint32_t 120 drivers/scsi/qla2xxx/qla_def.h #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) uint32_t 122 drivers/scsi/qla2xxx/qla_def.h #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) uint32_t 317 drivers/scsi/qla2xxx/qla_def.h uint32_t request_sense_length; uint32_t 318 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_sense_length; uint32_t 342 drivers/scsi/qla2xxx/qla_def.h uint32_t b24 : 24; uint32_t 452 drivers/scsi/qla2xxx/qla_def.h uint32_t flags; uint32_t 453 drivers/scsi/qla2xxx/qla_def.h uint32_t els_cmd; uint32_t 460 drivers/scsi/qla2xxx/qla_def.h uint32_t flags; uint32_t 461 drivers/scsi/qla2xxx/qla_def.h uint32_t els_cmd; uint32_t 469 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_status[3]; uint32_t 480 drivers/scsi/qla2xxx/qla_def.h uint32_t flags; uint32_t 481 drivers/scsi/qla2xxx/qla_def.h uint32_t data; uint32_t 492 drivers/scsi/qla2xxx/qla_def.h uint32_t req_len; uint32_t 493 drivers/scsi/qla2xxx/qla_def.h uint32_t rsp_len; uint32_t 511 drivers/scsi/qla2xxx/qla_def.h uint32_t cmd_hndl; uint32_t 542 drivers/scsi/qla2xxx/qla_def.h uint32_t dl; uint32_t 543 drivers/scsi/qla2xxx/qla_def.h uint32_t timeout_sec; uint32_t 604 drivers/scsi/qla2xxx/qla_def.h uint32_t handle; uint32_t 658 drivers/scsi/qla2xxx/qla_def.h uint32_t transfer_size; uint32_t 659 drivers/scsi/qla2xxx/qla_def.h uint32_t iteration_count; uint32_t 715 drivers/scsi/qla2xxx/qla_def.h uint32_t host_status; uint32_t 818 drivers/scsi/qla2xxx/qla_def.h uint32_t req_q_in; uint32_t 819 drivers/scsi/qla2xxx/qla_def.h uint32_t req_q_out; uint32_t 820 drivers/scsi/qla2xxx/qla_def.h uint32_t rsp_q_in; uint32_t 821 drivers/scsi/qla2xxx/qla_def.h uint32_t rsp_q_out; uint32_t 822 drivers/scsi/qla2xxx/qla_def.h uint32_t atio_q_in; uint32_t 823 drivers/scsi/qla2xxx/qla_def.h uint32_t atio_q_out; uint32_t 828 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox0; /* 00 */ uint32_t 829 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox1; /* 04 */ uint32_t 830 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox2; /* 08 */ uint32_t 831 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox3; /* 0C */ uint32_t 832 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox4; /* 10 */ uint32_t 833 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox5; /* 14 */ uint32_t 834 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox6; /* 18 */ uint32_t 835 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox7; /* 1C */ uint32_t 836 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox8; /* 20 */ uint32_t 837 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox9; /* 24 */ uint32_t 838 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox10; /* 28 */ uint32_t 839 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox11; uint32_t 840 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox12; uint32_t 841 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox13; uint32_t 842 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox14; uint32_t 843 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox15; uint32_t 844 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox16; uint32_t 845 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox17; uint32_t 846 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox18; uint32_t 847 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox19; uint32_t 848 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox20; uint32_t 849 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox21; uint32_t 850 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox22; uint32_t 851 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox23; uint32_t 852 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox24; uint32_t 853 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox25; uint32_t 854 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox26; uint32_t 855 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox27; uint32_t 856 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox28; uint32_t 857 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox29; uint32_t 858 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox30; uint32_t 859 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox31; uint32_t 860 drivers/scsi/qla2xxx/qla_def.h uint32_t aenmailbox0; uint32_t 861 drivers/scsi/qla2xxx/qla_def.h uint32_t aenmailbox1; uint32_t 862 drivers/scsi/qla2xxx/qla_def.h uint32_t aenmailbox2; uint32_t 863 drivers/scsi/qla2xxx/qla_def.h uint32_t aenmailbox3; uint32_t 864 drivers/scsi/qla2xxx/qla_def.h uint32_t aenmailbox4; uint32_t 865 drivers/scsi/qla2xxx/qla_def.h uint32_t aenmailbox5; uint32_t 866 drivers/scsi/qla2xxx/qla_def.h uint32_t aenmailbox6; uint32_t 867 drivers/scsi/qla2xxx/qla_def.h uint32_t aenmailbox7; uint32_t 869 drivers/scsi/qla2xxx/qla_def.h uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ uint32_t 870 drivers/scsi/qla2xxx/qla_def.h uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ uint32_t 872 drivers/scsi/qla2xxx/qla_def.h uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ uint32_t 873 drivers/scsi/qla2xxx/qla_def.h uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ uint32_t 875 drivers/scsi/qla2xxx/qla_def.h uint32_t initval0; /* B0 */ uint32_t 876 drivers/scsi/qla2xxx/qla_def.h uint32_t initval1; /* B4 */ uint32_t 877 drivers/scsi/qla2xxx/qla_def.h uint32_t initval2; /* B8 */ uint32_t 878 drivers/scsi/qla2xxx/qla_def.h uint32_t initval3; /* BC */ uint32_t 879 drivers/scsi/qla2xxx/qla_def.h uint32_t initval4; /* C0 */ uint32_t 880 drivers/scsi/qla2xxx/qla_def.h uint32_t initval5; /* C4 */ uint32_t 881 drivers/scsi/qla2xxx/qla_def.h uint32_t initval6; /* C8 */ uint32_t 882 drivers/scsi/qla2xxx/qla_def.h uint32_t initval7; /* CC */ uint32_t 883 drivers/scsi/qla2xxx/qla_def.h uint32_t fwheartbeat; /* D0 */ uint32_t 884 drivers/scsi/qla2xxx/qla_def.h uint32_t pseudoaen; /* D4 */ uint32_t 938 drivers/scsi/qla2xxx/qla_def.h uint32_t out_mb; /* outbound from driver */ uint32_t 939 drivers/scsi/qla2xxx/qla_def.h uint32_t in_mb; /* Incoming from RISC */ uint32_t 943 drivers/scsi/qla2xxx/qla_def.h uint32_t tov; uint32_t 951 drivers/scsi/qla2xxx/qla_def.h uint32_t out_mb; /* outbound from driver */ uint32_t 952 drivers/scsi/qla2xxx/qla_def.h uint32_t in_mb; /* Incoming from RISC */ uint32_t 953 drivers/scsi/qla2xxx/qla_def.h uint32_t mb[MAILBOX_REGISTER_COUNT]; uint32_t 956 drivers/scsi/qla2xxx/qla_def.h uint32_t tov; uint32_t 1477 drivers/scsi/qla2xxx/qla_def.h uint32_t link_fail_cnt; uint32_t 1478 drivers/scsi/qla2xxx/qla_def.h uint32_t loss_sync_cnt; uint32_t 1479 drivers/scsi/qla2xxx/qla_def.h uint32_t loss_sig_cnt; uint32_t 1480 drivers/scsi/qla2xxx/qla_def.h uint32_t prim_seq_err_cnt; uint32_t 1481 drivers/scsi/qla2xxx/qla_def.h uint32_t inval_xmit_word_cnt; uint32_t 1482 drivers/scsi/qla2xxx/qla_def.h uint32_t inval_crc_cnt; uint32_t 1483 drivers/scsi/qla2xxx/qla_def.h uint32_t lip_cnt; uint32_t 1484 drivers/scsi/qla2xxx/qla_def.h uint32_t link_up_cnt; uint32_t 1485 drivers/scsi/qla2xxx/qla_def.h uint32_t link_down_loop_init_tmo; uint32_t 1486 drivers/scsi/qla2xxx/qla_def.h uint32_t link_down_los; uint32_t 1487 drivers/scsi/qla2xxx/qla_def.h uint32_t link_down_loss_rcv_clk; uint32_t 1488 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved0[5]; uint32_t 1489 drivers/scsi/qla2xxx/qla_def.h uint32_t port_cfg_chg; uint32_t 1490 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved1[11]; uint32_t 1491 drivers/scsi/qla2xxx/qla_def.h uint32_t rsp_q_full; uint32_t 1492 drivers/scsi/qla2xxx/qla_def.h uint32_t atio_q_full; uint32_t 1493 drivers/scsi/qla2xxx/qla_def.h uint32_t drop_ae; uint32_t 1494 drivers/scsi/qla2xxx/qla_def.h uint32_t els_proto_err; uint32_t 1495 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved2; uint32_t 1496 drivers/scsi/qla2xxx/qla_def.h uint32_t tx_frames; uint32_t 1497 drivers/scsi/qla2xxx/qla_def.h uint32_t rx_frames; uint32_t 1498 drivers/scsi/qla2xxx/qla_def.h uint32_t discarded_frames; uint32_t 1499 drivers/scsi/qla2xxx/qla_def.h uint32_t dropped_frames; uint32_t 1500 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved3; uint32_t 1501 drivers/scsi/qla2xxx/qla_def.h uint32_t nos_rcvd; uint32_t 1502 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved4[4]; uint32_t 1503 drivers/scsi/qla2xxx/qla_def.h uint32_t tx_prjt; uint32_t 1504 drivers/scsi/qla2xxx/qla_def.h uint32_t rcv_exfail; uint32_t 1505 drivers/scsi/qla2xxx/qla_def.h uint32_t rcv_abts; uint32_t 1506 drivers/scsi/qla2xxx/qla_def.h uint32_t seq_frm_miss; uint32_t 1507 drivers/scsi/qla2xxx/qla_def.h uint32_t corr_err; uint32_t 1508 drivers/scsi/qla2xxx/qla_def.h uint32_t mb_rqst; uint32_t 1509 drivers/scsi/qla2xxx/qla_def.h uint32_t nport_full; uint32_t 1510 drivers/scsi/qla2xxx/qla_def.h uint32_t eofa; uint32_t 1511 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved5; uint32_t 1512 drivers/scsi/qla2xxx/qla_def.h uint32_t fpm_recv_word_cnt_lo; uint32_t 1513 drivers/scsi/qla2xxx/qla_def.h uint32_t fpm_recv_word_cnt_hi; uint32_t 1514 drivers/scsi/qla2xxx/qla_def.h uint32_t fpm_disc_word_cnt_lo; uint32_t 1515 drivers/scsi/qla2xxx/qla_def.h uint32_t fpm_disc_word_cnt_hi; uint32_t 1516 drivers/scsi/qla2xxx/qla_def.h uint32_t fpm_xmit_word_cnt_lo; uint32_t 1517 drivers/scsi/qla2xxx/qla_def.h uint32_t fpm_xmit_word_cnt_hi; uint32_t 1518 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved6[70]; uint32_t 1782 drivers/scsi/qla2xxx/qla_def.h uint32_t handle; /* System defined handle */ uint32_t 1784 drivers/scsi/qla2xxx/qla_def.h uint32_t signature; uint32_t 1796 drivers/scsi/qla2xxx/qla_def.h uint32_t signature; uint32_t 1825 drivers/scsi/qla2xxx/qla_def.h uint32_t handle; /* System handle. */ uint32_t 1838 drivers/scsi/qla2xxx/qla_def.h uint32_t byte_count; /* Total byte count. */ uint32_t 1854 drivers/scsi/qla2xxx/qla_def.h uint32_t handle; /* System handle. */ uint32_t 1862 drivers/scsi/qla2xxx/qla_def.h uint32_t byte_count; /* Total byte count. */ uint32_t 1875 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved; uint32_t 1914 drivers/scsi/qla2xxx/qla_def.h uint32_t handle; /* System handle. */ uint32_t 1928 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved_1; uint32_t 1931 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved_4; uint32_t 1933 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved_5[2]; uint32_t 1934 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved_6; uint32_t 1941 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved_2; uint32_t 1974 drivers/scsi/qla2xxx/qla_def.h uint32_t handle; /* System handle. */ uint32_t 1981 drivers/scsi/qla2xxx/qla_def.h uint32_t residual_length; /* Residual transfer length. */ uint32_t 2078 drivers/scsi/qla2xxx/qla_def.h uint32_t handle[15]; /* System handles. */ uint32_t 2103 drivers/scsi/qla2xxx/qla_def.h uint32_t sys_define_2; /* System defined. */ uint32_t 2127 drivers/scsi/qla2xxx/qla_def.h uint32_t handle1; /* System handle. */ uint32_t 2139 drivers/scsi/qla2xxx/qla_def.h uint32_t handle2; uint32_t 2140 drivers/scsi/qla2xxx/qla_def.h uint32_t rsp_bytecount; uint32_t 2141 drivers/scsi/qla2xxx/qla_def.h uint32_t req_bytecount; uint32_t 2166 drivers/scsi/qla2xxx/qla_def.h uint32_t handle; uint32_t 2173 drivers/scsi/qla2xxx/qla_def.h uint32_t sys_define2[2]; uint32_t 2183 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved_2[2]; uint32_t 2204 drivers/scsi/qla2xxx/qla_def.h uint32_t sys_define_2; /* System defined. */ uint32_t 2214 drivers/scsi/qla2xxx/qla_def.h uint32_t srr_rel_offs; uint32_t 2223 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved; uint32_t 2233 drivers/scsi/qla2xxx/qla_def.h uint32_t exchange_address; uint32_t 2234 drivers/scsi/qla2xxx/qla_def.h uint32_t srr_rel_offs; uint32_t 2256 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved_5; uint32_t 2299 drivers/scsi/qla2xxx/qla_def.h uint32_t handle; uint32_t 2408 drivers/scsi/qla2xxx/qla_def.h uint32_t nvme_prli_service_param; uint32_t 2415 drivers/scsi/qla2xxx/qla_def.h uint32_t nvme_first_burst_size; uint32_t 2447 drivers/scsi/qla2xxx/qla_def.h uint32_t flags; uint32_t 2644 drivers/scsi/qla2xxx/qla_def.h uint32_t max_ct_len; uint32_t 2649 drivers/scsi/qla2xxx/qla_def.h uint32_t count; uint32_t 2667 drivers/scsi/qla2xxx/qla_def.h uint32_t max_ct_len; uint32_t 2669 drivers/scsi/qla2xxx/qla_def.h uint32_t vendor_id; uint32_t 2670 drivers/scsi/qla2xxx/qla_def.h uint32_t num_ports; uint32_t 2678 drivers/scsi/qla2xxx/qla_def.h uint32_t count; uint32_t 2723 drivers/scsi/qla2xxx/qla_def.h uint32_t sup_speed; uint32_t 2724 drivers/scsi/qla2xxx/qla_def.h uint32_t cur_speed; uint32_t 2725 drivers/scsi/qla2xxx/qla_def.h uint32_t max_frame_size; uint32_t 2731 drivers/scsi/qla2xxx/qla_def.h uint32_t port_type; uint32_t 2732 drivers/scsi/qla2xxx/qla_def.h uint32_t port_supported_cos; uint32_t 2735 drivers/scsi/qla2xxx/qla_def.h uint32_t port_state; uint32_t 2736 drivers/scsi/qla2xxx/qla_def.h uint32_t num_ports; uint32_t 2737 drivers/scsi/qla2xxx/qla_def.h uint32_t port_id; uint32_t 2745 drivers/scsi/qla2xxx/qla_def.h uint32_t count; uint32_t 2754 drivers/scsi/qla2xxx/qla_def.h uint32_t sup_speed; uint32_t 2755 drivers/scsi/qla2xxx/qla_def.h uint32_t cur_speed; uint32_t 2756 drivers/scsi/qla2xxx/qla_def.h uint32_t max_frame_size; uint32_t 2763 drivers/scsi/qla2xxx/qla_def.h uint32_t count; uint32_t 2861 drivers/scsi/qla2xxx/qla_def.h uint32_t entry_count; uint32_t 2868 drivers/scsi/qla2xxx/qla_def.h uint32_t entry_count; uint32_t 2998 drivers/scsi/qla2xxx/qla_def.h uint32_t entry_count; uint32_t 3106 drivers/scsi/qla2xxx/qla_def.h uint32_t reserved_3; uint32_t 3121 drivers/scsi/qla2xxx/qla_def.h uint32_t segs[4]; uint32_t 3149 drivers/scsi/qla2xxx/qla_def.h uint32_t options; uint32_t 3177 drivers/scsi/qla2xxx/qla_def.h int (*load_risc) (struct scsi_qla_host *, uint32_t *); uint32_t 3197 drivers/scsi/qla2xxx/qla_def.h void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, uint32_t 3198 drivers/scsi/qla2xxx/qla_def.h uint32_t); uint32_t 3201 drivers/scsi/qla2xxx/qla_def.h uint32_t, uint32_t); uint32_t 3202 drivers/scsi/qla2xxx/qla_def.h int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, uint32_t 3203 drivers/scsi/qla2xxx/qla_def.h uint32_t); uint32_t 3212 drivers/scsi/qla2xxx/qla_def.h uint32_t, uint32_t); uint32_t 3213 drivers/scsi/qla2xxx/qla_def.h int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, uint32_t 3214 drivers/scsi/qla2xxx/qla_def.h uint32_t); uint32_t 3248 drivers/scsi/qla2xxx/qla_def.h uint32_t vector; uint32_t 3314 drivers/scsi/qla2xxx/qla_def.h uint32_t evtcode; uint32_t 3315 drivers/scsi/qla2xxx/qla_def.h uint32_t mbx[8]; uint32_t 3316 drivers/scsi/qla2xxx/qla_def.h uint32_t count; uint32_t 3354 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_update; uint32_t 3355 drivers/scsi/qla2xxx/qla_def.h uint32_t op_fw_version; uint32_t 3356 drivers/scsi/qla2xxx/qla_def.h uint32_t op_fw_size; uint32_t 3357 drivers/scsi/qla2xxx/qla_def.h uint32_t op_fw_seq_size; uint32_t 3358 drivers/scsi/qla2xxx/qla_def.h uint32_t diag_fw_version; uint32_t 3359 drivers/scsi/qla2xxx/qla_def.h uint32_t gold_fw_version; uint32_t 3367 drivers/scsi/qla2xxx/qla_def.h uint32_t dif_guard_err; uint32_t 3368 drivers/scsi/qla2xxx/qla_def.h uint32_t dif_ref_tag_err; uint32_t 3369 drivers/scsi/qla2xxx/qla_def.h uint32_t dif_app_tag_err; uint32_t 3373 drivers/scsi/qla2xxx/qla_def.h uint32_t total_isp_aborts; uint32_t 3378 drivers/scsi/qla2xxx/qla_def.h uint32_t control_requests; uint32_t 3381 drivers/scsi/qla2xxx/qla_def.h uint32_t stat_max_pend_cmds; uint32_t 3382 drivers/scsi/qla2xxx/qla_def.h uint32_t stat_max_qfull_cmds_alloc; uint32_t 3383 drivers/scsi/qla2xxx/qla_def.h uint32_t stat_max_qfull_cmds_dropped; uint32_t 3395 drivers/scsi/qla2xxx/qla_def.h uint32_t blk_sz; uint32_t 3396 drivers/scsi/qla2xxx/qla_def.h uint32_t bufflen; uint32_t 3439 drivers/scsi/qla2xxx/qla_def.h uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ uint32_t 3440 drivers/scsi/qla2xxx/qla_def.h uint32_t __iomem *rsp_q_out; uint32_t 3466 drivers/scsi/qla2xxx/qla_def.h uint32_t __iomem *req_q_in; /* FWI2-capable only. */ uint32_t 3467 drivers/scsi/qla2xxx/qla_def.h uint32_t __iomem *req_q_out; uint32_t 3480 drivers/scsi/qla2xxx/qla_def.h uint32_t current_outstanding_cmd; uint32_t 3494 drivers/scsi/qla2xxx/qla_def.h uint32_t lun_cnt; uint32_t 3508 drivers/scsi/qla2xxx/qla_def.h uint32_t online:1; uint32_t 3510 drivers/scsi/qla2xxx/qla_def.h uint32_t difdix_supported:1; uint32_t 3511 drivers/scsi/qla2xxx/qla_def.h uint32_t delete_in_progress:1; uint32_t 3512 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_started:1; uint32_t 3513 drivers/scsi/qla2xxx/qla_def.h uint32_t enable_class_2:1; uint32_t 3514 drivers/scsi/qla2xxx/qla_def.h uint32_t enable_explicit_conf:1; uint32_t 3515 drivers/scsi/qla2xxx/qla_def.h uint32_t use_shadow_reg:1; uint32_t 3535 drivers/scsi/qla2xxx/qla_def.h uint32_t retry_term_exchg_addr; uint32_t 3544 drivers/scsi/qla2xxx/qla_def.h uint32_t len; uint32_t 3556 drivers/scsi/qla2xxx/qla_def.h uint32_t node_name_set:1; uint32_t 3563 drivers/scsi/qla2xxx/qla_def.h uint32_t __iomem *atio_q_in; uint32_t 3564 drivers/scsi/qla2xxx/qla_def.h uint32_t __iomem *atio_q_out; uint32_t 3571 drivers/scsi/qla2xxx/qla_def.h uint32_t saved_firmware_options_1; uint32_t 3572 drivers/scsi/qla2xxx/qla_def.h uint32_t saved_firmware_options_2; uint32_t 3573 drivers/scsi/qla2xxx/qla_def.h uint32_t saved_firmware_options_3; uint32_t 3584 drivers/scsi/qla2xxx/qla_def.h uint32_t num_pend_cmds; uint32_t 3585 drivers/scsi/qla2xxx/qla_def.h uint32_t num_qfull_cmds_alloc; uint32_t 3586 drivers/scsi/qla2xxx/qla_def.h uint32_t num_qfull_cmds_dropped; uint32_t 3588 drivers/scsi/qla2xxx/qla_def.h uint32_t leak_exchg_thresh_hold; uint32_t 3613 drivers/scsi/qla2xxx/qla_def.h uint32_t mbox_int :1; uint32_t 3614 drivers/scsi/qla2xxx/qla_def.h uint32_t mbox_busy :1; uint32_t 3615 drivers/scsi/qla2xxx/qla_def.h uint32_t disable_risc_code_load :1; uint32_t 3616 drivers/scsi/qla2xxx/qla_def.h uint32_t enable_64bit_addressing :1; uint32_t 3617 drivers/scsi/qla2xxx/qla_def.h uint32_t enable_lip_reset :1; uint32_t 3618 drivers/scsi/qla2xxx/qla_def.h uint32_t enable_target_reset :1; uint32_t 3619 drivers/scsi/qla2xxx/qla_def.h uint32_t enable_lip_full_login :1; uint32_t 3620 drivers/scsi/qla2xxx/qla_def.h uint32_t enable_led_scheme :1; uint32_t 3622 drivers/scsi/qla2xxx/qla_def.h uint32_t msi_enabled :1; uint32_t 3623 drivers/scsi/qla2xxx/qla_def.h uint32_t msix_enabled :1; uint32_t 3624 drivers/scsi/qla2xxx/qla_def.h uint32_t disable_serdes :1; uint32_t 3625 drivers/scsi/qla2xxx/qla_def.h uint32_t gpsc_supported :1; uint32_t 3626 drivers/scsi/qla2xxx/qla_def.h uint32_t npiv_supported :1; uint32_t 3627 drivers/scsi/qla2xxx/qla_def.h uint32_t pci_channel_io_perm_failure :1; uint32_t 3628 drivers/scsi/qla2xxx/qla_def.h uint32_t fce_enabled :1; uint32_t 3629 drivers/scsi/qla2xxx/qla_def.h uint32_t fac_supported :1; uint32_t 3631 drivers/scsi/qla2xxx/qla_def.h uint32_t chip_reset_done :1; uint32_t 3632 drivers/scsi/qla2xxx/qla_def.h uint32_t running_gold_fw :1; uint32_t 3633 drivers/scsi/qla2xxx/qla_def.h uint32_t eeh_busy :1; uint32_t 3634 drivers/scsi/qla2xxx/qla_def.h uint32_t disable_msix_handshake :1; uint32_t 3635 drivers/scsi/qla2xxx/qla_def.h uint32_t fcp_prio_enabled :1; uint32_t 3636 drivers/scsi/qla2xxx/qla_def.h uint32_t isp82xx_fw_hung:1; uint32_t 3637 drivers/scsi/qla2xxx/qla_def.h uint32_t nic_core_hung:1; uint32_t 3639 drivers/scsi/qla2xxx/qla_def.h uint32_t quiesce_owner:1; uint32_t 3640 drivers/scsi/qla2xxx/qla_def.h uint32_t nic_core_reset_hdlr_active:1; uint32_t 3641 drivers/scsi/qla2xxx/qla_def.h uint32_t nic_core_reset_owner:1; uint32_t 3642 drivers/scsi/qla2xxx/qla_def.h uint32_t isp82xx_no_md_cap:1; uint32_t 3643 drivers/scsi/qla2xxx/qla_def.h uint32_t host_shutting_down:1; uint32_t 3644 drivers/scsi/qla2xxx/qla_def.h uint32_t idc_compl_status:1; uint32_t 3645 drivers/scsi/qla2xxx/qla_def.h uint32_t mr_reset_hdlr_active:1; uint32_t 3646 drivers/scsi/qla2xxx/qla_def.h uint32_t mr_intr_valid:1; uint32_t 3648 drivers/scsi/qla2xxx/qla_def.h uint32_t dport_enabled:1; uint32_t 3649 drivers/scsi/qla2xxx/qla_def.h uint32_t fawwpn_enabled:1; uint32_t 3650 drivers/scsi/qla2xxx/qla_def.h uint32_t exlogins_enabled:1; uint32_t 3651 drivers/scsi/qla2xxx/qla_def.h uint32_t exchoffld_enabled:1; uint32_t 3653 drivers/scsi/qla2xxx/qla_def.h uint32_t lip_ae:1; uint32_t 3654 drivers/scsi/qla2xxx/qla_def.h uint32_t n2n_ae:1; uint32_t 3655 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_started:1; uint32_t 3656 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_init_done:1; uint32_t 3658 drivers/scsi/qla2xxx/qla_def.h uint32_t detected_lr_sfp:1; uint32_t 3659 drivers/scsi/qla2xxx/qla_def.h uint32_t using_lr_setting:1; uint32_t 3660 drivers/scsi/qla2xxx/qla_def.h uint32_t rida_fmt2:1; uint32_t 3661 drivers/scsi/qla2xxx/qla_def.h uint32_t purge_mbox:1; uint32_t 3662 drivers/scsi/qla2xxx/qla_def.h uint32_t n2n_bigger:1; uint32_t 3663 drivers/scsi/qla2xxx/qla_def.h uint32_t secure_adapter:1; uint32_t 3664 drivers/scsi/qla2xxx/qla_def.h uint32_t secure_fw:1; uint32_t 3693 drivers/scsi/qla2xxx/qla_def.h uint32_t rqstq_intr_code; uint32_t 3694 drivers/scsi/qla2xxx/qla_def.h uint32_t mbx_intr_code; uint32_t 3695 drivers/scsi/qla2xxx/qla_def.h uint32_t req_que_len; uint32_t 3696 drivers/scsi/qla2xxx/qla_def.h uint32_t rsp_que_len; uint32_t 3697 drivers/scsi/qla2xxx/qla_def.h uint32_t req_que_off; uint32_t 3698 drivers/scsi/qla2xxx/qla_def.h uint32_t rsp_que_off; uint32_t 3765 drivers/scsi/qla2xxx/qla_def.h uint32_t isp_abort_cnt; uint32_t 3780 drivers/scsi/qla2xxx/qla_def.h uint32_t isp_type; uint32_t 3810 drivers/scsi/qla2xxx/qla_def.h uint32_t device_type; uint32_t 3938 drivers/scsi/qla2xxx/qla_def.h uint32_t login_retry_count; uint32_t 4006 drivers/scsi/qla2xxx/qla_def.h uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; uint32_t 4007 drivers/scsi/qla2xxx/qla_def.h uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; uint32_t 4043 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_memory_size; uint32_t 4044 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_transfer_size; uint32_t 4045 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_srisc_address; uint32_t 4058 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_shared_ram_start; uint32_t 4059 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_shared_ram_end; uint32_t 4060 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_ddr_ram_start; uint32_t 4061 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_ddr_ram_end; uint32_t 4069 drivers/scsi/qla2xxx/qla_def.h uint32_t mpi_capabilities; uint32_t 4080 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_dump_len; uint32_t 4103 drivers/scsi/qla2xxx/qla_def.h uint32_t chain_offset; uint32_t 4111 drivers/scsi/qla2xxx/qla_def.h uint32_t fce_bufs; uint32_t 4116 drivers/scsi/qla2xxx/qla_def.h uint32_t pci_attr; uint32_t 4127 drivers/scsi/qla2xxx/qla_def.h uint32_t optrom_size; uint32_t 4132 drivers/scsi/qla2xxx/qla_def.h uint32_t optrom_region_start; uint32_t 4133 drivers/scsi/qla2xxx/qla_def.h uint32_t optrom_region_size; uint32_t 4143 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_revision[4]; uint32_t 4145 drivers/scsi/qla2xxx/qla_def.h uint32_t gold_fw_version[4]; uint32_t 4148 drivers/scsi/qla2xxx/qla_def.h uint32_t flash_conf_off; uint32_t 4149 drivers/scsi/qla2xxx/qla_def.h uint32_t flash_data_off; uint32_t 4150 drivers/scsi/qla2xxx/qla_def.h uint32_t nvram_conf_off; uint32_t 4151 drivers/scsi/qla2xxx/qla_def.h uint32_t nvram_data_off; uint32_t 4153 drivers/scsi/qla2xxx/qla_def.h uint32_t fdt_wrt_disable; uint32_t 4154 drivers/scsi/qla2xxx/qla_def.h uint32_t fdt_wrt_enable; uint32_t 4155 drivers/scsi/qla2xxx/qla_def.h uint32_t fdt_erase_cmd; uint32_t 4156 drivers/scsi/qla2xxx/qla_def.h uint32_t fdt_block_size; uint32_t 4157 drivers/scsi/qla2xxx/qla_def.h uint32_t fdt_unprotect_sec_cmd; uint32_t 4158 drivers/scsi/qla2xxx/qla_def.h uint32_t fdt_protect_sec_cmd; uint32_t 4159 drivers/scsi/qla2xxx/qla_def.h uint32_t fdt_wrt_sts_reg_cmd; uint32_t 4162 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_flt; uint32_t 4163 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_fdt; uint32_t 4164 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_boot; uint32_t 4165 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_boot_sec; uint32_t 4166 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_fw; uint32_t 4167 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_fw_sec; uint32_t 4168 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_vpd_nvram; uint32_t 4169 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_vpd_nvram_sec; uint32_t 4170 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_vpd; uint32_t 4171 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_vpd_sec; uint32_t 4172 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_nvram; uint32_t 4173 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_nvram_sec; uint32_t 4174 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_npiv_conf; uint32_t 4175 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_gold_fw; uint32_t 4176 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_fcp_prio; uint32_t 4177 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_bootload; uint32_t 4178 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_img_status_pri; uint32_t 4179 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_img_status_sec; uint32_t 4180 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_aux_img_status_pri; uint32_t 4181 drivers/scsi/qla2xxx/qla_def.h uint32_t flt_region_aux_img_status_sec; uint32_t 4225 drivers/scsi/qla2xxx/qla_def.h uint32_t crb_win; uint32_t 4226 drivers/scsi/qla2xxx/qla_def.h uint32_t curr_window; uint32_t 4227 drivers/scsi/qla2xxx/qla_def.h uint32_t ddr_mn_window; uint32_t 4231 drivers/scsi/qla2xxx/qla_def.h uint32_t fcoe_dev_init_timeout; uint32_t 4232 drivers/scsi/qla2xxx/qla_def.h uint32_t fcoe_reset_timeout; uint32_t 4247 drivers/scsi/qla2xxx/qla_def.h uint32_t md_template_size; uint32_t 4251 drivers/scsi/qla2xxx/qla_def.h uint32_t md_dump_size; uint32_t 4256 drivers/scsi/qla2xxx/qla_def.h uint32_t idc_audit_ts; uint32_t 4257 drivers/scsi/qla2xxx/qla_def.h uint32_t idc_extend_tmo; uint32_t 4270 drivers/scsi/qla2xxx/qla_def.h uint32_t chip_reset; uint32_t 4274 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_ability_mask; uint32_t 4343 drivers/scsi/qla2xxx/qla_def.h uint32_t init_done :1; uint32_t 4344 drivers/scsi/qla2xxx/qla_def.h uint32_t online :1; uint32_t 4345 drivers/scsi/qla2xxx/qla_def.h uint32_t reset_active :1; uint32_t 4347 drivers/scsi/qla2xxx/qla_def.h uint32_t management_server_logged_in :1; uint32_t 4348 drivers/scsi/qla2xxx/qla_def.h uint32_t process_response_queue :1; uint32_t 4349 drivers/scsi/qla2xxx/qla_def.h uint32_t difdix_supported:1; uint32_t 4350 drivers/scsi/qla2xxx/qla_def.h uint32_t delete_progress:1; uint32_t 4352 drivers/scsi/qla2xxx/qla_def.h uint32_t fw_tgt_reported:1; uint32_t 4353 drivers/scsi/qla2xxx/qla_def.h uint32_t bbcr_enable:1; uint32_t 4354 drivers/scsi/qla2xxx/qla_def.h uint32_t qpairs_available:1; uint32_t 4355 drivers/scsi/qla2xxx/qla_def.h uint32_t qpairs_req_created:1; uint32_t 4356 drivers/scsi/qla2xxx/qla_def.h uint32_t qpairs_rsp_created:1; uint32_t 4357 drivers/scsi/qla2xxx/qla_def.h uint32_t nvme_enabled:1; uint32_t 4358 drivers/scsi/qla2xxx/qla_def.h uint32_t nvme_first_burst:1; uint32_t 4412 drivers/scsi/qla2xxx/qla_def.h uint32_t device_flags; uint32_t 4438 drivers/scsi/qla2xxx/qla_def.h uint32_t timer_active; uint32_t 4470 drivers/scsi/qla2xxx/qla_def.h uint32_t vp_abort_cnt; uint32_t 4536 drivers/scsi/qla2xxx/qla_def.h uint32_t checksum; uint32_t 4537 drivers/scsi/qla2xxx/qla_def.h uint32_t signature; uint32_t 4557 drivers/scsi/qla2xxx/qla_def.h uint32_t dma_len; /* OUT */ uint32_t 4559 drivers/scsi/qla2xxx/qla_def.h uint32_t tot_bytes; /* IN */ uint32_t 4563 drivers/scsi/qla2xxx/qla_def.h uint32_t bytes_consumed; uint32_t 4564 drivers/scsi/qla2xxx/qla_def.h uint32_t num_bytes; uint32_t 4565 drivers/scsi/qla2xxx/qla_def.h uint32_t tot_partial; uint32_t 4568 drivers/scsi/qla2xxx/qla_def.h uint32_t num_sg; uint32_t 4596 drivers/scsi/qla2xxx/qla_def.h uint32_t block_info; uint32_t 4597 drivers/scsi/qla2xxx/qla_def.h uint32_t signature_lo; uint32_t 4598 drivers/scsi/qla2xxx/qla_def.h uint32_t signature_hi; uint32_t 4599 drivers/scsi/qla2xxx/qla_def.h uint32_t signature_upper[0x3e]; uint32_t 4603 drivers/scsi/qla2xxx/qla_def.h uint32_t block_info; uint32_t 4604 drivers/scsi/qla2xxx/qla_def.h uint32_t signature_lo; uint32_t 4605 drivers/scsi/qla2xxx/qla_def.h uint32_t signature_hi; uint32_t 4606 drivers/scsi/qla2xxx/qla_def.h uint32_t signature_upper[0x3e]; uint32_t 4607 drivers/scsi/qla2xxx/qla_def.h uint32_t public_key[0x41]; uint32_t 267 drivers/scsi/qla2xxx/qla_dfs.c uint32_t cnt; uint32_t 268 drivers/scsi/qla2xxx/qla_dfs.c uint32_t *fce; uint32_t 282 drivers/scsi/qla2xxx/qla_dfs.c fce = (uint32_t *) ha->fce; uint32_t 153 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_1; uint32_t 154 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_2; uint32_t 155 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_3; uint32_t 218 drivers/scsi/qla2xxx/qla_fw.h uint32_t host_p; uint32_t 249 drivers/scsi/qla2xxx/qla_fw.h uint32_t efi_parameters; uint32_t 309 drivers/scsi/qla2xxx/qla_fw.h uint32_t checksum; uint32_t 378 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_1; uint32_t 399 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_2; uint32_t 425 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_3; uint32_t 441 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 462 drivers/scsi/qla2xxx/qla_fw.h uint32_t rd_byte_count; /* Total Byte count Read. */ uint32_t 463 drivers/scsi/qla2xxx/qla_fw.h uint32_t wr_byte_count; /* Total Byte count write. */ uint32_t 478 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 501 drivers/scsi/qla2xxx/qla_fw.h uint32_t byte_count; /* Total byte count. */ uint32_t 516 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 547 drivers/scsi/qla2xxx/qla_fw.h uint32_t byte_count; /* Total byte count. */ uint32_t 563 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 581 drivers/scsi/qla2xxx/qla_fw.h uint32_t byte_count; /* Total byte count. */ uint32_t 602 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 607 drivers/scsi/qla2xxx/qla_fw.h uint32_t residual_len; /* FW calc residual transfer length. */ uint32_t 623 drivers/scsi/qla2xxx/qla_fw.h uint32_t rsp_residual_count; /* FCP RSP residual count. */ uint32_t 625 drivers/scsi/qla2xxx/qla_fw.h uint32_t sense_len; /* FCP SENSE length. */ uint32_t 629 drivers/scsi/qla2xxx/qla_fw.h uint32_t rsp_data_len; /* FCP response data length */ uint32_t 670 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 699 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 717 drivers/scsi/qla2xxx/qla_fw.h uint32_t rsp_byte_count; uint32_t 718 drivers/scsi/qla2xxx/qla_fw.h uint32_t cmd_byte_count; uint32_t 733 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 746 drivers/scsi/qla2xxx/qla_fw.h uint32_t rx_xchg_address; /* Receive exchange address. */ uint32_t 779 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 790 drivers/scsi/qla2xxx/qla_fw.h uint32_t rx_xchg_address; /* Receive exchange address. */ uint32_t 802 drivers/scsi/qla2xxx/qla_fw.h uint32_t total_byte_count; uint32_t 803 drivers/scsi/qla2xxx/qla_fw.h uint32_t error_subcode_1; uint32_t 804 drivers/scsi/qla2xxx/qla_fw.h uint32_t error_subcode_2; uint32_t 816 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 829 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 865 drivers/scsi/qla2xxx/qla_fw.h uint32_t io_parameter[11]; /* General I/O parameters. */ uint32_t 891 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 903 drivers/scsi/qla2xxx/qla_fw.h uint32_t control_flags; /* Control Flags. */ uint32_t 926 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 934 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle_to_abort; /* System handle to abort. */ uint32_t 949 drivers/scsi/qla2xxx/qla_fw.h uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ uint32_t 1000 drivers/scsi/qla2xxx/qla_fw.h uint32_t flash_data; /* Flash/NVRAM BIOS data. */ uint32_t 1002 drivers/scsi/qla2xxx/qla_fw.h uint32_t ctrl_status; /* Control/Status. */ uint32_t 1028 drivers/scsi/qla2xxx/qla_fw.h uint32_t ictrl; /* Interrupt control. */ uint32_t 1031 drivers/scsi/qla2xxx/qla_fw.h uint32_t istatus; /* Interrupt status. */ uint32_t 1034 drivers/scsi/qla2xxx/qla_fw.h uint32_t unused_1[2]; /* Gap. */ uint32_t 1037 drivers/scsi/qla2xxx/qla_fw.h uint32_t req_q_in; /* In-Pointer. */ uint32_t 1038 drivers/scsi/qla2xxx/qla_fw.h uint32_t req_q_out; /* Out-Pointer. */ uint32_t 1040 drivers/scsi/qla2xxx/qla_fw.h uint32_t rsp_q_in; /* In-Pointer. */ uint32_t 1041 drivers/scsi/qla2xxx/qla_fw.h uint32_t rsp_q_out; /* Out-Pointer. */ uint32_t 1043 drivers/scsi/qla2xxx/qla_fw.h uint32_t preq_q_in; /* In-Pointer. */ uint32_t 1044 drivers/scsi/qla2xxx/qla_fw.h uint32_t preq_q_out; /* Out-Pointer. */ uint32_t 1046 drivers/scsi/qla2xxx/qla_fw.h uint32_t unused_2[2]; /* Gap. */ uint32_t 1049 drivers/scsi/qla2xxx/qla_fw.h uint32_t atio_q_in; /* In-Pointer. */ uint32_t 1050 drivers/scsi/qla2xxx/qla_fw.h uint32_t atio_q_out; /* Out-Pointer. */ uint32_t 1052 drivers/scsi/qla2xxx/qla_fw.h uint32_t host_status; uint32_t 1056 drivers/scsi/qla2xxx/qla_fw.h uint32_t hccr; /* Host command & control register. */ uint32_t 1078 drivers/scsi/qla2xxx/qla_fw.h uint32_t gpiod; /* GPIO Data register. */ uint32_t 1097 drivers/scsi/qla2xxx/qla_fw.h uint32_t gpioe; /* GPIO Enable register. */ uint32_t 1105 drivers/scsi/qla2xxx/qla_fw.h uint32_t iobase_addr; /* I/O Bus Base Address register. */ uint32_t 1107 drivers/scsi/qla2xxx/qla_fw.h uint32_t unused_3[10]; /* Gap. */ uint32_t 1142 drivers/scsi/qla2xxx/qla_fw.h uint32_t iobase_window; uint32_t 1143 drivers/scsi/qla2xxx/qla_fw.h uint32_t iobase_c4; uint32_t 1144 drivers/scsi/qla2xxx/qla_fw.h uint32_t iobase_c8; uint32_t 1145 drivers/scsi/qla2xxx/qla_fw.h uint32_t unused_4_1[6]; /* Gap. */ uint32_t 1146 drivers/scsi/qla2xxx/qla_fw.h uint32_t iobase_q; uint32_t 1147 drivers/scsi/qla2xxx/qla_fw.h uint32_t unused_5[2]; /* Gap. */ uint32_t 1148 drivers/scsi/qla2xxx/qla_fw.h uint32_t iobase_select; uint32_t 1149 drivers/scsi/qla2xxx/qla_fw.h uint32_t unused_6[2]; /* Gap. */ uint32_t 1150 drivers/scsi/qla2xxx/qla_fw.h uint32_t iobase_sdata; uint32_t 1249 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 1285 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 1348 drivers/scsi/qla2xxx/qla_fw.h uint32_t resv1; uint32_t 1398 drivers/scsi/qla2xxx/qla_fw.h uint32_t reserved_5; uint32_t 1410 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; /* System handle. */ uint32_t 1416 drivers/scsi/qla2xxx/qla_fw.h uint32_t exch_addr; uint32_t 1420 drivers/scsi/qla2xxx/qla_fw.h uint32_t io_parameter_0; uint32_t 1421 drivers/scsi/qla2xxx/qla_fw.h uint32_t io_parameter_1; uint32_t 1423 drivers/scsi/qla2xxx/qla_fw.h uint32_t tx_len; /* Data segment 0 length. */ uint32_t 1425 drivers/scsi/qla2xxx/qla_fw.h uint32_t rx_len; /* Data segment 1 length. */ uint32_t 1449 drivers/scsi/qla2xxx/qla_fw.h uint32_t block_size; uint32_t 1450 drivers/scsi/qla2xxx/qla_fw.h uint32_t alt_block_size; uint32_t 1451 drivers/scsi/qla2xxx/qla_fw.h uint32_t flash_size; uint32_t 1452 drivers/scsi/qla2xxx/qla_fw.h uint32_t wrt_enable_data; uint32_t 1535 drivers/scsi/qla2xxx/qla_fw.h uint32_t size; uint32_t 1536 drivers/scsi/qla2xxx/qla_fw.h uint32_t start; uint32_t 1537 drivers/scsi/qla2xxx/qla_fw.h uint32_t end; uint32_t 1587 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; uint32_t 1602 drivers/scsi/qla2xxx/qla_fw.h uint32_t fw_ver; uint32_t 1603 drivers/scsi/qla2xxx/qla_fw.h uint32_t exchange_address; uint32_t 1605 drivers/scsi/qla2xxx/qla_fw.h uint32_t reserved_3[3]; uint32_t 1606 drivers/scsi/qla2xxx/qla_fw.h uint32_t fw_size; uint32_t 1607 drivers/scsi/qla2xxx/qla_fw.h uint32_t fw_seq_size; uint32_t 1608 drivers/scsi/qla2xxx/qla_fw.h uint32_t relative_offset; uint32_t 1619 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; uint32_t 1633 drivers/scsi/qla2xxx/qla_fw.h uint32_t fw_ver; uint32_t 1634 drivers/scsi/qla2xxx/qla_fw.h uint32_t exchange_address; uint32_t 1636 drivers/scsi/qla2xxx/qla_fw.h uint32_t reserved_2[6]; uint32_t 1646 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; uint32_t 1659 drivers/scsi/qla2xxx/qla_fw.h uint32_t parameter1; uint32_t 1660 drivers/scsi/qla2xxx/qla_fw.h uint32_t parameter2; uint32_t 1661 drivers/scsi/qla2xxx/qla_fw.h uint32_t parameter3; uint32_t 1663 drivers/scsi/qla2xxx/qla_fw.h uint32_t reserved3[3]; uint32_t 1664 drivers/scsi/qla2xxx/qla_fw.h uint32_t total_byte_cnt; uint32_t 1665 drivers/scsi/qla2xxx/qla_fw.h uint32_t reserved4; uint32_t 1676 drivers/scsi/qla2xxx/qla_fw.h uint32_t handle; uint32_t 1680 drivers/scsi/qla2xxx/qla_fw.h uint32_t residual_count; uint32_t 1682 drivers/scsi/qla2xxx/qla_fw.h uint32_t reserved[12]; uint32_t 1757 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_1; uint32_t 1758 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_2; uint32_t 1759 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_3; uint32_t 1816 drivers/scsi/qla2xxx/qla_fw.h uint32_t host_p; uint32_t 1847 drivers/scsi/qla2xxx/qla_fw.h uint32_t efi_parameters; uint32_t 1900 drivers/scsi/qla2xxx/qla_fw.h uint32_t checksum; uint32_t 1959 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_1; uint32_t 1977 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_2; uint32_t 1998 drivers/scsi/qla2xxx/qla_fw.h uint32_t firmware_options_3; uint32_t 2052 drivers/scsi/qla2xxx/qla_fw.h uint32_t src_pid; /* Src port id. high order byte */ uint32_t 2054 drivers/scsi/qla2xxx/qla_fw.h uint32_t dst_pid; /* Src port id. high order byte */ uint32_t 35 drivers/scsi/qla2xxx/qla_gbl.h extern int qla2x00_load_risc(struct scsi_qla_host *, uint32_t *); uint32_t 36 drivers/scsi/qla2xxx/qla_gbl.h extern int qla24xx_load_risc(scsi_qla_host_t *, uint32_t *); uint32_t 37 drivers/scsi/qla2xxx/qla_gbl.h extern int qla81xx_load_risc(scsi_qla_host_t *, uint32_t *); uint32_t 72 drivers/scsi/qla2xxx/qla_gbl.h extern int qla2x00_async_tm_cmd(fc_port_t *, uint32_t, uint32_t, uint32_t); uint32_t 88 drivers/scsi/qla2xxx/qla_gbl.h extern int __qla83xx_set_idc_control(scsi_qla_host_t *, uint32_t); uint32_t 89 drivers/scsi/qla2xxx/qla_gbl.h extern int __qla83xx_get_idc_control(scsi_qla_host_t *, uint32_t *); uint32_t 131 drivers/scsi/qla2xxx/qla_gbl.h extern bool qla24xx_risc_firmware_invalid(uint32_t *); uint32_t 281 drivers/scsi/qla2xxx/qla_gbl.h extern uint32_t qla2xxx_get_next_handle(struct req_que *req); uint32_t 288 drivers/scsi/qla2xxx/qla_gbl.h extern int qla2x00_start_bidir(srb_t *, struct scsi_qla_host *, uint32_t); uint32_t 302 drivers/scsi/qla2xxx/qla_gbl.h extern int qla24xx_get_one_block_sg(uint32_t, struct qla2_sgx *, uint32_t *); uint32_t 309 drivers/scsi/qla2xxx/qla_gbl.h qla2x00_load_ram(scsi_qla_host_t *, dma_addr_t, uint32_t, uint32_t); uint32_t 312 drivers/scsi/qla2xxx/qla_gbl.h qla2x00_dump_ram(scsi_qla_host_t *, dma_addr_t, uint32_t, uint32_t); uint32_t 315 drivers/scsi/qla2xxx/qla_gbl.h qla2x00_execute_fw(scsi_qla_host_t *, uint32_t); uint32_t 330 drivers/scsi/qla2xxx/qla_gbl.h qla2x00_verify_checksum(scsi_qla_host_t *, uint32_t); uint32_t 427 drivers/scsi/qla2xxx/qla_gbl.h qla8044_write_serdes_word(scsi_qla_host_t *, uint32_t, uint32_t); uint32_t 429 drivers/scsi/qla2xxx/qla_gbl.h qla8044_read_serdes_word(scsi_qla_host_t *, uint32_t, uint32_t *); uint32_t 444 drivers/scsi/qla2xxx/qla_gbl.h uint32_t *); uint32_t 471 drivers/scsi/qla2xxx/qla_gbl.h qla81xx_fac_get_sector_size(scsi_qla_host_t *, uint32_t *); uint32_t 477 drivers/scsi/qla2xxx/qla_gbl.h qla81xx_fac_erase_sector(scsi_qla_host_t *, uint32_t, uint32_t); uint32_t 488 drivers/scsi/qla2xxx/qla_gbl.h qla2x00_read_ram_word(scsi_qla_host_t *, uint32_t, uint32_t *); uint32_t 491 drivers/scsi/qla2xxx/qla_gbl.h qla2x00_write_ram_word(scsi_qla_host_t *, uint32_t, uint32_t); uint32_t 508 drivers/scsi/qla2xxx/qla_gbl.h qla2x00_dump_mctp_data(scsi_qla_host_t *, dma_addr_t, uint32_t, uint32_t); uint32_t 527 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, dma_addr_t, uint32_t); uint32_t 529 drivers/scsi/qla2xxx/qla_gbl.h extern int qla2xxx_read_remote_register(scsi_qla_host_t *, uint32_t, uint32_t 530 drivers/scsi/qla2xxx/qla_gbl.h uint32_t *); uint32_t 531 drivers/scsi/qla2xxx/qla_gbl.h extern int qla2xxx_write_remote_register(scsi_qla_host_t *, uint32_t, uint32_t 532 drivers/scsi/qla2xxx/qla_gbl.h uint32_t); uint32_t 553 drivers/scsi/qla2xxx/qla_gbl.h uint32_t); uint32_t 564 drivers/scsi/qla2xxx/qla_gbl.h extern int qla24xx_read_flash_data(scsi_qla_host_t *, uint32_t *, uint32_t 565 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint32_t); uint32_t 566 drivers/scsi/qla2xxx/qla_gbl.h extern uint8_t *qla2x00_read_nvram_data(scsi_qla_host_t *, void *, uint32_t, uint32_t 567 drivers/scsi/qla2xxx/qla_gbl.h uint32_t); uint32_t 568 drivers/scsi/qla2xxx/qla_gbl.h extern uint8_t *qla24xx_read_nvram_data(scsi_qla_host_t *, void *, uint32_t, uint32_t 569 drivers/scsi/qla2xxx/qla_gbl.h uint32_t); uint32_t 570 drivers/scsi/qla2xxx/qla_gbl.h extern int qla2x00_write_nvram_data(scsi_qla_host_t *, void *, uint32_t, uint32_t 571 drivers/scsi/qla2xxx/qla_gbl.h uint32_t); uint32_t 572 drivers/scsi/qla2xxx/qla_gbl.h extern int qla24xx_write_nvram_data(scsi_qla_host_t *, void *, uint32_t, uint32_t 573 drivers/scsi/qla2xxx/qla_gbl.h uint32_t); uint32_t 574 drivers/scsi/qla2xxx/qla_gbl.h extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, void *, uint32_t, uint32_t 575 drivers/scsi/qla2xxx/qla_gbl.h uint32_t); uint32_t 576 drivers/scsi/qla2xxx/qla_gbl.h extern int qla25xx_write_nvram_data(scsi_qla_host_t *, void *, uint32_t, uint32_t 577 drivers/scsi/qla2xxx/qla_gbl.h uint32_t); uint32_t 579 drivers/scsi/qla2xxx/qla_gbl.h extern int qla2x00_is_a_vp_did(scsi_qla_host_t *, uint32_t); uint32_t 580 drivers/scsi/qla2xxx/qla_gbl.h bool qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *, uint32_t); uint32_t 592 drivers/scsi/qla2xxx/qla_gbl.h extern int qla83xx_wr_reg(scsi_qla_host_t *, uint32_t, uint32_t); uint32_t 593 drivers/scsi/qla2xxx/qla_gbl.h extern int qla83xx_rd_reg(scsi_qla_host_t *, uint32_t, uint32_t *); uint32_t 595 drivers/scsi/qla2xxx/qla_gbl.h extern int qla83xx_access_control(scsi_qla_host_t *, uint16_t, uint32_t, uint32_t 596 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint16_t *); uint32_t 599 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint32_t); uint32_t 601 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint32_t); uint32_t 603 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint32_t); uint32_t 605 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint32_t); uint32_t 607 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint32_t); uint32_t 609 drivers/scsi/qla2xxx/qla_gbl.h void *, uint32_t, uint32_t); uint32_t 655 drivers/scsi/qla2xxx/qla_gbl.h extern void *qla2x00_prep_ms_fdmi_iocb(scsi_qla_host_t *, uint32_t, uint32_t); uint32_t 656 drivers/scsi/qla2xxx/qla_gbl.h extern void *qla24xx_prep_ms_fdmi_iocb(scsi_qla_host_t *, uint32_t, uint32_t); uint32_t 759 drivers/scsi/qla2xxx/qla_gbl.h extern int qlafx00_post_aenfx_work(struct scsi_qla_host *, uint32_t, uint32_t 760 drivers/scsi/qla2xxx/qla_gbl.h uint32_t *, int); uint32_t 761 drivers/scsi/qla2xxx/qla_gbl.h extern uint32_t qlafx00_fw_state_show(struct device *, uint32_t 788 drivers/scsi/qla2xxx/qla_gbl.h extern int qla82xx_load_risc(scsi_qla_host_t *, uint32_t *); uint32_t 790 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint32_t); uint32_t 792 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint32_t); uint32_t 825 drivers/scsi/qla2xxx/qla_gbl.h extern uint32_t qla82xx_wait_for_state_change(scsi_qla_host_t *, uint32_t); uint32_t 843 drivers/scsi/qla2xxx/qla_gbl.h extern char *qdev_state(uint32_t); uint32_t 854 drivers/scsi/qla2xxx/qla_gbl.h dma_addr_t, size_t, uint32_t); uint32_t 874 drivers/scsi/qla2xxx/qla_gbl.h extern uint32_t qla8044_rd_reg(struct qla_hw_data *ha, ulong addr); uint32_t 875 drivers/scsi/qla2xxx/qla_gbl.h extern void qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val); uint32_t 878 drivers/scsi/qla2xxx/qla_gbl.h extern int qla8044_rd_direct(struct scsi_qla_host *vha, const uint32_t crb_reg); uint32_t 880 drivers/scsi/qla2xxx/qla_gbl.h const uint32_t crb_reg, const uint32_t value); uint32_t 888 drivers/scsi/qla2xxx/qla_gbl.h uint32_t, uint32_t); uint32_t 1400 drivers/scsi/qla2xxx/qla_gs.c qla2x00_prep_ms_fdmi_iocb(scsi_qla_host_t *vha, uint32_t req_size, uint32_t 1401 drivers/scsi/qla2xxx/qla_gs.c uint32_t rsp_size) uint32_t 1437 drivers/scsi/qla2xxx/qla_gs.c qla24xx_prep_ms_fdmi_iocb(scsi_qla_host_t *vha, uint32_t req_size, uint32_t 1438 drivers/scsi/qla2xxx/qla_gs.c uint32_t rsp_size) uint32_t 1466 drivers/scsi/qla2xxx/qla_gs.c qla2x00_update_ms_fdmi_iocb(scsi_qla_host_t *vha, uint32_t req_size) uint32_t 1514 drivers/scsi/qla2xxx/qla_gs.c uint32_t size, sn; uint32_t 1724 drivers/scsi/qla2xxx/qla_gs.c uint32_t size; uint32_t 1936 drivers/scsi/qla2xxx/qla_gs.c uint32_t size, sn; uint32_t 2297 drivers/scsi/qla2xxx/qla_gs.c uint32_t size; uint32_t 1781 drivers/scsi/qla2xxx/qla_init.c qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun, uint32_t 1782 drivers/scsi/qla2xxx/qla_init.c uint32_t tag) uint32_t 1845 drivers/scsi/qla2xxx/qla_init.c uint32_t handle; uint32_t 2095 drivers/scsi/qla2xxx/qla_init.c uint32_t idc_major_ver, idc_minor_ver; uint32_t 2355 drivers/scsi/qla2xxx/qla_init.c uint32_t cnt; uint32_t 2549 drivers/scsi/qla2xxx/qla_init.c uint32_t cnt; uint32_t 2713 drivers/scsi/qla2xxx/qla_init.c uint32_t cnt; uint32_t 2837 drivers/scsi/qla2xxx/qla_init.c qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) uint32_t 2847 drivers/scsi/qla2xxx/qla_init.c qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) uint32_t 2858 drivers/scsi/qla2xxx/qla_init.c uint32_t wd32 = 0; uint32_t 2957 drivers/scsi/qla2xxx/qla_init.c uint32_t cnt; uint32_t 3199 drivers/scsi/qla2xxx/qla_init.c uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, uint32_t 3226 drivers/scsi/qla2xxx/qla_init.c sizeof(uint32_t); uint32_t 3356 drivers/scsi/qla2xxx/qla_init.c uint32_t dw; uint32_t 3590 drivers/scsi/qla2xxx/qla_init.c uint32_t srisc_address = 0; uint32_t 3714 drivers/scsi/qla2xxx/qla_init.c uint32_t size; uint32_t 5059 drivers/scsi/qla2xxx/qla_init.c bp = (uint32_t *)ha->init_cb; uint32_t 6162 drivers/scsi/qla2xxx/qla_init.c uint32_t wait_time; uint32_t 6269 drivers/scsi/qla2xxx/qla_init.c uint32_t drv_presence, drv_presence_mask; uint32_t 6270 drivers/scsi/qla2xxx/qla_init.c uint32_t dev_part_info1, dev_part_info2, class_type; uint32_t 6271 drivers/scsi/qla2xxx/qla_init.c uint32_t class_type_mask = 0x3; uint32_t 6329 drivers/scsi/qla2xxx/qla_init.c uint32_t drv_ack; uint32_t 6345 drivers/scsi/qla2xxx/qla_init.c uint32_t drv_ack; uint32_t 6357 drivers/scsi/qla2xxx/qla_init.c qla83xx_dev_state_to_string(uint32_t dev_state) uint32_t 6384 drivers/scsi/qla2xxx/qla_init.c uint32_t idc_audit_reg = 0, duration_secs = 0; uint32_t 6414 drivers/scsi/qla2xxx/qla_init.c uint32_t idc_control, dev_state; uint32_t 6453 drivers/scsi/qla2xxx/qla_init.c __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) uint32_t 6459 drivers/scsi/qla2xxx/qla_init.c __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) uint32_t 6467 drivers/scsi/qla2xxx/qla_init.c uint32_t drv_presence = 0; uint32_t 7082 drivers/scsi/qla2xxx/qla_init.c uint32_t *dptr; uint32_t 7084 drivers/scsi/qla2xxx/qla_init.c uint32_t chksum; uint32_t 7110 drivers/scsi/qla2xxx/qla_init.c dptr = (uint32_t *)nv; uint32_t 7325 drivers/scsi/qla2xxx/qla_init.c (uint32_t)ha->zio_mode); uint32_t 7374 drivers/scsi/qla2xxx/qla_init.c uint32_t *p = (void *)image_status; uint32_t 7376 drivers/scsi/qla2xxx/qla_init.c uint32_t sum = 0; uint32_t 7570 drivers/scsi/qla2xxx/qla_init.c qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status), uint32_t 7617 drivers/scsi/qla2xxx/qla_init.c bool qla24xx_risc_firmware_invalid(uint32_t *dword) uint32_t 7625 drivers/scsi/qla2xxx/qla_init.c qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, uint32_t 7626 drivers/scsi/qla2xxx/qla_init.c uint32_t faddr) uint32_t 7633 drivers/scsi/qla2xxx/qla_init.c uint32_t *dcode; uint32_t 7634 drivers/scsi/qla2xxx/qla_init.c uint32_t risc_addr, risc_size, risc_attr = 0; uint32_t 7773 drivers/scsi/qla2xxx/qla_init.c qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) uint32_t 7778 drivers/scsi/qla2xxx/qla_init.c uint32_t risc_addr, risc_size, fwclen, wlen, *seg; uint32_t 7872 drivers/scsi/qla2xxx/qla_init.c qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) uint32_t 7876 drivers/scsi/qla2xxx/qla_init.c uint32_t *dcode; uint32_t 7878 drivers/scsi/qla2xxx/qla_init.c uint32_t risc_addr, risc_size, risc_attr = 0; uint32_t 7882 drivers/scsi/qla2xxx/qla_init.c uint32_t *fwcode; uint32_t 7932 drivers/scsi/qla2xxx/qla_init.c (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data), uint32_t 7966 drivers/scsi/qla2xxx/qla_init.c j, (uint32_t)((void *)fwcode - (void *)blob->fw->data), uint32_t 8028 drivers/scsi/qla2xxx/qla_init.c qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) uint32_t 8049 drivers/scsi/qla2xxx/qla_init.c qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) uint32_t 8261 drivers/scsi/qla2xxx/qla_init.c uint32_t *dptr; uint32_t 8263 drivers/scsi/qla2xxx/qla_init.c uint32_t chksum; uint32_t 8266 drivers/scsi/qla2xxx/qla_init.c uint32_t faddr; uint32_t 8308 drivers/scsi/qla2xxx/qla_init.c dptr = (uint32_t *)nv; uint32_t 8536 drivers/scsi/qla2xxx/qla_init.c (uint32_t)ha->zio_mode); uint32_t 8731 drivers/scsi/qla2xxx/qla_init.c uint32_t pid1, pid2; uint32_t 70 drivers/scsi/qla2xxx/qla_inline.h host_to_fcp_swap(uint8_t *fcp, uint32_t bsize) uint32_t 72 drivers/scsi/qla2xxx/qla_inline.h uint32_t *ifcp = (uint32_t *) fcp; uint32_t 73 drivers/scsi/qla2xxx/qla_inline.h uint32_t *ofcp = (uint32_t *) fcp; uint32_t 74 drivers/scsi/qla2xxx/qla_inline.h uint32_t iter = bsize >> 2; uint32_t 83 drivers/scsi/qla2xxx/qla_inline.h host_to_adap(uint8_t *src, uint8_t *dst, uint32_t bsize) uint32_t 85 drivers/scsi/qla2xxx/qla_inline.h uint32_t *isrc = (uint32_t *) src; uint32_t 87 drivers/scsi/qla2xxx/qla_inline.h uint32_t iter = bsize >> 2; uint32_t 228 drivers/scsi/qla2xxx/qla_inline.h return sizeof(uint32_t) * 32; uint32_t 300 drivers/scsi/qla2xxx/qla_iocb.c uint32_t qla2xxx_get_next_handle(struct req_que *req) uint32_t 302 drivers/scsi/qla2xxx/qla_iocb.c uint32_t index, handle = req->current_outstanding_cmd; uint32_t 328 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *clr_ptr; uint32_t 329 drivers/scsi/qla2xxx/qla_iocb.c uint32_t handle; uint32_t 400 drivers/scsi/qla2xxx/qla_iocb.c clr_ptr = (uint32_t *)cmd_pkt + 2; uint32_t 411 drivers/scsi/qla2xxx/qla_iocb.c cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); uint32_t 594 drivers/scsi/qla2xxx/qla_iocb.c uint32_t dsd_list_len; uint32_t 758 drivers/scsi/qla2xxx/qla_iocb.c uint32_t ref_tag; uint32_t 780 drivers/scsi/qla2xxx/qla_iocb.c pkt->ref_tag = cpu_to_le32((uint32_t) uint32_t 801 drivers/scsi/qla2xxx/qla_iocb.c pkt->ref_tag = cpu_to_le32((uint32_t) uint32_t 826 drivers/scsi/qla2xxx/qla_iocb.c pkt->ref_tag = cpu_to_le32((uint32_t) uint32_t 845 drivers/scsi/qla2xxx/qla_iocb.c qla24xx_get_one_block_sg(uint32_t blk_sz, struct qla2_sgx *sgx, uint32_t 846 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *partial) uint32_t 849 drivers/scsi/qla2xxx/qla_iocb.c uint32_t cumulative_partial, sg_len; uint32_t 892 drivers/scsi/qla2xxx/qla_iocb.c uint32_t dsd_list_len; uint32_t 897 drivers/scsi/qla2xxx/qla_iocb.c uint32_t prot_int; /* protection interval */ uint32_t 898 drivers/scsi/qla2xxx/qla_iocb.c uint32_t partial; uint32_t 901 drivers/scsi/qla2xxx/qla_iocb.c uint32_t sle_dma_len, tot_prot_dma_len = 0; uint32_t 1006 drivers/scsi/qla2xxx/qla_iocb.c uint32_t dsd_list_len; uint32_t 1392 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *fcp_dl; uint32_t 1395 drivers/scsi/qla2xxx/qla_iocb.c uint32_t total_bytes = 0; uint32_t 1396 drivers/scsi/qla2xxx/qla_iocb.c uint32_t data_bytes; uint32_t 1397 drivers/scsi/qla2xxx/qla_iocb.c uint32_t dif_bytes; uint32_t 1548 drivers/scsi/qla2xxx/qla_iocb.c fcp_dl = (uint32_t *)(crc_ctx_pkt->fcp_cmnd.cdb + 16 + uint32_t 1595 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *clr_ptr; uint32_t 1596 drivers/scsi/qla2xxx/qla_iocb.c uint32_t handle; uint32_t 1662 drivers/scsi/qla2xxx/qla_iocb.c clr_ptr = (uint32_t *)cmd_pkt + 2; uint32_t 1682 drivers/scsi/qla2xxx/qla_iocb.c cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); uint32_t 1726 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *clr_ptr; uint32_t 1727 drivers/scsi/qla2xxx/qla_iocb.c uint32_t handle; uint32_t 1739 drivers/scsi/qla2xxx/qla_iocb.c uint32_t status = 0; uint32_t 1784 drivers/scsi/qla2xxx/qla_iocb.c uint32_t partial; uint32_t 1848 drivers/scsi/qla2xxx/qla_iocb.c clr_ptr = (uint32_t *)cmd_pkt + 2; uint32_t 1912 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *clr_ptr; uint32_t 1913 drivers/scsi/qla2xxx/qla_iocb.c uint32_t handle; uint32_t 1982 drivers/scsi/qla2xxx/qla_iocb.c clr_ptr = (uint32_t *)cmd_pkt + 2; uint32_t 2002 drivers/scsi/qla2xxx/qla_iocb.c cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); uint32_t 2047 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *clr_ptr; uint32_t 2048 drivers/scsi/qla2xxx/qla_iocb.c uint32_t handle; uint32_t 2060 drivers/scsi/qla2xxx/qla_iocb.c uint32_t status = 0; uint32_t 2119 drivers/scsi/qla2xxx/qla_iocb.c uint32_t partial; uint32_t 2183 drivers/scsi/qla2xxx/qla_iocb.c clr_ptr = (uint32_t *)cmd_pkt + 2; uint32_t 2250 drivers/scsi/qla2xxx/qla_iocb.c uint32_t handle; uint32_t 2479 drivers/scsi/qla2xxx/qla_iocb.c uint32_t flags; uint32_t 2623 drivers/scsi/qla2xxx/qla_iocb.c host_to_fcp_swap(logo_pyld.s_id, sizeof(uint32_t)); uint32_t 3082 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *clr_ptr; uint32_t 3083 drivers/scsi/qla2xxx/qla_iocb.c uint32_t handle; uint32_t 3088 drivers/scsi/qla2xxx/qla_iocb.c uint32_t dbval; uint32_t 3089 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *fcp_dl; uint32_t 3237 drivers/scsi/qla2xxx/qla_iocb.c clr_ptr = (uint32_t *)cmd_pkt + 2; uint32_t 3271 drivers/scsi/qla2xxx/qla_iocb.c fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + uint32_t 3273 drivers/scsi/qla2xxx/qla_iocb.c *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); uint32_t 3280 drivers/scsi/qla2xxx/qla_iocb.c cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); uint32_t 3308 drivers/scsi/qla2xxx/qla_iocb.c clr_ptr = (uint32_t *)cmd_pkt + 2; uint32_t 3331 drivers/scsi/qla2xxx/qla_iocb.c cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); uint32_t 3639 drivers/scsi/qla2xxx/qla_iocb.c struct cmd_bidir *cmd_pkt, uint32_t tot_dsds) uint32_t 3643 drivers/scsi/qla2xxx/qla_iocb.c uint32_t req_data_len = 0; uint32_t 3644 drivers/scsi/qla2xxx/qla_iocb.c uint32_t rsp_data_len = 0; uint32_t 3725 drivers/scsi/qla2xxx/qla_iocb.c qla2x00_start_bidir(srb_t *sp, struct scsi_qla_host *vha, uint32_t tot_dsds) uint32_t 3730 drivers/scsi/qla2xxx/qla_iocb.c uint32_t handle; uint32_t 3733 drivers/scsi/qla2xxx/qla_iocb.c uint32_t *clr_ptr; uint32_t 3784 drivers/scsi/qla2xxx/qla_iocb.c clr_ptr = (uint32_t *)cmd_pkt + 2; uint32_t 128 drivers/scsi/qla2xxx/qla_isr.c qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *vha, uint32_t reg) uint32_t 169 drivers/scsi/qla2xxx/qla_isr.c uint32_t stat; uint32_t 277 drivers/scsi/qla2xxx/qla_isr.c uint32_t mboxes; uint32_t 419 drivers/scsi/qla2xxx/qla_isr.c uint32_t protocol_engine_id, fw_err_code, err_level; uint32_t 551 drivers/scsi/qla2xxx/qla_isr.c qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry) uint32_t 555 drivers/scsi/qla2xxx/qla_isr.c uint32_t vp_did; uint32_t 633 drivers/scsi/qla2xxx/qla_isr.c uint32_t handles[5]; uint32_t 638 drivers/scsi/qla2xxx/qla_isr.c uint32_t rscn_entry, host_pid; uint32_t 651 drivers/scsi/qla2xxx/qla_isr.c handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1])); uint32_t 676 drivers/scsi/qla2xxx/qla_isr.c handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6); uint32_t 684 drivers/scsi/qla2xxx/qla_isr.c handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6); uint32_t 685 drivers/scsi/qla2xxx/qla_isr.c handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7); uint32_t 690 drivers/scsi/qla2xxx/qla_isr.c handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1])); uint32_t 692 drivers/scsi/qla2xxx/qla_isr.c ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) | uint32_t 1274 drivers/scsi/qla2xxx/qla_isr.c struct req_que *req, uint32_t index) uint32_t 1557 drivers/scsi/qla2xxx/qla_isr.c uint32_t fw_status[3]; uint32_t 1687 drivers/scsi/qla2xxx/qla_isr.c uint32_t iop[2]; uint32_t 1894 drivers/scsi/qla2xxx/qla_isr.c uint32_t *inbuf, *outbuf; uint32_t 1897 drivers/scsi/qla2xxx/qla_isr.c inbuf = (uint32_t *)&sts->nvme_ersp_data; uint32_t 1898 drivers/scsi/qla2xxx/qla_isr.c outbuf = (uint32_t *)fd->rspaddr; uint32_t 2081 drivers/scsi/qla2xxx/qla_isr.c qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len, uint32_t 2082 drivers/scsi/qla2xxx/qla_isr.c uint32_t sense_len, struct rsp_que *rsp, int res) uint32_t 2086 drivers/scsi/qla2xxx/qla_isr.c uint32_t track_sense_len; uint32_t 2138 drivers/scsi/qla2xxx/qla_isr.c uint32_t e_ref_tag, a_ref_tag; uint32_t 2148 drivers/scsi/qla2xxx/qla_isr.c a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4)); uint32_t 2151 drivers/scsi/qla2xxx/qla_isr.c e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4)); uint32_t 2171 drivers/scsi/qla2xxx/qla_isr.c uint32_t blocks_done, resid; uint32_t 2175 drivers/scsi/qla2xxx/qla_isr.c blocks_done = e_ref_tag - (uint32_t)lba_s + 1; uint32_t 2185 drivers/scsi/qla2xxx/qla_isr.c uint32_t i, j = 0, k = 0, num_ent; uint32_t 2255 drivers/scsi/qla2xxx/qla_isr.c struct req_que *req, uint32_t index) uint32_t 2262 drivers/scsi/qla2xxx/qla_isr.c uint32_t rval = EXT_STATUS_OK; uint32_t 2420 drivers/scsi/qla2xxx/qla_isr.c uint32_t sense_len, par_sense_len, rsp_info_len, resid_len, uint32_t 2424 drivers/scsi/qla2xxx/qla_isr.c uint32_t handle; uint32_t 2440 drivers/scsi/qla2xxx/qla_isr.c handle = (uint32_t) LSW(sts->handle); uint32_t 2813 drivers/scsi/qla2xxx/qla_isr.c uint32_t sense_len; uint32_t 2925 drivers/scsi/qla2xxx/qla_isr.c uint32_t mboxes; uint32_t 3115 drivers/scsi/qla2xxx/qla_isr.c uint32_t cnt; uint32_t 3178 drivers/scsi/qla2xxx/qla_isr.c uint32_t stat; uint32_t 3179 drivers/scsi/qla2xxx/qla_isr.c uint32_t hccr; uint32_t 3312 drivers/scsi/qla2xxx/qla_isr.c uint32_t stat; uint32_t 3313 drivers/scsi/qla2xxx/qla_isr.c uint32_t hccr; uint32_t 110 drivers/scsi/qla2xxx/qla_mbx.c uint32_t cnt; uint32_t 111 drivers/scsi/qla2xxx/qla_mbx.c uint32_t mboxes; uint32_t 413 drivers/scsi/qla2xxx/qla_mbx.c uint32_t ictrl, host_status, hccr; uint32_t 595 drivers/scsi/qla2xxx/qla_mbx.c qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, uint32_t 596 drivers/scsi/qla2xxx/qla_mbx.c uint32_t risc_code_size) uint32_t 687 drivers/scsi/qla2xxx/qla_mbx.c qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) uint32_t 1343 drivers/scsi/qla2xxx/qla_mbx.c qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) uint32_t 1402 drivers/scsi/qla2xxx/qla_mbx.c dma_addr_t phys_addr, size_t size, uint32_t tov) uint32_t 1466 drivers/scsi/qla2xxx/qla_mbx.c uint32_t handle = 0; uint32_t 2366 drivers/scsi/qla2xxx/qla_mbx.c uint32_t iop[2]; uint32_t 3004 drivers/scsi/qla2xxx/qla_mbx.c uint32_t *iter = (void *)stats; uint32_t 3063 drivers/scsi/qla2xxx/qla_mbx.c uint32_t *iter, dwords; uint32_t 3110 drivers/scsi/qla2xxx/qla_mbx.c uint32_t handle; uint32_t 3193 drivers/scsi/qla2xxx/qla_mbx.c __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, uint32_t 3419 drivers/scsi/qla2xxx/qla_mbx.c qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) uint32_t 3455 drivers/scsi/qla2xxx/qla_mbx.c qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) uint32_t 3646 drivers/scsi/qla2xxx/qla_mbx.c uint16_t buffers, uint16_t *mb, uint32_t *dwords) uint32_t 4184 drivers/scsi/qla2xxx/qla_mbx.c qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, uint32_t 4185 drivers/scsi/qla2xxx/qla_mbx.c uint32_t size) uint32_t 4509 drivers/scsi/qla2xxx/qla_mbx.c qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) uint32_t 4579 drivers/scsi/qla2xxx/qla_mbx.c qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) uint32_t 4794 drivers/scsi/qla2xxx/qla_mbx.c uint32_t *bp; uint32_t 4821 drivers/scsi/qla2xxx/qla_mbx.c bp = (uint32_t *) buf; uint32_t 5041 drivers/scsi/qla2xxx/qla_mbx.c qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) uint32_t 5226 drivers/scsi/qla2xxx/qla_mbx.c qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) uint32_t 5264 drivers/scsi/qla2xxx/qla_mbx.c uint32_t stat, timer; uint32_t 5920 drivers/scsi/qla2xxx/qla_mbx.c qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) uint32_t 5994 drivers/scsi/qla2xxx/qla_mbx.c qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) uint32_t 6078 drivers/scsi/qla2xxx/qla_mbx.c uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size) uint32_t 6131 drivers/scsi/qla2xxx/qla_mbx.c qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, uint32_t 6132 drivers/scsi/qla2xxx/qla_mbx.c uint32_t size) uint32_t 6594 drivers/scsi/qla2xxx/qla_mbx.c uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr, uint32_t 6595 drivers/scsi/qla2xxx/qla_mbx.c uint32_t sfub_len) uint32_t 6627 drivers/scsi/qla2xxx/qla_mbx.c int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr, uint32_t 6628 drivers/scsi/qla2xxx/qla_mbx.c uint32_t data) uint32_t 6659 drivers/scsi/qla2xxx/qla_mbx.c int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr, uint32_t 6660 drivers/scsi/qla2xxx/qla_mbx.c uint32_t *data) uint32_t 6678 drivers/scsi/qla2xxx/qla_mbx.c *data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) | mcp->mb[3]); uint32_t 29 drivers/scsi/qla2xxx/qla_mid.c static uint32_t uint32_t 32 drivers/scsi/qla2xxx/qla_mid.c uint32_t vp_id; uint32_t 692 drivers/scsi/qla2xxx/qla_mid.c uint32_t cnt; uint32_t 48 drivers/scsi/qla2xxx/qla_mr.c uint32_t *iptr; uint32_t 49 drivers/scsi/qla2xxx/qla_mr.c uint32_t __iomem *optr; uint32_t 50 drivers/scsi/qla2xxx/qla_mr.c uint32_t cnt; uint32_t 51 drivers/scsi/qla2xxx/qla_mr.c uint32_t mboxes; uint32_t 113 drivers/scsi/qla2xxx/qla_mr.c optr = (uint32_t __iomem *)®->ispfx00.mailbox0; uint32_t 180 drivers/scsi/qla2xxx/qla_mr.c uint32_t *iptr2; uint32_t 194 drivers/scsi/qla2xxx/qla_mr.c iptr = (uint32_t *)&ha->mailbox_out32[0]; uint32_t 346 drivers/scsi/qla2xxx/qla_mr.c qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states) uint32_t 531 drivers/scsi/qla2xxx/qla_mr.c uint32_t cnt; uint32_t 532 drivers/scsi/qla2xxx/qla_mr.c uint32_t reg_val; uint32_t 908 drivers/scsi/qla2xxx/qla_mr.c uint32_t aenmbx, aenmbx7 = 0; uint32_t 909 drivers/scsi/qla2xxx/qla_mr.c uint32_t pseudo_aen; uint32_t 910 drivers/scsi/qla2xxx/qla_mr.c uint32_t state[5]; uint32_t 1070 drivers/scsi/qla2xxx/qla_mr.c uint32_t state[5]; uint32_t 1441 drivers/scsi/qla2xxx/qla_mr.c uint32_t status = QLA_FUNCTION_FAILED; uint32_t 1444 drivers/scsi/qla2xxx/qla_mr.c uint32_t aenmbx7; uint32_t 1486 drivers/scsi/qla2xxx/qla_mr.c uint32_t fw_heart_beat; uint32_t 1487 drivers/scsi/qla2xxx/qla_mr.c uint32_t aenmbx0; uint32_t 1489 drivers/scsi/qla2xxx/qla_mr.c uint32_t tempc; uint32_t 1538 drivers/scsi/qla2xxx/qla_mr.c uint32_t data0, data1; uint32_t 1718 drivers/scsi/qla2xxx/qla_mr.c uint32_t aen_code, aen_data; uint32_t 2025 drivers/scsi/qla2xxx/qla_mr.c uint32_t tempc; uint32_t 2083 drivers/scsi/qla2xxx/qla_mr.c uint32_t uint32_t 2089 drivers/scsi/qla2xxx/qla_mr.c uint32_t state[1]; uint32_t 2130 drivers/scsi/qla2xxx/qla_mr.c qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len, uint32_t 2131 drivers/scsi/qla2xxx/qla_mr.c uint32_t sense_len, struct rsp_que *rsp, int res) uint32_t 2135 drivers/scsi/qla2xxx/qla_mr.c uint32_t track_sense_len; uint32_t 2287 drivers/scsi/qla2xxx/qla_mr.c uint32_t sense_len, par_sense_len, rsp_info_len, resid_len, uint32_t 2291 drivers/scsi/qla2xxx/qla_mr.c uint32_t hindex, handle; uint32_t 2561 drivers/scsi/qla2xxx/qla_mr.c uint32_t sense_len; uint32_t 2639 drivers/scsi/qla2xxx/qla_mr.c uint32_t handle, hindex, handle_count, i; uint32_t 2864 drivers/scsi/qla2xxx/qla_mr.c (uint32_t *)ha->aenmb, data_size); uint32_t 2873 drivers/scsi/qla2xxx/qla_mr.c qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0) uint32_t 2876 drivers/scsi/qla2xxx/qla_mr.c uint32_t __iomem *wptr; uint32_t 2886 drivers/scsi/qla2xxx/qla_mr.c wptr = (uint32_t __iomem *)®->mailbox17; uint32_t 2911 drivers/scsi/qla2xxx/qla_mr.c uint32_t stat; uint32_t 2912 drivers/scsi/qla2xxx/qla_mr.c uint32_t mb[8]; uint32_t 2915 drivers/scsi/qla2xxx/qla_mr.c uint32_t clr_intr = 0; uint32_t 2916 drivers/scsi/qla2xxx/qla_mr.c uint32_t intr_stat = 0; uint32_t 3078 drivers/scsi/qla2xxx/qla_mr.c uint32_t handle; uint32_t 3152 drivers/scsi/qla2xxx/qla_mr.c lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); uint32_t 3213 drivers/scsi/qla2xxx/qla_mr.c if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) { uint32_t 26 drivers/scsi/qla2xxx/qla_mr.h uint32_t handle; /* System handle. */ uint32_t 61 drivers/scsi/qla2xxx/qla_mr.h uint32_t handle; /* System handle. */ uint32_t 62 drivers/scsi/qla2xxx/qla_mr.h uint32_t reserved_3; /* System handle. */ uint32_t 75 drivers/scsi/qla2xxx/qla_mr.h uint32_t sense_len; /* FCP SENSE length. */ uint32_t 101 drivers/scsi/qla2xxx/qla_mr.h uint32_t reserved_0; uint32_t 144 drivers/scsi/qla2xxx/qla_mr.h uint32_t handle; /* System handle. */ uint32_t 145 drivers/scsi/qla2xxx/qla_mr.h uint32_t reserved_0; /* System handle. */ uint32_t 151 drivers/scsi/qla2xxx/qla_mr.h uint32_t adapid; /* Adapter ID */ uint32_t 152 drivers/scsi/qla2xxx/qla_mr.h uint32_t dataword_r_extra; uint32_t 156 drivers/scsi/qla2xxx/qla_mr.h uint32_t residuallen; uint32_t 192 drivers/scsi/qla2xxx/qla_mr.h uint32_t tgt_node_state; uint32_t 194 drivers/scsi/qla2xxx/qla_mr.h uint32_t reserved_1[8]; uint32_t 211 drivers/scsi/qla2xxx/qla_mr.h uint32_t up_port_state; uint32_t 230 drivers/scsi/qla2xxx/qla_mr.h uint32_t link_config; uint32_t 244 drivers/scsi/qla2xxx/qla_mr.h uint32_t uiReserved[48]; uint32_t 260 drivers/scsi/qla2xxx/qla_mr.h uint32_t os_type; uint32_t 268 drivers/scsi/qla2xxx/qla_mr.h uint32_t reserved[64]; uint32_t 274 drivers/scsi/qla2xxx/qla_mr.h uint32_t reserved[64]; /* future additions */ uint32_t 279 drivers/scsi/qla2xxx/qla_mr.h #define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32) uint32_t 300 drivers/scsi/qla2xxx/qla_mr.h uint32_t log_size; uint32_t 308 drivers/scsi/qla2xxx/qla_mr.h uint32_t cluster_key_len; uint32_t 314 drivers/scsi/qla2xxx/qla_mr.h uint32_t enabled_capabilities; uint32_t 315 drivers/scsi/qla2xxx/qla_mr.h uint32_t nominal_temp_value; uint32_t 426 drivers/scsi/qla2xxx/qla_mr.h uint32_t reserved_1; uint32_t 433 drivers/scsi/qla2xxx/qla_mr.h uint32_t adapid; uint32_t 434 drivers/scsi/qla2xxx/qla_mr.h uint32_t adapid_hi; uint32_t 436 drivers/scsi/qla2xxx/qla_mr.h uint32_t reserved_2; uint32_t 481 drivers/scsi/qla2xxx/qla_mr.h uint32_t old_fw_hbt_cnt; uint32_t 485 drivers/scsi/qla2xxx/qla_mr.h uint32_t old_aenmbx0_state; uint32_t 486 drivers/scsi/qla2xxx/qla_mr.h uint32_t critical_temperature; uint32_t 355 drivers/scsi/qla2xxx/qla_nvme.c uint32_t *clr_ptr; uint32_t 356 drivers/scsi/qla2xxx/qla_nvme.c uint32_t handle; uint32_t 370 drivers/scsi/qla2xxx/qla_nvme.c uint32_t rval = QLA_SUCCESS; uint32_t 419 drivers/scsi/qla2xxx/qla_nvme.c clr_ptr = (uint32_t *)cmd_pkt + 2; uint32_t 50 drivers/scsi/qla2xxx/qla_nvme.h uint32_t handle; /* System handle. */ uint32_t 70 drivers/scsi/qla2xxx/qla_nvme.h uint32_t byte_count; /* Total byte count. */ uint32_t 84 drivers/scsi/qla2xxx/qla_nvme.h uint32_t handle; uint32_t 99 drivers/scsi/qla2xxx/qla_nvme.h uint32_t exchange_address; uint32_t 100 drivers/scsi/qla2xxx/qla_nvme.h uint32_t rsvd3; uint32_t 101 drivers/scsi/qla2xxx/qla_nvme.h uint32_t rx_byte_count; uint32_t 102 drivers/scsi/qla2xxx/qla_nvme.h uint32_t tx_byte_count; uint32_t 118 drivers/scsi/qla2xxx/qla_nvme.h uint32_t exchange_address; uint32_t 130 drivers/scsi/qla2xxx/qla_nvme.h uint32_t param; uint32_t 131 drivers/scsi/qla2xxx/qla_nvme.h uint32_t desc0; uint32_t 134 drivers/scsi/qla2xxx/qla_nvme.h uint32_t desc_len; uint32_t 135 drivers/scsi/qla2xxx/qla_nvme.h uint32_t payload[3]; uint32_t 350 drivers/scsi/qla2xxx/qla_nx.c char *qdev_state(uint32_t dev_state) uint32_t 865 drivers/scsi/qla2xxx/qla_nx.c uint32_t lock_owner = 0; uint32_t 936 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) uint32_t 938 drivers/scsi/qla2xxx/qla_nx.c uint32_t off_value, rval = 0; uint32_t 971 drivers/scsi/qla2xxx/qla_nx.c uint32_t lock_owner = 0; uint32_t 992 drivers/scsi/qla2xxx/qla_nx.c qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) uint32_t 1011 drivers/scsi/qla2xxx/qla_nx.c uint32_t done = 1 ; uint32_t 1012 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; uint32_t 1035 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; uint32_t 1051 drivers/scsi/qla2xxx/qla_nx.c qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) uint32_t 1085 drivers/scsi/qla2xxx/qla_nx.c uint32_t lock_owner = 0; uint32_t 1103 drivers/scsi/qla2xxx/qla_nx.c qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, uint32_t 1104 drivers/scsi/qla2xxx/qla_nx.c uint32_t data) uint32_t 1337 drivers/scsi/qla2xxx/qla_nx.c uint32_t temp; uint32_t 1376 drivers/scsi/qla2xxx/qla_nx.c tmpw = *((uint32_t *)data); uint32_t 1474 drivers/scsi/qla2xxx/qla_nx.c uint32_t temp; uint32_t 1548 drivers/scsi/qla2xxx/qla_nx.c *(uint32_t *)data = val; uint32_t 1561 drivers/scsi/qla2xxx/qla_nx.c uint32_t i; uint32_t 1667 drivers/scsi/qla2xxx/qla_nx.c uint32_t len = 0; uint32_t 1849 drivers/scsi/qla2xxx/qla_nx.c uint32_t i; uint32_t 1855 drivers/scsi/qla2xxx/qla_nx.c uint32_t flagbit; uint32_t 1886 drivers/scsi/qla2xxx/qla_nx.c uint32_t min_size; uint32_t 2038 drivers/scsi/qla2xxx/qla_nx.c uint32_t stat = 0; uint32_t 2121 drivers/scsi/qla2xxx/qla_nx.c uint32_t stat = 0; uint32_t 2122 drivers/scsi/qla2xxx/qla_nx.c uint32_t host_int = 0; uint32_t 2186 drivers/scsi/qla2xxx/qla_nx.c uint32_t host_int = 0; uint32_t 2217 drivers/scsi/qla2xxx/qla_nx.c uint32_t stat; uint32_t 2218 drivers/scsi/qla2xxx/qla_nx.c uint32_t host_int = 0; uint32_t 2322 drivers/scsi/qla2xxx/qla_nx.c uint32_t drv_active; uint32_t 2344 drivers/scsi/qla2xxx/qla_nx.c uint32_t drv_active; uint32_t 2362 drivers/scsi/qla2xxx/qla_nx.c uint32_t drv_active; uint32_t 2372 drivers/scsi/qla2xxx/qla_nx.c uint32_t drv_state; uint32_t 2387 drivers/scsi/qla2xxx/qla_nx.c uint32_t drv_state; uint32_t 2406 drivers/scsi/qla2xxx/qla_nx.c uint32_t drv_state; uint32_t 2416 drivers/scsi/qla2xxx/qla_nx.c uint32_t qsnt_state; uint32_t 2427 drivers/scsi/qla2xxx/qla_nx.c uint32_t qsnt_state; uint32_t 2552 drivers/scsi/qla2xxx/qla_nx.c static uint32_t * uint32_t 2553 drivers/scsi/qla2xxx/qla_nx.c qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, uint32_t 2554 drivers/scsi/qla2xxx/qla_nx.c uint32_t length) uint32_t 2556 drivers/scsi/qla2xxx/qla_nx.c uint32_t i; uint32_t 2557 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; uint32_t 2577 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; uint32_t 2611 drivers/scsi/qla2xxx/qla_nx.c uint32_t val; uint32_t 2675 drivers/scsi/qla2xxx/qla_nx.c uint32_t offset, uint32_t length) uint32_t 2678 drivers/scsi/qla2xxx/qla_nx.c qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); uint32_t 2684 drivers/scsi/qla2xxx/qla_nx.c qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, uint32_t 2685 drivers/scsi/qla2xxx/qla_nx.c uint32_t faddr, uint32_t dwords) uint32_t 2688 drivers/scsi/qla2xxx/qla_nx.c uint32_t liter; uint32_t 2689 drivers/scsi/qla2xxx/qla_nx.c uint32_t rest_addr; uint32_t 2783 drivers/scsi/qla2xxx/qla_nx.c uint32_t offset, uint32_t length) uint32_t 2805 drivers/scsi/qla2xxx/qla_nx.c uint32_t dbval; uint32_t 2834 drivers/scsi/qla2xxx/qla_nx.c uint32_t lock_owner = 0; uint32_t 2866 drivers/scsi/qla2xxx/qla_nx.c uint32_t old_count, count; uint32_t 2928 drivers/scsi/qla2xxx/qla_nx.c uint32_t dev_state, drv_state, drv_active; uint32_t 2996 drivers/scsi/qla2xxx/qla_nx.c uint32_t uint32_t 2997 drivers/scsi/qla2xxx/qla_nx.c qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) uint32_t 3000 drivers/scsi/qla2xxx/qla_nx.c uint32_t dev_state; uint32_t 3051 drivers/scsi/qla2xxx/qla_nx.c uint32_t dev_state, drv_state, drv_active; uint32_t 3052 drivers/scsi/qla2xxx/qla_nx.c uint32_t active_mask = 0; uint32_t 3178 drivers/scsi/qla2xxx/qla_nx.c uint32_t fw_heartbeat_counter; uint32_t 3220 drivers/scsi/qla2xxx/qla_nx.c uint32_t dev_state; uint32_t 3221 drivers/scsi/qla2xxx/qla_nx.c uint32_t old_dev_state; uint32_t 3327 drivers/scsi/qla2xxx/qla_nx.c uint32_t temp, temp_state, temp_val; uint32_t 3351 drivers/scsi/qla2xxx/qla_nx.c uint32_t temp; uint32_t 3373 drivers/scsi/qla2xxx/qla_nx.c uint32_t dev_state, halt_status; uint32_t 3448 drivers/scsi/qla2xxx/qla_nx.c int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) uint32_t 3469 drivers/scsi/qla2xxx/qla_nx.c uint32_t dev_state = 0; uint32_t 3727 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) uint32_t 3731 drivers/scsi/qla2xxx/qla_nx.c uint32_t read_value, opcode, poll_time; uint32_t 3732 drivers/scsi/qla2xxx/qla_nx.c uint32_t addr, index, crb_addr; uint32_t 3735 drivers/scsi/qla2xxx/qla_nx.c uint32_t rval = QLA_SUCCESS; uint32_t 3844 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) uint32_t 3847 drivers/scsi/qla2xxx/qla_nx.c uint32_t r_addr, r_stride, loop_cnt, i, r_value; uint32_t 3849 drivers/scsi/qla2xxx/qla_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 3866 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) uint32_t 3869 drivers/scsi/qla2xxx/qla_nx.c uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; uint32_t 3871 drivers/scsi/qla2xxx/qla_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 3892 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) uint32_t 3895 drivers/scsi/qla2xxx/qla_nx.c uint32_t r_addr, r_stride, loop_cnt, i, r_value; uint32_t 3897 drivers/scsi/qla2xxx/qla_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 3915 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) uint32_t 3918 drivers/scsi/qla2xxx/qla_nx.c uint32_t addr, r_addr, c_addr, t_r_addr; uint32_t 3919 drivers/scsi/qla2xxx/qla_nx.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; uint32_t 3921 drivers/scsi/qla2xxx/qla_nx.c uint32_t c_value_w, c_value_r; uint32_t 3924 drivers/scsi/qla2xxx/qla_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 3974 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) uint32_t 3977 drivers/scsi/qla2xxx/qla_nx.c uint32_t addr, r_addr, c_addr, t_r_addr; uint32_t 3978 drivers/scsi/qla2xxx/qla_nx.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; uint32_t 3979 drivers/scsi/qla2xxx/qla_nx.c uint32_t c_value_w; uint32_t 3981 drivers/scsi/qla2xxx/qla_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 4009 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) uint32_t 4012 drivers/scsi/qla2xxx/qla_nx.c uint32_t s_addr, r_addr; uint32_t 4013 drivers/scsi/qla2xxx/qla_nx.c uint32_t r_stride, r_value, r_cnt, qid = 0; uint32_t 4014 drivers/scsi/qla2xxx/qla_nx.c uint32_t i, k, loop_cnt; uint32_t 4016 drivers/scsi/qla2xxx/qla_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 4039 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) uint32_t 4042 drivers/scsi/qla2xxx/qla_nx.c uint32_t r_addr, r_value; uint32_t 4043 drivers/scsi/qla2xxx/qla_nx.c uint32_t i, loop_cnt; uint32_t 4045 drivers/scsi/qla2xxx/qla_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 4049 drivers/scsi/qla2xxx/qla_nx.c loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); uint32_t 4058 drivers/scsi/qla2xxx/qla_nx.c r_addr += sizeof(uint32_t); uint32_t 4065 drivers/scsi/qla2xxx/qla_nx.c qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) uint32_t 4068 drivers/scsi/qla2xxx/qla_nx.c uint32_t r_addr, r_value, r_data; uint32_t 4069 drivers/scsi/qla2xxx/qla_nx.c uint32_t i, j, loop_cnt; uint32_t 4073 drivers/scsi/qla2xxx/qla_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 4137 drivers/scsi/qla2xxx/qla_nx.c uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; uint32_t 4138 drivers/scsi/qla2xxx/qla_nx.c int count = ha->md_template_size/sizeof(uint32_t); uint32_t 4166 drivers/scsi/qla2xxx/qla_nx.c uint32_t *data_ptr; uint32_t 4167 drivers/scsi/qla2xxx/qla_nx.c uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; uint32_t 4171 drivers/scsi/qla2xxx/qla_nx.c data_ptr = (uint32_t *)ha->md_dump; uint32_t 721 drivers/scsi/qla2xxx/qla_nx.h uint32_t int_vec_bit; uint32_t 722 drivers/scsi/qla2xxx/qla_nx.h uint32_t tgt_status_reg; uint32_t 723 drivers/scsi/qla2xxx/qla_nx.h uint32_t tgt_mask_reg; uint32_t 724 drivers/scsi/qla2xxx/qla_nx.h uint32_t pci_int_reg; uint32_t 803 drivers/scsi/qla2xxx/qla_nx.h uint32_t findex; uint32_t 804 drivers/scsi/qla2xxx/qla_nx.h uint32_t num_entries; uint32_t 805 drivers/scsi/qla2xxx/qla_nx.h uint32_t entry_size; uint32_t 806 drivers/scsi/qla2xxx/qla_nx.h uint32_t reserved[5]; uint32_t 810 drivers/scsi/qla2xxx/qla_nx.h uint32_t findex; uint32_t 811 drivers/scsi/qla2xxx/qla_nx.h uint32_t size; uint32_t 812 drivers/scsi/qla2xxx/qla_nx.h uint32_t reserved[5]; uint32_t 832 drivers/scsi/qla2xxx/qla_nx.h uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */ uint32_t 833 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */ uint32_t 834 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */ uint32_t 838 drivers/scsi/qla2xxx/qla_nx.h uint32_t hint; /* Host interrupt register */ uint32_t 842 drivers/scsi/qla2xxx/qla_nx.h uint32_t unused_3[48]; uint32_t 844 drivers/scsi/qla2xxx/qla_nx.h uint32_t host_status; /* host status */ uint32_t 847 drivers/scsi/qla2xxx/qla_nx.h uint32_t host_int; /* Interrupt status. */ uint32_t 982 drivers/scsi/qla2xxx/qla_nx.h uint32_t entry_type; uint32_t 983 drivers/scsi/qla2xxx/qla_nx.h uint32_t first_entry_offset; uint32_t 984 drivers/scsi/qla2xxx/qla_nx.h uint32_t size_of_template; uint32_t 985 drivers/scsi/qla2xxx/qla_nx.h uint32_t capture_debug_level; uint32_t 987 drivers/scsi/qla2xxx/qla_nx.h uint32_t num_of_entries; uint32_t 988 drivers/scsi/qla2xxx/qla_nx.h uint32_t version; uint32_t 989 drivers/scsi/qla2xxx/qla_nx.h uint32_t driver_timestamp; uint32_t 990 drivers/scsi/qla2xxx/qla_nx.h uint32_t template_checksum; uint32_t 992 drivers/scsi/qla2xxx/qla_nx.h uint32_t driver_capture_mask; uint32_t 993 drivers/scsi/qla2xxx/qla_nx.h uint32_t driver_info[3]; uint32_t 995 drivers/scsi/qla2xxx/qla_nx.h uint32_t saved_state_array[QLA82XX_DBG_STATE_ARRAY_LEN]; uint32_t 996 drivers/scsi/qla2xxx/qla_nx.h uint32_t capture_size_array[QLA82XX_DBG_CAP_SIZE_ARRAY_LEN]; uint32_t 999 drivers/scsi/qla2xxx/qla_nx.h uint32_t markers_array[QLA82XX_DBG_RSVD_ARRAY_LEN]; uint32_t 1000 drivers/scsi/qla2xxx/qla_nx.h uint32_t num_of_free_entries; /* For internal use */ uint32_t 1001 drivers/scsi/qla2xxx/qla_nx.h uint32_t free_entry_offset; /* For internal use */ uint32_t 1002 drivers/scsi/qla2xxx/qla_nx.h uint32_t total_table_size; /* For internal use */ uint32_t 1003 drivers/scsi/qla2xxx/qla_nx.h uint32_t bkup_table_offset; /* For internal use */ uint32_t 1015 drivers/scsi/qla2xxx/qla_nx.h uint32_t entry_type; uint32_t 1016 drivers/scsi/qla2xxx/qla_nx.h uint32_t entry_size; uint32_t 1017 drivers/scsi/qla2xxx/qla_nx.h uint32_t entry_capture_size; uint32_t 1031 drivers/scsi/qla2xxx/qla_nx.h uint32_t addr; uint32_t 1038 drivers/scsi/qla2xxx/qla_nx.h uint32_t data_size; uint32_t 1039 drivers/scsi/qla2xxx/qla_nx.h uint32_t op_count; uint32_t 1048 drivers/scsi/qla2xxx/qla_nx.h uint32_t value_1; uint32_t 1049 drivers/scsi/qla2xxx/qla_nx.h uint32_t value_2; uint32_t 1050 drivers/scsi/qla2xxx/qla_nx.h uint32_t value_3; uint32_t 1059 drivers/scsi/qla2xxx/qla_nx.h uint32_t tag_reg_addr; uint32_t 1065 drivers/scsi/qla2xxx/qla_nx.h uint32_t data_size; uint32_t 1066 drivers/scsi/qla2xxx/qla_nx.h uint32_t op_count; uint32_t 1068 drivers/scsi/qla2xxx/qla_nx.h uint32_t control_addr; uint32_t 1075 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_addr; uint32_t 1089 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd_0; uint32_t 1090 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd_1; uint32_t 1091 drivers/scsi/qla2xxx/qla_nx.h uint32_t data_size; uint32_t 1092 drivers/scsi/qla2xxx/qla_nx.h uint32_t op_count; uint32_t 1094 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd_2; uint32_t 1095 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd_3; uint32_t 1096 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_addr; uint32_t 1097 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_addr_stride; uint32_t 1098 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_addr_cntrl; uint32_t 1106 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd[6]; uint32_t 1107 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_addr; uint32_t 1108 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_data_size; uint32_t 1116 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd[6]; uint32_t 1117 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_addr; uint32_t 1118 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_data_size; uint32_t 1124 drivers/scsi/qla2xxx/qla_nx.h uint32_t select_addr; uint32_t 1125 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd_0; uint32_t 1126 drivers/scsi/qla2xxx/qla_nx.h uint32_t data_size; uint32_t 1127 drivers/scsi/qla2xxx/qla_nx.h uint32_t op_count; uint32_t 1129 drivers/scsi/qla2xxx/qla_nx.h uint32_t select_value; uint32_t 1130 drivers/scsi/qla2xxx/qla_nx.h uint32_t select_value_stride; uint32_t 1131 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_addr; uint32_t 1132 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd_1; uint32_t 1138 drivers/scsi/qla2xxx/qla_nx.h uint32_t select_addr; uint32_t 1144 drivers/scsi/qla2xxx/qla_nx.h uint32_t data_size; uint32_t 1145 drivers/scsi/qla2xxx/qla_nx.h uint32_t op_count; uint32_t 1146 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd_1; uint32_t 1147 drivers/scsi/qla2xxx/qla_nx.h uint32_t rsvd_2; uint32_t 1149 drivers/scsi/qla2xxx/qla_nx.h uint32_t read_addr; uint32_t 16 drivers/scsi/qla2xxx/qla_nx2.c static const uint32_t qla8044_reg_tbl[] = { uint32_t 34 drivers/scsi/qla2xxx/qla_nx2.c uint32_t uint32_t 41 drivers/scsi/qla2xxx/qla_nx2.c qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val) uint32_t 48 drivers/scsi/qla2xxx/qla_nx2.c const uint32_t crb_reg) uint32_t 60 drivers/scsi/qla2xxx/qla_nx2.c const uint32_t crb_reg, uint32_t 61 drivers/scsi/qla2xxx/qla_nx2.c const uint32_t value) uint32_t 70 drivers/scsi/qla2xxx/qla_nx2.c qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr) uint32_t 72 drivers/scsi/qla2xxx/qla_nx2.c uint32_t val; uint32_t 90 drivers/scsi/qla2xxx/qla_nx2.c qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) uint32_t 105 drivers/scsi/qla2xxx/qla_nx2.c qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) uint32_t 130 drivers/scsi/qla2xxx/qla_nx2.c uint32_t raddr, uint32_t waddr) uint32_t 132 drivers/scsi/qla2xxx/qla_nx2.c uint32_t value; uint32_t 139 drivers/scsi/qla2xxx/qla_nx2.c qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1, uint32_t 140 drivers/scsi/qla2xxx/qla_nx2.c uint32_t mask) uint32_t 143 drivers/scsi/qla2xxx/qla_nx2.c uint32_t temp; uint32_t 161 drivers/scsi/qla2xxx/qla_nx2.c static uint32_t uint32_t 163 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr) uint32_t 165 drivers/scsi/qla2xxx/qla_nx2.c uint32_t temp; uint32_t 187 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask) uint32_t 190 drivers/scsi/qla2xxx/qla_nx2.c uint32_t temp; uint32_t 209 drivers/scsi/qla2xxx/qla_nx2.c qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1, uint32_t 210 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value) uint32_t 239 drivers/scsi/qla2xxx/qla_nx2.c uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr) uint32_t 241 drivers/scsi/qla2xxx/qla_nx2.c uint32_t value; uint32_t 259 drivers/scsi/qla2xxx/qla_nx2.c uint32_t qsnt_state; uint32_t 272 drivers/scsi/qla2xxx/qla_nx2.c uint32_t qsnt_state; uint32_t 310 drivers/scsi/qla2xxx/qla_nx2.c uint32_t lock = 0, lockid; uint32_t 360 drivers/scsi/qla2xxx/qla_nx2.c uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0; uint32_t 361 drivers/scsi/qla2xxx/qla_nx2.c uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0; uint32_t 452 drivers/scsi/qla2xxx/qla_nx2.c uint32_t lock_status = 0; uint32_t 509 drivers/scsi/qla2xxx/qla_nx2.c uint32_t flash_addr, int u32_word_count) uint32_t 512 drivers/scsi/qla2xxx/qla_nx2.c uint32_t u32_word; uint32_t 547 drivers/scsi/qla2xxx/qla_nx2.c *(uint32_t *)p_data = u32_word; uint32_t 564 drivers/scsi/qla2xxx/qla_nx2.c uint32_t offset, uint32_t length) uint32_t 580 drivers/scsi/qla2xxx/qla_nx2.c uint32_t drv_state, drv_active; uint32_t 608 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i; uint32_t 616 drivers/scsi/qla2xxx/qla_nx2.c udelay((uint32_t)(p_hdr->delay)); uint32_t 634 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i; uint32_t 643 drivers/scsi/qla2xxx/qla_nx2.c udelay((uint32_t)(p_hdr->delay)); uint32_t 660 drivers/scsi/qla2xxx/qla_nx2.c qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr, uint32_t 661 drivers/scsi/qla2xxx/qla_nx2.c int duration, uint32_t test_mask, uint32_t test_result) uint32_t 663 drivers/scsi/qla2xxx/qla_nx2.c uint32_t value; uint32_t 719 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i; uint32_t 720 drivers/scsi/qla2xxx/qla_nx2.c uint32_t value; uint32_t 775 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i; uint32_t 821 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i; uint32_t 833 drivers/scsi/qla2xxx/qla_nx2.c udelay((uint32_t)(p_hdr->delay)); uint32_t 850 drivers/scsi/qla2xxx/qla_nx2.c mdelay((uint32_t)((long)p_hdr->delay)); uint32_t 893 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i; uint32_t 894 drivers/scsi/qla2xxx/qla_nx2.c uint32_t value; uint32_t 1032 drivers/scsi/qla2xxx/qla_nx2.c uint32_t flash_addr, uint8_t *p_data, int u32_word_count) uint32_t 1034 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i; uint32_t 1035 drivers/scsi/qla2xxx/qla_nx2.c uint32_t u32_word; uint32_t 1036 drivers/scsi/qla2xxx/qla_nx2.c uint32_t flash_offset; uint32_t 1037 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr = flash_addr; uint32_t 1060 drivers/scsi/qla2xxx/qla_nx2.c if ((flash_offset + (u32_word_count * sizeof(uint32_t))) > uint32_t 1072 drivers/scsi/qla2xxx/qla_nx2.c *(uint32_t *)p_data = u32_word; uint32_t 1101 drivers/scsi/qla2xxx/qla_nx2.c *(uint32_t *)p_data = u32_word; uint32_t 1123 drivers/scsi/qla2xxx/qla_nx2.c uint64_t addr, uint32_t *data, uint32_t count) uint32_t 1126 drivers/scsi/qla2xxx/qla_nx2.c uint32_t agt_ctrl; uint32_t 1218 drivers/scsi/qla2xxx/qla_nx2.c uint32_t src, count, size; uint32_t 1244 drivers/scsi/qla2xxx/qla_nx2.c p_cache, size/sizeof(uint32_t)); uint32_t 1255 drivers/scsi/qla2xxx/qla_nx2.c (uint32_t *)p_cache, count); uint32_t 1319 drivers/scsi/qla2xxx/qla_nx2.c uint32_t val, ret_val = QLA_FUNCTION_FAILED; uint32_t 1367 drivers/scsi/qla2xxx/qla_nx2.c uint32_t drv_active; uint32_t 1391 drivers/scsi/qla2xxx/qla_nx2.c uint32_t old_count = 0, count = 0; uint32_t 1393 drivers/scsi/qla2xxx/qla_nx2.c uint32_t idc_ctrl; uint32_t 1488 drivers/scsi/qla2xxx/qla_nx2.c uint32_t sum = 0; uint32_t 1518 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size; uint32_t 1533 drivers/scsi/qla2xxx/qla_nx2.c sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t); uint32_t 1550 drivers/scsi/qla2xxx/qla_nx2.c tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t); uint32_t 1563 drivers/scsi/qla2xxx/qla_nx2.c vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t); uint32_t 1611 drivers/scsi/qla2xxx/qla_nx2.c uint32_t idc_ctrl; uint32_t 1624 drivers/scsi/qla2xxx/qla_nx2.c uint32_t drv_state; uint32_t 1648 drivers/scsi/qla2xxx/qla_nx2.c uint32_t dev_state = 0, drv_state, drv_active; uint32_t 1742 drivers/scsi/qla2xxx/qla_nx2.c uint32_t drv_active; uint32_t 1760 drivers/scsi/qla2xxx/qla_nx2.c uint32_t drv_active; uint32_t 1773 drivers/scsi/qla2xxx/qla_nx2.c uint32_t idc_ctrl; uint32_t 1788 drivers/scsi/qla2xxx/qla_nx2.c uint32_t drv_active; uint32_t 1832 drivers/scsi/qla2xxx/qla_nx2.c uint32_t drv_active; uint32_t 1867 drivers/scsi/qla2xxx/qla_nx2.c uint32_t drv_state, drv_active, dev_state; uint32_t 1930 drivers/scsi/qla2xxx/qla_nx2.c uint32_t dev_state; uint32_t 2040 drivers/scsi/qla2xxx/qla_nx2.c uint32_t temp, temp_state, temp_val; uint32_t 2065 drivers/scsi/qla2xxx/qla_nx2.c uint32_t temp; uint32_t 2080 drivers/scsi/qla2xxx/qla_nx2.c uint32_t fw_heartbeat_counter; uint32_t 2081 drivers/scsi/qla2xxx/qla_nx2.c uint32_t halt_status1, halt_status2; uint32_t 2125 drivers/scsi/qla2xxx/qla_nx2.c uint32_t dev_state, halt_status; uint32_t 2211 drivers/scsi/qla2xxx/qla_nx2.c uint32_t read_value, opcode, poll_time, addr, index; uint32_t 2212 drivers/scsi/qla2xxx/qla_nx2.c uint32_t crb_addr, rval = QLA_SUCCESS; uint32_t 2329 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 2331 drivers/scsi/qla2xxx/qla_nx2.c uint32_t r_addr, r_stride, loop_cnt, i, r_value; uint32_t 2333 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2352 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 2354 drivers/scsi/qla2xxx/qla_nx2.c uint32_t r_addr, r_value, r_data; uint32_t 2355 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i, j, loop_cnt; uint32_t 2358 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2429 drivers/scsi/qla2xxx/qla_nx2.c static uint32_t uint32_t 2431 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 2433 drivers/scsi/qla2xxx/qla_nx2.c uint32_t fl_addr, u32_count, rval; uint32_t 2435 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2439 drivers/scsi/qla2xxx/qla_nx2.c u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t); uint32_t 2473 drivers/scsi/qla2xxx/qla_nx2.c uint32_t **d_ptr) uint32_t 2475 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr, r_addr, c_addr, t_r_addr; uint32_t 2476 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; uint32_t 2478 drivers/scsi/qla2xxx/qla_nx2.c uint32_t c_value_w, c_value_r; uint32_t 2481 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2530 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 2532 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr, r_addr, c_addr, t_r_addr; uint32_t 2533 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; uint32_t 2534 drivers/scsi/qla2xxx/qla_nx2.c uint32_t c_value_w; uint32_t 2536 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2564 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 2566 drivers/scsi/qla2xxx/qla_nx2.c uint32_t r_addr, r_stride, loop_cnt, i, r_value; uint32_t 2568 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2588 drivers/scsi/qla2xxx/qla_nx2.c __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))); uint32_t 2596 drivers/scsi/qla2xxx/qla_nx2.c uint32_t **d_ptr) uint32_t 2598 drivers/scsi/qla2xxx/qla_nx2.c uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; uint32_t 2600 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2624 drivers/scsi/qla2xxx/qla_nx2.c uint32_t **d_ptr) uint32_t 2626 drivers/scsi/qla2xxx/qla_nx2.c uint32_t s_addr, r_addr; uint32_t 2627 drivers/scsi/qla2xxx/qla_nx2.c uint32_t r_stride, r_value, r_cnt, qid = 0; uint32_t 2628 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i, k, loop_cnt; uint32_t 2630 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2653 drivers/scsi/qla2xxx/qla_nx2.c static uint32_t uint32_t 2656 drivers/scsi/qla2xxx/qla_nx2.c uint32_t **d_ptr) uint32_t 2658 drivers/scsi/qla2xxx/qla_nx2.c uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; uint32_t 2661 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2703 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 2705 drivers/scsi/qla2xxx/qla_nx2.c uint32_t sel_val1, sel_val2, t_sel_val, data, i; uint32_t 2706 drivers/scsi/qla2xxx/qla_nx2.c uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; uint32_t 2708 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2744 drivers/scsi/qla2xxx/qla_nx2.c static uint32_t uint32_t 2747 drivers/scsi/qla2xxx/qla_nx2.c uint32_t **d_ptr) uint32_t 2749 drivers/scsi/qla2xxx/qla_nx2.c uint32_t poll_wait, poll_mask, r_value, data; uint32_t 2750 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr_1, addr_2, value_1, value_2; uint32_t 2752 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 2826 drivers/scsi/qla2xxx/qla_nx2.c uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; uint32_t 2856 drivers/scsi/qla2xxx/qla_nx2.c uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; uint32_t 2909 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 2914 drivers/scsi/qla2xxx/qla_nx2.c uint32_t chunk_size, read_size; uint32_t 3000 drivers/scsi/qla2xxx/qla_nx2.c static uint32_t uint32_t 3002 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 3005 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr1, addr2, value, data, temp, wrVal; uint32_t 3008 drivers/scsi/qla2xxx/qla_nx2.c uint32_t poll, mask, modify_mask; uint32_t 3009 drivers/scsi/qla2xxx/qla_nx2.c uint32_t wait_count = 0; uint32_t 3010 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 3096 drivers/scsi/qla2xxx/qla_nx2.c static uint32_t uint32_t 3098 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 3101 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr1, addr2, value1, value2, data, selVal; uint32_t 3103 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr3, addr4, addr5, addr6, addr7; uint32_t 3105 drivers/scsi/qla2xxx/qla_nx2.c uint32_t mask; uint32_t 3106 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr = *d_ptr; uint32_t 3174 drivers/scsi/qla2xxx/qla_nx2.c static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha, uint32_t 3175 drivers/scsi/qla2xxx/qla_nx2.c struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) uint32_t 3177 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr1, addr2, value1, value2, poll, r_value; uint32_t 3178 drivers/scsi/qla2xxx/qla_nx2.c uint32_t wait_count = 0; uint32_t 3231 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *data_ptr; uint32_t 3232 drivers/scsi/qla2xxx/qla_nx2.c uint32_t data_collected = 0, f_capture_mask; uint32_t 3235 drivers/scsi/qla2xxx/qla_nx2.c uint32_t timestamp, idc_control; uint32_t 3282 drivers/scsi/qla2xxx/qla_nx2.c data_ptr = (uint32_t *)((uint8_t *)ha->md_dump); uint32_t 3503 drivers/scsi/qla2xxx/qla_nx2.c uint32_t flash_status; uint32_t 3530 drivers/scsi/qla2xxx/qla_nx2.c uint32_t data) uint32_t 3533 drivers/scsi/qla2xxx/qla_nx2.c uint32_t cmd; uint32_t 3606 drivers/scsi/qla2xxx/qla_nx2.c uint32_t sector_start_addr) uint32_t 3608 drivers/scsi/qla2xxx/qla_nx2.c uint32_t reversed_addr; uint32_t 3661 drivers/scsi/qla2xxx/qla_nx2.c qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr, uint32_t 3662 drivers/scsi/qla2xxx/qla_nx2.c uint32_t *p_data) uint32_t 3696 drivers/scsi/qla2xxx/qla_nx2.c qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t 3697 drivers/scsi/qla2xxx/qla_nx2.c uint32_t faddr, uint32_t dwords) uint32_t 3700 drivers/scsi/qla2xxx/qla_nx2.c uint32_t spi_val; uint32_t 3779 drivers/scsi/qla2xxx/qla_nx2.c qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t 3780 drivers/scsi/qla2xxx/qla_nx2.c uint32_t faddr, uint32_t dwords) uint32_t 3783 drivers/scsi/qla2xxx/qla_nx2.c uint32_t liter; uint32_t 3800 drivers/scsi/qla2xxx/qla_nx2.c uint32_t offset, uint32_t length) uint32_t 3804 drivers/scsi/qla2xxx/qla_nx2.c uint32_t erase_offset; uint32_t 3815 drivers/scsi/qla2xxx/qla_nx2.c dword_count = length / sizeof(uint32_t); uint32_t 3849 drivers/scsi/qla2xxx/qla_nx2.c rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src, uint32_t 3857 drivers/scsi/qla2xxx/qla_nx2.c (uint32_t *)p_src, offset, uint32_t 3860 drivers/scsi/qla2xxx/qla_nx2.c p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; uint32_t 3861 drivers/scsi/qla2xxx/qla_nx2.c offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; uint32_t 3897 drivers/scsi/qla2xxx/qla_nx2.c uint32_t stat; uint32_t 3899 drivers/scsi/qla2xxx/qla_nx2.c uint32_t leg_int_ptr = 0, pf_bit; uint32_t 3991 drivers/scsi/qla2xxx/qla_nx2.c uint32_t idc_ctrl; uint32_t 4000 drivers/scsi/qla2xxx/qla_nx2.c uint32_t drv_state; uint32_t 4020 drivers/scsi/qla2xxx/qla_nx2.c uint32_t dev_state; uint32_t 240 drivers/scsi/qla2xxx/qla_nx2.h uint32_t test_mask; uint32_t 241 drivers/scsi/qla2xxx/qla_nx2.h uint32_t test_value; uint32_t 246 drivers/scsi/qla2xxx/qla_nx2.h uint32_t test_mask; uint32_t 247 drivers/scsi/qla2xxx/qla_nx2.h uint32_t xor_value; uint32_t 248 drivers/scsi/qla2xxx/qla_nx2.h uint32_t or_value; uint32_t 257 drivers/scsi/qla2xxx/qla_nx2.h uint32_t arg1; uint32_t 258 drivers/scsi/qla2xxx/qla_nx2.h uint32_t arg2; uint32_t 263 drivers/scsi/qla2xxx/qla_nx2.h uint32_t dr_addr; uint32_t 264 drivers/scsi/qla2xxx/qla_nx2.h uint32_t dr_value; uint32_t 265 drivers/scsi/qla2xxx/qla_nx2.h uint32_t ar_addr; uint32_t 266 drivers/scsi/qla2xxx/qla_nx2.h uint32_t ar_value; uint32_t 273 drivers/scsi/qla2xxx/qla_nx2.h uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES]; uint32_t 287 drivers/scsi/qla2xxx/qla_nx2.h uint32_t entry_type; uint32_t 288 drivers/scsi/qla2xxx/qla_nx2.h uint32_t entry_size; uint32_t 289 drivers/scsi/qla2xxx/qla_nx2.h uint32_t entry_capture_size; uint32_t 301 drivers/scsi/qla2xxx/qla_nx2.h uint32_t addr; uint32_t 307 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 308 drivers/scsi/qla2xxx/qla_nx2.h uint32_t op_count; uint32_t 317 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value_1; uint32_t 318 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value_2; uint32_t 319 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value_3; uint32_t 324 drivers/scsi/qla2xxx/qla_nx2.h uint32_t tag_reg_addr; uint32_t 329 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 330 drivers/scsi/qla2xxx/qla_nx2.h uint32_t op_count; uint32_t 331 drivers/scsi/qla2xxx/qla_nx2.h uint32_t control_addr; uint32_t 337 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr; uint32_t 348 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd_0; uint32_t 349 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd_1; uint32_t 350 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 351 drivers/scsi/qla2xxx/qla_nx2.h uint32_t op_count; uint32_t 352 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd_2; uint32_t 353 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd_3; uint32_t 354 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr; uint32_t 355 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr_stride; uint32_t 361 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd[6]; uint32_t 362 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr; uint32_t 363 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_data_size; uint32_t 369 drivers/scsi/qla2xxx/qla_nx2.h uint32_t desc_card_addr; uint32_t 372 drivers/scsi/qla2xxx/qla_nx2.h uint32_t start_dma_cmd; uint32_t 374 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr; uint32_t 375 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_data_size; uint32_t 381 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd[6]; uint32_t 382 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr; uint32_t 383 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_data_size; uint32_t 389 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_addr; uint32_t 390 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd_0; uint32_t 391 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 392 drivers/scsi/qla2xxx/qla_nx2.h uint32_t op_count; uint32_t 393 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_value; uint32_t 394 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_value_stride; uint32_t 395 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr; uint32_t 396 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd_1; uint32_t 402 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_addr; uint32_t 407 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 408 drivers/scsi/qla2xxx/qla_nx2.h uint32_t op_count; uint32_t 409 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd_1; uint32_t 410 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd_2; uint32_t 411 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr; uint32_t 422 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_addr; uint32_t 423 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr; uint32_t 424 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_value; uint32_t 427 drivers/scsi/qla2xxx/qla_nx2.h uint32_t poll_wait; uint32_t 428 drivers/scsi/qla2xxx/qla_nx2.h uint32_t poll_mask; uint32_t 429 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 430 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd_1; uint32_t 435 drivers/scsi/qla2xxx/qla_nx2.h uint32_t addr_1; uint32_t 436 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value; uint32_t 440 drivers/scsi/qla2xxx/qla_nx2.h uint32_t poll; uint32_t 441 drivers/scsi/qla2xxx/qla_nx2.h uint32_t mask; uint32_t 442 drivers/scsi/qla2xxx/qla_nx2.h uint32_t modify_mask; uint32_t 443 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 444 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd; uint32_t 451 drivers/scsi/qla2xxx/qla_nx2.h uint32_t addr_1; uint32_t 452 drivers/scsi/qla2xxx/qla_nx2.h uint32_t addr_2; uint32_t 453 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value_1; uint32_t 457 drivers/scsi/qla2xxx/qla_nx2.h uint32_t poll; uint32_t 458 drivers/scsi/qla2xxx/qla_nx2.h uint32_t mask; uint32_t 459 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value_2; uint32_t 460 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 466 drivers/scsi/qla2xxx/qla_nx2.h uint32_t addr_1; uint32_t 467 drivers/scsi/qla2xxx/qla_nx2.h uint32_t addr_2; uint32_t 468 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value_1; uint32_t 469 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value_2; uint32_t 470 drivers/scsi/qla2xxx/qla_nx2.h uint32_t poll; uint32_t 471 drivers/scsi/qla2xxx/qla_nx2.h uint32_t mask; uint32_t 472 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 473 drivers/scsi/qla2xxx/qla_nx2.h uint32_t rsvd; uint32_t 480 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_addr_1; uint32_t 481 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_addr_2; uint32_t 482 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_value_1; uint32_t 483 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_value_2; uint32_t 484 drivers/scsi/qla2xxx/qla_nx2.h uint32_t op_count; uint32_t 485 drivers/scsi/qla2xxx/qla_nx2.h uint32_t select_value_mask; uint32_t 486 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_addr; uint32_t 495 drivers/scsi/qla2xxx/qla_nx2.h uint32_t addr_1; uint32_t 496 drivers/scsi/qla2xxx/qla_nx2.h uint32_t addr_2; uint32_t 497 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value_1; uint32_t 498 drivers/scsi/qla2xxx/qla_nx2.h uint32_t value_2; uint32_t 499 drivers/scsi/qla2xxx/qla_nx2.h uint32_t poll_wait; uint32_t 500 drivers/scsi/qla2xxx/qla_nx2.h uint32_t poll_mask; uint32_t 501 drivers/scsi/qla2xxx/qla_nx2.h uint32_t modify_mask; uint32_t 502 drivers/scsi/qla2xxx/qla_nx2.h uint32_t data_size; uint32_t 507 drivers/scsi/qla2xxx/qla_nx2.h uint32_t request_desc; /* IDC request descriptor */ uint32_t 508 drivers/scsi/qla2xxx/qla_nx2.h uint32_t info1; /* IDC additional info */ uint32_t 509 drivers/scsi/qla2xxx/qla_nx2.h uint32_t info2; /* IDC additional info */ uint32_t 510 drivers/scsi/qla2xxx/qla_nx2.h uint32_t info3; /* IDC additional info */ uint32_t 550 drivers/scsi/qla2xxx/qla_nx2.h uint32_t entry_type; uint32_t 551 drivers/scsi/qla2xxx/qla_nx2.h uint32_t first_entry_offset; uint32_t 552 drivers/scsi/qla2xxx/qla_nx2.h uint32_t size_of_template; uint32_t 553 drivers/scsi/qla2xxx/qla_nx2.h uint32_t capture_debug_level; uint32_t 554 drivers/scsi/qla2xxx/qla_nx2.h uint32_t num_of_entries; uint32_t 555 drivers/scsi/qla2xxx/qla_nx2.h uint32_t version; uint32_t 556 drivers/scsi/qla2xxx/qla_nx2.h uint32_t driver_timestamp; uint32_t 557 drivers/scsi/qla2xxx/qla_nx2.h uint32_t checksum; uint32_t 559 drivers/scsi/qla2xxx/qla_nx2.h uint32_t driver_capture_mask; uint32_t 560 drivers/scsi/qla2xxx/qla_nx2.h uint32_t driver_info_word2; uint32_t 561 drivers/scsi/qla2xxx/qla_nx2.h uint32_t driver_info_word3; uint32_t 562 drivers/scsi/qla2xxx/qla_nx2.h uint32_t driver_info_word4; uint32_t 564 drivers/scsi/qla2xxx/qla_nx2.h uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN]; uint32_t 565 drivers/scsi/qla2xxx/qla_nx2.h uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN]; uint32_t 566 drivers/scsi/qla2xxx/qla_nx2.h uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN]; uint32_t 571 drivers/scsi/qla2xxx/qla_nx2.h uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */ uint32_t 566 drivers/scsi/qla2xxx/qla_os.c uint32_t pci_bus; uint32_t 569 drivers/scsi/qla2xxx/qla_os.c uint32_t lstat, lspeed, lwidth; uint32_t 818 drivers/scsi/qla2xxx/qla_os.c uint32_t tag; uint32_t 1197 drivers/scsi/qla2xxx/qla_os.c uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) uint32_t 1235 drivers/scsi/qla2xxx/qla_os.c uint32_t ratov_j; uint32_t 1701 drivers/scsi/qla2xxx/qla_os.c uint32_t ratov_j; uint32_t 4986 drivers/scsi/qla2xxx/qla_os.c qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, uint32_t 4987 drivers/scsi/qla2xxx/qla_os.c uint32_t *data, int cnt) uint32_t 5460 drivers/scsi/qla2xxx/qla_os.c uint32_t dev_state = 0; uint32_t 5482 drivers/scsi/qla2xxx/qla_os.c uint32_t dev_state = 0; uint32_t 5497 drivers/scsi/qla2xxx/qla_os.c uint32_t heart_beat_counter1, heart_beat_counter2; uint32_t 5528 drivers/scsi/qla2xxx/qla_os.c uint32_t dev_state = 0; uint32_t 5567 drivers/scsi/qla2xxx/qla_os.c uint32_t dev_state, idc_control; uint32_t 5614 drivers/scsi/qla2xxx/qla_os.c uint32_t data; uint32_t 5615 drivers/scsi/qla2xxx/qla_os.c uint32_t idc_lck_rcvry_stage_mask = 0x3; uint32_t 5616 drivers/scsi/qla2xxx/qla_os.c uint32_t idc_lck_rcvry_owner_mask = 0x3c; uint32_t 5676 drivers/scsi/qla2xxx/qla_os.c uint32_t o_drv_lockid, n_drv_lockid; uint32_t 5710 drivers/scsi/qla2xxx/qla_os.c uint32_t data; uint32_t 5711 drivers/scsi/qla2xxx/qla_os.c uint32_t lock_owner; uint32_t 5751 drivers/scsi/qla2xxx/qla_os.c uint32_t data; uint32_t 5810 drivers/scsi/qla2xxx/qla_os.c uint32_t drv_presence; uint32_t 5839 drivers/scsi/qla2xxx/qla_os.c uint32_t drv_presence; uint32_t 5867 drivers/scsi/qla2xxx/qla_os.c uint32_t drv_ack, drv_presence; uint32_t 5906 drivers/scsi/qla2xxx/qla_os.c uint32_t idc_control; uint32_t 5942 drivers/scsi/qla2xxx/qla_os.c uint32_t dev_state; uint32_t 6138 drivers/scsi/qla2xxx/qla_os.c uint32_t online; uint32_t 6954 drivers/scsi/qla2xxx/qla_os.c uint32_t stat; uint32_t 104 drivers/scsi/qla2xxx/qla_sup.c qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) uint32_t 153 drivers/scsi/qla2xxx/qla_sup.c qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) uint32_t 156 drivers/scsi/qla2xxx/qla_sup.c uint32_t nv_cmd; uint32_t 186 drivers/scsi/qla2xxx/qla_sup.c qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data) uint32_t 190 drivers/scsi/qla2xxx/qla_sup.c uint32_t nv_cmd, wait_cnt; uint32_t 243 drivers/scsi/qla2xxx/qla_sup.c qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, uint32_t 244 drivers/scsi/qla2xxx/qla_sup.c uint16_t data, uint32_t tmo) uint32_t 248 drivers/scsi/qla2xxx/qla_sup.c uint32_t nv_cmd; uint32_t 310 drivers/scsi/qla2xxx/qla_sup.c uint32_t word, wait_cnt; uint32_t 375 drivers/scsi/qla2xxx/qla_sup.c uint32_t word, wait_cnt; uint32_t 429 drivers/scsi/qla2xxx/qla_sup.c static inline uint32_t uint32_t 430 drivers/scsi/qla2xxx/qla_sup.c flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) uint32_t 435 drivers/scsi/qla2xxx/qla_sup.c static inline uint32_t uint32_t 436 drivers/scsi/qla2xxx/qla_sup.c flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) uint32_t 441 drivers/scsi/qla2xxx/qla_sup.c static inline uint32_t uint32_t 442 drivers/scsi/qla2xxx/qla_sup.c nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) uint32_t 447 drivers/scsi/qla2xxx/qla_sup.c static inline uint32_t uint32_t 448 drivers/scsi/qla2xxx/qla_sup.c nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) uint32_t 454 drivers/scsi/qla2xxx/qla_sup.c qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data) uint32_t 477 drivers/scsi/qla2xxx/qla_sup.c qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, uint32_t 478 drivers/scsi/qla2xxx/qla_sup.c uint32_t dwords) uint32_t 497 drivers/scsi/qla2xxx/qla_sup.c qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) uint32_t 521 drivers/scsi/qla2xxx/qla_sup.c uint32_t faddr, ids = 0; uint32_t 548 drivers/scsi/qla2xxx/qla_sup.c qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) uint32_t 551 drivers/scsi/qla2xxx/qla_sup.c uint32_t pcihdr, pcids; uint32_t 556 drivers/scsi/qla2xxx/qla_sup.c uint32_t *dcode = (void *)req->ring; uint32_t 637 drivers/scsi/qla2xxx/qla_sup.c qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) uint32_t 640 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_fw[] = uint32_t 642 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_boot[] = uint32_t 644 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_vpd_nvram[] = uint32_t 646 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_vpd0[] = uint32_t 648 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_vpd1[] = uint32_t 650 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_nvram0[] = uint32_t 652 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_nvram1[] = uint32_t 654 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_fdt[] = uint32_t 657 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_npiv_conf0[] = uint32_t 660 drivers/scsi/qla2xxx/qla_sup.c const uint32_t def_npiv_conf1[] = uint32_t 663 drivers/scsi/qla2xxx/qla_sup.c const uint32_t fcp_prio_cfg0[] = uint32_t 666 drivers/scsi/qla2xxx/qla_sup.c const uint32_t fcp_prio_cfg1[] = uint32_t 671 drivers/scsi/qla2xxx/qla_sup.c uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0; uint32_t 675 drivers/scsi/qla2xxx/qla_sup.c uint32_t start; uint32_t 1045 drivers/scsi/qla2xxx/qla_sup.c uint32_t *wptr; uint32_t 1052 drivers/scsi/qla2xxx/qla_sup.c wptr = (uint32_t *)req->ring; uint32_t 1074 drivers/scsi/qla2xxx/qla_sup.c uint32_t flt_addr; uint32_t 1221 drivers/scsi/qla2xxx/qla_sup.c uint32_t faddr, dword; uint32_t 1250 drivers/scsi/qla2xxx/qla_sup.c qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) uint32_t 1253 drivers/scsi/qla2xxx/qla_sup.c uint32_t start, finish; uint32_t 1268 drivers/scsi/qla2xxx/qla_sup.c qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, uint32_t 1269 drivers/scsi/qla2xxx/qla_sup.c uint32_t dwords) uint32_t 1274 drivers/scsi/qla2xxx/qla_sup.c uint32_t sec_mask, rest_addr, fdata; uint32_t 1378 drivers/scsi/qla2xxx/qla_sup.c qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, uint32_t 1379 drivers/scsi/qla2xxx/qla_sup.c uint32_t bytes) uint32_t 1381 drivers/scsi/qla2xxx/qla_sup.c uint32_t i; uint32_t 1397 drivers/scsi/qla2xxx/qla_sup.c qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, uint32_t 1398 drivers/scsi/qla2xxx/qla_sup.c uint32_t bytes) uint32_t 1401 drivers/scsi/qla2xxx/qla_sup.c uint32_t *dwptr = buf; uint32_t 1402 drivers/scsi/qla2xxx/qla_sup.c uint32_t i; uint32_t 1420 drivers/scsi/qla2xxx/qla_sup.c qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, uint32_t 1421 drivers/scsi/qla2xxx/qla_sup.c uint32_t bytes) uint32_t 1424 drivers/scsi/qla2xxx/qla_sup.c uint32_t i; uint32_t 1454 drivers/scsi/qla2xxx/qla_sup.c qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, uint32_t 1455 drivers/scsi/qla2xxx/qla_sup.c uint32_t bytes) uint32_t 1459 drivers/scsi/qla2xxx/qla_sup.c uint32_t *dwptr = buf; uint32_t 1460 drivers/scsi/qla2xxx/qla_sup.c uint32_t i; uint32_t 1501 drivers/scsi/qla2xxx/qla_sup.c qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, uint32_t 1502 drivers/scsi/qla2xxx/qla_sup.c uint32_t bytes) uint32_t 1505 drivers/scsi/qla2xxx/qla_sup.c uint32_t *dwptr = buf; uint32_t 1506 drivers/scsi/qla2xxx/qla_sup.c uint32_t i; uint32_t 1523 drivers/scsi/qla2xxx/qla_sup.c qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, uint32_t 1524 drivers/scsi/qla2xxx/qla_sup.c uint32_t bytes) uint32_t 1727 drivers/scsi/qla2xxx/qla_sup.c uint32_t gpio_data; uint32_t 1757 drivers/scsi/qla2xxx/qla_sup.c static uint32_t uint32_t 1760 drivers/scsi/qla2xxx/qla_sup.c uint32_t led_select_value = 0; uint32_t 1777 drivers/scsi/qla2xxx/qla_sup.c uint32_t led_select_value; uint32_t 1781 drivers/scsi/qla2xxx/qla_sup.c uint32_t led_10_value, led_43_value; uint32_t 1855 drivers/scsi/qla2xxx/qla_sup.c uint32_t gpio_data; uint32_t 1907 drivers/scsi/qla2xxx/qla_sup.c uint32_t gpio_data; uint32_t 2005 drivers/scsi/qla2xxx/qla_sup.c qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) uint32_t 2066 drivers/scsi/qla2xxx/qla_sup.c qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) uint32_t 2129 drivers/scsi/qla2xxx/qla_sup.c qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, uint32_t 2134 drivers/scsi/qla2xxx/qla_sup.c uint32_t cnt; uint32_t 2169 drivers/scsi/qla2xxx/qla_sup.c qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, uint32_t 2242 drivers/scsi/qla2xxx/qla_sup.c qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, uint32_t 2243 drivers/scsi/qla2xxx/qla_sup.c uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) uint32_t 2284 drivers/scsi/qla2xxx/qla_sup.c uint32_t saddr, uint32_t length) uint32_t 2287 drivers/scsi/qla2xxx/qla_sup.c uint32_t midpoint, ilength; uint32_t 2351 drivers/scsi/qla2xxx/qla_sup.c uint32_t offset, uint32_t length) uint32_t 2353 drivers/scsi/qla2xxx/qla_sup.c uint32_t addr, midpoint; uint32_t 2385 drivers/scsi/qla2xxx/qla_sup.c uint32_t offset, uint32_t length) uint32_t 2391 drivers/scsi/qla2xxx/qla_sup.c uint32_t addr, liter, sec_mask, rest_addr; uint32_t 2604 drivers/scsi/qla2xxx/qla_sup.c uint32_t offset, uint32_t length) uint32_t 2623 drivers/scsi/qla2xxx/qla_sup.c qla28xx_extract_sfub_and_verify(struct scsi_qla_host *vha, uint32_t *buf, uint32_t 2624 drivers/scsi/qla2xxx/qla_sup.c uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf) uint32_t 2626 drivers/scsi/qla2xxx/qla_sup.c uint32_t *p, check_sum = 0; uint32_t 2651 drivers/scsi/qla2xxx/qla_sup.c qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start, uint32_t 2680 drivers/scsi/qla2xxx/qla_sup.c qla28xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, uint32_t 2681 drivers/scsi/qla2xxx/qla_sup.c uint32_t dwords) uint32_t 2686 drivers/scsi/qla2xxx/qla_sup.c uint32_t sec_mask, rest_addr, fdata; uint32_t 2692 drivers/scsi/qla2xxx/qla_sup.c uint32_t offset = faddr << 2; uint32_t 2693 drivers/scsi/qla2xxx/qla_sup.c uint32_t buf_size_without_sfub = 0; uint32_t 2696 drivers/scsi/qla2xxx/qla_sup.c uint32_t risc_size, risc_attr = 0; uint32_t 2697 drivers/scsi/qla2xxx/qla_sup.c uint32_t *fw_array = NULL; uint32_t 2973 drivers/scsi/qla2xxx/qla_sup.c uint32_t offset, uint32_t length) uint32_t 2984 drivers/scsi/qla2xxx/qla_sup.c rval = qla28xx_write_flash_data(vha, (uint32_t *)buf, uint32_t 2987 drivers/scsi/qla2xxx/qla_sup.c rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, uint32_t 2998 drivers/scsi/qla2xxx/qla_sup.c uint32_t offset, uint32_t length) uint32_t 3004 drivers/scsi/qla2xxx/qla_sup.c uint32_t faddr, left, burst; uint32_t 3085 drivers/scsi/qla2xxx/qla_sup.c qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) uint32_t 3088 drivers/scsi/qla2xxx/qla_sup.c uint32_t istart, iend, iter, vend; uint32_t 3163 drivers/scsi/qla2xxx/qla_sup.c uint32_t pcihdr, pcids; uint32_t 3294 drivers/scsi/qla2xxx/qla_sup.c uint32_t pcihdr, pcids; uint32_t 3295 drivers/scsi/qla2xxx/qla_sup.c uint32_t *dcode = mbuf; uint32_t 3403 drivers/scsi/qla2xxx/qla_sup.c uint32_t pcihdr = 0, pcids = 0; uint32_t 3404 drivers/scsi/qla2xxx/qla_sup.c uint32_t *dcode = mbuf; uint32_t 3409 drivers/scsi/qla2xxx/qla_sup.c uint32_t faddr = 0; uint32_t 3595 drivers/scsi/qla2xxx/qla_sup.c uint32_t fcp_prio_addr; uint32_t 124 drivers/scsi/qla2xxx/qla_target.c uint32_t add_flags, uint16_t resp_code, int resp_code_valid, uint32_t 135 drivers/scsi/qla2xxx/qla_target.c static int qlt_check_reserve_free_req(struct qla_qpair *qpair, uint32_t); uint32_t 136 drivers/scsi/qla2xxx/qla_target.c static inline uint32_t qlt_make_handle(struct qla_qpair *); uint32_t 194 drivers/scsi/qla2xxx/qla_target.c uint32_t key; uint32_t 1658 drivers/scsi/qla2xxx/qla_target.c uint32_t add_flags, uint16_t resp_code, int resp_code_valid, uint32_t 1720 drivers/scsi/qla2xxx/qla_target.c uint32_t f_ctl, h; uint32_t 1803 drivers/scsi/qla2xxx/qla_target.c struct abts_recv_from_24xx *abts, uint32_t status, uint32_t 1809 drivers/scsi/qla2xxx/qla_target.c uint32_t f_ctl; uint32_t 1957 drivers/scsi/qla2xxx/qla_target.c uint32_t key; uint32_t 1963 drivers/scsi/qla2xxx/qla_target.c uint32_t op_key; uint32_t 1974 drivers/scsi/qla2xxx/qla_target.c uint32_t op_key; uint32_t 1985 drivers/scsi/qla2xxx/qla_target.c uint32_t cmd_key; uint32_t 2020 drivers/scsi/qla2xxx/qla_target.c uint32_t tag; uint32_t 2128 drivers/scsi/qla2xxx/qla_target.c uint32_t tag = abts->exchange_addr_to_abort; uint32_t 2195 drivers/scsi/qla2xxx/qla_target.c struct qla_tgt_mgmt_cmd *mcmd, uint32_t resp_code) uint32_t 2472 drivers/scsi/qla2xxx/qla_target.c uint32_t req_cnt) uint32_t 2474 drivers/scsi/qla2xxx/qla_target.c uint32_t cnt; uint32_t 2512 drivers/scsi/qla2xxx/qla_target.c static inline uint32_t qlt_make_handle(struct qla_qpair *qpair) uint32_t 2514 drivers/scsi/qla2xxx/qla_target.c uint32_t h; uint32_t 2551 drivers/scsi/qla2xxx/qla_target.c uint32_t h; uint32_t 2723 drivers/scsi/qla2xxx/qla_target.c uint32_t *full_req_cnt) uint32_t 2801 drivers/scsi/qla2xxx/qla_target.c prm->sense_buffer_len = min_t(uint32_t, prm->sense_buffer_len, uint32_t 2802 drivers/scsi/qla2xxx/qla_target.c (uint32_t)sizeof(ctio->u.status1.sense_data)); uint32_t 2836 drivers/scsi/qla2xxx/qla_target.c ((uint32_t *)ctio->u.status1.sense_data)[i] = uint32_t 2837 drivers/scsi/qla2xxx/qla_target.c cpu_to_be32(((uint32_t *)prm->sense_buffer)[i]); uint32_t 2902 drivers/scsi/qla2xxx/qla_target.c uint32_t lba = 0xffffffff & se_cmd->t_task_lba; uint32_t 2905 drivers/scsi/qla2xxx/qla_target.c uint32_t t32 = 0; uint32_t 2987 drivers/scsi/qla2xxx/qla_target.c uint32_t transfer_length = 0; uint32_t 2988 drivers/scsi/qla2xxx/qla_target.c uint32_t data_bytes; uint32_t 2989 drivers/scsi/qla2xxx/qla_target.c uint32_t dif_bytes; uint32_t 2998 drivers/scsi/qla2xxx/qla_target.c uint32_t h; uint32_t 3202 drivers/scsi/qla2xxx/qla_target.c uint32_t full_req_cnt = 0; uint32_t 3452 drivers/scsi/qla2xxx/qla_target.c cmd->a_ref_tag = be32_to_cpu(*(uint32_t *)(ap + 4)); uint32_t 3456 drivers/scsi/qla2xxx/qla_target.c cmd->e_ref_tag = be32_to_cpu(*(uint32_t *)(ep + 4)); uint32_t 3727 drivers/scsi/qla2xxx/qla_target.c uint32_t total_leaked; uint32_t 3817 drivers/scsi/qla2xxx/qla_target.c struct qla_tgt_cmd *cmd, uint32_t status) uint32_t 3849 drivers/scsi/qla2xxx/qla_target.c struct rsp_que *rsp, uint32_t handle, void *ctio) uint32_t 3854 drivers/scsi/qla2xxx/qla_target.c uint32_t h = handle & ~QLA_TGT_HANDLE_MASK; uint32_t 3903 drivers/scsi/qla2xxx/qla_target.c struct rsp_que *rsp, uint32_t handle, uint32_t status, void *ctio) uint32_t 4089 drivers/scsi/qla2xxx/qla_target.c uint32_t data_length; uint32_t 4632 drivers/scsi/qla2xxx/qla_target.c uint32_t key; uint32_t 4642 drivers/scsi/qla2xxx/qla_target.c uint32_t op_key = sid_to_key(op->atio.u.isp24.fcp_hdr.s_id); uint32_t 4651 drivers/scsi/qla2xxx/qla_target.c uint32_t op_key = sid_to_key(op->atio.u.isp24.fcp_hdr.s_id); uint32_t 4660 drivers/scsi/qla2xxx/qla_target.c uint32_t cmd_key = sid_to_key(cmd->atio.u.isp24.fcp_hdr.s_id); uint32_t 5135 drivers/scsi/qla2xxx/qla_target.c uint32_t add_flags = 0; uint32_t 138 drivers/scsi/qla2xxx/qla_target.h uint32_t sys_define_2; /* System defined. */ uint32_t 148 drivers/scsi/qla2xxx/qla_target.h uint32_t srr_rel_offs; uint32_t 157 drivers/scsi/qla2xxx/qla_target.h uint32_t handle; uint32_t 165 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_address; uint32_t 166 drivers/scsi/qla2xxx/qla_target.h uint32_t srr_rel_offs; uint32_t 207 drivers/scsi/qla2xxx/qla_target.h uint32_t handle; /* System defined handle */ uint32_t 214 drivers/scsi/qla2xxx/qla_target.h uint32_t relative_offset; uint32_t 215 drivers/scsi/qla2xxx/qla_target.h uint32_t residual; uint32_t 218 drivers/scsi/qla2xxx/qla_target.h uint32_t transfer_length; uint32_t 260 drivers/scsi/qla2xxx/qla_target.h uint32_t parameter; uint32_t 275 drivers/scsi/qla2xxx/qla_target.h uint32_t parameter; uint32_t 322 drivers/scsi/qla2xxx/qla_target.h uint32_t sys_define_2; /* System defined. */ uint32_t 332 drivers/scsi/qla2xxx/qla_target.h uint32_t data_length; uint32_t 343 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_addr; uint32_t 355 drivers/scsi/qla2xxx/qla_target.h uint32_t signature; uint32_t 382 drivers/scsi/qla2xxx/qla_target.h return (be32_to_cpu(get_unaligned((uint32_t *) uint32_t 398 drivers/scsi/qla2xxx/qla_target.h uint32_t handle; /* System defined handle */ uint32_t 407 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_addr; uint32_t 412 drivers/scsi/qla2xxx/qla_target.h uint32_t residual; uint32_t 415 drivers/scsi/qla2xxx/qla_target.h uint32_t relative_offset; uint32_t 416 drivers/scsi/qla2xxx/qla_target.h uint32_t reserved2; uint32_t 417 drivers/scsi/qla2xxx/qla_target.h uint32_t transfer_length; uint32_t 418 drivers/scsi/qla2xxx/qla_target.h uint32_t reserved3; uint32_t 424 drivers/scsi/qla2xxx/qla_target.h uint32_t residual; uint32_t 443 drivers/scsi/qla2xxx/qla_target.h uint32_t handle; /* System defined handle */ uint32_t 449 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_address; uint32_t 452 drivers/scsi/qla2xxx/qla_target.h uint32_t residual; uint32_t 455 drivers/scsi/qla2xxx/qla_target.h uint32_t relative_offset; uint32_t 492 drivers/scsi/qla2xxx/qla_target.h uint32_t handle; /* System handle. */ uint32_t 503 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_addr; /* rcv exchange address */ uint32_t 506 drivers/scsi/qla2xxx/qla_target.h uint32_t residual; uint32_t 510 drivers/scsi/qla2xxx/qla_target.h uint32_t reserved5; uint32_t 512 drivers/scsi/qla2xxx/qla_target.h uint32_t reserved6; uint32_t 525 drivers/scsi/qla2xxx/qla_target.h uint32_t handle; /* System handle. */ uint32_t 529 drivers/scsi/qla2xxx/qla_target.h uint32_t reserved1; uint32_t 533 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_address; /* rcv exchange address */ uint32_t 536 drivers/scsi/qla2xxx/qla_target.h uint32_t resid_xfer_length; uint32_t 567 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_address; uint32_t 570 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_addr_to_abort; uint32_t 607 drivers/scsi/qla2xxx/qla_target.h uint32_t handle; uint32_t 615 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_address; uint32_t 621 drivers/scsi/qla2xxx/qla_target.h uint32_t reserved_4; uint32_t 622 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_addr_to_abort; uint32_t 637 drivers/scsi/qla2xxx/qla_target.h uint32_t handle; uint32_t 646 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_address; uint32_t 649 drivers/scsi/qla2xxx/qla_target.h uint32_t error_subcode1; uint32_t 651 drivers/scsi/qla2xxx/qla_target.h uint32_t error_subcode2; uint32_t 652 drivers/scsi/qla2xxx/qla_target.h uint32_t exchange_addr_to_abort; uint32_t 671 drivers/scsi/qla2xxx/qla_target.h unsigned char *, uint32_t, int, int, int); uint32_t 674 drivers/scsi/qla2xxx/qla_target.h uint32_t); uint32_t 690 drivers/scsi/qla2xxx/qla_target.h int (*chk_dif_tags)(uint32_t tag); uint32_t 819 drivers/scsi/qla2xxx/qla_target.h uint32_t chip_reset; uint32_t 860 drivers/scsi/qla2xxx/qla_target.h uint32_t reset_count; uint32_t 910 drivers/scsi/qla2xxx/qla_target.h uint32_t prot_sg_cnt; uint32_t 911 drivers/scsi/qla2xxx/qla_target.h uint32_t blk_sz, num_blks; uint32_t 918 drivers/scsi/qla2xxx/qla_target.h uint32_t a_ref_tag, e_ref_tag; uint32_t 956 drivers/scsi/qla2xxx/qla_target.h uint32_t reset_count; uint32_t 1033 drivers/scsi/qla2xxx/qla_target.h static inline uint32_t sid_to_key(const be_id_t s_id) uint32_t 25 drivers/scsi/qla2xxx/qla_tmpl.c qla27xx_insert32(uint32_t value, void *buf, ulong *len) uint32_t 69 drivers/scsi/qla2xxx/qla_tmpl.c uint32_t value = ~0; uint32_t 96 drivers/scsi/qla2xxx/qla_tmpl.c uint offset, uint32_t data, void *buf) uint32_t 107 drivers/scsi/qla2xxx/qla_tmpl.c uint32_t addr, uint offset, uint count, uint width, void *buf, uint32_t 313 drivers/scsi/qla2xxx/qla_tmpl.c *len += dwords * sizeof(uint32_t); uint32_t 531 drivers/scsi/qla2xxx/qla_tmpl.c qla27xx_insert32(*len + sizeof(uint32_t), buf, len); uint32_t 533 drivers/scsi/qla2xxx/qla_tmpl.c ent->t269.scratch_size = 5 * sizeof(uint32_t); uint32_t 552 drivers/scsi/qla2xxx/qla_tmpl.c addr += sizeof(uint32_t); uint32_t 589 drivers/scsi/qla2xxx/qla_tmpl.c *len += dwords * sizeof(uint32_t); uint32_t 600 drivers/scsi/qla2xxx/qla_tmpl.c uint32_t value; uint32_t 611 drivers/scsi/qla2xxx/qla_tmpl.c addr += sizeof(uint32_t); uint32_t 894 drivers/scsi/qla2xxx/qla_tmpl.c static inline uint32_t uint32_t 16 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t template_size; uint32_t 17 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t count; /* borrow field for running/residual count */ uint32_t 20 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t template_version; uint32_t 21 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t capture_timestamp; uint32_t 22 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t template_checksum; uint32_t 24 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t reserved_2; uint32_t 25 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t driver_info[3]; uint32_t 27 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t saved_state[16]; uint32_t 29 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t reserved_3[8]; uint32_t 30 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t firmware_version[5]; uint32_t 70 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t reserved_1; uint32_t 135 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t num_queues; uint32_t 141 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t fce_trace_size; uint32_t 144 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t fce_enable_mb0; uint32_t 145 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t fce_enable_mb2; uint32_t 146 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t fce_enable_mb3; uint32_t 147 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t fce_enable_mb4; uint32_t 148 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t fce_enable_mb5; uint32_t 149 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t fce_enable_mb6; uint32_t 167 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t buf_size; uint32_t 172 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t scratch_size; uint32_t 196 drivers/scsi/qla2xxx/qla_tmpl.h uint32_t num_queues; uint32_t 421 drivers/scsi/qla2xxx/tcm_qla2xxx.c unsigned char *cdb, uint32_t data_length, int fcp_task_attr, uint32_t 526 drivers/scsi/qla2xxx/tcm_qla2xxx.c static int tcm_qla2xxx_chk_dif_tags(uint32_t tag) uint32_t 549 drivers/scsi/qla2xxx/tcm_qla2xxx.c uint16_t tmr_func, uint32_t tag) uint32_t 16 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t qla4_83xx_rd_reg(struct scsi_qla_host *ha, ulong addr) uint32_t 21 drivers/scsi/qla4xxx/ql4_83xx.c void qla4_83xx_wr_reg(struct scsi_qla_host *ha, ulong addr, uint32_t val) uint32_t 26 drivers/scsi/qla4xxx/ql4_83xx.c static int qla4_83xx_set_win_base(struct scsi_qla_host *ha, uint32_t addr) uint32_t 28 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t val; uint32_t 42 drivers/scsi/qla4xxx/ql4_83xx.c int qla4_83xx_rd_reg_indirect(struct scsi_qla_host *ha, uint32_t addr, uint32_t 43 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t *data) uint32_t 60 drivers/scsi/qla4xxx/ql4_83xx.c int qla4_83xx_wr_reg_indirect(struct scsi_qla_host *ha, uint32_t addr, uint32_t 61 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t data) uint32_t 80 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t lock_status = 0; uint32_t 110 drivers/scsi/qla4xxx/ql4_83xx.c int qla4_83xx_flash_read_u32(struct scsi_qla_host *ha, uint32_t flash_addr, uint32_t 114 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t u32_word; uint32_t 115 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t addr = flash_addr; uint32_t 161 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t flash_addr, uint8_t *p_data, uint32_t 164 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t i; uint32_t 165 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t u32_word; uint32_t 166 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t flash_offset; uint32_t 167 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t addr = flash_addr; uint32_t 188 drivers/scsi/qla4xxx/ql4_83xx.c if ((flash_offset + (u32_word_count * sizeof(uint32_t))) > uint32_t 260 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t lock = 0, lockid; uint32_t 312 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t status = 0; uint32_t 314 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t first_owner = 0; uint32_t 315 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t tmo_owner = 0; uint32_t 316 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t lock_id; uint32_t 317 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t func_num; uint32_t 318 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t lock_cnt; uint32_t 396 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t idc_ctrl; uint32_t 407 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t idc_ctrl; uint32_t 418 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t idc_ctrl; uint32_t 441 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t drv_active; uint32_t 442 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t dev_part, dev_part1, dev_part2; uint32_t 512 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t dev_state, drv_state, drv_active; uint32_t 584 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t idc_params, ret_val; uint32_t 627 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t src, count, size; uint32_t 651 drivers/scsi/qla4xxx/ql4_83xx.c size / sizeof(uint32_t)); uint32_t 661 drivers/scsi/qla4xxx/ql4_83xx.c ret_val = qla4_8xxx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache, uint32_t 681 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t val, ret_val = QLA_ERROR; uint32_t 709 drivers/scsi/qla4xxx/ql4_83xx.c static int qla4_83xx_poll_reg(struct scsi_qla_host *ha, uint32_t addr, uint32_t 710 drivers/scsi/qla4xxx/ql4_83xx.c int duration, uint32_t test_mask, uint32_t 711 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t test_result) uint32_t 713 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t value; uint32_t 748 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t sum = 0; uint32_t 778 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size; uint32_t 779 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t ret_val; uint32_t 793 drivers/scsi/qla4xxx/ql4_83xx.c sizeof(uint32_t); uint32_t 812 drivers/scsi/qla4xxx/ql4_83xx.c tmplt_hdr_size = ha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t); uint32_t 823 drivers/scsi/qla4xxx/ql4_83xx.c ha->reset_tmplt.hdr->hdr_size) / sizeof(uint32_t); uint32_t 874 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t raddr, uint32_t waddr) uint32_t 876 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t value; uint32_t 893 drivers/scsi/qla4xxx/ql4_83xx.c static void qla4_83xx_rmw_crb_reg(struct scsi_qla_host *ha, uint32_t raddr, uint32_t 894 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t waddr, uint32_t 897 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t value; uint32_t 919 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t i; uint32_t 927 drivers/scsi/qla4xxx/ql4_83xx.c udelay((uint32_t)(p_hdr->delay)); uint32_t 935 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t i; uint32_t 943 drivers/scsi/qla4xxx/ql4_83xx.c udelay((uint32_t)(p_hdr->delay)); uint32_t 953 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t i; uint32_t 954 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t value; uint32_t 991 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t i; uint32_t 1022 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t i; uint32_t 1033 drivers/scsi/qla4xxx/ql4_83xx.c udelay((uint32_t)(p_hdr->delay)); uint32_t 1041 drivers/scsi/qla4xxx/ql4_83xx.c mdelay((uint32_t)((long)p_hdr->delay)); uint32_t 1051 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t i; uint32_t 1052 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t value; uint32_t 1205 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t idc_ctrl; uint32_t 1272 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t mb_int, ret; uint32_t 1298 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t mb_int; uint32_t 1316 drivers/scsi/qla4xxx/ql4_83xx.c void qla4_83xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, uint32_t 1351 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t dev_state; uint32_t 1584 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t drv_active; uint32_t 90 drivers/scsi/qla4xxx/ql4_83xx.h static const uint32_t qla4_83xx_reg_tbl[] = { uint32_t 233 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t array[QLA83XX_MAX_RESET_SEQ_ENTRIES]; uint32_t 246 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t select_addr; uint32_t 247 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t read_addr; uint32_t 248 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t select_value; uint32_t 251 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t poll_wait; uint32_t 252 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t poll_mask; uint32_t 253 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t data_size; uint32_t 254 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t rsvd_1; uint32_t 259 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t addr_1; uint32_t 260 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t value; uint32_t 264 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t poll; uint32_t 265 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t mask; uint32_t 266 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t modify_mask; uint32_t 267 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t data_size; uint32_t 268 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t rsvd; uint32_t 275 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t addr_1; uint32_t 276 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t addr_2; uint32_t 277 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t value_1; uint32_t 281 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t poll; uint32_t 282 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t mask; uint32_t 283 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t value_2; uint32_t 284 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t data_size; uint32_t 290 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t addr_1; uint32_t 291 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t addr_2; uint32_t 292 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t value_1; uint32_t 293 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t value_2; uint32_t 294 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t poll; uint32_t 295 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t mask; uint32_t 296 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t data_size; uint32_t 297 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t rsvd; uint32_t 304 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t select_addr_1; uint32_t 305 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t select_addr_2; uint32_t 306 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t select_value_1; uint32_t 307 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t select_value_2; uint32_t 308 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t op_count; uint32_t 309 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t select_value_mask; uint32_t 310 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t read_addr; uint32_t 319 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t addr_1; uint32_t 320 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t addr_2; uint32_t 321 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t value_1; uint32_t 322 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t value_2; uint32_t 323 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t poll_wait; uint32_t 324 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t poll_mask; uint32_t 325 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t modify_mask; uint32_t 326 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t data_size; uint32_t 331 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t request_desc; /* IDC request descriptor */ uint32_t 332 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t info1; /* IDC additional info */ uint32_t 333 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t info2; /* IDC additional info */ uint32_t 334 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t info3; /* IDC additional info */ uint32_t 350 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t desc_card_addr; uint32_t 353 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t start_dma_cmd; uint32_t 355 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t read_addr; uint32_t 356 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t read_data_size; uint32_t 361 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */ uint32_t 37 drivers/scsi/qla4xxx/ql4_attr.c uint32_t dev_state; uint32_t 19 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t offset = 0; uint32_t 20 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t length = 0; uint32_t 84 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t length = 0; uint32_t 85 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t offset = 0; uint32_t 86 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t options = 0; uint32_t 149 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t status[MBOX_REG_COUNT]; uint32_t 150 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t acb_idx; uint32_t 151 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t ip_idx; uint32_t 206 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t offset = 0; uint32_t 207 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t len = 0; uint32_t 208 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t total_len = 0; uint32_t 278 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t offset = 0; uint32_t 279 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t len = 0; uint32_t 280 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t total_len = 0; uint32_t 347 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t region = 0; uint32_t 348 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t field0 = 0; uint32_t 349 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t field1 = 0; uint32_t 391 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t acb_type = 0; uint32_t 392 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t len = 0; uint32_t 456 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 457 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 471 drivers/scsi/qla4xxx/ql4_bsg.c sizeof(uint32_t) * MBOX_REG_COUNT); uint32_t 558 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t *mbox_cmd) uint32_t 560 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t config = 0; uint32_t 609 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t *mbox_cmd) uint32_t 612 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t config = 0; uint32_t 660 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 661 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 684 drivers/scsi/qla4xxx/ql4_bsg.c sizeof(uint32_t) * MBOX_REG_COUNT); uint32_t 758 drivers/scsi/qla4xxx/ql4_bsg.c uint32_t diag_cmd; uint32_t 13 drivers/scsi/qla4xxx/ql4_dbg.c void qla4xxx_dump_buffer(void *b, uint32_t size) uint32_t 15 drivers/scsi/qla4xxx/ql4_dbg.c uint32_t cnt; uint32_t 137 drivers/scsi/qla4xxx/ql4_dbg.c uint32_t halt_status1, halt_status2; uint32_t 266 drivers/scsi/qla4xxx/ql4_def.h uint32_t mbox_cmd; uint32_t 268 drivers/scsi/qla4xxx/ql4_def.h uint32_t pid; uint32_t 275 drivers/scsi/qla4xxx/ql4_def.h uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; uint32_t 292 drivers/scsi/qla4xxx/ql4_def.h uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ uint32_t 298 drivers/scsi/qla4xxx/ql4_def.h int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index, uint32_t 299 drivers/scsi/qla4xxx/ql4_def.h struct ddb_entry *ddb_entry, uint32_t state); uint32_t 313 drivers/scsi/qla4xxx/ql4_def.h uint32_t default_time2wait; /* Default Min time between uint32_t 369 drivers/scsi/qla4xxx/ql4_def.h uint32_t data_size; uint32_t 373 drivers/scsi/qla4xxx/ql4_def.h uint32_t status; uint32_t 374 drivers/scsi/qla4xxx/ql4_def.h uint32_t pid; uint32_t 375 drivers/scsi/qla4xxx/ql4_def.h uint32_t data_size; uint32_t 383 drivers/scsi/qla4xxx/ql4_def.h uint32_t flash_conf_off; uint32_t 384 drivers/scsi/qla4xxx/ql4_def.h uint32_t flash_data_off; uint32_t 386 drivers/scsi/qla4xxx/ql4_def.h uint32_t fdt_wrt_disable; uint32_t 387 drivers/scsi/qla4xxx/ql4_def.h uint32_t fdt_erase_cmd; uint32_t 388 drivers/scsi/qla4xxx/ql4_def.h uint32_t fdt_block_size; uint32_t 389 drivers/scsi/qla4xxx/ql4_def.h uint32_t fdt_unprotect_sec_cmd; uint32_t 390 drivers/scsi/qla4xxx/ql4_def.h uint32_t fdt_protect_sec_cmd; uint32_t 392 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_region_flt; uint32_t 393 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_region_fdt; uint32_t 394 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_region_boot; uint32_t 395 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_region_bootload; uint32_t 396 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_region_fw; uint32_t 398 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_iscsi_param; uint32_t 399 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_region_chap; uint32_t 400 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_chap_size; uint32_t 401 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_region_ddb; uint32_t 402 drivers/scsi/qla4xxx/ql4_def.h uint32_t flt_ddb_size; uint32_t 406 drivers/scsi/qla4xxx/ql4_def.h uint32_t int_vec_bit; uint32_t 407 drivers/scsi/qla4xxx/ql4_def.h uint32_t tgt_status_reg; uint32_t 408 drivers/scsi/qla4xxx/ql4_def.h uint32_t tgt_mask_reg; uint32_t 409 drivers/scsi/qla4xxx/ql4_def.h uint32_t pci_int_reg; uint32_t 426 drivers/scsi/qla4xxx/ql4_def.h void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); uint32_t 435 drivers/scsi/qla4xxx/ql4_def.h uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong); uint32_t 436 drivers/scsi/qla4xxx/ql4_def.h void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t); uint32_t 437 drivers/scsi/qla4xxx/ql4_def.h int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *); uint32_t 438 drivers/scsi/qla4xxx/ql4_def.h int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t); uint32_t 442 drivers/scsi/qla4xxx/ql4_def.h void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int); uint32_t 447 drivers/scsi/qla4xxx/ql4_def.h uint32_t size; uint32_t 448 drivers/scsi/qla4xxx/ql4_def.h uint32_t size_cmask_02; uint32_t 449 drivers/scsi/qla4xxx/ql4_def.h uint32_t size_cmask_04; uint32_t 450 drivers/scsi/qla4xxx/ql4_def.h uint32_t size_cmask_08; uint32_t 451 drivers/scsi/qla4xxx/ql4_def.h uint32_t size_cmask_10; uint32_t 452 drivers/scsi/qla4xxx/ql4_def.h uint32_t size_cmask_FF; uint32_t 453 drivers/scsi/qla4xxx/ql4_def.h uint32_t version; uint32_t 465 drivers/scsi/qla4xxx/ql4_def.h uint32_t ipv6_options; uint32_t 466 drivers/scsi/qla4xxx/ql4_def.h uint32_t ipv6_addl_options; uint32_t 494 drivers/scsi/qla4xxx/ql4_def.h uint32_t ipv6_nd_reach_time; uint32_t 495 drivers/scsi/qla4xxx/ql4_def.h uint32_t ipv6_nd_rexmit_timer; uint32_t 496 drivers/scsi/qla4xxx/ql4_def.h uint32_t ipv6_nd_stale_timeout; uint32_t 498 drivers/scsi/qla4xxx/ql4_def.h uint32_t ipv6_gw_advrt_mtu; uint32_t 595 drivers/scsi/qla4xxx/ql4_def.h uint32_t tot_ddbs; uint32_t 619 drivers/scsi/qla4xxx/ql4_def.h uint32_t eeprom_cmd_data; uint32_t 629 drivers/scsi/qla4xxx/ql4_def.h uint32_t bytes_xfered; uint32_t 630 drivers/scsi/qla4xxx/ql4_def.h uint32_t spurious_int_count; uint32_t 631 drivers/scsi/qla4xxx/ql4_def.h uint32_t aborted_io_count; uint32_t 632 drivers/scsi/qla4xxx/ql4_def.h uint32_t io_timeout_count; uint32_t 633 drivers/scsi/qla4xxx/ql4_def.h uint32_t mailbox_timeout_count; uint32_t 634 drivers/scsi/qla4xxx/ql4_def.h uint32_t seconds_since_last_intr; uint32_t 635 drivers/scsi/qla4xxx/ql4_def.h uint32_t seconds_since_last_heartbeat; uint32_t 636 drivers/scsi/qla4xxx/ql4_def.h uint32_t mac_index; uint32_t 640 drivers/scsi/qla4xxx/ql4_def.h uint32_t firmware_version[2]; uint32_t 641 drivers/scsi/qla4xxx/ql4_def.h uint32_t patch_number; uint32_t 642 drivers/scsi/qla4xxx/ql4_def.h uint32_t build_number; uint32_t 643 drivers/scsi/qla4xxx/ql4_def.h uint32_t board_id; uint32_t 657 drivers/scsi/qla4xxx/ql4_def.h uint32_t firmware_state; uint32_t 658 drivers/scsi/qla4xxx/ql4_def.h uint32_t addl_fw_state; uint32_t 666 drivers/scsi/qla4xxx/ql4_def.h uint32_t timer_active; uint32_t 670 drivers/scsi/qla4xxx/ql4_def.h uint32_t retry_reset_ha_cnt; uint32_t 671 drivers/scsi/qla4xxx/ql4_def.h uint32_t isp_reset_timer; /* reset test timer */ uint32_t 672 drivers/scsi/qla4xxx/ql4_def.h uint32_t nic_reset_timer; /* simulated nic reset test timer */ uint32_t 715 drivers/scsi/qla4xxx/ql4_def.h volatile uint32_t mbox_status[MBOX_REG_COUNT]; uint32_t 733 drivers/scsi/qla4xxx/ql4_def.h uint32_t crb_win; uint32_t 734 drivers/scsi/qla4xxx/ql4_def.h uint32_t curr_window; uint32_t 735 drivers/scsi/qla4xxx/ql4_def.h uint32_t ddr_mn_window; uint32_t 747 drivers/scsi/qla4xxx/ql4_def.h uint32_t fw_heartbeat_counter; uint32_t 752 drivers/scsi/qla4xxx/ql4_def.h uint32_t nx_dev_init_timeout; uint32_t 753 drivers/scsi/qla4xxx/ql4_def.h uint32_t nx_reset_timeout; uint32_t 755 drivers/scsi/qla4xxx/ql4_def.h uint32_t fw_dump_size; uint32_t 756 drivers/scsi/qla4xxx/ql4_def.h uint32_t fw_dump_capture_mask; uint32_t 758 drivers/scsi/qla4xxx/ql4_def.h uint32_t fw_dump_tmplt_size; uint32_t 759 drivers/scsi/qla4xxx/ql4_def.h uint32_t fw_dump_skip_size; uint32_t 770 drivers/scsi/qla4xxx/ql4_def.h uint32_t fw_uptime_secs; /* seconds elapsed since fw bootup */ uint32_t 771 drivers/scsi/qla4xxx/ql4_def.h uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */ uint32_t 774 drivers/scsi/qla4xxx/ql4_def.h uint32_t flash_state; uint32_t 807 drivers/scsi/qla4xxx/ql4_def.h uint32_t mrb_index; uint32_t 809 drivers/scsi/qla4xxx/ql4_def.h uint32_t *reg_tbl; uint32_t 814 drivers/scsi/qla4xxx/ql4_def.h uint32_t pf_bit; uint32_t 830 drivers/scsi/qla4xxx/ql4_def.h uint32_t req_len; uint32_t 833 drivers/scsi/qla4xxx/ql4_def.h uint32_t resp_len; uint32_t 1047 drivers/scsi/qla4xxx/ql4_def.h const uint32_t crb_reg) uint32_t 1053 drivers/scsi/qla4xxx/ql4_def.h const uint32_t crb_reg, uint32_t 1054 drivers/scsi/qla4xxx/ql4_def.h const uint32_t value) uint32_t 200 drivers/scsi/qla4xxx/ql4_fw.h static inline uint32_t set_rmask(uint32_t val) uint32_t 206 drivers/scsi/qla4xxx/ql4_fw.h static inline uint32_t clr_rmask(uint32_t val) uint32_t 278 drivers/scsi/qla4xxx/ql4_fw.h uint32_t Asuint32_t; uint32_t 312 drivers/scsi/qla4xxx/ql4_fw.h uint32_t block_size; uint32_t 313 drivers/scsi/qla4xxx/ql4_fw.h uint32_t alt_block_size; uint32_t 314 drivers/scsi/qla4xxx/ql4_fw.h uint32_t flash_size; uint32_t 315 drivers/scsi/qla4xxx/ql4_fw.h uint32_t wrt_enable_data; uint32_t 356 drivers/scsi/qla4xxx/ql4_fw.h uint32_t code; uint32_t 357 drivers/scsi/qla4xxx/ql4_fw.h uint32_t size; uint32_t 358 drivers/scsi/qla4xxx/ql4_fw.h uint32_t start; uint32_t 359 drivers/scsi/qla4xxx/ql4_fw.h uint32_t end; uint32_t 585 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rqq_addr_lo; /* 18-1B */ uint32_t 586 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rqq_addr_hi; /* 1C-1F */ uint32_t 587 drivers/scsi/qla4xxx/ql4_fw.h uint32_t compq_addr_lo; /* 20-23 */ uint32_t 588 drivers/scsi/qla4xxx/ql4_fw.h uint32_t compq_addr_hi; /* 24-27 */ uint32_t 589 drivers/scsi/qla4xxx/ql4_fw.h uint32_t shdwreg_addr_lo; /* 28-2B */ uint32_t 590 drivers/scsi/qla4xxx/ql4_fw.h uint32_t shdwreg_addr_hi; /* 2C-2F */ uint32_t 645 drivers/scsi/qla4xxx/ql4_fw.h uint32_t res5; /* 4C-4F */ uint32_t 674 drivers/scsi/qla4xxx/ql4_fw.h uint32_t cookie; /* 200-203 */ uint32_t 713 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ipv6_nd_reach_time; /* 250-253 */ uint32_t 714 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ uint32_t 715 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ipv6_nd_stale_timeout; /* 258-25B */ uint32_t 719 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ uint32_t 778 drivers/scsi/qla4xxx/ql4_fw.h uint32_t cookie; /* 200-203 */ uint32_t 796 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ipv6_nd_reach_time; /* 250-253 */ uint32_t 797 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ uint32_t 798 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ipv6_nd_stale_timeout; /* 258-25B */ uint32_t 802 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ uint32_t 874 drivers/scsi/qla4xxx/ql4_fw.h uint32_t res1; /* 10-13 */ uint32_t 910 drivers/scsi/qla4xxx/ql4_fw.h uint32_t stat_sn; /* 1C8-1CB */ uint32_t 911 drivers/scsi/qla4xxx/ql4_fw.h uint32_t exp_stat_sn; /* 1CC-1CF */ uint32_t 942 drivers/scsi/qla4xxx/ql4_fw.h uint32_t cookie; /* 00-03 */ uint32_t 943 drivers/scsi/qla4xxx/ql4_fw.h uint32_t physAddrCount; /* 04-07 */ uint32_t 947 drivers/scsi/qla4xxx/ql4_fw.h uint32_t serialNumber; /* 128-12B */ uint32_t 950 drivers/scsi/qla4xxx/ql4_fw.h uint32_t pciDeviceVendor; /* 12C-12F */ uint32_t 951 drivers/scsi/qla4xxx/ql4_fw.h uint32_t pciDeviceId; /* 130-133 */ uint32_t 952 drivers/scsi/qla4xxx/ql4_fw.h uint32_t pciSubsysVendor; /* 134-137 */ uint32_t 953 drivers/scsi/qla4xxx/ql4_fw.h uint32_t pciSubsysId; /* 138-13B */ uint32_t 956 drivers/scsi/qla4xxx/ql4_fw.h uint32_t crumbs; /* 13C-13F */ uint32_t 958 drivers/scsi/qla4xxx/ql4_fw.h uint32_t enterpriseNumber; /* 140-143 */ uint32_t 960 drivers/scsi/qla4xxx/ql4_fw.h uint32_t mtu; /* 144-147 */ uint32_t 961 drivers/scsi/qla4xxx/ql4_fw.h uint32_t reserved0; /* 148-14b */ uint32_t 962 drivers/scsi/qla4xxx/ql4_fw.h uint32_t crumbs2; /* 14c-14f */ uint32_t 964 drivers/scsi/qla4xxx/ql4_fw.h uint32_t crumbs3; /* 160-16f */ uint32_t 969 drivers/scsi/qla4xxx/ql4_fw.h uint32_t reserved1[39]; /* 170-1ff */ uint32_t 980 drivers/scsi/qla4xxx/ql4_fw.h uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */ uint32_t 981 drivers/scsi/qla4xxx/ql4_fw.h uint32_t pci_func; /* 20-23 this PCI function */ uint32_t 1020 drivers/scsi/qla4xxx/ql4_fw.h uint32_t time_of_crash_in_secs; /* 48 - 4B */ uint32_t 1021 drivers/scsi/qla4xxx/ql4_fw.h uint32_t time_of_crash_in_ms; /* 4C - 4F */ uint32_t 1037 drivers/scsi/qla4xxx/ql4_fw.h uint32_t timestamp_sec; /* 00 - 03 seconds since boot */ uint32_t 1038 drivers/scsi/qla4xxx/ql4_fw.h uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */ uint32_t 1081 drivers/scsi/qla4xxx/ql4_fw.h uint32_t signature; uint32_t 1094 drivers/scsi/qla4xxx/ql4_fw.h uint32_t addrLow; uint32_t 1095 drivers/scsi/qla4xxx/ql4_fw.h uint32_t addrHigh; uint32_t 1099 drivers/scsi/qla4xxx/ql4_fw.h uint32_t count; uint32_t 1108 drivers/scsi/qla4xxx/ql4_fw.h uint32_t handle; /* 04-07 */ uint32_t 1134 drivers/scsi/qla4xxx/ql4_fw.h uint32_t cmdSeqNum; /* 28-2B */ uint32_t 1137 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ttlByteCnt; /* 30-33 */ uint32_t 1162 drivers/scsi/qla4xxx/ql4_fw.h uint32_t system_defined; /* 04-07 */ uint32_t 1182 drivers/scsi/qla4xxx/ql4_fw.h uint32_t handle; /* 04-07 */ uint32_t 1212 drivers/scsi/qla4xxx/ql4_fw.h uint32_t residualByteCnt; /* 10-13 */ uint32_t 1213 drivers/scsi/qla4xxx/ql4_fw.h uint32_t bidiResidualByteCnt; /* 14-17 */ uint32_t 1214 drivers/scsi/qla4xxx/ql4_fw.h uint32_t expSeqNum; /* 18-1B */ uint32_t 1215 drivers/scsi/qla4xxx/ql4_fw.h uint32_t maxCmdSeqNum; /* 1C-1F */ uint32_t 1228 drivers/scsi/qla4xxx/ql4_fw.h uint32_t handle; /* 04-07 */ uint32_t 1244 drivers/scsi/qla4xxx/ql4_fw.h uint32_t res1; /* 1C-1F */ uint32_t 1251 drivers/scsi/qla4xxx/ql4_fw.h uint32_t handle; /* 04-07 */ uint32_t 1263 drivers/scsi/qla4xxx/ql4_fw.h uint32_t outResidual; /* 1C-1F */ uint32_t 1265 drivers/scsi/qla4xxx/ql4_fw.h uint32_t inResidual; /* 2C-2F */ uint32_t 1271 drivers/scsi/qla4xxx/ql4_fw.h uint32_t handle; /* 04-07 */ uint32_t 1272 drivers/scsi/qla4xxx/ql4_fw.h uint32_t in_mbox[8]; /* 08-25 */ uint32_t 1273 drivers/scsi/qla4xxx/ql4_fw.h uint32_t res1[6]; /* 26-3F */ uint32_t 1278 drivers/scsi/qla4xxx/ql4_fw.h uint32_t handle; /* 04-07 */ uint32_t 1279 drivers/scsi/qla4xxx/ql4_fw.h uint32_t out_mbox[8]; /* 08-25 */ uint32_t 1280 drivers/scsi/qla4xxx/ql4_fw.h uint32_t res1[6]; /* 26-3F */ uint32_t 1288 drivers/scsi/qla4xxx/ql4_fw.h uint32_t signature; uint32_t 1375 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_cmd_pdu; /* 0290-0293 */ uint32_t 1376 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_resp_pdu; /* 0294-0297 */ uint32_t 1377 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_cmd_pdu; /* 0298-029B */ uint32_t 1378 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_resp_pdu; /* 029C-029F */ uint32_t 1383 drivers/scsi/qla4xxx/ql4_fw.h uint32_t hdr_digest_err; /* 02B0–02B3 */ uint32_t 1384 drivers/scsi/qla4xxx/ql4_fw.h uint32_t data_digest_err; /* 02B4–02B7 */ uint32_t 1385 drivers/scsi/qla4xxx/ql4_fw.h uint32_t conn_timeout_err; /* 02B8–02BB */ uint32_t 1386 drivers/scsi/qla4xxx/ql4_fw.h uint32_t framing_err; /* 02BC–02BF */ uint32_t 1388 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_nopout_pdus; /* 02C0–02C3 */ uint32_t 1389 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_scsi_cmd_pdus; /* 02C4–02C7 */ uint32_t 1390 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */ uint32_t 1391 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_login_cmd_pdus; /* 02CC–02CF */ uint32_t 1392 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */ uint32_t 1393 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */ uint32_t 1394 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */ uint32_t 1395 drivers/scsi/qla4xxx/ql4_fw.h uint32_t tx_snack_req_pdus; /* 02DC–02DF */ uint32_t 1397 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_nopin_pdus; /* 02E0–02E3 */ uint32_t 1398 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */ uint32_t 1399 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */ uint32_t 1400 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_login_resp_pdus; /* 02EC–02EF */ uint32_t 1401 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_text_resp_pdus; /* 02F0–02F3 */ uint32_t 1402 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */ uint32_t 1403 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_logout_resp_pdus; /* 02F8–02FB */ uint32_t 1405 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_r2t_pdus; /* 02FC–02FF */ uint32_t 1406 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_async_pdus; /* 0300–0303 */ uint32_t 1407 drivers/scsi/qla4xxx/ql4_fw.h uint32_t rx_reject_pdus; /* 0304–0307 */ uint32_t 1423 drivers/scsi/qla4xxx/ql4_fw.h uint32_t entry_type; uint32_t 1424 drivers/scsi/qla4xxx/ql4_fw.h uint32_t first_entry_offset; uint32_t 1425 drivers/scsi/qla4xxx/ql4_fw.h uint32_t size_of_template; uint32_t 1426 drivers/scsi/qla4xxx/ql4_fw.h uint32_t capture_debug_level; uint32_t 1427 drivers/scsi/qla4xxx/ql4_fw.h uint32_t num_of_entries; uint32_t 1428 drivers/scsi/qla4xxx/ql4_fw.h uint32_t version; uint32_t 1429 drivers/scsi/qla4xxx/ql4_fw.h uint32_t driver_timestamp; uint32_t 1430 drivers/scsi/qla4xxx/ql4_fw.h uint32_t checksum; uint32_t 1432 drivers/scsi/qla4xxx/ql4_fw.h uint32_t driver_capture_mask; uint32_t 1433 drivers/scsi/qla4xxx/ql4_fw.h uint32_t driver_info_word2; uint32_t 1434 drivers/scsi/qla4xxx/ql4_fw.h uint32_t driver_info_word3; uint32_t 1435 drivers/scsi/qla4xxx/ql4_fw.h uint32_t driver_info_word4; uint32_t 1437 drivers/scsi/qla4xxx/ql4_fw.h uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN]; uint32_t 1438 drivers/scsi/qla4xxx/ql4_fw.h uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN]; uint32_t 1439 drivers/scsi/qla4xxx/ql4_fw.h uint32_t ocm_window_reg[QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN]; uint32_t 1440 drivers/scsi/qla4xxx/ql4_fw.h uint32_t capabilities[QLA80XX_TEMPLATE_RESERVED_BITS]; uint32_t 30 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t offset, uint32_t len); uint32_t 41 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *num_valid_ddb_entries, uint32_t 42 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *next_ddb_index, uint32_t 43 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *fw_ddb_device_state, uint32_t 44 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *conn_err_detail, uint32_t 49 drivers/scsi/qla4xxx/ql4_glbl.h dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts); uint32_t 50 drivers/scsi/qla4xxx/ql4_glbl.h uint8_t qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, uint32_t 51 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma); uint32_t 57 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, uint32_t 58 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *mbox_sts, dma_addr_t acb_dma); uint32_t 60 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t acb_type, uint32_t len); uint32_t 61 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx, uint32_t 62 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t ip_idx, uint32_t *sts); uint32_t 70 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t intr_status); uint32_t 74 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t index); uint32_t 75 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_process_ddb_changed(struct scsi_qla_host *ha, uint32_t fw_ddb_index, uint32_t 76 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t state, uint32_t conn_error); uint32_t 77 drivers/scsi/qla4xxx/ql4_glbl.h void qla4xxx_dump_buffer(void *b, uint32_t size); uint32_t 81 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t offset, uint32_t length, uint32_t options); uint32_t 83 drivers/scsi/qla4xxx/ql4_glbl.h uint8_t outCount, uint32_t *mbx_cmd, uint32_t *mbx_sts); uint32_t 106 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *mbox_cmd, uint32_t 107 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *mbox_sts, uint32_t 122 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t qla4_82xx_rd_32(struct scsi_qla_host *, ulong); uint32_t 127 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t intr_status); uint32_t 152 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *mbx_sts); uint32_t 155 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t fw_ddb_index, uint32_t 156 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *mbx_sts); uint32_t 157 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t fw_ddb_index); uint32_t 172 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t offset, uint32_t size); uint32_t 174 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t offset, uint32_t size); uint32_t 176 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t region, uint32_t field0, uint32_t 177 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t field1); uint32_t 182 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_flash_ddb_change(struct scsi_qla_host *ha, uint32_t fw_ddb_index, uint32_t 183 drivers/scsi/qla4xxx/ql4_glbl.h struct ddb_entry *ddb_entry, uint32_t state); uint32_t 184 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_ddb_change(struct scsi_qla_host *ha, uint32_t fw_ddb_index, uint32_t 185 drivers/scsi/qla4xxx/ql4_glbl.h struct ddb_entry *ddb_entry, uint32_t state); uint32_t 189 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t data_size, uint8_t *data); uint32_t 190 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_ping_iocb(struct scsi_qla_host *ha, uint32_t options, uint32_t 191 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t payload_size, uint32_t pid, uint8_t *ipaddr); uint32_t 193 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t status, uint32_t pid, uint32_t 194 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t data_size, uint8_t *data); uint32_t 212 drivers/scsi/qla4xxx/ql4_glbl.h int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data); uint32_t 213 drivers/scsi/qla4xxx/ql4_glbl.h int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data); uint32_t 215 drivers/scsi/qla4xxx/ql4_glbl.h void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, uint32_t 218 drivers/scsi/qla4xxx/ql4_glbl.h void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, uint32_t 227 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t intr_status); uint32_t 231 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t qla4_83xx_rd_reg(struct scsi_qla_host *ha, ulong addr); uint32_t 232 drivers/scsi/qla4xxx/ql4_glbl.h void qla4_83xx_wr_reg(struct scsi_qla_host *ha, ulong addr, uint32_t val); uint32_t 233 drivers/scsi/qla4xxx/ql4_glbl.h int qla4_83xx_rd_reg_indirect(struct scsi_qla_host *ha, uint32_t addr, uint32_t 234 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *data); uint32_t 235 drivers/scsi/qla4xxx/ql4_glbl.h int qla4_83xx_wr_reg_indirect(struct scsi_qla_host *ha, uint32_t addr, uint32_t 236 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t data); uint32_t 240 drivers/scsi/qla4xxx/ql4_glbl.h void qla4_83xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, uint32_t 247 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t flash_addr, uint8_t *p_data, uint32_t 251 drivers/scsi/qla4xxx/ql4_glbl.h int qla4_83xx_flash_read_u32(struct scsi_qla_host *ha, uint32_t flash_addr, uint32_t 266 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options, uint32_t 271 drivers/scsi/qla4xxx/ql4_glbl.h int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, uint32_t 272 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t *mbox_sts, dma_addr_t acb_dma); uint32_t 274 drivers/scsi/qla4xxx/ql4_glbl.h uint32_t acb_type, uint32_t len); uint32_t 277 drivers/scsi/qla4xxx/ql4_glbl.h uint64_t addr, uint32_t *data, uint32_t count); uint32_t 279 drivers/scsi/qla4xxx/ql4_glbl.h int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config); uint32_t 280 drivers/scsi/qla4xxx/ql4_glbl.h int qla4_83xx_set_port_config(struct scsi_qla_host *ha, uint32_t *config); uint32_t 16 drivers/scsi/qla4xxx/ql4_init.c uint32_t value; uint32_t 290 drivers/scsi/qla4xxx/ql4_init.c uint32_t *cap_offset; uint32_t 292 drivers/scsi/qla4xxx/ql4_init.c cap_offset = (uint32_t *)((char *)md_hdr + offset); uint32_t 310 drivers/scsi/qla4xxx/ql4_init.c uint32_t capture_debug_level; uint32_t 406 drivers/scsi/qla4xxx/ql4_init.c uint32_t timeout_count; uint32_t 686 drivers/scsi/qla4xxx/ql4_init.c uint32_t mbox_status; uint32_t 721 drivers/scsi/qla4xxx/ql4_init.c uint32_t ctrl_status; uint32_t 793 drivers/scsi/qla4xxx/ql4_init.c uint32_t mbox_status; uint32_t 916 drivers/scsi/qla4xxx/ql4_init.c uint32_t idx = 0, next_idx = 0; uint32_t 917 drivers/scsi/qla4xxx/ql4_init.c uint32_t state = 0, conn_err = 0; uint32_t 1000 drivers/scsi/qla4xxx/ql4_init.c int qla4xxx_ddb_change(struct scsi_qla_host *ha, uint32_t fw_ddb_index, uint32_t 1001 drivers/scsi/qla4xxx/ql4_init.c struct ddb_entry *ddb_entry, uint32_t state) uint32_t 1003 drivers/scsi/qla4xxx/ql4_init.c uint32_t old_fw_ddb_device_state; uint32_t 1094 drivers/scsi/qla4xxx/ql4_init.c int qla4xxx_flash_ddb_change(struct scsi_qla_host *ha, uint32_t fw_ddb_index, uint32_t 1095 drivers/scsi/qla4xxx/ql4_init.c struct ddb_entry *ddb_entry, uint32_t state) uint32_t 1097 drivers/scsi/qla4xxx/ql4_init.c uint32_t old_fw_ddb_device_state; uint32_t 1166 drivers/scsi/qla4xxx/ql4_init.c uint32_t fw_ddb_index, uint32_t 1167 drivers/scsi/qla4xxx/ql4_init.c uint32_t state, uint32_t conn_err) uint32_t 1209 drivers/scsi/qla4xxx/ql4_init.c uint32_t mbx_sts = 0; uint32_t 22 drivers/scsi/qla4xxx/ql4_inline.h qla4xxx_lookup_ddb_by_fw_index(struct scsi_qla_host *ha, uint32_t fw_ddb_index) uint32_t 216 drivers/scsi/qla4xxx/ql4_iocb.c uint32_t dbval = 0; uint32_t 282 drivers/scsi/qla4xxx/ql4_iocb.c uint32_t index; uint32_t 292 drivers/scsi/qla4xxx/ql4_iocb.c index = (uint32_t)cmd->request->tag; uint32_t 464 drivers/scsi/qla4xxx/ql4_iocb.c uint32_t *in_mbox) uint32_t 467 drivers/scsi/qla4xxx/ql4_iocb.c uint32_t i; uint32_t 469 drivers/scsi/qla4xxx/ql4_iocb.c uint32_t index = 0; uint32_t 507 drivers/scsi/qla4xxx/ql4_iocb.c int qla4xxx_ping_iocb(struct scsi_qla_host *ha, uint32_t options, uint32_t 508 drivers/scsi/qla4xxx/ql4_iocb.c uint32_t payload_size, uint32_t pid, uint8_t *ipaddr) uint32_t 510 drivers/scsi/qla4xxx/ql4_iocb.c uint32_t in_mbox[8]; uint32_t 122 drivers/scsi/qla4xxx/ql4_isr.c uint32_t residual; uint32_t 373 drivers/scsi/qla4xxx/ql4_isr.c uint32_t fw_ddb_index; uint32_t 404 drivers/scsi/qla4xxx/ql4_isr.c uint32_t index) uint32_t 427 drivers/scsi/qla4xxx/ql4_isr.c uint32_t status; uint32_t 428 drivers/scsi/qla4xxx/ql4_isr.c uint32_t data_size; uint32_t 476 drivers/scsi/qla4xxx/ql4_isr.c uint32_t count = 0; uint32_t 610 drivers/scsi/qla4xxx/ql4_isr.c uint32_t ipaddr_idx, uint32_t 611 drivers/scsi/qla4xxx/ql4_isr.c uint32_t ipaddr_fw_state) uint32_t 639 drivers/scsi/qla4xxx/ql4_isr.c uint32_t *mbox_sts) uint32_t 642 drivers/scsi/qla4xxx/ql4_isr.c &mbox_sts[2], sizeof(uint32_t)); uint32_t 644 drivers/scsi/qla4xxx/ql4_isr.c &mbox_sts[3], sizeof(uint32_t)); uint32_t 646 drivers/scsi/qla4xxx/ql4_isr.c &mbox_sts[4], sizeof(uint32_t)); uint32_t 648 drivers/scsi/qla4xxx/ql4_isr.c &mbox_sts[5], sizeof(uint32_t)); uint32_t 660 drivers/scsi/qla4xxx/ql4_isr.c uint32_t mbox_status) uint32_t 663 drivers/scsi/qla4xxx/ql4_isr.c uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; uint32_t 665 drivers/scsi/qla4xxx/ql4_isr.c uint32_t opcode = 0; uint32_t 1028 drivers/scsi/qla4xxx/ql4_isr.c uint32_t intr_status) uint32_t 1052 drivers/scsi/qla4xxx/ql4_isr.c uint32_t intr_status) uint32_t 1077 drivers/scsi/qla4xxx/ql4_isr.c uint32_t intr_status) uint32_t 1125 drivers/scsi/qla4xxx/ql4_isr.c uint32_t intr_status; uint32_t 1221 drivers/scsi/qla4xxx/ql4_isr.c uint32_t intr_status; uint32_t 1222 drivers/scsi/qla4xxx/ql4_isr.c uint32_t status; uint32_t 1287 drivers/scsi/qla4xxx/ql4_isr.c uint32_t leg_int_ptr = 0; uint32_t 1356 drivers/scsi/qla4xxx/ql4_isr.c uint32_t ival = 0; uint32_t 1396 drivers/scsi/qla4xxx/ql4_isr.c uint32_t intr_status; uint32_t 1434 drivers/scsi/qla4xxx/ql4_isr.c uint32_t ival = 0; uint32_t 1476 drivers/scsi/qla4xxx/ql4_isr.c uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; uint32_t 15 drivers/scsi/qla4xxx/ql4_mbx.c void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, uint32_t 84 drivers/scsi/qla4xxx/ql4_mbx.c uint8_t outCount, uint32_t *mbx_cmd, uint32_t 85 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *mbx_sts) uint32_t 91 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t dev_state; uint32_t 287 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 288 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 318 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 319 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 372 drivers/scsi/qla4xxx/ql4_mbx.c qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, uint32_t 373 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma) uint32_t 399 drivers/scsi/qla4xxx/ql4_mbx.c qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, uint32_t 400 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma) uint32_t 585 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *mbox_cmd, uint32_t 586 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *mbox_sts, uint32_t 624 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 625 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 706 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 707 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 743 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 744 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 774 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 775 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 826 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *num_valid_ddb_entries, uint32_t 827 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *next_ddb_index, uint32_t 828 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *fw_ddb_device_state, uint32_t 829 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *conn_err_detail, uint32_t 835 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 836 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 850 drivers/scsi/qla4xxx/ql4_mbx.c mbox_cmd[1] = (uint32_t) fw_ddb_index; uint32_t 918 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 919 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 947 drivers/scsi/qla4xxx/ql4_mbx.c dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts) uint32_t 949 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 950 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 960 drivers/scsi/qla4xxx/ql4_mbx.c mbox_cmd[1] = (uint32_t) fw_ddb_index; uint32_t 979 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 980 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1013 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1014 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1017 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t crash_record_size = 0; uint32_t 1071 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1072 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1075 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t event_log_size = 0; uint32_t 1076 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t num_valid_entries; uint32_t 1077 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t oldest_entry = 0; uint32_t 1078 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t max_event_log_entries; uint32_t 1170 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1171 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1175 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t index; uint32_t 1225 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1226 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1227 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t scsi_lun[2]; uint32_t 1272 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1273 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1300 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t offset, uint32_t len) uint32_t 1302 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1303 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1336 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1337 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1397 drivers/scsi/qla4xxx/ql4_mbx.c int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options, uint32_t 1400 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1401 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1420 drivers/scsi/qla4xxx/ql4_mbx.c int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index, uint32_t 1421 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *mbx_sts) uint32_t 1424 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1425 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1444 drivers/scsi/qla4xxx/ql4_mbx.c int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index) uint32_t 1447 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1448 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1467 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t offset, uint32_t length, uint32_t options) uint32_t 1469 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1470 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1496 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO; uint32_t 1497 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t dev_db_end_offset; uint32_t 1530 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t dev_db_start_offset; uint32_t 1531 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t dev_db_end_offset; uint32_t 1580 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t offset = 0, chap_size; uint32_t 1642 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t offset = 0; uint32_t 1644 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t chap_size = 0; uint32_t 1835 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1836 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1863 drivers/scsi/qla4xxx/ql4_mbx.c static int qla4_84xx_extend_idc_tmo(struct scsi_qla_host *ha, uint32_t ext_tmo) uint32_t 1865 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1866 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1897 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1898 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1934 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t acb_type, uint32_t len) uint32_t 1936 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 1937 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 1958 drivers/scsi/qla4xxx/ql4_mbx.c int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, uint32_t 1959 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *mbox_sts, dma_addr_t acb_dma) uint32_t 1983 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t *mbx_sts) uint32_t 1997 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t options = 0; uint32_t 2147 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2148 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2168 drivers/scsi/qla4xxx/ql4_mbx.c int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx, uint32_t 2169 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t ip_idx, uint32_t *sts) uint32_t 2171 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2172 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2192 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t offset, uint32_t size) uint32_t 2195 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2196 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2218 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t offset, uint32_t size) uint32_t 2221 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2222 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2244 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t region, uint32_t field0, uint32_t 2245 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t field1) uint32_t 2248 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2249 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2276 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2277 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2278 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t status; uint32_t 2313 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2314 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2339 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2340 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2342 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t acb_len = sizeof(struct addr_ctrl_blk); uint32_t 2412 drivers/scsi/qla4xxx/ql4_mbx.c int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config) uint32_t 2414 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2415 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2434 drivers/scsi/qla4xxx/ql4_mbx.c int qla4_83xx_set_port_config(struct scsi_qla_host *ha, uint32_t *config) uint32_t 2436 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2437 drivers/scsi/qla4xxx/ql4_mbx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 13 drivers/scsi/qla4xxx/ql4_nvram.c static inline void eeprom_cmd(uint32_t cmd, struct scsi_qla_host *ha) uint32_t 184 drivers/scsi/qla4xxx/ql4_nvram.c uint32_t index; uint32_t 205 drivers/scsi/qla4xxx/ql4_nvram.c uint32_t value; uint32_t 242 drivers/scsi/qla4xxx/ql4_nvram.c uint32_t value; uint32_t 403 drivers/scsi/qla4xxx/ql4_nx.c uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off) uint32_t 428 drivers/scsi/qla4xxx/ql4_nx.c int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data) uint32_t 430 drivers/scsi/qla4xxx/ql4_nx.c uint32_t win_read, off_value; uint32_t 454 drivers/scsi/qla4xxx/ql4_nx.c int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data) uint32_t 456 drivers/scsi/qla4xxx/ql4_nx.c uint32_t win_read, off_value; uint32_t 1193 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data, uint32_t count) uint32_t 1196 drivers/scsi/qla4xxx/ql4_nx.c uint32_t agt_ctrl; uint32_t 1289 drivers/scsi/qla4xxx/ql4_nx.c qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) uint32_t 1334 drivers/scsi/qla4xxx/ql4_nx.c static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) uint32_t 1371 drivers/scsi/qla4xxx/ql4_nx.c uint32_t temp; uint32_t 1447 drivers/scsi/qla4xxx/ql4_nx.c *(uint32_t *)data = val; uint32_t 1462 drivers/scsi/qla4xxx/ql4_nx.c uint32_t temp; uint32_t 1501 drivers/scsi/qla4xxx/ql4_nx.c tmpw = *((uint32_t *)data); uint32_t 1591 drivers/scsi/qla4xxx/ql4_nx.c uint32_t state = 0; uint32_t 1621 drivers/scsi/qla4xxx/ql4_nx.c uint32_t drv_active; uint32_t 1643 drivers/scsi/qla4xxx/ql4_nx.c uint32_t drv_active; uint32_t 1664 drivers/scsi/qla4xxx/ql4_nx.c uint32_t drv_state, drv_active; uint32_t 1688 drivers/scsi/qla4xxx/ql4_nx.c uint32_t drv_state; uint32_t 1709 drivers/scsi/qla4xxx/ql4_nx.c uint32_t drv_state; uint32_t 1731 drivers/scsi/qla4xxx/ql4_nx.c uint32_t qsnt_state; uint32_t 1750 drivers/scsi/qla4xxx/ql4_nx.c qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) uint32_t 1826 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha, uint32_t 1827 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr1, uint32_t mask) uint32_t 1830 drivers/scsi/qla4xxx/ql4_nx.c uint32_t rval = QLA_SUCCESS; uint32_t 1831 drivers/scsi/qla4xxx/ql4_nx.c uint32_t temp; uint32_t 1848 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1, uint32_t 1849 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t 1850 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr) uint32_t 1853 drivers/scsi/qla4xxx/ql4_nx.c uint32_t temp; uint32_t 1854 drivers/scsi/qla4xxx/ql4_nx.c uint32_t data; uint32_t 1875 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha, uint32_t 1876 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr1, uint32_t 1877 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr2, uint32_t 1878 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr3, uint32_t 1879 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mask) uint32_t 1882 drivers/scsi/qla4xxx/ql4_nx.c uint32_t temp; uint32_t 1883 drivers/scsi/qla4xxx/ql4_nx.c uint32_t rval = QLA_SUCCESS; uint32_t 1900 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr1, uint32_t addr3, uint32_t 1901 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mask, uint32_t addr, uint32_t 1902 drivers/scsi/qla4xxx/ql4_nx.c uint32_t value) uint32_t 1923 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 1925 drivers/scsi/qla4xxx/ql4_nx.c uint32_t r_addr, r_stride, loop_cnt, i, r_value; uint32_t 1927 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 1947 drivers/scsi/qla4xxx/ql4_nx.c uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; uint32_t 1977 drivers/scsi/qla4xxx/ql4_nx.c uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; uint32_t 2031 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2035 drivers/scsi/qla4xxx/ql4_nx.c uint32_t size, read_size; uint32_t 2108 drivers/scsi/qla4xxx/ql4_nx.c (uint32_t *)&dma_desc, uint32_t 2136 drivers/scsi/qla4xxx/ql4_nx.c *d_ptr = (uint32_t *)data_ptr; uint32_t 2148 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2150 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr, r_addr, c_addr, t_r_addr; uint32_t 2151 drivers/scsi/qla4xxx/ql4_nx.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; uint32_t 2153 drivers/scsi/qla4xxx/ql4_nx.c uint32_t c_value_w, c_value_r; uint32_t 2156 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2209 drivers/scsi/qla4xxx/ql4_nx.c uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; uint32_t 2210 drivers/scsi/qla4xxx/ql4_nx.c uint32_t crb_addr; uint32_t 2324 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2326 drivers/scsi/qla4xxx/ql4_nx.c uint32_t r_addr, r_stride, loop_cnt, i, r_value; uint32_t 2328 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2346 drivers/scsi/qla4xxx/ql4_nx.c __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)))); uint32_t 2352 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2354 drivers/scsi/qla4xxx/ql4_nx.c uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; uint32_t 2356 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2378 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2380 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr, r_addr, c_addr, t_r_addr; uint32_t 2381 drivers/scsi/qla4xxx/ql4_nx.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; uint32_t 2382 drivers/scsi/qla4xxx/ql4_nx.c uint32_t c_value_w; uint32_t 2384 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2412 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2414 drivers/scsi/qla4xxx/ql4_nx.c uint32_t s_addr, r_addr; uint32_t 2415 drivers/scsi/qla4xxx/ql4_nx.c uint32_t r_stride, r_value, r_cnt, qid = 0; uint32_t 2416 drivers/scsi/qla4xxx/ql4_nx.c uint32_t i, k, loop_cnt; uint32_t 2418 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2445 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2447 drivers/scsi/qla4xxx/ql4_nx.c uint32_t r_addr, r_value; uint32_t 2448 drivers/scsi/qla4xxx/ql4_nx.c uint32_t i, loop_cnt; uint32_t 2450 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2455 drivers/scsi/qla4xxx/ql4_nx.c loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); uint32_t 2468 drivers/scsi/qla4xxx/ql4_nx.c r_addr += sizeof(uint32_t); uint32_t 2479 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2481 drivers/scsi/qla4xxx/ql4_nx.c uint32_t r_addr, r_value, r_data; uint32_t 2482 drivers/scsi/qla4xxx/ql4_nx.c uint32_t i, j, loop_cnt; uint32_t 2485 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2561 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2563 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2591 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha, uint32_t 2593 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2595 drivers/scsi/qla4xxx/ql4_nx.c uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; uint32_t 2597 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2598 drivers/scsi/qla4xxx/ql4_nx.c uint32_t rval = QLA_SUCCESS; uint32_t 2640 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha, uint32_t 2642 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2645 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr1, addr2, value, data, temp, wrval; uint32_t 2648 drivers/scsi/qla4xxx/ql4_nx.c uint32_t poll, mask, data_size, modify_mask; uint32_t 2649 drivers/scsi/qla4xxx/ql4_nx.c uint32_t wait_count = 0; uint32_t 2650 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2652 drivers/scsi/qla4xxx/ql4_nx.c uint32_t rval = QLA_SUCCESS; uint32_t 2736 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha, uint32_t 2738 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2741 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr1, addr2, value1, value2, data, selval; uint32_t 2743 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr3, addr4, addr5, addr6, addr7; uint32_t 2745 drivers/scsi/qla4xxx/ql4_nx.c uint32_t poll, mask; uint32_t 2746 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2812 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha, uint32_t 2814 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2816 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr1, addr2, value1, value2, poll, mask, r_value; uint32_t 2818 drivers/scsi/qla4xxx/ql4_nx.c uint32_t wait_count = 0; uint32_t 2819 drivers/scsi/qla4xxx/ql4_nx.c uint32_t rval = QLA_SUCCESS; uint32_t 2863 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2865 drivers/scsi/qla4xxx/ql4_nx.c uint32_t sel_val1, sel_val2, t_sel_val, data, i; uint32_t 2866 drivers/scsi/qla4xxx/ql4_nx.c uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; uint32_t 2868 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2904 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha, uint32_t 2906 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2908 drivers/scsi/qla4xxx/ql4_nx.c uint32_t poll_wait, poll_mask, r_value, data; uint32_t 2909 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr_1, addr_2, value_1, value_2; uint32_t 2910 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2911 drivers/scsi/qla4xxx/ql4_nx.c uint32_t rval = QLA_SUCCESS; uint32_t 2970 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha, uint32_t 2972 drivers/scsi/qla4xxx/ql4_nx.c uint32_t **d_ptr) uint32_t 2974 drivers/scsi/qla4xxx/ql4_nx.c uint32_t fl_addr, u32_count, rval; uint32_t 2976 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr = *d_ptr; uint32_t 2980 drivers/scsi/qla4xxx/ql4_nx.c u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t); uint32_t 3010 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *data_ptr; uint32_t 3011 drivers/scsi/qla4xxx/ql4_nx.c uint32_t data_collected = 0; uint32_t 3014 drivers/scsi/qla4xxx/ql4_nx.c uint32_t timestamp; uint32_t 3025 drivers/scsi/qla4xxx/ql4_nx.c data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump + uint32_t 3266 drivers/scsi/qla4xxx/ql4_nx.c uint32_t old_count, count; uint32_t 3326 drivers/scsi/qla4xxx/ql4_nx.c uint32_t dev_state, drv_state, drv_active; uint32_t 3327 drivers/scsi/qla4xxx/ql4_nx.c uint32_t active_mask = 0xFFFFFFFF; uint32_t 3414 drivers/scsi/qla4xxx/ql4_nx.c uint32_t drv_active; uint32_t 3436 drivers/scsi/qla4xxx/ql4_nx.c uint32_t drv_active; uint32_t 3473 drivers/scsi/qla4xxx/ql4_nx.c uint32_t drv_active; uint32_t 3514 drivers/scsi/qla4xxx/ql4_nx.c uint32_t dev_state; uint32_t 3647 drivers/scsi/qla4xxx/ql4_nx.c static inline uint32_t uint32_t 3648 drivers/scsi/qla4xxx/ql4_nx.c flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) uint32_t 3653 drivers/scsi/qla4xxx/ql4_nx.c static inline uint32_t uint32_t 3654 drivers/scsi/qla4xxx/ql4_nx.c flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) uint32_t 3659 drivers/scsi/qla4xxx/ql4_nx.c static uint32_t * uint32_t 3660 drivers/scsi/qla4xxx/ql4_nx.c qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, uint32_t 3661 drivers/scsi/qla4xxx/ql4_nx.c uint32_t faddr, uint32_t length) uint32_t 3663 drivers/scsi/qla4xxx/ql4_nx.c uint32_t i; uint32_t 3664 drivers/scsi/qla4xxx/ql4_nx.c uint32_t val; uint32_t 3696 drivers/scsi/qla4xxx/ql4_nx.c uint32_t offset, uint32_t length) uint32_t 3698 drivers/scsi/qla4xxx/ql4_nx.c qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length); uint32_t 3703 drivers/scsi/qla4xxx/ql4_nx.c qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) uint32_t 3720 drivers/scsi/qla4xxx/ql4_nx.c qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) uint32_t 3725 drivers/scsi/qla4xxx/ql4_nx.c uint32_t start, status; uint32_t 3900 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *wptr; uint32_t 3904 drivers/scsi/qla4xxx/ql4_nx.c wptr = (uint32_t *)ha->request_ring; uint32_t 3923 drivers/scsi/qla4xxx/ql4_nx.c void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, uint32_t 3960 drivers/scsi/qla4xxx/ql4_nx.c uint32_t flt_addr; uint32_t 3990 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 3991 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 4013 drivers/scsi/qla4xxx/ql4_nx.c uint32_t dev_state; uint32_t 4049 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 4050 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 4113 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 4114 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 4134 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 4135 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 602 drivers/scsi/qla4xxx/ql4_nx.h static const uint32_t qla4_82xx_reg_tbl[] = { uint32_t 891 drivers/scsi/qla4xxx/ql4_nx.h uint32_t entry_type; uint32_t 892 drivers/scsi/qla4xxx/ql4_nx.h uint32_t entry_size; uint32_t 893 drivers/scsi/qla4xxx/ql4_nx.h uint32_t entry_capture_size; uint32_t 905 drivers/scsi/qla4xxx/ql4_nx.h uint32_t addr; uint32_t 911 drivers/scsi/qla4xxx/ql4_nx.h uint32_t data_size; uint32_t 912 drivers/scsi/qla4xxx/ql4_nx.h uint32_t op_count; uint32_t 921 drivers/scsi/qla4xxx/ql4_nx.h uint32_t value_1; uint32_t 922 drivers/scsi/qla4xxx/ql4_nx.h uint32_t value_2; uint32_t 923 drivers/scsi/qla4xxx/ql4_nx.h uint32_t value_3; uint32_t 928 drivers/scsi/qla4xxx/ql4_nx.h uint32_t tag_reg_addr; uint32_t 933 drivers/scsi/qla4xxx/ql4_nx.h uint32_t data_size; uint32_t 934 drivers/scsi/qla4xxx/ql4_nx.h uint32_t op_count; uint32_t 935 drivers/scsi/qla4xxx/ql4_nx.h uint32_t control_addr; uint32_t 941 drivers/scsi/qla4xxx/ql4_nx.h uint32_t read_addr; uint32_t 952 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd_0; uint32_t 953 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd_1; uint32_t 954 drivers/scsi/qla4xxx/ql4_nx.h uint32_t data_size; uint32_t 955 drivers/scsi/qla4xxx/ql4_nx.h uint32_t op_count; uint32_t 956 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd_2; uint32_t 957 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd_3; uint32_t 958 drivers/scsi/qla4xxx/ql4_nx.h uint32_t read_addr; uint32_t 959 drivers/scsi/qla4xxx/ql4_nx.h uint32_t read_addr_stride; uint32_t 965 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd[6]; uint32_t 966 drivers/scsi/qla4xxx/ql4_nx.h uint32_t read_addr; uint32_t 967 drivers/scsi/qla4xxx/ql4_nx.h uint32_t read_data_size; uint32_t 973 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd[6]; uint32_t 974 drivers/scsi/qla4xxx/ql4_nx.h uint32_t read_addr; uint32_t 975 drivers/scsi/qla4xxx/ql4_nx.h uint32_t read_data_size; uint32_t 981 drivers/scsi/qla4xxx/ql4_nx.h uint32_t select_addr; uint32_t 982 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd_0; uint32_t 983 drivers/scsi/qla4xxx/ql4_nx.h uint32_t data_size; uint32_t 984 drivers/scsi/qla4xxx/ql4_nx.h uint32_t op_count; uint32_t 985 drivers/scsi/qla4xxx/ql4_nx.h uint32_t select_value; uint32_t 986 drivers/scsi/qla4xxx/ql4_nx.h uint32_t select_value_stride; uint32_t 987 drivers/scsi/qla4xxx/ql4_nx.h uint32_t read_addr; uint32_t 988 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd_1; uint32_t 994 drivers/scsi/qla4xxx/ql4_nx.h uint32_t select_addr; uint32_t 999 drivers/scsi/qla4xxx/ql4_nx.h uint32_t data_size; uint32_t 1000 drivers/scsi/qla4xxx/ql4_nx.h uint32_t op_count; uint32_t 1001 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd_1; uint32_t 1002 drivers/scsi/qla4xxx/ql4_nx.h uint32_t rsvd_2; uint32_t 1003 drivers/scsi/qla4xxx/ql4_nx.h uint32_t read_addr; uint32_t 116 drivers/scsi/qla4xxx/ql4_os.c uint32_t len); uint32_t 130 drivers/scsi/qla4xxx/ql4_os.c qla4xxx_conn_create(struct iscsi_cls_session *cls_sess, uint32_t conn_idx); uint32_t 137 drivers/scsi/qla4xxx/ql4_os.c uint16_t qdepth, uint32_t initial_cmdsn); uint32_t 146 drivers/scsi/qla4xxx/ql4_os.c static int qla4xxx_send_ping(struct Scsi_Host *shost, uint32_t iface_num, uint32_t 147 drivers/scsi/qla4xxx/ql4_os.c uint32_t iface_type, uint32_t payload_size, uint32_t 148 drivers/scsi/qla4xxx/ql4_os.c uint32_t pid, struct sockaddr *dst_addr); uint32_t 150 drivers/scsi/qla4xxx/ql4_os.c uint32_t *num_entries, char *buf); uint32_t 282 drivers/scsi/qla4xxx/ql4_os.c static int qla4xxx_send_ping(struct Scsi_Host *shost, uint32_t iface_num, uint32_t 283 drivers/scsi/qla4xxx/ql4_os.c uint32_t iface_type, uint32_t payload_size, uint32_t 284 drivers/scsi/qla4xxx/ql4_os.c uint32_t pid, struct sockaddr *dst_addr) uint32_t 289 drivers/scsi/qla4xxx/ql4_os.c uint32_t options = 0; uint32_t 601 drivers/scsi/qla4xxx/ql4_os.c uint32_t offset; uint32_t 603 drivers/scsi/qla4xxx/ql4_os.c uint32_t chap_size = 0; uint32_t 736 drivers/scsi/qla4xxx/ql4_os.c uint32_t *num_entries, char *buf) uint32_t 841 drivers/scsi/qla4xxx/ql4_os.c uint32_t offset = 0; uint32_t 842 drivers/scsi/qla4xxx/ql4_os.c uint32_t chap_size; uint32_t 1867 drivers/scsi/qla4xxx/ql4_os.c uint32_t speed = ISCSI_PORT_SPEED_UNKNOWN; uint32_t 1892 drivers/scsi/qla4xxx/ql4_os.c uint32_t state = ISCSI_PORT_STATE_DOWN; uint32_t 2220 drivers/scsi/qla4xxx/ql4_os.c cpu_to_le32(*(uint32_t *)iface_param->value); uint32_t 2226 drivers/scsi/qla4xxx/ql4_os.c cpu_to_le32(*(uint32_t *)iface_param->value); uint32_t 2232 drivers/scsi/qla4xxx/ql4_os.c cpu_to_le32(*(uint32_t *)iface_param->value); uint32_t 2243 drivers/scsi/qla4xxx/ql4_os.c cpu_to_le32(*(uint32_t *)iface_param->value); uint32_t 2592 drivers/scsi/qla4xxx/ql4_os.c cpu_to_le32(*(uint32_t *)iface_param->value) / uint32_t 2599 drivers/scsi/qla4xxx/ql4_os.c cpu_to_le32(*(uint32_t *)iface_param->value) / uint32_t 2612 drivers/scsi/qla4xxx/ql4_os.c cpu_to_le32(*(uint32_t *)iface_param->value) / uint32_t 2695 drivers/scsi/qla4xxx/ql4_os.c qla4xxx_iface_set_param(struct Scsi_Host *shost, void *data, uint32_t len) uint32_t 2702 drivers/scsi/qla4xxx/ql4_os.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 2703 drivers/scsi/qla4xxx/ql4_os.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 2704 drivers/scsi/qla4xxx/ql4_os.c uint32_t rem = len; uint32_t 2909 drivers/scsi/qla4xxx/ql4_os.c uint32_t mbx_sts = 0; uint32_t 3054 drivers/scsi/qla4xxx/ql4_os.c uint32_t initial_cmdsn) uint32_t 3111 drivers/scsi/qla4xxx/ql4_os.c uint32_t ddb_state; uint32_t 3160 drivers/scsi/qla4xxx/ql4_os.c qla4xxx_conn_create(struct iscsi_cls_session *cls_sess, uint32_t conn_idx) uint32_t 3222 drivers/scsi/qla4xxx/ql4_os.c uint32_t mbx_sts = 0; uint32_t 3323 drivers/scsi/qla4xxx/ql4_os.c uint32_t data_len; uint32_t 3880 drivers/scsi/qla4xxx/ql4_os.c uint32_t ddb_state; uint32_t 3922 drivers/scsi/qla4xxx/ql4_os.c uint32_t ddb_state; uint32_t 4289 drivers/scsi/qla4xxx/ql4_os.c uint32_t temp, temp_state, temp_val; uint32_t 4325 drivers/scsi/qla4xxx/ql4_os.c uint32_t fw_heartbeat_counter; uint32_t 4355 drivers/scsi/qla4xxx/ql4_os.c uint32_t halt_status; uint32_t 4403 drivers/scsi/qla4xxx/ql4_os.c uint32_t dev_state; uint32_t 4404 drivers/scsi/qla4xxx/ql4_os.c uint32_t idc_ctrl; uint32_t 4592 drivers/scsi/qla4xxx/ql4_os.c uint32_t index = 0; uint32_t 4596 drivers/scsi/qla4xxx/ql4_os.c uint32_t wtmo; uint32_t 4638 drivers/scsi/qla4xxx/ql4_os.c uint32_t ctrl_status; uint32_t 4670 drivers/scsi/qla4xxx/ql4_os.c uint32_t max_wait_time; uint32_t 4673 drivers/scsi/qla4xxx/ql4_os.c uint32_t ctrl_status; uint32_t 4825 drivers/scsi/qla4xxx/ql4_os.c uint32_t dev_state; uint32_t 5168 drivers/scsi/qla4xxx/ql4_os.c qla4xxx_alloc_work(struct scsi_qla_host *ha, uint32_t data_size, uint32_t 5172 drivers/scsi/qla4xxx/ql4_os.c uint32_t size = sizeof(struct qla4_work_evt) + data_size; uint32_t 5196 drivers/scsi/qla4xxx/ql4_os.c uint32_t data_size, uint8_t *data) uint32_t 5214 drivers/scsi/qla4xxx/ql4_os.c uint32_t status, uint32_t pid, uint32_t 5215 drivers/scsi/qla4xxx/ql4_os.c uint32_t data_size, uint8_t *data) uint32_t 5887 drivers/scsi/qla4xxx/ql4_os.c uint32_t addr, pri_addr, sec_addr; uint32_t 5888 drivers/scsi/qla4xxx/ql4_os.c uint32_t offset; uint32_t 6337 drivers/scsi/qla4xxx/ql4_os.c uint32_t *index) uint32_t 6627 drivers/scsi/qla4xxx/ql4_os.c uint32_t idx = 0; uint32_t 6628 drivers/scsi/qla4xxx/ql4_os.c uint32_t ip_idx[IP_ADDR_COUNT] = {0, 1, 2, 3}; /* 4 IP interfaces */ uint32_t 6629 drivers/scsi/qla4xxx/ql4_os.c uint32_t sts[MBOX_REG_COUNT]; uint32_t 6630 drivers/scsi/qla4xxx/ql4_os.c uint32_t ip_state; uint32_t 6696 drivers/scsi/qla4xxx/ql4_os.c uint32_t fw_idx, uint32_t *flash_index) uint32_t 6700 drivers/scsi/qla4xxx/ql4_os.c uint32_t idx = 0; uint32_t 6760 drivers/scsi/qla4xxx/ql4_os.c uint32_t idx = 0, next_idx = 0; uint32_t 6761 drivers/scsi/qla4xxx/ql4_os.c uint32_t state = 0, conn_err = 0; uint32_t 6762 drivers/scsi/qla4xxx/ql4_os.c uint32_t flash_index = -1; uint32_t 6833 drivers/scsi/qla4xxx/ql4_os.c uint32_t next_idx = 0; uint32_t 6834 drivers/scsi/qla4xxx/ql4_os.c uint32_t state = 0, conn_err = 0; uint32_t 6858 drivers/scsi/qla4xxx/ql4_os.c uint32_t max_ddbs = 0; uint32_t 6884 drivers/scsi/qla4xxx/ql4_os.c uint32_t initial_cmdsn = 0; uint32_t 6987 drivers/scsi/qla4xxx/ql4_os.c uint32_t idx = 0, next_idx = 0; uint32_t 6988 drivers/scsi/qla4xxx/ql4_os.c uint32_t state = 0, conn_err = 0; uint32_t 6989 drivers/scsi/qla4xxx/ql4_os.c uint32_t ddb_idx = -1; uint32_t 7095 drivers/scsi/qla4xxx/ql4_os.c uint32_t idx = 0, next_idx = 0; uint32_t 7096 drivers/scsi/qla4xxx/ql4_os.c uint32_t state = 0, conn_err = 0; uint32_t 7272 drivers/scsi/qla4xxx/ql4_os.c uint32_t options = 0; uint32_t 7273 drivers/scsi/qla4xxx/ql4_os.c uint32_t rval = QLA_ERROR; uint32_t 7346 drivers/scsi/qla4xxx/ql4_os.c uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO; uint32_t 7349 drivers/scsi/qla4xxx/ql4_os.c uint32_t options = 0; uint32_t 7404 drivers/scsi/qla4xxx/ql4_os.c uint32_t mbx_sts = 0; uint32_t 7405 drivers/scsi/qla4xxx/ql4_os.c uint32_t state = 0, conn_err = 0; uint32_t 7538 drivers/scsi/qla4xxx/ql4_os.c uint32_t options = 0; uint32_t 7600 drivers/scsi/qla4xxx/ql4_os.c uint32_t ddb_state; uint32_t 7725 drivers/scsi/qla4xxx/ql4_os.c uint32_t next_idx = 0; uint32_t 7726 drivers/scsi/qla4xxx/ql4_os.c uint32_t state = 0, conn_err = 0; uint32_t 8092 drivers/scsi/qla4xxx/ql4_os.c uint32_t rem = len; uint32_t 8272 drivers/scsi/qla4xxx/ql4_os.c fnode_conn->statsn = *(uint32_t *)fnode_param->value; uint32_t 8276 drivers/scsi/qla4xxx/ql4_os.c *(uint32_t *)fnode_param->value; uint32_t 8313 drivers/scsi/qla4xxx/ql4_os.c uint32_t dev_db_start_offset; uint32_t 8314 drivers/scsi/qla4xxx/ql4_os.c uint32_t dev_db_end_offset; uint32_t 8534 drivers/scsi/qla4xxx/ql4_os.c uint32_t ddb_state; uint32_t 8609 drivers/scsi/qla4xxx/ql4_os.c uint32_t dev_state; uint32_t 8636 drivers/scsi/qla4xxx/ql4_os.c ha->reg_tbl = (uint32_t *) qla4_82xx_reg_tbl; uint32_t 8648 drivers/scsi/qla4xxx/ql4_os.c ha->reg_tbl = (uint32_t *)qla4_83xx_reg_tbl; uint32_t 8912 drivers/scsi/qla4xxx/ql4_os.c uint32_t ddb_state; uint32_t 9061 drivers/scsi/qla4xxx/ql4_os.c uint32_t index) uint32_t 9097 drivers/scsi/qla4xxx/ql4_os.c uint32_t max_wait_time = EH_WAIT_CMD_TOV; uint32_t 9463 drivers/scsi/qla4xxx/ql4_os.c uint32_t mbox_cmd[MBOX_REG_COUNT]; uint32_t 9464 drivers/scsi/qla4xxx/ql4_os.c uint32_t mbox_sts[MBOX_REG_COUNT]; uint32_t 9466 drivers/scsi/qla4xxx/ql4_os.c uint32_t acb_len = sizeof(struct addr_ctrl_blk_def); uint32_t 9516 drivers/scsi/qla4xxx/ql4_os.c uint32_t idc_ctrl; uint32_t 9630 drivers/scsi/qla4xxx/ql4_os.c static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha) uint32_t 9632 drivers/scsi/qla4xxx/ql4_os.c uint32_t rval = QLA_ERROR; uint32_t 3595 drivers/scsi/scsi_transport_fc.c int cmdlen = sizeof(uint32_t); /* start with length of msgcode */ uint32_t 3655 drivers/scsi/scsi_transport_fc.c BUG_ON(job->reply_len < sizeof(uint32_t)); uint32_t 3658 drivers/scsi/scsi_transport_fc.c job->reply_len = sizeof(uint32_t); uint32_t 3688 drivers/scsi/scsi_transport_fc.c int cmdlen = sizeof(uint32_t); /* start with length of msgcode */ uint32_t 3724 drivers/scsi/scsi_transport_fc.c BUG_ON(job->reply_len < sizeof(uint32_t)); uint32_t 3727 drivers/scsi/scsi_transport_fc.c job->reply_len = sizeof(uint32_t); uint32_t 752 drivers/scsi/scsi_transport_iscsi.c uint32_t iface_type, uint32_t iface_num, int dd_size) uint32_t 1372 drivers/scsi/scsi_transport_iscsi.c iscsi_get_flashnode_by_index(struct Scsi_Host *shost, uint32_t idx) uint32_t 1490 drivers/scsi/scsi_transport_iscsi.c int cmdlen = sizeof(uint32_t); /* start with length of msgcode */ uint32_t 1494 drivers/scsi/scsi_transport_iscsi.c if (job->request_len < sizeof(uint32_t)) { uint32_t 1527 drivers/scsi/scsi_transport_iscsi.c BUG_ON(job->reply_len < sizeof(uint32_t)); uint32_t 1530 drivers/scsi/scsi_transport_iscsi.c job->reply_len = sizeof(uint32_t); uint32_t 1616 drivers/scsi/scsi_transport_iscsi.c static uint32_t iscsi_conn_get_sid(struct iscsi_cls_conn *conn) uint32_t 1625 drivers/scsi/scsi_transport_iscsi.c static struct iscsi_cls_session *iscsi_session_lookup(uint32_t sid) uint32_t 1644 drivers/scsi/scsi_transport_iscsi.c static struct iscsi_cls_conn *iscsi_conn_lookup(uint32_t sid, uint32_t cid) uint32_t 2237 drivers/scsi/scsi_transport_iscsi.c iscsi_create_conn(struct iscsi_cls_session *session, int dd_size, uint32_t cid) uint32_t 2328 drivers/scsi/scsi_transport_iscsi.c iscsi_multicast_skb(struct sk_buff *skb, uint32_t group, gfp_t gfp) uint32_t 2340 drivers/scsi/scsi_transport_iscsi.c char *data, uint32_t data_size) uint32_t 2378 drivers/scsi/scsi_transport_iscsi.c struct iscsi_transport *transport, uint32_t type, uint32_t 2480 drivers/scsi/scsi_transport_iscsi.c void iscsi_post_host_event(uint32_t host_no, struct iscsi_transport *transport, uint32_t 2481 drivers/scsi/scsi_transport_iscsi.c enum iscsi_host_event_code code, uint32_t data_size, uint32_t 2511 drivers/scsi/scsi_transport_iscsi.c void iscsi_ping_comp_event(uint32_t host_no, struct iscsi_transport *transport, uint32_t 2512 drivers/scsi/scsi_transport_iscsi.c uint32_t status, uint32_t pid, uint32_t data_size, uint32_t 2696 drivers/scsi/scsi_transport_iscsi.c uint32_t initial_cmdsn, uint16_t cmds_max, uint32_t 2972 drivers/scsi/scsi_transport_iscsi.c struct iscsi_uevent *ev, uint32_t len) uint32_t 3030 drivers/scsi/scsi_transport_iscsi.c uint32_t chap_buf_size; uint32_t 3090 drivers/scsi/scsi_transport_iscsi.c struct iscsi_uevent *ev, uint32_t len) uint32_t 3157 drivers/scsi/scsi_transport_iscsi.c struct iscsi_uevent *ev, uint32_t len) uint32_t 3164 drivers/scsi/scsi_transport_iscsi.c uint32_t idx; uint32_t 3210 drivers/scsi/scsi_transport_iscsi.c struct iscsi_uevent *ev, uint32_t len) uint32_t 3249 drivers/scsi/scsi_transport_iscsi.c uint32_t idx; uint32_t 3291 drivers/scsi/scsi_transport_iscsi.c uint32_t idx; uint32_t 3343 drivers/scsi/scsi_transport_iscsi.c uint32_t idx; uint32_t 3498 drivers/scsi/scsi_transport_iscsi.c iscsi_if_recv_msg(struct sk_buff *skb, struct nlmsghdr *nlh, uint32_t *group) uint32_t 3705 drivers/scsi/scsi_transport_iscsi.c uint32_t rlen; uint32_t 3708 drivers/scsi/scsi_transport_iscsi.c uint32_t group; uint32_t 4336 drivers/scsi/scsi_transport_iscsi.c uint32_t port_speed = ihost->port_speed; uint32_t 4362 drivers/scsi/scsi_transport_iscsi.c uint32_t port_state = ihost->port_state; uint32_t 142 drivers/scsi/ufs/ufs-hisi.c uint32_t value; uint32_t 143 drivers/scsi/ufs/ufs-hisi.c uint32_t reg; uint32_t 692 drivers/scsi/ufs/ufs-qcom.c uint32_t value; uint32_t 177 drivers/scsi/ufs/ufs-qcom.h uint32_t client_handle; uint32_t 178 drivers/scsi/ufs/ufs-qcom.h uint32_t curr_vote; uint32_t 155 drivers/scsi/xen-scsifront.c static int _scsifront_put_rqid(struct vscsifrnt_info *info, uint32_t id) uint32_t 165 drivers/scsi/xen-scsifront.c static void scsifront_put_rqid(struct vscsifrnt_info *info, uint32_t id) uint32_t 184 drivers/scsi/xen-scsifront.c uint32_t id; uint32_t 252 drivers/scsi/xen-scsifront.c uint32_t id; uint32_t 193 drivers/slimbus/qcom-ngd-ctrl.c uint32_t instance; uint32_t 216 drivers/slimbus/qcom-ngd-ctrl.c .elem_size = sizeof(uint32_t), uint32_t 60 drivers/soc/bcm/brcmstb/pm/aon_defs.h uint32_t dtu_state_map[BRCMSTB_DTU_STATE_MAP_ENTRIES]; uint32_t 61 drivers/soc/bcm/brcmstb/pm/aon_defs.h uint32_t dtu_config[BRCMSTB_DTU_CONFIG_ENTRIES]; uint32_t 72 drivers/soc/bcm/brcmstb/pm/aon_defs.h uint32_t magic; /* BRCMSTB_S3_MAGIC */ uint32_t 76 drivers/soc/bcm/brcmstb/pm/aon_defs.h uint32_t hash[BRCMSTB_HASH_LEN / 4]; uint32_t 88 drivers/soc/bcm/brcmstb/pm/aon_defs.h uint32_t desc_offset_2; uint32_t 96 drivers/soc/bcm/brcmstb/pm/aon_defs.h uint32_t spare[70]; uint32_t 73 drivers/spi/spi-st-ssc4.c uint32_t word = 0; uint32_t 97 drivers/spi/spi-st-ssc4.c uint32_t word = 0; uint32_t 123 drivers/spi/spi-st-ssc4.c uint32_t ctl = 0; uint32_t 561 drivers/spi/spi-synquacer.c uint32_t val; uint32_t 581 drivers/spi/spi-synquacer.c uint32_t val; uint32_t 217 drivers/staging/android/vsoc.c static inline uint32_t vsoc_device_region_size(struct vsoc_device_region *r) uint32_t 411 drivers/staging/android/vsoc.c if (arg->offset & (sizeof(uint32_t) - 1)) uint32_t 415 drivers/staging/android/vsoc.c sizeof(uint32_t) > region_p->region_end_offset) uint32_t 507 drivers/staging/android/vsoc.c static int do_vsoc_cond_wake(struct file *filp, uint32_t offset) uint32_t 513 drivers/staging/android/vsoc.c if (offset & (sizeof(uint32_t) - 1)) uint32_t 517 drivers/staging/android/vsoc.c sizeof(uint32_t) > region_p->region_end_offset) uint32_t 43 drivers/staging/greybus/tools/loopback_test.c uint32_t latency_max; uint32_t 44 drivers/staging/greybus/tools/loopback_test.c uint32_t latency_min; uint32_t 45 drivers/staging/greybus/tools/loopback_test.c uint32_t latency_jitter; uint32_t 48 drivers/staging/greybus/tools/loopback_test.c uint32_t request_max; uint32_t 49 drivers/staging/greybus/tools/loopback_test.c uint32_t request_min; uint32_t 50 drivers/staging/greybus/tools/loopback_test.c uint32_t request_jitter; uint32_t 53 drivers/staging/greybus/tools/loopback_test.c uint32_t throughput_max; uint32_t 54 drivers/staging/greybus/tools/loopback_test.c uint32_t throughput_min; uint32_t 55 drivers/staging/greybus/tools/loopback_test.c uint32_t throughput_jitter; uint32_t 58 drivers/staging/greybus/tools/loopback_test.c uint32_t apbridge_unipro_latency_max; uint32_t 59 drivers/staging/greybus/tools/loopback_test.c uint32_t apbridge_unipro_latency_min; uint32_t 60 drivers/staging/greybus/tools/loopback_test.c uint32_t apbridge_unipro_latency_jitter; uint32_t 63 drivers/staging/greybus/tools/loopback_test.c uint32_t gbphy_firmware_latency_max; uint32_t 64 drivers/staging/greybus/tools/loopback_test.c uint32_t gbphy_firmware_latency_min; uint32_t 65 drivers/staging/greybus/tools/loopback_test.c uint32_t gbphy_firmware_latency_jitter; uint32_t 67 drivers/staging/greybus/tools/loopback_test.c uint32_t error; uint32_t 113 drivers/staging/greybus/tools/loopback_test.c uint32_t max = 0; \ uint32_t 127 drivers/staging/greybus/tools/loopback_test.c uint32_t min = ~0; \ uint32_t 141 drivers/staging/greybus/tools/loopback_test.c uint32_t val = 0; \ uint32_t 142 drivers/staging/greybus/tools/loopback_test.c uint32_t count = 0; \ uint32_t 386 drivers/staging/octeon/octeon-stubs.h uint32_t dropped_octets; uint32_t 387 drivers/staging/octeon/octeon-stubs.h uint32_t dropped_packets; uint32_t 388 drivers/staging/octeon/octeon-stubs.h uint32_t pci_raw_packets; uint32_t 389 drivers/staging/octeon/octeon-stubs.h uint32_t octets; uint32_t 390 drivers/staging/octeon/octeon-stubs.h uint32_t packets; uint32_t 391 drivers/staging/octeon/octeon-stubs.h uint32_t multicast_packets; uint32_t 392 drivers/staging/octeon/octeon-stubs.h uint32_t broadcast_packets; uint32_t 393 drivers/staging/octeon/octeon-stubs.h uint32_t len_64_packets; uint32_t 394 drivers/staging/octeon/octeon-stubs.h uint32_t len_65_127_packets; uint32_t 395 drivers/staging/octeon/octeon-stubs.h uint32_t len_128_255_packets; uint32_t 396 drivers/staging/octeon/octeon-stubs.h uint32_t len_256_511_packets; uint32_t 397 drivers/staging/octeon/octeon-stubs.h uint32_t len_512_1023_packets; uint32_t 398 drivers/staging/octeon/octeon-stubs.h uint32_t len_1024_1518_packets; uint32_t 399 drivers/staging/octeon/octeon-stubs.h uint32_t len_1519_max_packets; uint32_t 400 drivers/staging/octeon/octeon-stubs.h uint32_t fcs_align_err_packets; uint32_t 401 drivers/staging/octeon/octeon-stubs.h uint32_t runt_packets; uint32_t 402 drivers/staging/octeon/octeon-stubs.h uint32_t runt_crc_packets; uint32_t 403 drivers/staging/octeon/octeon-stubs.h uint32_t oversize_packets; uint32_t 404 drivers/staging/octeon/octeon-stubs.h uint32_t oversize_crc_packets; uint32_t 405 drivers/staging/octeon/octeon-stubs.h uint32_t inb_packets; uint32_t 411 drivers/staging/octeon/octeon-stubs.h uint32_t packets; uint32_t 1407 drivers/staging/octeon/octeon-stubs.h static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, uint32_t 2825 drivers/staging/qlge/qlge_main.c uint32_t curr_idx, clean_idx; uint32_t 155 drivers/staging/ralink-gdma/ralink-gdma.c static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev, uint32_t 162 drivers/staging/ralink-gdma/ralink-gdma.c unsigned int reg, uint32_t val) uint32_t 25 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t version; uint32_t 26 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t version_min; uint32_t 78 drivers/staging/vc04_services/interface/vchi/vchi.h extern void *vchi_allocate_buffer(VCHI_SERVICE_HANDLE_T handle, uint32_t *length); uint32_t 80 drivers/staging/vc04_services/interface/vchi/vchi.h extern uint32_t vchi_current_time(VCHI_INSTANCE_T instance_handle); uint32_t 126 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t max_data_size_to_read, uint32_t 127 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t *actual_msg_size, uint32_t 135 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t *msg_size, uint32_t 147 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t *msg_size, // } obtained from HELD_MSG_T uint32_t 167 drivers/staging/vc04_services/interface/vchi/vchi.h extern uint32_t vchi_held_msg_tx_timestamp(const struct vchi_held_msg *message); uint32_t 170 drivers/staging/vc04_services/interface/vchi/vchi.h extern uint32_t vchi_held_msg_rx_timestamp(const struct vchi_held_msg *message); uint32_t 181 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t *msg_size); uint32_t 195 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t *msg_size, // } uint32_t 205 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t data_size, uint32_t 211 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t offset, uint32_t 212 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t data_size, uint32_t 219 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t data_size, uint32_t 232 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t offset, uint32_t 233 drivers/staging/vc04_services/interface/vchi/vchi.h uint32_t data_size, uint32_t 114 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h typedef uint32_t BITSET_T; uint32_t 657 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, uint32_t 41 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c uint32_t *msg_size, uint32_t 106 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c uint32_t data_size) uint32_t 203 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c uint32_t data_size, uint32_t 263 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c uint32_t data_size, uint32_t 325 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c uint32_t max_data_size_to_read, uint32_t 326 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c uint32_t *actual_msg_size, uint32_t 399 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_shim.c uint32_t *msg_size, uint32_t 86 drivers/staging/wusbcore/host/whci/asl.c static uint32_t process_qset(struct whc *whc, struct whc_qset *qset) uint32_t 89 drivers/staging/wusbcore/host/whci/asl.c uint32_t status = 0; uint32_t 163 drivers/staging/wusbcore/host/whci/asl.c void asl_update(struct whc *whc, uint32_t wusbcmd) uint32_t 213 drivers/staging/wusbcore/host/whci/asl.c uint32_t wusbcmd = WUSBCMD_ASYNC_UPDATED | WUSBCMD_ASYNC_SYNCED_DB; uint32_t 95 drivers/staging/wusbcore/host/whci/pzl.c uint32_t status = 0; uint32_t 176 drivers/staging/wusbcore/host/whci/pzl.c void pzl_update(struct whc *whc, uint32_t wusbcmd) uint32_t 241 drivers/staging/wusbcore/host/whci/pzl.c uint32_t wusbcmd = WUSBCMD_PERIODIC_UPDATED | WUSBCMD_PERIODIC_SYNCED_DB; uint32_t 184 drivers/staging/wusbcore/host/whci/qset.c uint32_t status; uint32_t 750 drivers/staging/wusbcore/host/whci/qset.c uint32_t status; uint32_t 195 drivers/staging/wusbcore/host/whci/whcd.h void pzl_update(struct whc *whc, uint32_t wusbcmd); uint32_t 196 drivers/staging/wusbcore/host/whci/whcd.h void asl_update(struct whc *whc, uint32_t wusbcmd); uint32_t 130 drivers/staging/wusbcore/host/whci/wusb.c static int whc_set_key(struct whc *whc, u8 key_index, uint32_t tkid, uint32_t 133 drivers/staging/wusbcore/host/whci/wusb.c uint32_t setkeycmd; uint32_t 134 drivers/staging/wusbcore/host/whci/wusb.c uint32_t seckey[4]; uint32_t 135 drivers/target/target_core_user.c uint32_t max_blocks; uint32_t 141 drivers/target/target_core_user.c uint32_t dbi_max; uint32_t 142 drivers/target/target_core_user.c uint32_t dbi_thresh; uint32_t 177 drivers/target/target_core_user.c uint32_t dbi_cnt; uint32_t 178 drivers/target/target_core_user.c uint32_t dbi_cur; uint32_t 179 drivers/target/target_core_user.c uint32_t *dbi; uint32_t 476 drivers/target/target_core_user.c static void tcmu_cmd_free_data(struct tcmu_cmd *tcmu_cmd, uint32_t len) uint32_t 479 drivers/target/target_core_user.c uint32_t i; uint32_t 538 drivers/target/target_core_user.c tcmu_get_block_page(struct tcmu_dev *udev, uint32_t dbi) uint32_t 563 drivers/target/target_core_user.c static inline uint32_t tcmu_cmd_get_block_cnt(struct tcmu_cmd *tcmu_cmd) uint32_t 586 drivers/target/target_core_user.c tcmu_cmd->dbi = kcalloc(tcmu_cmd->dbi_cnt, sizeof(uint32_t), uint32_t 739 drivers/target/target_core_user.c bool bidi, uint32_t read_len) uint32_t 749 drivers/target/target_core_user.c uint32_t count = 0; uint32_t 803 drivers/target/target_core_user.c static inline size_t spc_bitmap_free(unsigned long *bitmap, uint32_t thresh) uint32_t 818 drivers/target/target_core_user.c uint32_t blocks_needed = (data_needed + DATA_BLOCK_SIZE - 1) uint32_t 963 drivers/target/target_core_user.c uint32_t cmd_head; uint32_t 1135 drivers/target/target_core_user.c uint32_t read_len; uint32_t 1503 drivers/target/target_core_user.c static struct page *tcmu_try_get_block_page(struct tcmu_dev *udev, uint32_t dbi) uint32_t 1549 drivers/target/target_core_user.c uint32_t dbi; uint32_t 72 drivers/thermal/hisi_thermal.c uint32_t id; uint32_t 73 drivers/thermal/hisi_thermal.c uint32_t thres_temp; uint32_t 47 drivers/tty/ehv_bytechan.c uint32_t handle; uint32_t 111 drivers/tty/ehv_bytechan.c const uint32_t *iprop; uint32_t 671 drivers/tty/ehv_bytechan.c const uint32_t *iprop; uint32_t 113 drivers/tty/hvc/hvc_console.c static int __hvc_flush(const struct hv_ops *ops, uint32_t vtermno, bool wait) uint32_t 123 drivers/tty/hvc/hvc_console.c static int hvc_console_flush(const struct hv_ops *ops, uint32_t vtermno) uint32_t 143 drivers/tty/hvc/hvc_console.c static uint32_t vtermnos[MAX_NR_HVC_CONSOLES] = uint32_t 285 drivers/tty/hvc/hvc_console.c int hvc_instantiate(uint32_t vtermno, int index, const struct hv_ops *ops) uint32_t 911 drivers/tty/hvc/hvc_console.c struct hvc_struct *hvc_alloc(uint32_t vtermno, int data, uint32_t 43 drivers/tty/hvc/hvc_console.h uint32_t vtermno; uint32_t 55 drivers/tty/hvc/hvc_console.h int (*get_chars)(uint32_t vtermno, char *buf, int count); uint32_t 56 drivers/tty/hvc/hvc_console.h int (*put_chars)(uint32_t vtermno, const char *buf, int count); uint32_t 57 drivers/tty/hvc/hvc_console.h int (*flush)(uint32_t vtermno, bool wait); uint32_t 73 drivers/tty/hvc/hvc_console.h extern int hvc_instantiate(uint32_t vtermno, int index, uint32_t 77 drivers/tty/hvc/hvc_console.h extern struct hvc_struct * hvc_alloc(uint32_t vtermno, int data, uint32_t 15 drivers/tty/hvc/hvc_dcc.c static int hvc_dcc_put_chars(uint32_t vt, const char *buf, int count) uint32_t 29 drivers/tty/hvc/hvc_dcc.c static int hvc_dcc_get_chars(uint32_t vt, char *buf, int count) uint32_t 132 drivers/tty/hvc/hvc_iucv.c static struct hvc_iucv_private *hvc_iucv_get_private(uint32_t num) uint32_t 316 drivers/tty/hvc/hvc_iucv.c static int hvc_iucv_get_chars(uint32_t vtermno, char *buf, int count) uint32_t 461 drivers/tty/hvc/hvc_iucv.c static int hvc_iucv_put_chars(uint32_t vtermno, const char *buf, int count) uint32_t 61 drivers/tty/hvc/hvc_opal.c static int hvc_opal_hvsi_get_chars(uint32_t vtermno, char *buf, int count) uint32_t 71 drivers/tty/hvc/hvc_opal.c static int hvc_opal_hvsi_put_chars(uint32_t vtermno, const char *buf, int count) uint32_t 18 drivers/tty/hvc/hvc_riscv_sbi.c static int hvc_sbi_tty_put(uint32_t vtermno, const char *buf, int count) uint32_t 28 drivers/tty/hvc/hvc_riscv_sbi.c static int hvc_sbi_tty_get(uint32_t vtermno, char *buf, int count) uint32_t 34 drivers/tty/hvc/hvc_rtas.c static inline int hvc_rtas_write_console(uint32_t vtermno, const char *buf, uint32_t 47 drivers/tty/hvc/hvc_rtas.c static int hvc_rtas_read_console(uint32_t vtermno, char *buf, int count) uint32_t 22 drivers/tty/hvc/hvc_udbg.c static int hvc_udbg_put(uint32_t vtermno, const char *buf, int count) uint32_t 32 drivers/tty/hvc/hvc_udbg.c static int hvc_udbg_get(uint32_t vtermno, char *buf, int count) uint32_t 69 drivers/tty/hvc/hvc_vio.c static int hvterm_raw_get_chars(uint32_t vtermno, char *buf, int count) uint32_t 118 drivers/tty/hvc/hvc_vio.c static int hvterm_raw_put_chars(uint32_t vtermno, const char *buf, int count) uint32_t 136 drivers/tty/hvc/hvc_vio.c static int hvterm_hvsi_get_chars(uint32_t vtermno, char *buf, int count) uint32_t 146 drivers/tty/hvc/hvc_vio.c static int hvterm_hvsi_put_chars(uint32_t vtermno, const char *buf, int count) uint32_t 102 drivers/tty/hvc/hvc_xen.c static int domU_write_console(uint32_t vtermno, const char *data, int len) uint32_t 128 drivers/tty/hvc/hvc_xen.c static int domU_read_console(uint32_t vtermno, char *buf, int len) uint32_t 161 drivers/tty/hvc/hvc_xen.c static int dom0_read_console(uint32_t vtermno, char *buf, int len) uint32_t 170 drivers/tty/hvc/hvc_xen.c static int dom0_write_console(uint32_t vtermno, const char *str, int len) uint32_t 596 drivers/tty/hvc/hvc_xen.c static void xen_hvm_early_write(uint32_t vtermno, const char *str, int len) uint32_t 602 drivers/tty/hvc/hvc_xen.c static void xen_hvm_early_write(uint32_t vtermno, const char *str, int len) { } uint32_t 284 drivers/tty/hvc/hvcs.c uint32_t p_unit_address; /* partner unit address */ uint32_t 285 drivers/tty/hvc/hvcs.c uint32_t p_partition_ID; /* partner partition ID */ uint32_t 314 drivers/tty/hvc/hvcs.c uint32_t unit_address, unsigned int irq, struct vio_dev *dev); uint32_t 425 drivers/tty/hvc/hvcs.c (uint32_t)hvcsd->p_partition_ID); uint32_t 546 drivers/tty/hvc/hvcs.c uint32_t unit_address = hvcsd->vdev->unit_address; uint32_t 576 drivers/tty/hvc/hvcs.c uint32_t unit_address; uint32_t 702 drivers/tty/hvc/hvcs.c (uint32_t)hvcsd->p_partition_ID); uint32_t 894 drivers/tty/hvc/hvcs.c uint32_t unit_address = hvcsd->vdev->unit_address; uint32_t 1023 drivers/tty/hvc/hvcs.c static int hvcs_enable_device(struct hvcs_struct *hvcsd, uint32_t unit_address, uint32_t 73 drivers/tty/hvc/hvsi.c uint32_t vtermno; uint32_t 74 drivers/tty/hvc/hvsi.c uint32_t virq; uint32_t 257 drivers/tty/hvc/hvsi.c uint32_t mctrl_word; uint32_t 414 drivers/tty/hvc/hvsi_lib.c int (*get_chars)(uint32_t termno, char *buf, int count), uint32_t 415 drivers/tty/hvc/hvsi_lib.c int (*put_chars)(uint32_t termno, const char *buf, uint32_t 656 drivers/tty/serial/atmel_serial.c uint32_t ier = 0; uint32_t 689 drivers/tty/serial/atmel_serial.c uint32_t idr = 0; uint32_t 335 drivers/tty/vt/vt.c typedef uint32_t char32_t; uint32_t 2538 drivers/tty/vt/vt.c uint32_t first; uint32_t 2539 drivers/tty/vt/vt.c uint32_t last; uint32_t 2544 drivers/tty/vt/vt.c uint32_t ucs = *(uint32_t *)key; uint32_t 2554 drivers/tty/vt/vt.c static int is_double_width(uint32_t ucs) uint32_t 2648 drivers/tty/vt/vt.c static const uint32_t utf8_length_changes[] = { 0x0000007f, 0x000007ff, 0x0000ffff, 0x001fffff, 0x03ffffff, 0x7fffffff }; uint32_t 1036 drivers/usb/gadget/function/f_ncm.c uint32_t crc; uint32_t 1042 drivers/usb/gadget/function/f_ncm.c crc_pos = skb_put(skb, sizeof(uint32_t)); uint32_t 1188 drivers/usb/gadget/function/f_ncm.c unsigned crc_len = ncm->is_crc ? sizeof(uint32_t) : 0; uint32_t 1268 drivers/usb/gadget/function/f_ncm.c uint32_t crc, crc2; uint32_t 88 drivers/usb/gadget/udc/s3c2410_udc.c static uint32_t s3c2410_ticks = 0; uint32_t 1825 drivers/usb/host/max3421-hcd.c uint32_t value[2]; uint32_t 143 drivers/usb/host/ohci-pxa27x.c uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); uint32_t 144 drivers/usb/host/ohci-pxa27x.c uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB); uint32_t 224 drivers/usb/host/ohci-pxa27x.c uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); uint32_t 225 drivers/usb/host/ohci-pxa27x.c uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); uint32_t 263 drivers/usb/host/ohci-pxa27x.c uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); uint32_t 280 drivers/usb/host/ohci-pxa27x.c uint32_t uhchr; uint32_t 323 drivers/usb/host/ohci-pxa27x.c uint32_t uhccoms; uint32_t 406 drivers/vfio/pci/vfio_pci_intrs.c unsigned count, uint32_t flags, void *data) uint32_t 433 drivers/vfio/pci/vfio_pci_intrs.c unsigned count, uint32_t flags, void *data) uint32_t 453 drivers/vfio/pci/vfio_pci_intrs.c unsigned count, uint32_t flags, void *data) uint32_t 496 drivers/vfio/pci/vfio_pci_intrs.c unsigned count, uint32_t flags, void *data) uint32_t 546 drivers/vfio/pci/vfio_pci_intrs.c unsigned int count, uint32_t flags, uint32_t 602 drivers/vfio/pci/vfio_pci_intrs.c unsigned count, uint32_t flags, void *data) uint32_t 613 drivers/vfio/pci/vfio_pci_intrs.c unsigned count, uint32_t flags, void *data) uint32_t 622 drivers/vfio/pci/vfio_pci_intrs.c int vfio_pci_set_irqs_ioctl(struct vfio_pci_device *vdev, uint32_t flags, uint32_t 627 drivers/vfio/pci/vfio_pci_intrs.c unsigned start, unsigned count, uint32_t flags, uint32_t 218 drivers/vfio/pci/vfio_pci_nvlink2.c uint32_t mem_phandle = 0; uint32_t 137 drivers/vfio/pci/vfio_pci_private.h uint32_t flags, unsigned index, uint32_t 43 drivers/vfio/platform/vfio_platform_irq.c unsigned count, uint32_t flags, uint32_t 103 drivers/vfio/platform/vfio_platform_irq.c unsigned count, uint32_t flags, uint32_t 220 drivers/vfio/platform/vfio_platform_irq.c unsigned count, uint32_t flags, uint32_t 257 drivers/vfio/platform/vfio_platform_irq.c uint32_t flags, unsigned index, unsigned start, uint32_t 261 drivers/vfio/platform/vfio_platform_irq.c unsigned start, unsigned count, uint32_t flags, uint32_t 62 drivers/vfio/platform/vfio_platform_private.h uint32_t flags; uint32_t 90 drivers/vfio/platform/vfio_platform_private.h uint32_t flags, unsigned index, uint32_t 2287 drivers/vfio/vfio_iommu_type1.c uint32_t mask = VFIO_DMA_MAP_FLAG_READ | uint32_t 47 drivers/video/backlight/tdo24m.c static const uint32_t lcd_panel_reset[] = { uint32_t 55 drivers/video/backlight/tdo24m.c static const uint32_t lcd_panel_on[] = { uint32_t 63 drivers/video/backlight/tdo24m.c static const uint32_t lcd_panel_off[] = { uint32_t 71 drivers/video/backlight/tdo24m.c static const uint32_t lcd_vga_pass_through_tdo24m[] = { uint32_t 80 drivers/video/backlight/tdo24m.c static const uint32_t lcd_qvga_pass_through_tdo24m[] = { uint32_t 89 drivers/video/backlight/tdo24m.c static const uint32_t lcd_vga_transfer_tdo24m[] = { uint32_t 102 drivers/video/backlight/tdo24m.c static const uint32_t lcd_qvga_transfer[] = { uint32_t 115 drivers/video/backlight/tdo24m.c static const uint32_t lcd_vga_pass_through_tdo35s[] = { uint32_t 123 drivers/video/backlight/tdo24m.c static const uint32_t lcd_qvga_pass_through_tdo35s[] = { uint32_t 131 drivers/video/backlight/tdo24m.c static const uint32_t lcd_vga_transfer_tdo35s[] = { uint32_t 144 drivers/video/backlight/tdo24m.c static const uint32_t lcd_panel_config[] = { uint32_t 175 drivers/video/backlight/tdo24m.c static int tdo24m_writes(struct tdo24m *lcd, const uint32_t *array) uint32_t 178 drivers/video/backlight/tdo24m.c const uint32_t *p = array; uint32_t 179 drivers/video/backlight/tdo24m.c uint32_t data; uint32_t 1006 drivers/video/fbdev/fsl-diu-fb.c uint32_t mask = 1 << 31; uint32_t 1007 drivers/video/fbdev/fsl-diu-fb.c uint32_t line = be32_to_cpup(image); uint32_t 1046 drivers/video/fbdev/fsl-diu-fb.c uint32_t xx, yy; uint32_t 1068 drivers/video/fbdev/fsl-diu-fb.c DIV_ROUND_UP(image_size, sizeof(uint32_t)); uint32_t 1071 drivers/video/fbdev/fsl-diu-fb.c uint32_t *image, *source, *mask; uint32_t 1089 drivers/video/fbdev/fsl-diu-fb.c image = (uint32_t *)data->next_cursor; uint32_t 1090 drivers/video/fbdev/fsl-diu-fb.c source = (uint32_t *)cursor->image.data; uint32_t 1091 drivers/video/fbdev/fsl-diu-fb.c mask = (uint32_t *)cursor->mask; uint32_t 1581 drivers/video/fbdev/fsl-diu-fb.c uint32_t status = in_be32(&hw->int_status); uint32_t 79 drivers/video/fbdev/gbefb.c static uint32_t pseudo_palette[16]; uint32_t 80 drivers/video/fbdev/gbefb.c static uint32_t gbe_cmap[256]; uint32_t 25 drivers/video/fbdev/geode/display_gx.c uint32_t hi, lo; uint32_t 33 drivers/video/fbdev/geode/gxfb.h uint32_t gp[GP_REG_COUNT]; uint32_t 34 drivers/video/fbdev/geode/gxfb.h uint32_t dc[DC_REG_COUNT]; uint32_t 38 drivers/video/fbdev/geode/gxfb.h uint32_t pal[DC_PAL_COUNT]; uint32_t 298 drivers/video/fbdev/geode/gxfb.h static inline uint32_t read_gp(struct gxfb_par *par, int reg) uint32_t 303 drivers/video/fbdev/geode/gxfb.h static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val) uint32_t 308 drivers/video/fbdev/geode/gxfb.h static inline uint32_t read_dc(struct gxfb_par *par, int reg) uint32_t 313 drivers/video/fbdev/geode/gxfb.h static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val) uint32_t 318 drivers/video/fbdev/geode/gxfb.h static inline uint32_t read_vp(struct gxfb_par *par, int reg) uint32_t 323 drivers/video/fbdev/geode/gxfb.h static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val) uint32_t 328 drivers/video/fbdev/geode/gxfb.h static inline uint32_t read_fp(struct gxfb_par *par, int reg) uint32_t 333 drivers/video/fbdev/geode/gxfb.h static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val) uint32_t 43 drivers/video/fbdev/geode/lxfb.h uint32_t gp[GP_REG_COUNT]; uint32_t 44 drivers/video/fbdev/geode/lxfb.h uint32_t dc[DC_REG_COUNT]; uint32_t 48 drivers/video/fbdev/geode/lxfb.h uint32_t dc_pal[DC_PAL_COUNT]; uint32_t 49 drivers/video/fbdev/geode/lxfb.h uint32_t vp_pal[VP_PAL_COUNT]; uint32_t 50 drivers/video/fbdev/geode/lxfb.h uint32_t hcoeff[DC_HFILT_COUNT * 2]; uint32_t 51 drivers/video/fbdev/geode/lxfb.h uint32_t vcoeff[DC_VFILT_COUNT]; uint32_t 52 drivers/video/fbdev/geode/lxfb.h uint32_t vp_coeff[VP_COEFF_SIZE / 4]; uint32_t 381 drivers/video/fbdev/geode/lxfb.h static inline uint32_t read_gp(struct lxfb_par *par, int reg) uint32_t 386 drivers/video/fbdev/geode/lxfb.h static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val) uint32_t 391 drivers/video/fbdev/geode/lxfb.h static inline uint32_t read_dc(struct lxfb_par *par, int reg) uint32_t 396 drivers/video/fbdev/geode/lxfb.h static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val) uint32_t 401 drivers/video/fbdev/geode/lxfb.h static inline uint32_t read_vp(struct lxfb_par *par, int reg) uint32_t 406 drivers/video/fbdev/geode/lxfb.h static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val) uint32_t 411 drivers/video/fbdev/geode/lxfb.h static inline uint32_t read_fp(struct lxfb_par *par, int reg) uint32_t 416 drivers/video/fbdev/geode/lxfb.h static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val) uint32_t 315 drivers/video/fbdev/geode/lxfb_ops.c uint32_t hi, lo; uint32_t 587 drivers/video/fbdev/geode/lxfb_ops.c uint32_t filt; uint32_t 666 drivers/video/fbdev/geode/lxfb_ops.c uint32_t filt; uint32_t 43 drivers/video/fbdev/geode/suspend_gx.c static void gx_set_dotpll(uint32_t dotpll_hi) uint32_t 45 drivers/video/fbdev/geode/suspend_gx.c uint32_t dotpll_lo; uint32_t 175 drivers/video/fbdev/geode/suspend_gx.c gx_set_dotpll((uint32_t) (par->msr.dotpll >> 32)); uint32_t 211 drivers/video/fbdev/geode/suspend_gx.c uint32_t fp; uint32_t 244 drivers/video/fbdev/mx3fb.c uint32_t h_start_width; uint32_t 245 drivers/video/fbdev/mx3fb.c uint32_t v_start_width; uint32_t 258 drivers/video/fbdev/mx3fb.c uint32_t cur_ipu_buf; uint32_t 354 drivers/video/fbdev/mx3fb.c uint32_t b0, b1, b2; uint32_t 366 drivers/video/fbdev/mx3fb.c uint32_t reg; uint32_t 374 drivers/video/fbdev/mx3fb.c static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi) uint32_t 377 drivers/video/fbdev/mx3fb.c uint32_t reg; uint32_t 448 drivers/video/fbdev/mx3fb.c uint32_t enabled; uint32_t 507 drivers/video/fbdev/mx3fb.c uint32_t pixel_clk, uint32_t 515 drivers/video/fbdev/mx3fb.c uint32_t reg; uint32_t 516 drivers/video/fbdev/mx3fb.c uint32_t old_conf; uint32_t 517 drivers/video/fbdev/mx3fb.c uint32_t div; uint32_t 527 drivers/video/fbdev/mx3fb.c reg = ((uint32_t) (h_sync_width - 1) << 26) | uint32_t 528 drivers/video/fbdev/mx3fb.c ((uint32_t) (width + h_start_width + h_end_width - 1) << 16); uint32_t 535 drivers/video/fbdev/mx3fb.c reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | uint32_t 536 drivers/video/fbdev/mx3fb.c ((uint32_t) (height + v_start_width + v_end_width - 1) << 16); uint32_t 633 drivers/video/fbdev/mx3fb.c bool enable, uint32_t color_key) uint32_t 635 drivers/video/fbdev/mx3fb.c uint32_t reg, sdc_conf; uint32_t 672 drivers/video/fbdev/mx3fb.c uint32_t reg; uint32_t 679 drivers/video/fbdev/mx3fb.c mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL); uint32_t 711 drivers/video/fbdev/mx3fb.c static uint32_t bpp_to_pixfmt(int bpp) uint32_t 713 drivers/video/fbdev/mx3fb.c uint32_t pixfmt = 0; uint32_t 1354 drivers/video/fbdev/mx3fb.c (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len); uint32_t 288 drivers/video/fbdev/pxafb.c static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var) uint32_t 291 drivers/video/fbdev/pxafb.c uint32_t lccr3; uint32_t 626 drivers/video/fbdev/pxafb.c uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0); uint32_t 635 drivers/video/fbdev/pxafb.c uint32_t lccr5; uint32_t 681 drivers/video/fbdev/pxafb.c uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0); uint32_t 682 drivers/video/fbdev/pxafb.c uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0); uint32_t 683 drivers/video/fbdev/pxafb.c uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0); uint32_t 698 drivers/video/fbdev/pxafb.c uint32_t lccr5; uint32_t 1152 drivers/video/fbdev/pxafb.c uint32_t prsr; uint32_t 1478 drivers/video/fbdev/pxafb.c uint32_t lccr0; uint32_t 96 drivers/video/fbdev/pxafb.h uint32_t usage; uint32_t 97 drivers/video/fbdev/pxafb.h uint32_t control[2]; uint32_t 425 drivers/video/fbdev/udlfb.c uint32_t *device_address_ptr, uint32_t 432 drivers/video/fbdev/udlfb.c uint32_t dev_addr = *device_address_ptr; uint32_t 162 drivers/virt/fsl_hypervisor.c uint32_t count; /* The number of bytes left to copy */ uint32_t 473 drivers/virt/fsl_hypervisor.c uint32_t q[QSIZE]; uint32_t 483 drivers/virt/fsl_hypervisor.c uint32_t doorbell; /* The doorbell handle */ uint32_t 484 drivers/virt/fsl_hypervisor.c uint32_t partition; /* The partition handle, if used */ uint32_t 490 drivers/virt/fsl_hypervisor.c static void fsl_hv_queue_doorbell(uint32_t doorbell) uint32_t 598 drivers/virt/fsl_hypervisor.c uint32_t __user *p = (uint32_t __user *) buf; /* for put_user() */ uint32_t 603 drivers/virt/fsl_hypervisor.c while (len >= sizeof(uint32_t)) { uint32_t 604 drivers/virt/fsl_hypervisor.c uint32_t dbell; /* Local copy of doorbell queue data */ uint32_t 646 drivers/virt/fsl_hypervisor.c count += sizeof(uint32_t); uint32_t 647 drivers/virt/fsl_hypervisor.c len -= sizeof(uint32_t); uint32_t 733 drivers/virt/fsl_hypervisor.c const uint32_t *prop; uint32_t 734 drivers/virt/fsl_hypervisor.c uint32_t handle; uint32_t 750 drivers/virt/fsl_hypervisor.c if (!prop || (len != sizeof(uint32_t))) { uint32_t 842 drivers/virt/fsl_hypervisor.c const uint32_t *handle; uint32_t 58 drivers/watchdog/bcm2835_wdt.c uint32_t cur; uint32_t 68 drivers/watchdog/bcm2835_wdt.c uint32_t cur; uint32_t 96 drivers/watchdog/bcm2835_wdt.c uint32_t ret = readl_relaxed(wdt->base + PM_WDOG); uint32_t 58 drivers/watchdog/bcm_kona_wdt.c static int secure_register_read(struct bcm_kona_wdt *wdt, uint32_t offset) uint32_t 60 drivers/watchdog/bcm_kona_wdt.c uint32_t val; uint32_t 91 drivers/watchdog/digicolor_wdt.c uint32_t count = readl_relaxed(wdt->base + TIMER_A_COUNT); uint32_t 142 drivers/watchdog/pnx833x_wdt.c uint32_t timeout, timeout_left = 0; uint32_t 159 drivers/watchdog/st_lpc_wdt.c uint32_t mode; uint32_t 61 drivers/xen/events/events_fifo.c uint32_t head[EVTCHN_FIFO_MAX_QUEUES]; uint32_t 258 drivers/xen/events/events_fifo.c static uint32_t clear_linked(volatile event_word_t *word) uint32_t 288 drivers/xen/events/events_fifo.c uint32_t head; uint32_t 122 drivers/xen/gntalloc.c uint32_t *gref_ids, struct gntalloc_file_private_data *priv) uint32_t 219 drivers/xen/gntalloc.c uint64_t index, uint32_t count) uint32_t 288 drivers/xen/gntalloc.c uint32_t *gref_ids; uint32_t 1318 drivers/xen/grant-table.c uint32_t base, width; uint32_t 58 drivers/xen/mcelog.c static uint32_t ncpus; uint32_t 225 drivers/xen/mcelog.c uint32_t i; uint32_t 285 drivers/xen/mcelog.c static int mc_queue_handle(uint32_t flags) uint32_t 48 drivers/xen/pci.c uint32_t pxm; uint32_t 60 drivers/xen/pcpu.c uint32_t cpu_id; uint32_t 61 drivers/xen/pcpu.c uint32_t flags; uint32_t 73 drivers/xen/pcpu.c static int xen_pcpu_down(uint32_t cpu_id) uint32_t 84 drivers/xen/pcpu.c static int xen_pcpu_up(uint32_t cpu_id) uint32_t 162 drivers/xen/pcpu.c static bool xen_pcpu_online(uint32_t flags) uint32_t 183 drivers/xen/pcpu.c static struct pcpu *get_pcpu(uint32_t cpu_id) uint32_t 269 drivers/xen/pcpu.c static int sync_pcpu(uint32_t cpu, uint32_t *max_cpu) uint32_t 316 drivers/xen/pcpu.c uint32_t cpu = 0, max_cpu = 0; uint32_t 359 drivers/xen/pcpu.c int xen_pcpu_id(uint32_t acpi_id) uint32_t 63 drivers/xen/pvcalls-back.c uint32_t ring_order; uint32_t 303 drivers/xen/pvcalls-back.c uint32_t evtchn, uint32_t 92 drivers/xen/pvcalls-front.c uint32_t inflight_req_id; uint32_t 908 drivers/xen/pvcalls-front.c uint32_t req_id = READ_ONCE(map->passive.inflight_req_id); uint32_t 406 drivers/xen/sys-hypervisor.c uint32_t mode; uint32_t 447 drivers/xen/sys-hypervisor.c uint32_t mode; uint32_t 455 drivers/xen/sys-hypervisor.c mode = (uint32_t)xp.val; uint32_t 469 drivers/xen/sys-hypervisor.c uint32_t features; uint32_t 497 drivers/xen/sys-hypervisor.c return sprintf(buffer, "0x%x\n", (uint32_t)xp.val); uint32_t 167 drivers/xen/xen-acpi-cpuhotplug.c apic_id = (uint32_t)lapic->id; uint32_t 124 drivers/xen/xen-scsiback.c uint32_t data_len; uint32_t 125 drivers/xen/xen-scsiback.c uint32_t result; uint32_t 323 drivers/xen/xen-scsiback.c char *sense_buffer, int32_t result, uint32_t resid, uint32_t 361 drivers/xen/xen-scsiback.c uint32_t resid, struct vscsibk_pend *pending_req) uint32_t 732 drivers/xen/xen-scsiback.c uint32_t result; uint32_t 79 drivers/xen/xenbus/xenbus.h uint32_t caller_req_id; uint32_t 81 drivers/xen/xenbus/xenbus_comms.c char *buf, uint32_t *len) uint32_t 91 drivers/xen/xenbus/xenbus_comms.c const char *buf, uint32_t *len) uint32_t 352 drivers/xen/xenbus/xenbus_dev_frontend.c struct xenbus_file_priv *u, uint32_t tx_id) uint32_t 555 drivers/xen/xenbus/xenbus_dev_frontend.c uint32_t msg_type; uint32_t 70 drivers/xen/xenbus/xenbus_xs.c static uint32_t xs_request_id; uint32_t 115 drivers/xen/xenbus/xenbus_xs.c static uint32_t xs_request_enter(struct xb_req_data *req) uint32_t 117 drivers/xen/xenbus/xenbus_xs.c uint32_t rq_id; uint32_t 729 drivers/xen/xenbus/xenbus_xs.c uint32_t eax, ebx, ecx, edx, base; uint32_t 19 drivers/xen/xenfs/xensyms.c uint32_t namelen; uint32_t 102 drivers/xen/xlate_mmu.c uint32_t i; uint32_t 640 fs/befs/linuxvfs.c uint32_t generation) uint32_t 336 fs/cachefiles/namei.c (uint32_t) ktime_get_real_seconds(), uint32_t 337 fs/cachefiles/namei.c (uint32_t) atomic_inc_return(&cache->gravecounter)); uint32_t 35 fs/cifs/cifs_spnego.h uint32_t version; uint32_t 36 fs/cifs/cifs_spnego.h uint32_t flags; uint32_t 37 fs/cifs/cifs_spnego.h uint32_t sesskey_len; uint32_t 38 fs/cifs/cifs_spnego.h uint32_t secblob_len; uint32_t 216 fs/cifs/cifsacl.c is_well_known_sid(const struct cifs_sid *psid, uint32_t *puid, bool is_group) uint32_t 365 fs/cifs/cifsacl.c uint32_t unix_id; uint32_t 51 fs/dlm/ast.c int dlm_add_lkb_callback(struct dlm_lkb *lkb, uint32_t flags, int mode, uint32_t 52 fs/dlm/ast.c int status, uint32_t sbflags, uint64_t seq) uint32_t 173 fs/dlm/ast.c void dlm_add_cb(struct dlm_lkb *lkb, uint32_t flags, int mode, int status, uint32_t 174 fs/dlm/ast.c uint32_t sbflags) uint32_t 15 fs/dlm/ast.h int dlm_add_lkb_callback(struct dlm_lkb *lkb, uint32_t flags, int mode, uint32_t 16 fs/dlm/ast.h int status, uint32_t sbflags, uint64_t seq); uint32_t 19 fs/dlm/ast.h void dlm_add_cb(struct dlm_lkb *lkb, uint32_t flags, int mode, int status, uint32_t 20 fs/dlm/ast.h uint32_t sbflags); uint32_t 38 fs/dlm/config.c static uint32_t dlm_comm_count; uint32_t 685 fs/dlm/config.c uint32_t seq = 0; uint32_t 822 fs/dlm/config.c int dlm_comm_seq(int nodeid, uint32_t *seq) uint32_t 19 fs/dlm/config.h uint32_t comm_seq; uint32_t 47 fs/dlm/config.h int dlm_comm_seq(int nodeid, uint32_t *seq); uint32_t 33 fs/dlm/dir.c int dlm_hash2nodeid(struct dlm_ls *ls, uint32_t hash) uint32_t 35 fs/dlm/dir.c uint32_t node; uint32_t 201 fs/dlm/dir.c uint32_t hash, bucket; uint32_t 16 fs/dlm/dir.h int dlm_hash2nodeid(struct dlm_ls *ls, uint32_t hash); uint32_t 112 fs/dlm/dlm_internal.h uint32_t flags; uint32_t 127 fs/dlm/dlm_internal.h uint32_t generation; uint32_t 146 fs/dlm/dlm_internal.h uint32_t flags; uint32_t 225 fs/dlm/dlm_internal.h uint32_t flags; /* DLM_CBF_ */ uint32_t 236 fs/dlm/dlm_internal.h uint32_t lkb_id; /* our lock ID */ uint32_t 237 fs/dlm/dlm_internal.h uint32_t lkb_remid; /* lock ID on remote partner */ uint32_t 238 fs/dlm/dlm_internal.h uint32_t lkb_exflags; /* external flags from caller */ uint32_t 239 fs/dlm/dlm_internal.h uint32_t lkb_sbflags; /* lksb flags */ uint32_t 240 fs/dlm/dlm_internal.h uint32_t lkb_flags; /* internal flags */ uint32_t 241 fs/dlm/dlm_internal.h uint32_t lkb_lvbseq; /* lvb sequence number */ uint32_t 302 fs/dlm/dlm_internal.h uint32_t res_lvbseq; uint32_t 303 fs/dlm/dlm_internal.h uint32_t res_hash; uint32_t 304 fs/dlm/dlm_internal.h uint32_t res_bucket; /* rsbtbl */ uint32_t 306 fs/dlm/dlm_internal.h uint32_t res_first_lkid; uint32_t 380 fs/dlm/dlm_internal.h uint32_t h_version; uint32_t 381 fs/dlm/dlm_internal.h uint32_t h_lockspace; uint32_t 382 fs/dlm/dlm_internal.h uint32_t h_nodeid; /* nodeid of sender */ uint32_t 406 fs/dlm/dlm_internal.h uint32_t m_type; /* DLM_MSG_ */ uint32_t 407 fs/dlm/dlm_internal.h uint32_t m_nodeid; uint32_t 408 fs/dlm/dlm_internal.h uint32_t m_pid; uint32_t 409 fs/dlm/dlm_internal.h uint32_t m_lkid; /* lkid on sender */ uint32_t 410 fs/dlm/dlm_internal.h uint32_t m_remid; /* lkid on receiver */ uint32_t 411 fs/dlm/dlm_internal.h uint32_t m_parent_lkid; uint32_t 412 fs/dlm/dlm_internal.h uint32_t m_parent_remid; uint32_t 413 fs/dlm/dlm_internal.h uint32_t m_exflags; uint32_t 414 fs/dlm/dlm_internal.h uint32_t m_sbflags; uint32_t 415 fs/dlm/dlm_internal.h uint32_t m_flags; uint32_t 416 fs/dlm/dlm_internal.h uint32_t m_lvbseq; uint32_t 417 fs/dlm/dlm_internal.h uint32_t m_hash; uint32_t 448 fs/dlm/dlm_internal.h uint32_t rc_type; /* DLM_RCOM_ */ uint32_t 522 fs/dlm/dlm_internal.h uint32_t ls_global_id; /* global unique lockspace ID */ uint32_t 523 fs/dlm/dlm_internal.h uint32_t ls_generation; uint32_t 524 fs/dlm/dlm_internal.h uint32_t ls_exflags; uint32_t 537 fs/dlm/dlm_internal.h uint32_t ls_rsbtbl_size; uint32_t 598 fs/dlm/dlm_internal.h uint32_t ls_recover_status; /* DLM_RS_ */ uint32_t 350 fs/dlm/lock.c uint32_t bucket = r->res_bucket; uint32_t 544 fs/dlm/lock.c uint32_t hash, uint32_t b, uint32_t 723 fs/dlm/lock.c uint32_t hash, uint32_t b, uint32_t 819 fs/dlm/lock.c uint32_t hash, b; uint32_t 914 fs/dlm/lock.c uint32_t hash, b; uint32_t 1083 fs/dlm/lock.c static void dlm_dump_rsb_hash(struct dlm_ls *ls, uint32_t hash) uint32_t 1103 fs/dlm/lock.c uint32_t hash, b; uint32_t 1218 fs/dlm/lock.c static int find_lkb(struct dlm_ls *ls, uint32_t lkid, struct dlm_lkb **lkb_ret) uint32_t 1247 fs/dlm/lock.c uint32_t lkid = lkb->lkb_id; uint32_t 2806 fs/dlm/lock.c static int set_lock_args(int mode, struct dlm_lksb *lksb, uint32_t flags, uint32_t 2872 fs/dlm/lock.c static int set_unlock_args(uint32_t flags, void *astarg, struct dlm_args *args) uint32_t 3413 fs/dlm/lock.c uint32_t flags, uint32_t 3416 fs/dlm/lock.c uint32_t parent_lkid, uint32_t 3464 fs/dlm/lock.c uint32_t lkid, uint32_t 3465 fs/dlm/lock.c uint32_t flags, uint32_t 4020 fs/dlm/lock.c uint32_t hash, b; uint32_t 4390 fs/dlm/lock.c uint32_t hash, b; uint32_t 4859 fs/dlm/lock.c uint32_t saved_seq) uint32_t 5011 fs/dlm/lock.c uint32_t saved_seq) uint32_t 5546 fs/dlm/lock.c uint32_t remid) uint32_t 5558 fs/dlm/lock.c uint32_t remid) uint32_t 5631 fs/dlm/lock.c uint32_t remid = 0; uint32_t 5712 fs/dlm/lock.c uint32_t lkid, remid; uint32_t 5772 fs/dlm/lock.c int mode, uint32_t flags, void *name, unsigned int namelen, uint32_t 5837 fs/dlm/lock.c int mode, uint32_t flags, uint32_t lkid, char *lvb_in, uint32_t 5897 fs/dlm/lock.c int mode, uint32_t flags, void *name, unsigned int namelen, uint32_t 5898 fs/dlm/lock.c unsigned long timeout_cs, uint32_t *lkid) uint32_t 5963 fs/dlm/lock.c uint32_t flags, uint32_t lkid, char *lvb_in) uint32_t 6012 fs/dlm/lock.c uint32_t flags, uint32_t lkid) uint32_t 6049 fs/dlm/lock.c int dlm_user_deadlock(struct dlm_ls *ls, uint32_t flags, uint32_t lkid) uint32_t 18 fs/dlm/lock.h uint32_t saved_seq); uint32_t 45 fs/dlm/lock.h uint32_t flags, void *name, unsigned int namelen, uint32_t 48 fs/dlm/lock.h int mode, uint32_t flags, uint32_t lkid, char *lvb_in, uint32_t 51 fs/dlm/lock.h int mode, uint32_t flags, void *name, unsigned int namelen, uint32_t 52 fs/dlm/lock.h unsigned long timeout_cs, uint32_t *lkid); uint32_t 54 fs/dlm/lock.h uint32_t flags, uint32_t lkid, char *lvb_in); uint32_t 56 fs/dlm/lock.h uint32_t flags, uint32_t lkid); uint32_t 59 fs/dlm/lock.h int dlm_user_deadlock(struct dlm_ls *ls, uint32_t flags, uint32_t lkid); uint32_t 105 fs/dlm/lockspace.c uint32_t status = dlm_recover_status(ls); uint32_t 318 fs/dlm/lockspace.c struct dlm_ls *dlm_find_lockspace_global(uint32_t id) uint32_t 424 fs/dlm/lockspace.c uint32_t flags, int lvblen, uint32_t 697 fs/dlm/lockspace.c uint32_t flags, int lvblen, uint32_t 17 fs/dlm/lockspace.h struct dlm_ls *dlm_find_lockspace_global(uint32_t id); uint32_t 103 fs/dlm/lowcomms.c uint32_t nodeid; /* So we know who we are in the list */ uint32_t 61 fs/dlm/member.c static void log_slots(struct dlm_ls *ls, uint32_t gen, int num_slots, uint32_t 104 fs/dlm/member.c uint32_t gen; uint32_t 165 fs/dlm/member.c struct dlm_slot **slots_out, uint32_t *gen_out) uint32_t 174 fs/dlm/member.c uint32_t gen = 0; uint32_t 458 fs/dlm/member.c uint32_t seq; uint32_t 27 fs/dlm/member.h struct dlm_slot **slots_out, uint32_t *gen_out); uint32_t 68 fs/dlm/midcomms.c uint32_t lockspace; uint32_t 13 fs/dlm/netlink.c static uint32_t dlm_nl_seqnum; uint32_t 14 fs/dlm/netlink.c static uint32_t listener_nlportid; uint32_t 73 fs/dlm/rcom.c uint32_t flags) uint32_t 83 fs/dlm/rcom.c uint32_t num_slots) uint32_t 142 fs/dlm/rcom.c int dlm_rcom_status(struct dlm_ls *ls, int nodeid, uint32_t status_flags) uint32_t 197 fs/dlm/rcom.c uint32_t status; uint32_t 538 fs/dlm/rcom.c uint32_t status; uint32_t 15 fs/dlm/rcom.h int dlm_rcom_status(struct dlm_ls *ls, int nodeid, uint32_t status_flags); uint32_t 74 fs/dlm/recover.c uint32_t dlm_recover_status(struct dlm_ls *ls) uint32_t 76 fs/dlm/recover.c uint32_t status; uint32_t 83 fs/dlm/recover.c static void _set_recover_status(struct dlm_ls *ls, uint32_t status) uint32_t 88 fs/dlm/recover.c void dlm_set_recover_status(struct dlm_ls *ls, uint32_t status) uint32_t 95 fs/dlm/recover.c static int wait_status_all(struct dlm_ls *ls, uint32_t wait_status, uint32_t 128 fs/dlm/recover.c static int wait_status_low(struct dlm_ls *ls, uint32_t wait_status, uint32_t 129 fs/dlm/recover.c uint32_t status_flags) uint32_t 154 fs/dlm/recover.c static int wait_status(struct dlm_ls *ls, uint32_t status) uint32_t 156 fs/dlm/recover.c uint32_t status_all = status << 1; uint32_t 175 fs/dlm/recover.c uint32_t gen; uint32_t 736 fs/dlm/recover.c uint32_t high_seq = 0; uint32_t 16 fs/dlm/recover.h uint32_t dlm_recover_status(struct dlm_ls *ls); uint32_t 17 fs/dlm/recover.h void dlm_set_recover_status(struct dlm_ls *ls, uint32_t status); uint32_t 20 fs/dlm/requestqueue.c uint32_t recover_seq; uint32_t 130 fs/dlm/requestqueue.c uint32_t type = ms->m_type; uint32_t 175 fs/dlm/user.c void dlm_user_add_ast(struct dlm_lkb *lkb, uint32_t flags, int mode, uint32_t 176 fs/dlm/user.c int status, uint32_t sbflags, uint64_t seq) uint32_t 241 fs/dlm/user.c uint32_t lkid; uint32_t 687 fs/dlm/user.c uint32_t flags, int mode, int copy_lvb, uint32_t 9 fs/dlm/user.h void dlm_user_add_ast(struct dlm_lkb *lkb, uint32_t flags, int mode, uint32_t 10 fs/dlm/user.h int status, uint32_t sbflags, uint64_t seq); uint32_t 30 fs/efs/efs.h typedef uint32_t efs_ino_t; uint32_t 16 fs/ext4/fsmap.h uint32_t fmr_flags; /* mapping flags */ uint32_t 23 fs/ext4/fsmap.h uint32_t fmh_iflags; /* control flags */ uint32_t 24 fs/ext4/fsmap.h uint32_t fmh_oflags; /* output flags */ uint32_t 80 fs/fscache/fsdef.c uint32_t version; uint32_t 241 fs/fuse/fuse_i.h uint32_t opcode; uint32_t 680 fs/gfs2/incore.h uint32_t ls_recover_mount; /* gen in first recover_done cb */ uint32_t 681 fs/gfs2/incore.h uint32_t ls_recover_start; /* gen in last recover_done cb */ uint32_t 682 fs/gfs2/incore.h uint32_t ls_recover_block; /* copy recover_start in last recover_prep */ uint32_t 683 fs/gfs2/incore.h uint32_t ls_recover_size; /* size of recover_submit, recover_result */ uint32_t 684 fs/gfs2/incore.h uint32_t *ls_recover_submit; /* gen in last recover_slot cb per jid */ uint32_t 685 fs/gfs2/incore.h uint32_t *ls_recover_result; /* result of last jid recovery */ uint32_t 465 fs/gfs2/lock_dlm.c static void control_lvb_read(struct lm_lockstruct *ls, uint32_t *lvb_gen, uint32_t 474 fs/gfs2/lock_dlm.c static void control_lvb_write(struct lm_lockstruct *ls, uint32_t lvb_gen, uint32_t 517 fs/gfs2/lock_dlm.c static int sync_lock(struct gfs2_sbd *sdp, int mode, uint32_t flags, uint32_t 554 fs/gfs2/lock_dlm.c static int mounted_lock(struct gfs2_sbd *sdp, int mode, uint32_t flags) uint32_t 567 fs/gfs2/lock_dlm.c static int control_lock(struct gfs2_sbd *sdp, int mode, uint32_t flags) uint32_t 578 fs/gfs2/lock_dlm.c uint32_t block_gen, start_gen, lvb_gen, flags; uint32_t 755 fs/gfs2/lock_dlm.c uint32_t start_gen, block_gen, mount_gen, lvb_gen; uint32_t 939 fs/gfs2/lock_dlm.c memset(ls->ls_recover_submit, 0, ls->ls_recover_size*sizeof(uint32_t)); uint32_t 940 fs/gfs2/lock_dlm.c memset(ls->ls_recover_result, 0, ls->ls_recover_size*sizeof(uint32_t)); uint32_t 953 fs/gfs2/lock_dlm.c uint32_t start_gen, block_gen; uint32_t 990 fs/gfs2/lock_dlm.c memset(ls->ls_recover_submit, 0, ls->ls_recover_size*sizeof(uint32_t)); uint32_t 991 fs/gfs2/lock_dlm.c memset(ls->ls_recover_result, 0, ls->ls_recover_size*sizeof(uint32_t)); uint32_t 1020 fs/gfs2/lock_dlm.c uint32_t *submit = NULL; uint32_t 1021 fs/gfs2/lock_dlm.c uint32_t *result = NULL; uint32_t 1022 fs/gfs2/lock_dlm.c uint32_t old_size, new_size; uint32_t 1044 fs/gfs2/lock_dlm.c submit = kcalloc(new_size, sizeof(uint32_t), GFP_NOFS); uint32_t 1045 fs/gfs2/lock_dlm.c result = kcalloc(new_size, sizeof(uint32_t), GFP_NOFS); uint32_t 1053 fs/gfs2/lock_dlm.c memcpy(submit, ls->ls_recover_submit, old_size * sizeof(uint32_t)); uint32_t 1054 fs/gfs2/lock_dlm.c memcpy(result, ls->ls_recover_result, old_size * sizeof(uint32_t)); uint32_t 1123 fs/gfs2/lock_dlm.c int our_slot, uint32_t generation) uint32_t 1200 fs/gfs2/lock_dlm.c uint32_t flags; uint32_t 61 fs/jffs2/acl.c uint32_t ver; uint32_t 310 fs/jffs2/build.c uint32_t size; uint32_t 28 fs/jffs2/compr.c static uint32_t none_stat_compr_blocks=0,none_stat_decompr_blocks=0,none_stat_compr_size=0; uint32_t 35 fs/jffs2/compr.c struct jffs2_compressor *best, uint32_t size, uint32_t bestsize) uint32_t 79 fs/jffs2/compr.c uint32_t orig_slen, orig_dlen; uint32_t 150 fs/jffs2/compr.c uint32_t *datalen, uint32_t *cdatalen) uint32_t 156 fs/jffs2/compr.c uint32_t orig_slen, orig_dlen; uint32_t 157 fs/jffs2/compr.c uint32_t best_slen=0, best_dlen=0; uint32_t 255 fs/jffs2/compr.c unsigned char *data_out, uint32_t cdatalen, uint32_t datalen) uint32_t 54 fs/jffs2/compr.h uint32_t *srclen, uint32_t *destlen); uint32_t 56 fs/jffs2/compr.h uint32_t cdatalen, uint32_t datalen); uint32_t 60 fs/jffs2/compr.h uint32_t compr_buf_size; /* used by size compr. mode */ uint32_t 61 fs/jffs2/compr.h uint32_t stat_compr_orig_size; uint32_t 62 fs/jffs2/compr.h uint32_t stat_compr_new_size; uint32_t 63 fs/jffs2/compr.h uint32_t stat_compr_blocks; uint32_t 64 fs/jffs2/compr.h uint32_t stat_decompr_blocks; uint32_t 75 fs/jffs2/compr.h uint32_t *datalen, uint32_t *cdatalen); uint32_t 79 fs/jffs2/compr.h unsigned char *data_out, uint32_t cdatalen, uint32_t datalen); uint32_t 44 fs/jffs2/compr_lzo.c uint32_t *sourcelen, uint32_t *dstlen) uint32_t 69 fs/jffs2/compr_lzo.c uint32_t srclen, uint32_t destlen) uint32_t 34 fs/jffs2/compr_rtime.c uint32_t *sourcelen, uint32_t *dstlen) uint32_t 75 fs/jffs2/compr_rtime.c uint32_t srclen, uint32_t destlen) uint32_t 263 fs/jffs2/compr_rubin.c unsigned char *cpage_out, uint32_t *sourcelen, uint32_t 264 fs/jffs2/compr_rubin.c uint32_t *dstlen) uint32_t 298 fs/jffs2/compr_rubin.c uint32_t *sourcelen, uint32_t *dstlen) uint32_t 306 fs/jffs2/compr_rubin.c uint32_t *sourcelen, uint32_t *dstlen) uint32_t 312 fs/jffs2/compr_rubin.c uint32_t mysrclen, mydstlen; uint32_t 370 fs/jffs2/compr_rubin.c unsigned char *page_out, uint32_t srclen, uint32_t 371 fs/jffs2/compr_rubin.c uint32_t destlen) uint32_t 386 fs/jffs2/compr_rubin.c uint32_t sourcelen, uint32_t dstlen) uint32_t 395 fs/jffs2/compr_rubin.c uint32_t sourcelen, uint32_t dstlen) uint32_t 74 fs/jffs2/compr_zlib.c uint32_t *sourcelen, uint32_t *dstlen) uint32_t 143 fs/jffs2/compr_zlib.c uint32_t srclen, uint32_t destlen) uint32_t 126 fs/jffs2/debug.c uint32_t ofs, int len) uint32_t 163 fs/jffs2/debug.c uint32_t free = 0, dirty = 0, used = 0, wasted = 0, uint32_t 313 fs/jffs2/debug.c uint32_t my_used_size = 0; uint32_t 314 fs/jffs2/debug.c uint32_t my_unchecked_size = 0; uint32_t 315 fs/jffs2/debug.c uint32_t my_dirty_size = 0; uint32_t 319 fs/jffs2/debug.c uint32_t totlen = ref_totlen(c, jeb, ref2); uint32_t 503 fs/jffs2/debug.c uint32_t dirty = 0; uint32_t 525 fs/jffs2/debug.c uint32_t dirty = 0; uint32_t 548 fs/jffs2/debug.c uint32_t dirty = 0; uint32_t 706 fs/jffs2/debug.c uint32_t lastofs = 0; uint32_t 737 fs/jffs2/debug.c __jffs2_dbg_dump_buffer(unsigned char *buf, int len, uint32_t offs) uint32_t 773 fs/jffs2/debug.c __jffs2_dbg_dump_node(struct jffs2_sb_info *c, uint32_t ofs) uint32_t 778 fs/jffs2/debug.c uint32_t crc; uint32_t 192 fs/jffs2/debug.h uint32_t ofs, int len); uint32_t 214 fs/jffs2/debug.h __jffs2_dbg_dump_buffer(unsigned char *buf, int len, uint32_t offs); uint32_t 216 fs/jffs2/debug.h __jffs2_dbg_dump_node(struct jffs2_sb_info *c, uint32_t ofs); uint32_t 80 fs/jffs2/dir.c uint32_t ino = 0; uint32_t 230 fs/jffs2/dir.c uint32_t now = JFFS2_NOW(); uint32_t 250 fs/jffs2/dir.c uint32_t now; uint32_t 289 fs/jffs2/dir.c uint32_t alloclen; uint32_t 451 fs/jffs2/dir.c uint32_t alloclen; uint32_t 591 fs/jffs2/dir.c uint32_t now = JFFS2_NOW(); uint32_t 620 fs/jffs2/dir.c uint32_t alloclen; uint32_t 763 fs/jffs2/dir.c uint32_t now; uint32_t 24 fs/jffs2/erase.c static void jffs2_erase_failed(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t bad_offset); uint32_t 32 fs/jffs2/erase.c uint32_t bad_offset; uint32_t 174 fs/jffs2/erase.c static void jffs2_erase_failed(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t bad_offset) uint32_t 178 fs/jffs2/erase.c if (jffs2_cleanmarker_oob(c) && (bad_offset != (uint32_t)MTD_FAIL_ADDR_UNKNOWN)) { uint32_t 313 fs/jffs2/erase.c static int jffs2_block_check_erase(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t *bad_offset) uint32_t 316 fs/jffs2/erase.c uint32_t ofs; uint32_t 362 fs/jffs2/erase.c uint32_t readlen = min((uint32_t)PAGE_SIZE, jeb->offset + c->sector_size - ofs); uint32_t 404 fs/jffs2/erase.c uint32_t uninitialized_var(bad_offset); uint32_t 139 fs/jffs2/file.c uint32_t pageofs = index << PAGE_SHIFT; uint32_t 154 fs/jffs2/file.c uint32_t alloc_len; uint32_t 177 fs/jffs2/file.c ri.isize = cpu_to_je32(max((uint32_t)inode->i_size, pageofs)); uint32_t 250 fs/jffs2/file.c uint32_t writtenlen = 0; uint32_t 285 fs/jffs2/file.c ri->isize = cpu_to_je32((uint32_t)inode->i_size); uint32_t 42 fs/jffs2/fs.c uint32_t alloclen; uint32_t 493 fs/jffs2/fs.c static int calculate_inocache_hashsize(uint32_t flash_size) uint32_t 36 fs/jffs2/gc.c uint32_t start, uint32_t end); uint32_t 39 fs/jffs2/gc.c uint32_t start, uint32_t end); uint32_t 130 fs/jffs2/gc.c uint32_t gcblock_dirty; uint32_t 503 fs/jffs2/gc.c uint32_t start = 0, end = 0, nrfrags = 0; uint32_t 598 fs/jffs2/gc.c uint32_t phys_ofs, alloclen; uint32_t 599 fs/jffs2/gc.c uint32_t crc, rawlen; uint32_t 713 fs/jffs2/gc.c uint32_t dummy; uint32_t 767 fs/jffs2/gc.c uint32_t alloclen, ilen; uint32_t 855 fs/jffs2/gc.c uint32_t alloclen; uint32_t 912 fs/jffs2/gc.c uint32_t name_crc = crc32(0, fd->name, name_len); uint32_t 913 fs/jffs2/gc.c uint32_t rawlen = ref_totlen(c, jeb, fd->raw); uint32_t 1015 fs/jffs2/gc.c uint32_t start, uint32_t end) uint32_t 1020 fs/jffs2/gc.c uint32_t alloclen, ilen; uint32_t 1030 fs/jffs2/gc.c uint32_t crc; uint32_t 1166 fs/jffs2/gc.c uint32_t start, uint32_t end) uint32_t 1171 fs/jffs2/gc.c uint32_t alloclen, offset, orig_end, orig_start; uint32_t 1194 fs/jffs2/gc.c uint32_t min, max; uint32_t 1343 fs/jffs2/gc.c uint32_t datalen; uint32_t 1344 fs/jffs2/gc.c uint32_t cdatalen; uint32_t 1355 fs/jffs2/gc.c cdatalen = min_t(uint32_t, alloclen - sizeof(ri), end - offset); uint32_t 30 fs/jffs2/jffs2_fs_i.h uint32_t highest_version; uint32_t 51 fs/jffs2/jffs2_fs_sb.h uint32_t highest_ino; uint32_t 52 fs/jffs2/jffs2_fs_sb.h uint32_t check_ino; /* *NEXT* inode to be checked */ uint32_t 63 fs/jffs2/jffs2_fs_sb.h uint32_t cleanmarker_size; /* Size of an _inline_ CLEANMARKER uint32_t 66 fs/jffs2/jffs2_fs_sb.h uint32_t flash_size; uint32_t 67 fs/jffs2/jffs2_fs_sb.h uint32_t used_size; uint32_t 68 fs/jffs2/jffs2_fs_sb.h uint32_t dirty_size; uint32_t 69 fs/jffs2/jffs2_fs_sb.h uint32_t wasted_size; uint32_t 70 fs/jffs2/jffs2_fs_sb.h uint32_t free_size; uint32_t 71 fs/jffs2/jffs2_fs_sb.h uint32_t erasing_size; uint32_t 72 fs/jffs2/jffs2_fs_sb.h uint32_t bad_size; uint32_t 73 fs/jffs2/jffs2_fs_sb.h uint32_t sector_size; uint32_t 74 fs/jffs2/jffs2_fs_sb.h uint32_t unchecked_size; uint32_t 76 fs/jffs2/jffs2_fs_sb.h uint32_t nr_free_blocks; uint32_t 77 fs/jffs2/jffs2_fs_sb.h uint32_t nr_erasing_blocks; uint32_t 88 fs/jffs2/jffs2_fs_sb.h uint32_t nospc_dirty_size; uint32_t 90 fs/jffs2/jffs2_fs_sb.h uint32_t nr_blocks; uint32_t 124 fs/jffs2/jffs2_fs_sb.h uint32_t wbuf_pagesize; /* 0 for NOR and other flashes with no wbuf */ uint32_t 131 fs/jffs2/jffs2_fs_sb.h uint32_t wbuf_ofs; uint32_t 132 fs/jffs2/jffs2_fs_sb.h uint32_t wbuf_len; uint32_t 147 fs/jffs2/jffs2_fs_sb.h uint32_t highest_xid; uint32_t 148 fs/jffs2/jffs2_fs_sb.h uint32_t highest_xseqno; uint32_t 155 fs/jffs2/jffs2_fs_sb.h uint32_t xdatum_mem_usage; uint32_t 156 fs/jffs2/jffs2_fs_sb.h uint32_t xdatum_mem_threshold; uint32_t 59 fs/jffs2/nodelist.c uint32_t jffs2_truncate_fragtree(struct jffs2_sb_info *c, struct rb_root *list, uint32_t size) uint32_t 149 fs/jffs2/nodelist.c static struct jffs2_node_frag * new_fragment(struct jffs2_full_dnode *fn, uint32_t ofs, uint32_t size) uint32_t 171 fs/jffs2/nodelist.c struct jffs2_node_frag *this, uint32_t lastend) uint32_t 218 fs/jffs2/nodelist.c uint32_t lastend; uint32_t 421 fs/jffs2/nodelist.c struct jffs2_inode_cache *jffs2_get_ino_cache(struct jffs2_sb_info *c, uint32_t ino) uint32_t 524 fs/jffs2/nodelist.c struct jffs2_node_frag *jffs2_lookup_node_frag(struct rb_root *fragtree, uint32_t offset) uint32_t 587 fs/jffs2/nodelist.c uint32_t ofs, uint32_t len, uint32_t 616 fs/jffs2/nodelist.c uint32_t last_len = ref_totlen(c, jeb, jeb->last_node); uint32_t 663 fs/jffs2/nodelist.c uint32_t size) uint32_t 682 fs/jffs2/nodelist.c uint32_t ofs = jeb->offset + c->sector_size - jeb->free_size; uint32_t 692 fs/jffs2/nodelist.c static inline uint32_t __ref_totlen(struct jffs2_sb_info *c, uint32_t 696 fs/jffs2/nodelist.c uint32_t ref_end; uint32_t 718 fs/jffs2/nodelist.c uint32_t __jffs2_ref_totlen(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t 721 fs/jffs2/nodelist.c uint32_t ret; uint32_t 88 fs/jffs2/nodelist.h uint32_t flash_offset; uint32_t 91 fs/jffs2/nodelist.h uint32_t __totlen; /* This may die; use ref_totlen(c, jeb, ) below */ uint32_t 174 fs/jffs2/nodelist.h uint32_t ino; uint32_t 179 fs/jffs2/nodelist.h uint32_t pino_nlink; /* Directories store parent inode uint32_t 216 fs/jffs2/nodelist.h uint32_t ofs; /* The offset to which the data of this node belongs */ uint32_t 217 fs/jffs2/nodelist.h uint32_t size; uint32_t 218 fs/jffs2/nodelist.h uint32_t frags; /* Number of fragments which currently refer uint32_t 232 fs/jffs2/nodelist.h uint32_t version; uint32_t 233 fs/jffs2/nodelist.h uint32_t data_crc; uint32_t 234 fs/jffs2/nodelist.h uint32_t partial_crc; uint32_t 235 fs/jffs2/nodelist.h uint32_t csize; uint32_t 244 fs/jffs2/nodelist.h uint32_t highest_version; uint32_t 245 fs/jffs2/nodelist.h uint32_t latest_mctime; uint32_t 246 fs/jffs2/nodelist.h uint32_t mctime_ver; uint32_t 258 fs/jffs2/nodelist.h uint32_t version; uint32_t 259 fs/jffs2/nodelist.h uint32_t ino; /* == zero for unlink */ uint32_t 273 fs/jffs2/nodelist.h uint32_t size; uint32_t 274 fs/jffs2/nodelist.h uint32_t ofs; /* The offset to which this fragment belongs */ uint32_t 281 fs/jffs2/nodelist.h uint32_t offset; /* of this block in the MTD */ uint32_t 283 fs/jffs2/nodelist.h uint32_t unchecked_size; uint32_t 284 fs/jffs2/nodelist.h uint32_t used_size; uint32_t 285 fs/jffs2/nodelist.h uint32_t dirty_size; uint32_t 286 fs/jffs2/nodelist.h uint32_t wasted_size; uint32_t 287 fs/jffs2/nodelist.h uint32_t free_size; /* Note that sector_size - free_size uint32_t 289 fs/jffs2/nodelist.h uint32_t allocated_refs; uint32_t 366 fs/jffs2/nodelist.h struct jffs2_inode_cache *jffs2_get_ino_cache(struct jffs2_sb_info *c, uint32_t ino); uint32_t 371 fs/jffs2/nodelist.h struct jffs2_node_frag *jffs2_lookup_node_frag(struct rb_root *fragtree, uint32_t offset); uint32_t 374 fs/jffs2/nodelist.h uint32_t jffs2_truncate_fragtree (struct jffs2_sb_info *c, struct rb_root *list, uint32_t size); uint32_t 377 fs/jffs2/nodelist.h uint32_t ofs, uint32_t len, uint32_t 379 fs/jffs2/nodelist.h extern uint32_t __jffs2_ref_totlen(struct jffs2_sb_info *c, uint32_t 385 fs/jffs2/nodelist.h int jffs2_reserve_space(struct jffs2_sb_info *c, uint32_t minsize, uint32_t 386 fs/jffs2/nodelist.h uint32_t *len, int prio, uint32_t sumsize); uint32_t 387 fs/jffs2/nodelist.h int jffs2_reserve_space_gc(struct jffs2_sb_info *c, uint32_t minsize, uint32_t 388 fs/jffs2/nodelist.h uint32_t *len, uint32_t sumsize); uint32_t 390 fs/jffs2/nodelist.h uint32_t ofs, uint32_t len, uint32_t 396 fs/jffs2/nodelist.h int jffs2_do_new_inode(struct jffs2_sb_info *c, struct jffs2_inode_info *f, uint32_t mode, struct jffs2_raw_inode *ri); uint32_t 400 fs/jffs2/nodelist.h uint32_t datalen, int alloc_mode); uint32_t 403 fs/jffs2/nodelist.h uint32_t namelen, int alloc_mode); uint32_t 406 fs/jffs2/nodelist.h uint32_t offset, uint32_t writelen, uint32_t *retlen); uint32_t 410 fs/jffs2/nodelist.h int namelen, struct jffs2_inode_info *dead_f, uint32_t time); uint32_t 411 fs/jffs2/nodelist.h int jffs2_do_link(struct jffs2_sb_info *c, struct jffs2_inode_info *dir_f, uint32_t ino, uint32_t 412 fs/jffs2/nodelist.h uint8_t type, const char *name, int namelen, uint32_t time); uint32_t 417 fs/jffs2/nodelist.h uint32_t ino, struct jffs2_raw_inode *latest_node); uint32_t 457 fs/jffs2/nodelist.h unsigned char *buf, uint32_t offset, uint32_t len); uint32_t 463 fs/jffs2/nodelist.h struct jffs2_inode_cache *jffs2_scan_make_ino_cache(struct jffs2_sb_info *c, uint32_t ino); uint32_t 465 fs/jffs2/nodelist.h int jffs2_scan_dirty_space(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t size); uint32_t 476 fs/jffs2/nodelist.h int jffs2_flush_wbuf_gc(struct jffs2_sb_info *c, uint32_t ino); uint32_t 26 fs/jffs2/nodemgmt.c uint32_t avail; uint32_t 71 fs/jffs2/nodemgmt.c static int jffs2_do_reserve_space(struct jffs2_sb_info *c, uint32_t minsize, uint32_t 72 fs/jffs2/nodemgmt.c uint32_t *len, uint32_t sumsize); uint32_t 74 fs/jffs2/nodemgmt.c int jffs2_reserve_space(struct jffs2_sb_info *c, uint32_t minsize, uint32_t 75 fs/jffs2/nodemgmt.c uint32_t *len, int prio, uint32_t sumsize) uint32_t 101 fs/jffs2/nodemgmt.c uint32_t dirty, avail; uint32_t 212 fs/jffs2/nodemgmt.c int jffs2_reserve_space_gc(struct jffs2_sb_info *c, uint32_t minsize, uint32_t 213 fs/jffs2/nodemgmt.c uint32_t *len, uint32_t sumsize) uint32_t 354 fs/jffs2/nodemgmt.c static int jffs2_do_reserve_space(struct jffs2_sb_info *c, uint32_t minsize, uint32_t 355 fs/jffs2/nodemgmt.c uint32_t *len, uint32_t sumsize) uint32_t 358 fs/jffs2/nodemgmt.c uint32_t reserved_size; /* for summary information at the end of the jeb */ uint32_t 408 fs/jffs2/nodemgmt.c uint32_t waste; uint32_t 501 fs/jffs2/nodemgmt.c uint32_t ofs, uint32_t len, uint32_t 586 fs/jffs2/nodemgmt.c uint32_t freed_len; uint32_t 840 fs/jffs2/nodemgmt.c uint32_t dirty; uint32_t 34 fs/jffs2/os-linux.h #define JFFS2_CLAMP_TIME(t) ((uint32_t)clamp_t(time64_t, (t), 0, U32_MAX)) uint32_t 116 fs/jffs2/os-linux.h int jffs2_flash_writev(struct jffs2_sb_info *c, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen, uint32_t ino); uint32_t 122 fs/jffs2/os-linux.h int jffs2_write_nand_badblock(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t bad_offset); uint32_t 125 fs/jffs2/os-linux.h int jffs2_flush_wbuf_gc(struct jffs2_sb_info *c, uint32_t ino); uint32_t 29 fs/jffs2/read.c uint32_t crc; uint32_t 158 fs/jffs2/read.c unsigned char *buf, uint32_t offset, uint32_t len) uint32_t 160 fs/jffs2/read.c uint32_t end = offset + len; uint32_t 179 fs/jffs2/read.c uint32_t holesize = end - offset; uint32_t 192 fs/jffs2/read.c uint32_t holeend = min(end, frag->ofs + frag->size); uint32_t 202 fs/jffs2/read.c uint32_t readlen; uint32_t 203 fs/jffs2/read.c uint32_t fragofs; /* offset within the frag to start reading */ uint32_t 37 fs/jffs2/readinode.c uint32_t crc, ofs, len; uint32_t 175 fs/jffs2/readinode.c static struct jffs2_tmp_dnode_info *jffs2_lookup_tn(struct rb_root *tn_root, uint32_t offset) uint32_t 222 fs/jffs2/readinode.c uint32_t fn_end = tn->fn->ofs + tn->fn->size; uint32_t 457 fs/jffs2/readinode.c uint32_t high_ver = 0; uint32_t 591 fs/jffs2/readinode.c uint32_t crc; uint32_t 653 fs/jffs2/readinode.c min_t(uint32_t, rd->nsize, (read - sizeof(*rd)) )); uint32_t 702 fs/jffs2/readinode.c uint32_t len, csize; uint32_t 704 fs/jffs2/readinode.c uint32_t crc; uint32_t 779 fs/jffs2/readinode.c len = min_t(uint32_t, rdlen - sizeof(*rd), csize); uint32_t 929 fs/jffs2/readinode.c uint32_t offs; uint32_t 1134 fs/jffs2/readinode.c uint32_t crc, new_size; uint32_t 1252 fs/jffs2/readinode.c uint32_t csize = je32_to_cpu(latest_node->csize); uint32_t 1313 fs/jffs2/readinode.c uint32_t ino, struct jffs2_raw_inode *latest_node) uint32_t 37 fs/jffs2/scan.c static uint32_t pseudo_random; uint32_t 40 fs/jffs2/scan.c unsigned char *buf, uint32_t buf_size, struct jffs2_summary *s); uint32_t 47 fs/jffs2/scan.c struct jffs2_raw_inode *ri, uint32_t ofs, struct jffs2_summary *s); uint32_t 49 fs/jffs2/scan.c struct jffs2_raw_dirent *rd, uint32_t ofs, struct jffs2_summary *s); uint32_t 53 fs/jffs2/scan.c uint32_t min = 2 * sizeof(struct jffs2_raw_inode); uint32_t 62 fs/jffs2/scan.c static inline uint32_t EMPTY_SCAN_SIZE(uint32_t sector_size) { uint32_t 94 fs/jffs2/scan.c uint32_t empty_blocks = 0, bad_blocks = 0; uint32_t 96 fs/jffs2/scan.c uint32_t buf_size = 0; uint32_t 131 fs/jffs2/scan.c buf_size = (uint32_t)try_size; uint32_t 255 fs/jffs2/scan.c uint32_t skip = c->nextblock->free_size % c->wbuf_pagesize; uint32_t 288 fs/jffs2/scan.c uint32_t ofs, uint32_t len) uint32_t 328 fs/jffs2/scan.c struct jffs2_raw_xattr *rx, uint32_t ofs, uint32_t 332 fs/jffs2/scan.c uint32_t xid, version, totlen, crc; uint32_t 384 fs/jffs2/scan.c struct jffs2_raw_xref *rr, uint32_t ofs, uint32_t 388 fs/jffs2/scan.c uint32_t crc; uint32_t 443 fs/jffs2/scan.c unsigned char *buf, uint32_t buf_size, struct jffs2_summary *s) { uint32_t 446 fs/jffs2/scan.c uint32_t ofs, prevofs, max_ofs; uint32_t 447 fs/jffs2/scan.c uint32_t hdr_crc, buf_ofs, buf_len; uint32_t 485 fs/jffs2/scan.c uint32_t sumlen; uint32_t 571 fs/jffs2/scan.c while(ofs < max_ofs && *(uint32_t *)(&buf[ofs]) == 0xFFFFFFFF) uint32_t 649 fs/jffs2/scan.c buf_len = min_t(uint32_t, buf_size, jeb->offset + c->sector_size - ofs); uint32_t 661 fs/jffs2/scan.c if (*(uint32_t *)(&buf[ofs-buf_ofs]) == 0xffffffff) { uint32_t 662 fs/jffs2/scan.c uint32_t inbuf_ofs; uint32_t 663 fs/jffs2/scan.c uint32_t empty_start, scan_end; uint32_t 667 fs/jffs2/scan.c scan_end = min_t(uint32_t, EMPTY_SCAN_SIZE(c->sector_size)/8, buf_len); uint32_t 673 fs/jffs2/scan.c if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) { uint32_t 702 fs/jffs2/scan.c buf_len = min_t(uint32_t, buf_size, jeb->offset + c->sector_size - ofs); uint32_t 799 fs/jffs2/scan.c buf_len = min_t(uint32_t, buf_size, jeb->offset + c->sector_size - ofs); uint32_t 816 fs/jffs2/scan.c buf_len = min_t(uint32_t, buf_size, jeb->offset + c->sector_size - ofs); uint32_t 834 fs/jffs2/scan.c buf_len = min_t(uint32_t, buf_size, jeb->offset + c->sector_size - ofs); uint32_t 851 fs/jffs2/scan.c buf_len = min_t(uint32_t, buf_size, jeb->offset + c->sector_size - ofs); uint32_t 962 fs/jffs2/scan.c struct jffs2_inode_cache *jffs2_scan_make_ino_cache(struct jffs2_sb_info *c, uint32_t ino) uint32_t 989 fs/jffs2/scan.c struct jffs2_raw_inode *ri, uint32_t ofs, struct jffs2_summary *s) uint32_t 992 fs/jffs2/scan.c uint32_t crc, ino = je32_to_cpu(ri->ino); uint32_t 1043 fs/jffs2/scan.c struct jffs2_raw_dirent *rd, uint32_t ofs, struct jffs2_summary *s) uint32_t 1047 fs/jffs2/scan.c uint32_t checkedlen; uint32_t 1048 fs/jffs2/scan.c uint32_t crc; uint32_t 1119 fs/jffs2/scan.c uint32_t count = 0; uint32_t 1130 fs/jffs2/scan.c static void rotate_list(struct list_head *head, uint32_t count) uint32_t 1143 fs/jffs2/scan.c uint32_t x; uint32_t 1144 fs/jffs2/scan.c uint32_t rotateby; uint32_t 28 fs/jffs2/summary.c uint32_t sum_size = min_t(uint32_t, c->sector_size, MAX_SUMMARY_SIZE); uint32_t 108 fs/jffs2/summary.c int jffs2_sum_add_padding_mem(struct jffs2_summary *s, uint32_t size) uint32_t 116 fs/jffs2/summary.c uint32_t ofs) uint32_t 134 fs/jffs2/summary.c uint32_t ofs) uint32_t 158 fs/jffs2/summary.c int jffs2_sum_add_xattr_mem(struct jffs2_summary *s, struct jffs2_raw_xattr *rx, uint32_t ofs) uint32_t 176 fs/jffs2/summary.c int jffs2_sum_add_xref_mem(struct jffs2_summary *s, struct jffs2_raw_xref *rr, uint32_t ofs) uint32_t 249 fs/jffs2/summary.c unsigned long count, uint32_t ofs) uint32_t 372 fs/jffs2/summary.c uint32_t ofs, uint32_t len, uint32_t 387 fs/jffs2/summary.c struct jffs2_raw_summary *summary, uint32_t *pseudo_random) uint32_t 530 fs/jffs2/summary.c (uint32_t)PAD(sizeof(struct jffs2_raw_xref))); uint32_t 573 fs/jffs2/summary.c struct jffs2_raw_summary *summary, uint32_t sumsize, uint32_t 574 fs/jffs2/summary.c uint32_t *pseudo_random) uint32_t 578 fs/jffs2/summary.c uint32_t crc; uint32_t 675 fs/jffs2/summary.c uint32_t infosize, uint32_t datasize, int padsize) uint32_t 681 fs/jffs2/summary.c uint32_t sum_ofs; uint32_t 153 fs/jffs2/summary.h uint32_t sum_size; /* collected summary information for nextblock */ uint32_t 154 fs/jffs2/summary.h uint32_t sum_num; uint32_t 155 fs/jffs2/summary.h uint32_t sum_padded; uint32_t 182 fs/jffs2/summary.h unsigned long count, uint32_t to); uint32_t 184 fs/jffs2/summary.h int jffs2_sum_add_padding_mem(struct jffs2_summary *s, uint32_t size); uint32_t 185 fs/jffs2/summary.h int jffs2_sum_add_inode_mem(struct jffs2_summary *s, struct jffs2_raw_inode *ri, uint32_t ofs); uint32_t 186 fs/jffs2/summary.h int jffs2_sum_add_dirent_mem(struct jffs2_summary *s, struct jffs2_raw_dirent *rd, uint32_t ofs); uint32_t 187 fs/jffs2/summary.h int jffs2_sum_add_xattr_mem(struct jffs2_summary *s, struct jffs2_raw_xattr *rx, uint32_t ofs); uint32_t 188 fs/jffs2/summary.h int jffs2_sum_add_xref_mem(struct jffs2_summary *s, struct jffs2_raw_xref *rr, uint32_t ofs); uint32_t 190 fs/jffs2/summary.h struct jffs2_raw_summary *summary, uint32_t sumlen, uint32_t 191 fs/jffs2/summary.h uint32_t *pseudo_random); uint32_t 113 fs/jffs2/super.c uint32_t generation) uint32_t 138 fs/jffs2/super.c uint32_t pino; uint32_t 42 fs/jffs2/wbuf.c uint32_t ino; uint32_t 48 fs/jffs2/wbuf.c static int jffs2_wbuf_pending_for_ino(struct jffs2_sb_info *c, uint32_t ino) uint32_t 85 fs/jffs2/wbuf.c static void jffs2_wbuf_dirties_inode(struct jffs2_sb_info *c, uint32_t ino) uint32_t 165 fs/jffs2/wbuf.c uint32_t oldfree = jeb->free_size; uint32_t 231 fs/jffs2/wbuf.c uint32_t ofs) uint32_t 283 fs/jffs2/wbuf.c uint32_t start, end, ofs, len; uint32_t 415 fs/jffs2/wbuf.c uint32_t towrite = (end-start) - ((end-start)%c->wbuf_pagesize); uint32_t 464 fs/jffs2/wbuf.c uint32_t rawlen = ref_totlen(c, jeb, raw); uint32_t 658 fs/jffs2/wbuf.c uint32_t waste = c->wbuf_pagesize - c->wbuf_len; uint32_t 702 fs/jffs2/wbuf.c int jffs2_flush_wbuf_gc(struct jffs2_sb_info *c, uint32_t ino) uint32_t 704 fs/jffs2/wbuf.c uint32_t old_wbuf_ofs; uint32_t 705 fs/jffs2/wbuf.c uint32_t old_wbuf_len; uint32_t 790 fs/jffs2/wbuf.c c->wbuf_len += (uint32_t) len; uint32_t 796 fs/jffs2/wbuf.c uint32_t ino) uint32_t 800 fs/jffs2/wbuf.c uint32_t outvec_to = to; uint32_t 906 fs/jffs2/wbuf.c int res = jffs2_sum_add_kvec(c, invecs, count, (uint32_t) to); uint32_t 1133 fs/jffs2/wbuf.c int jffs2_write_nand_badblock(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t bad_offset) uint32_t 24 fs/jffs2/write.c uint32_t mode, struct jffs2_raw_inode *ri) uint32_t 61 fs/jffs2/write.c uint32_t datalen, int alloc_mode) uint32_t 66 fs/jffs2/write.c uint32_t flash_ofs; uint32_t 130 fs/jffs2/write.c uint32_t dummy; uint32_t 207 fs/jffs2/write.c uint32_t namelen, int alloc_mode) uint32_t 212 fs/jffs2/write.c uint32_t flash_ofs; uint32_t 282 fs/jffs2/write.c uint32_t dummy; uint32_t 342 fs/jffs2/write.c uint32_t offset, uint32_t writelen, uint32_t *retlen) uint32_t 345 fs/jffs2/write.c uint32_t writtenlen = 0; uint32_t 354 fs/jffs2/write.c uint32_t alloclen; uint32_t 355 fs/jffs2/write.c uint32_t datalen, cdatalen; uint32_t 369 fs/jffs2/write.c datalen = min_t(uint32_t, writelen, uint32_t 371 fs/jffs2/write.c cdatalen = min_t(uint32_t, alloclen - sizeof(*ri), datalen); uint32_t 448 fs/jffs2/write.c uint32_t alloclen; uint32_t 549 fs/jffs2/write.c uint32_t time) uint32_t 553 fs/jffs2/write.c uint32_t alloclen; uint32_t 601 fs/jffs2/write.c uint32_t nhash = full_name_hash(NULL, name, namelen); uint32_t 669 fs/jffs2/write.c int jffs2_do_link (struct jffs2_sb_info *c, struct jffs2_inode_info *dir_f, uint32_t ino, uint8_t type, const char *name, int namelen, uint32_t time) uint32_t 673 fs/jffs2/write.c uint32_t alloclen; uint32_t 22 fs/jffs2/writev.c res = jffs2_sum_add_kvec(c, vecs, count, (uint32_t) to); uint32_t 45 fs/jffs2/writev.c res = jffs2_sum_add_kvec(c, vecs, 1, (uint32_t) ofs); uint32_t 64 fs/jffs2/xattr.c static uint32_t xattr_datum_hashkey(int xprefix, const char *xname, const char *xvalue, int xsize) uint32_t 106 fs/jffs2/xattr.c uint32_t target, before; uint32_t 139 fs/jffs2/xattr.c uint32_t crc, offset, totlen; uint32_t 209 fs/jffs2/xattr.c uint32_t crc, length; uint32_t 291 fs/jffs2/xattr.c uint32_t phys_ofs = write_ofs(c); uint32_t 342 fs/jffs2/xattr.c uint32_t hashkey, name_len; uint32_t 450 fs/jffs2/xattr.c uint32_t crc, offset, totlen; uint32_t 511 fs/jffs2/xattr.c uint32_t xseqno, phys_ofs = write_ofs(c); uint32_t 725 fs/jffs2/xattr.c static struct jffs2_xattr_datum *jffs2_find_xattr_datum(struct jffs2_sb_info *c, uint32_t xid) uint32_t 890 fs/jffs2/xattr.c uint32_t xid, uint32_t version) uint32_t 1101 fs/jffs2/xattr.c uint32_t length, request; uint32_t 1222 fs/jffs2/xattr.c uint32_t totlen, length, old_ofs; uint32_t 1258 fs/jffs2/xattr.c uint32_t totlen, length, old_ofs; uint32_t 1294 fs/jffs2/xattr.c uint32_t totlen; uint32_t 33 fs/jffs2/xattr.h uint32_t xid; uint32_t 34 fs/jffs2/xattr.h uint32_t version; uint32_t 36 fs/jffs2/xattr.h uint32_t data_crc; uint32_t 37 fs/jffs2/xattr.h uint32_t hashkey; uint32_t 39 fs/jffs2/xattr.h uint32_t name_len; /* length of xname */ uint32_t 41 fs/jffs2/xattr.h uint32_t value_len; /* length of xvalue */ uint32_t 53 fs/jffs2/xattr.h uint32_t xseqno; uint32_t 56 fs/jffs2/xattr.h uint32_t ino; /* only used in scanning/building */ uint32_t 60 fs/jffs2/xattr.h uint32_t xid; /* only used in sccanning/building */ uint32_t 78 fs/jffs2/xattr.h uint32_t xid, uint32_t version); uint32_t 67 fs/lockd/clntproc.c static inline int nlm_pidbusy(struct nlm_host *host, uint32_t pid) uint32_t 77 fs/lockd/clntproc.c static inline uint32_t __nlm_alloc_pid(struct nlm_host *host) uint32_t 79 fs/lockd/clntproc.c uint32_t res; uint32_t 683 fs/nfs/blocklayout/blocklayout.c uint32_t count; uint32_t 67 fs/nfs/callback.h uint32_t bitmap[2]; uint32_t 72 fs/nfs/callback.h uint32_t bitmap[2]; uint32_t 82 fs/nfs/callback.h uint32_t truncate; uint32_t 88 fs/nfs/callback.h uint32_t rc_sequenceid; uint32_t 89 fs/nfs/callback.h uint32_t rc_slotid; uint32_t 94 fs/nfs/callback.h uint32_t rcl_nrefcalls; uint32_t 101 fs/nfs/callback.h uint32_t csa_sequenceid; uint32_t 102 fs/nfs/callback.h uint32_t csa_slotid; uint32_t 103 fs/nfs/callback.h uint32_t csa_highestslotid; uint32_t 104 fs/nfs/callback.h uint32_t csa_cachethis; uint32_t 105 fs/nfs/callback.h uint32_t csa_nrclists; uint32_t 112 fs/nfs/callback.h uint32_t csr_sequenceid; uint32_t 113 fs/nfs/callback.h uint32_t csr_slotid; uint32_t 114 fs/nfs/callback.h uint32_t csr_highestslotid; uint32_t 115 fs/nfs/callback.h uint32_t csr_target_highestslotid; uint32_t 133 fs/nfs/callback.h uint32_t craa_objs_to_keep; uint32_t 134 fs/nfs/callback.h uint32_t craa_type_mask; uint32_t 141 fs/nfs/callback.h uint32_t crsa_target_highest_slotid; uint32_t 147 fs/nfs/callback.h uint32_t cbl_recall_type; uint32_t 148 fs/nfs/callback.h uint32_t cbl_layout_type; uint32_t 149 fs/nfs/callback.h uint32_t cbl_layoutchanged; uint32_t 164 fs/nfs/callback.h uint32_t cbd_notify_type; uint32_t 165 fs/nfs/callback.h uint32_t cbd_layout_type; uint32_t 167 fs/nfs/callback.h uint32_t cbd_immediate; uint32_t 191 fs/nfs/callback.h uint32_t error; uint32_t 460 fs/nfs/callback_proc.c uint32_t nrclists, uint32_t 105 fs/nfs/callback_xdr.c static __be32 decode_bitmap(struct xdr_stream *xdr, uint32_t *bitmap) uint32_t 218 fs/nfs/callback_xdr.c uint32_t iomode; uint32_t 220 fs/nfs/callback_xdr.c p = xdr_inline_decode(xdr, 4 * sizeof(uint32_t)); uint32_t 268 fs/nfs/callback_xdr.c p = xdr_inline_decode(xdr, sizeof(uint32_t)); uint32_t 291 fs/nfs/callback_xdr.c p = xdr_inline_decode(xdr, (4 * sizeof(uint32_t)) + uint32_t 323 fs/nfs/callback_xdr.c p = xdr_inline_decode(xdr, sizeof(uint32_t)); uint32_t 373 fs/nfs/callback_xdr.c p = xdr_inline_decode(xdr, sizeof(uint32_t)); uint32_t 380 fs/nfs/callback_xdr.c rc_list->rcl_nrefcalls * 2 * sizeof(uint32_t)); uint32_t 412 fs/nfs/callback_xdr.c p = xdr_inline_decode(xdr, 5 * sizeof(uint32_t)); uint32_t 452 fs/nfs/callback_xdr.c uint32_t bitmap[2]; uint32_t 597 fs/nfs/callback_xdr.c static __be32 encode_attr_bitmap(struct xdr_stream *xdr, const uint32_t *bitmap, size_t sz) uint32_t 604 fs/nfs/callback_xdr.c static __be32 encode_attr_change(struct xdr_stream *xdr, const uint32_t *bitmap, uint64_t change) uint32_t 617 fs/nfs/callback_xdr.c static __be32 encode_attr_size(struct xdr_stream *xdr, const uint32_t *bitmap, uint64_t size) uint32_t 642 fs/nfs/callback_xdr.c static __be32 encode_attr_ctime(struct xdr_stream *xdr, const uint32_t *bitmap, const struct timespec *time) uint32_t 649 fs/nfs/callback_xdr.c static __be32 encode_attr_mtime(struct xdr_stream *xdr, const uint32_t *bitmap, const struct timespec *time) uint32_t 672 fs/nfs/callback_xdr.c static __be32 encode_op_hdr(struct xdr_stream *xdr, uint32_t op, __be32 res) uint32_t 745 fs/nfs/callback_xdr.c p = xdr_reserve_space(xdr, 4 * sizeof(uint32_t)); uint32_t 658 fs/nfs/filelayout/filelayout.c uint32_t nfl_util; uint32_t 34 fs/nfs/fscache.c uint32_t minorversion; /* NFSv4 minor version */ uint32_t 15 fs/nfs/netns.h uint32_t major, minor; uint32_t 944 fs/nfs/nfs4xdr.c uint32_t nops; uint32_t 946 fs/nfs/nfs4xdr.c uint32_t taglen; uint32_t 948 fs/nfs/nfs4xdr.c uint32_t replen; /* expected reply words */ uint32_t 1037 fs/nfs/nfs4xdr.c uint32_t replen, uint32_t 1073 fs/nfs/nfs4xdr.c const uint32_t attrmask[]) uint32_t 1081 fs/nfs/nfs4xdr.c uint32_t len = 0; uint32_t 1082 fs/nfs/nfs4xdr.c uint32_t bmval[3] = { 0 }; uint32_t 1595 fs/nfs/nfs4xdr.c uint32_t attrs[3] = { uint32_t 1599 fs/nfs/nfs4xdr.c uint32_t dircount = readdir->count >> 1; uint32_t 1601 fs/nfs/nfs4xdr.c uint32_t attrlen = 0; uint32_t 2584 fs/nfs/nfs4xdr.c uint32_t replen; uint32_t 2798 fs/nfs/nfs4xdr.c uint32_t replen; uint32_t 3181 fs/nfs/nfs4xdr.c uint32_t opnum; uint32_t 3232 fs/nfs/nfs4xdr.c decode_bitmap4(struct xdr_stream *xdr, uint32_t *bitmap, size_t sz) uint32_t 3244 fs/nfs/nfs4xdr.c static int decode_attr_bitmap(struct xdr_stream *xdr, uint32_t *bitmap) uint32_t 3251 fs/nfs/nfs4xdr.c static int decode_attr_length(struct xdr_stream *xdr, uint32_t *attrlen, unsigned int *savep) uint32_t 3263 fs/nfs/nfs4xdr.c static int decode_attr_supported(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *bitmask) uint32_t 3278 fs/nfs/nfs4xdr.c static int decode_attr_type(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *type) uint32_t 3303 fs/nfs/nfs4xdr.c uint32_t *bitmap, uint32_t *type) uint32_t 3321 fs/nfs/nfs4xdr.c static int decode_attr_change(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *change) uint32_t 3342 fs/nfs/nfs4xdr.c static int decode_attr_size(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *size) uint32_t 3362 fs/nfs/nfs4xdr.c static int decode_attr_link_support(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *res) uint32_t 3380 fs/nfs/nfs4xdr.c static int decode_attr_symlink_support(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *res) uint32_t 3398 fs/nfs/nfs4xdr.c static int decode_attr_fsid(struct xdr_stream *xdr, uint32_t *bitmap, struct nfs_fsid *fsid) uint32_t 3422 fs/nfs/nfs4xdr.c static int decode_attr_lease_time(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *res) uint32_t 3440 fs/nfs/nfs4xdr.c static int decode_attr_error(struct xdr_stream *xdr, uint32_t *bitmap, int32_t *res) uint32_t 3457 fs/nfs/nfs4xdr.c uint32_t *bitmap, uint32_t *bitmask) uint32_t 3472 fs/nfs/nfs4xdr.c static int decode_attr_filehandle(struct xdr_stream *xdr, uint32_t *bitmap, struct nfs_fh *fh) uint32_t 3501 fs/nfs/nfs4xdr.c static int decode_attr_aclsupport(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *res) uint32_t 3519 fs/nfs/nfs4xdr.c static int decode_attr_fileid(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *fileid) uint32_t 3539 fs/nfs/nfs4xdr.c static int decode_attr_mounted_on_fileid(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *fileid) uint32_t 3559 fs/nfs/nfs4xdr.c static int decode_attr_files_avail(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *res) uint32_t 3578 fs/nfs/nfs4xdr.c static int decode_attr_files_free(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *res) uint32_t 3597 fs/nfs/nfs4xdr.c static int decode_attr_files_total(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *res) uint32_t 3658 fs/nfs/nfs4xdr.c static int decode_attr_fs_locations(struct xdr_stream *xdr, uint32_t *bitmap, struct nfs4_fs_locations *res) uint32_t 3736 fs/nfs/nfs4xdr.c static int decode_attr_maxfilesize(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *res) uint32_t 3755 fs/nfs/nfs4xdr.c static int decode_attr_maxlink(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *maxlink) uint32_t 3774 fs/nfs/nfs4xdr.c static int decode_attr_maxname(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *maxname) uint32_t 3793 fs/nfs/nfs4xdr.c static int decode_attr_maxread(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *res) uint32_t 3809 fs/nfs/nfs4xdr.c *res = (uint32_t)maxread; uint32_t 3816 fs/nfs/nfs4xdr.c static int decode_attr_maxwrite(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *res) uint32_t 3832 fs/nfs/nfs4xdr.c *res = (uint32_t)maxwrite; uint32_t 3839 fs/nfs/nfs4xdr.c static int decode_attr_mode(struct xdr_stream *xdr, uint32_t *bitmap, umode_t *mode) uint32_t 3841 fs/nfs/nfs4xdr.c uint32_t tmp; uint32_t 3861 fs/nfs/nfs4xdr.c static int decode_attr_nlink(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t *nlink) uint32_t 3894 fs/nfs/nfs4xdr.c static int decode_attr_owner(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t 3928 fs/nfs/nfs4xdr.c static int decode_attr_group(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t 3962 fs/nfs/nfs4xdr.c static int decode_attr_rdev(struct xdr_stream *xdr, uint32_t *bitmap, dev_t *rdev) uint32_t 3964 fs/nfs/nfs4xdr.c uint32_t major = 0, minor = 0; uint32_t 3989 fs/nfs/nfs4xdr.c static int decode_attr_space_avail(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *res) uint32_t 4008 fs/nfs/nfs4xdr.c static int decode_attr_space_free(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *res) uint32_t 4027 fs/nfs/nfs4xdr.c static int decode_attr_space_total(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *res) uint32_t 4046 fs/nfs/nfs4xdr.c static int decode_attr_space_used(struct xdr_stream *xdr, uint32_t *bitmap, uint64_t *used) uint32_t 4089 fs/nfs/nfs4xdr.c static int decode_attr_time_access(struct xdr_stream *xdr, uint32_t *bitmap, struct timespec *time) uint32_t 4107 fs/nfs/nfs4xdr.c static int decode_attr_time_metadata(struct xdr_stream *xdr, uint32_t *bitmap, struct timespec *time) uint32_t 4125 fs/nfs/nfs4xdr.c static int decode_attr_time_delta(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t 4143 fs/nfs/nfs4xdr.c static int decode_attr_security_label(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t 4146 fs/nfs/nfs4xdr.c uint32_t pi = 0; uint32_t 4147 fs/nfs/nfs4xdr.c uint32_t lfs = 0; uint32_t 4189 fs/nfs/nfs4xdr.c static int decode_attr_time_modify(struct xdr_stream *xdr, uint32_t *bitmap, struct timespec *time) uint32_t 4207 fs/nfs/nfs4xdr.c static int verify_attr_len(struct xdr_stream *xdr, unsigned int savep, uint32_t attrlen) uint32_t 4240 fs/nfs/nfs4xdr.c uint32_t supp, acc; uint32_t 4333 fs/nfs/nfs4xdr.c uint32_t bmlen; uint32_t 4354 fs/nfs/nfs4xdr.c uint32_t attrlen, bitmap[3] = {0}; uint32_t 4386 fs/nfs/nfs4xdr.c uint32_t attrlen, bitmap[3] = {0}; uint32_t 4423 fs/nfs/nfs4xdr.c uint32_t attrlen, bitmap[3] = {0}; uint32_t 4445 fs/nfs/nfs4xdr.c uint32_t *bitmap, uint32_t 4447 fs/nfs/nfs4xdr.c uint32_t hint_bit) uint32_t 4466 fs/nfs/nfs4xdr.c uint32_t bitmap[3] = {0,}, attrlen; uint32_t 4515 fs/nfs/nfs4xdr.c uint32_t *bitmap, uint32_t 4520 fs/nfs/nfs4xdr.c uint32_t num; uint32_t 4545 fs/nfs/nfs4xdr.c static int decode_getfattr_attrs(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t 4552 fs/nfs/nfs4xdr.c uint32_t type; uint32_t 4680 fs/nfs/nfs4xdr.c uint32_t attrlen, uint32_t 4726 fs/nfs/nfs4xdr.c uint32_t i; uint32_t 4758 fs/nfs/nfs4xdr.c static int decode_attr_pnfstype(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t 4776 fs/nfs/nfs4xdr.c static int decode_attr_layout_blksize(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t 4777 fs/nfs/nfs4xdr.c uint32_t *res) uint32_t 4796 fs/nfs/nfs4xdr.c static int decode_attr_clone_blksize(struct xdr_stream *xdr, uint32_t *bitmap, uint32_t 4797 fs/nfs/nfs4xdr.c uint32_t *res) uint32_t 4816 fs/nfs/nfs4xdr.c uint32_t attrlen, bitmap[3]; uint32_t 4870 fs/nfs/nfs4xdr.c uint32_t len; uint32_t 4911 fs/nfs/nfs4xdr.c uint32_t namelen, type; uint32_t 4998 fs/nfs/nfs4xdr.c uint32_t limit_type, nblocks, blocksize; uint32_t 5020 fs/nfs/nfs4xdr.c uint32_t delegation_type, uint32_t 5049 fs/nfs/nfs4xdr.c uint32_t why_no_delegation; uint32_t 5067 fs/nfs/nfs4xdr.c uint32_t delegation_type; uint32_t 5089 fs/nfs/nfs4xdr.c uint32_t savewords, bmlen, i; uint32_t 5114 fs/nfs/nfs4xdr.c savewords = min_t(uint32_t, bmlen, NFS4_BITMAP_SIZE); uint32_t 5164 fs/nfs/nfs4xdr.c uint32_t count, eof, recvd; uint32_t 5282 fs/nfs/nfs4xdr.c uint32_t attrlen, uint32_t 5346 fs/nfs/nfs4xdr.c uint32_t opnum; uint32_t 5366 fs/nfs/nfs4xdr.c uint32_t len; uint32_t 5504 fs/nfs/nfs4xdr.c uint32_t bitmap_words; uint32_t 5524 fs/nfs/nfs4xdr.c uint32_t dummy; uint32_t 5527 fs/nfs/nfs4xdr.c uint32_t impl_id_count; uint32_t 5798 fs/nfs/nfs4xdr.c uint32_t len, type; uint32_t 5838 fs/nfs/nfs4xdr.c uint32_t i; uint32_t 7366 fs/nfs/nfs4xdr.c uint32_t bitmap[3] = {0}; uint32_t 7367 fs/nfs/nfs4xdr.c uint32_t len; uint32_t 28 fs/nfsd/export.h uint32_t locations_count; uint32_t 59 fs/nfsd/export.h uint32_t ex_nflavors; uint32_t 110 fs/nfsd/nfs4idmap.c static uint32_t uint32_t 113 fs/nfsd/nfs4idmap.c uint32_t hash; uint32_t 865 fs/nfsd/nfs4recover.c uint32_t xid; uint32_t 1509 fs/ocfs2/ocfs2_fs.h uint32_t feature_incompat) uint32_t 845 fs/ocfs2/stack_user.c int mode, uint32_t flags, uint32_t 951 fs/ocfs2/stack_user.c uint32_t generation) uint32_t 22 fs/orangefs/devorangefs-req.c uint32_t orangefs_userspace_version; uint32_t 389 fs/orangefs/orangefs-kernel.h extern uint32_t orangefs_userspace_version; uint32_t 34 fs/pstore/ram_core.c uint32_t sig; uint32_t 2308 fs/ubifs/debug.c uint32_t blka, blkb; uint32_t 2375 fs/ubifs/debug.c uint32_t hasha, hashb; uint32_t 193 fs/ubifs/gc.c uint32_t hasha = key_hash(c, &sa->key); uint32_t 194 fs/ubifs/gc.c uint32_t hashb = key_hash(c, &sb->key); uint32_t 229 fs/ubifs/io.c uint32_t crc, node_crc, magic; uint32_t 308 fs/ubifs/io.c uint32_t crc; uint32_t 379 fs/ubifs/io.c uint32_t crc; uint32_t 450 fs/ubifs/io.c uint32_t crc; uint32_t 42 fs/ubifs/key.h static inline uint32_t key_mask_hash(uint32_t hash) uint32_t 55 fs/ubifs/key.h static inline uint32_t key_r5_hash(const char *s, int len) uint32_t 57 fs/ubifs/key.h uint32_t a = 0; uint32_t 75 fs/ubifs/key.h static inline uint32_t key_test_hash(const char *str, int len) uint32_t 77 fs/ubifs/key.h uint32_t a = 0; uint32_t 79 fs/ubifs/key.h len = min_t(uint32_t, len, 4); uint32_t 150 fs/ubifs/key.h uint32_t hash = c->key_hash(fname_name(nm), fname_len(nm)); uint32_t 168 fs/ubifs/key.h uint32_t hash) uint32_t 187 fs/ubifs/key.h uint32_t hash = c->key_hash(fname_name(nm), fname_len(nm)); uint32_t 220 fs/ubifs/key.h uint32_t hash = c->key_hash(fname_name(nm), fname_len(nm)); uint32_t 238 fs/ubifs/key.h uint32_t hash = c->key_hash(fname_name(nm), fname_len(nm)); uint32_t 370 fs/ubifs/key.h static inline uint32_t key_hash(const struct ubifs_info *c, uint32_t 381 fs/ubifs/key.h static inline uint32_t key_hash_flash(const struct ubifs_info *c, const void *k) uint32_t 222 fs/ubifs/lpt.c static void pack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, uint32_t val, int nrbits) uint32_t 273 fs/ubifs/lpt.c uint32_t ubifs_unpack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, int nrbits) uint32_t 278 fs/ubifs/lpt.c uint32_t uninitialized_var(val); uint32_t 291 fs/ubifs/lpt.c val = p[1] | ((uint32_t)p[2] << 8); uint32_t 294 fs/ubifs/lpt.c val = p[1] | ((uint32_t)p[2] << 8) | uint32_t 295 fs/ubifs/lpt.c ((uint32_t)p[3] << 16); uint32_t 298 fs/ubifs/lpt.c val = p[1] | ((uint32_t)p[2] << 8) | uint32_t 299 fs/ubifs/lpt.c ((uint32_t)p[3] << 16) | uint32_t 300 fs/ubifs/lpt.c ((uint32_t)p[4] << 24); uint32_t 311 fs/ubifs/lpt.c val = p[0] | ((uint32_t)p[1] << 8); uint32_t 314 fs/ubifs/lpt.c val = p[0] | ((uint32_t)p[1] << 8) | uint32_t 315 fs/ubifs/lpt.c ((uint32_t)p[2] << 16); uint32_t 318 fs/ubifs/lpt.c val = p[0] | ((uint32_t)p[1] << 8) | uint32_t 319 fs/ubifs/lpt.c ((uint32_t)p[2] << 16) | uint32_t 320 fs/ubifs/lpt.c ((uint32_t)p[3] << 24); uint32_t 1409 fs/ubifs/recovery.c uint32_t crc; uint32_t 517 fs/ubifs/replay.c uint32_t data; uint32_t 61 fs/ubifs/scan.c uint32_t magic; uint32_t 323 fs/ubifs/scan.c if (*(uint32_t *)buf != 0xffffffff) uint32_t 449 fs/ubifs/tnc.c uint32_t crc, node_crc; uint32_t 1884 fs/ubifs/tnc.c struct ubifs_dent_node *dent, uint32_t cookie, uint32_t 1924 fs/ubifs/tnc.c struct ubifs_dent_node *dent, uint32_t cookie) uint32_t 1961 fs/ubifs/tnc.c void *node, uint32_t cookie) uint32_t 2696 fs/ubifs/tnc.c uint32_t cookie) uint32_t 286 fs/ubifs/ubifs.h uint32_t u32[UBIFS_SK_LEN/4]; uint32_t 1339 fs/ubifs/ubifs.h uint32_t (*key_hash)(const char *str, int len); uint32_t 1823 fs/ubifs/ubifs.h void *node, uint32_t secondary_hash); uint32_t 1837 fs/ubifs/ubifs.h uint32_t cookie); uint32_t 1952 fs/ubifs/ubifs.h uint32_t ubifs_unpack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, int nrbits); uint32_t 108 fs/udf/balloc.c uint32_t offset, uint32_t 109 fs/udf/balloc.c uint32_t count) uint32_t 173 fs/udf/balloc.c uint16_t partition, uint32_t first_block, uint32_t 174 fs/udf/balloc.c uint32_t block_count) uint32_t 221 fs/udf/balloc.c uint32_t goal, int *err) uint32_t 360 fs/udf/balloc.c uint32_t offset, uint32_t 361 fs/udf/balloc.c uint32_t count) uint32_t 365 fs/udf/balloc.c uint32_t start, end; uint32_t 366 fs/udf/balloc.c uint32_t elen; uint32_t 400 fs/udf/balloc.c uint32_t tmp = ((0x3FFFFFFF - elen) >> uint32_t 417 fs/udf/balloc.c uint32_t tmp = ((0x3FFFFFFF - elen) >> uint32_t 500 fs/udf/balloc.c uint32_t first_block, uint32_t block_count) uint32_t 504 fs/udf/balloc.c uint32_t elen, adsize; uint32_t 560 fs/udf/balloc.c uint32_t goal, int *err) uint32_t 563 fs/udf/balloc.c uint32_t spread = 0xFFFFFFFF, nspread = 0xFFFFFFFF; uint32_t 565 fs/udf/balloc.c uint32_t adsize; uint32_t 566 fs/udf/balloc.c uint32_t elen, goal_elen = 0; uint32_t 652 fs/udf/balloc.c struct kernel_lb_addr *bloc, uint32_t offset, uint32_t 653 fs/udf/balloc.c uint32_t count) uint32_t 674 fs/udf/balloc.c uint16_t partition, uint32_t first_block, uint32_t 675 fs/udf/balloc.c uint32_t block_count) uint32_t 700 fs/udf/balloc.c uint16_t partition, uint32_t goal, int *err) uint32_t 56 fs/udf/dir.c uint32_t elen; uint32_t 25 fs/udf/directory.c struct kernel_lb_addr *eloc, uint32_t *elen, uint32_t 55 fs/udf/directory.c uint32_t lextoffset = epos->offset; uint32_t 114 fs/udf/directory.c uint32_t lextoffset = epos->offset; uint32_t 199 fs/udf/directory.c struct short_ad *udf_get_fileshortad(uint8_t *ptr, int maxoffset, uint32_t *offset, uint32_t 222 fs/udf/directory.c struct long_ad *udf_get_filelongad(uint8_t *ptr, int maxoffset, uint32_t *offset, int inc) uint32_t 169 fs/udf/ecma_167.h uint32_t extLength; uint32_t 170 fs/udf/ecma_167.h uint32_t extLocation; uint32_t 377 fs/udf/ecma_167.h uint32_t logicalBlockNum; uint32_t 395 fs/udf/ecma_167.h uint32_t extLength; uint32_t 409 fs/udf/ecma_167.h uint32_t extLength; uint32_t 410 fs/udf/ecma_167.h uint32_t recordedLength; uint32_t 411 fs/udf/ecma_167.h uint32_t informationLength; uint32_t 54 fs/udf/ialloc.c uint32_t start = UDF_I(dir)->i_location.logicalBlockNum; uint32_t 61 fs/udf/inode.c struct kernel_lb_addr, uint32_t); uint32_t 488 fs/udf/inode.c uint32_t add; uint32_t 492 fs/udf/inode.c uint32_t prealloc_len = 0; uint32_t 543 fs/udf/inode.c uint32_t tmplen; uint32_t 610 fs/udf/inode.c uint32_t final_block_len) uint32_t 613 fs/udf/inode.c uint32_t added_bytes; uint32_t 629 fs/udf/inode.c uint32_t elen; uint32_t 694 fs/udf/inode.c uint32_t elen = 0, tmpelen; uint32_t 1180 fs/udf/inode.c uint32_t tmplen; uint32_t 1313 fs/udf/inode.c uint32_t uid, gid; uint32_t 1627 fs/udf/inode.c uint32_t permissions; uint32_t 1628 fs/udf/inode.c uint32_t flags; uint32_t 1684 fs/udf/inode.c uint32_t udfperms; uint32_t 1975 fs/udf/inode.c uint32_t cp_len; uint32_t 1980 fs/udf/inode.c cp_len |= ((uint32_t)cp_type) << 30; uint32_t 2002 fs/udf/inode.c struct kernel_lb_addr *eloc, uint32_t elen, int inc) uint32_t 2051 fs/udf/inode.c struct kernel_lb_addr *eloc, uint32_t elen, int inc) uint32_t 2082 fs/udf/inode.c struct kernel_lb_addr *eloc, uint32_t elen, int inc) uint32_t 2140 fs/udf/inode.c struct kernel_lb_addr *eloc, uint32_t *elen, int inc) uint32_t 2171 fs/udf/inode.c struct kernel_lb_addr *eloc, uint32_t *elen, int inc) uint32_t 2225 fs/udf/inode.c struct kernel_lb_addr neloc, uint32_t nelen) uint32_t 2228 fs/udf/inode.c uint32_t oelen; uint32_t 2253 fs/udf/inode.c uint32_t elen; uint32_t 2331 fs/udf/inode.c uint32_t *elen, sector_t *offset) uint32_t 2364 fs/udf/inode.c uint32_t elen; uint32_t 47 fs/udf/misc.c struct genericFormat *udf_add_extendedattr(struct inode *inode, uint32_t size, uint32_t 48 fs/udf/misc.c uint32_t type, uint8_t loc) uint32_t 105 fs/udf/misc.c uint32_t aal = uint32_t 115 fs/udf/misc.c uint32_t ial = uint32_t 126 fs/udf/misc.c uint32_t aal = uint32_t 148 fs/udf/misc.c struct genericFormat *udf_get_extendedattr(struct inode *inode, uint32_t type, uint32_t 153 fs/udf/misc.c uint32_t offset; uint32_t 199 fs/udf/misc.c struct buffer_head *udf_read_tagged(struct super_block *sb, uint32_t block, uint32_t 200 fs/udf/misc.c uint32_t location, uint16_t *ident) uint32_t 260 fs/udf/misc.c uint32_t offset, uint16_t *ident) uint32_t 277 fs/udf/misc.c uint32_t loc, int length) uint32_t 175 fs/udf/namei.c uint32_t elen; uint32_t 341 fs/udf/namei.c uint32_t elen = 0; uint32_t 729 fs/udf/namei.c uint32_t elen; uint32_t 914 fs/udf/namei.c uint32_t bsize; uint32_t 29 fs/udf/partition.c uint32_t udf_get_pblock(struct super_block *sb, uint32_t block, uint32_t 30 fs/udf/partition.c uint16_t partition, uint32_t offset) uint32_t 46 fs/udf/partition.c uint32_t udf_get_pblock_virt15(struct super_block *sb, uint32_t block, uint32_t 47 fs/udf/partition.c uint16_t partition, uint32_t offset) uint32_t 50 fs/udf/partition.c uint32_t newblock; uint32_t 51 fs/udf/partition.c uint32_t index; uint32_t 52 fs/udf/partition.c uint32_t loc; uint32_t 72 fs/udf/partition.c index = (sb->s_blocksize - vdata->s_start_offset) / sizeof(uint32_t); uint32_t 75 fs/udf/partition.c newblock = 1 + (block / (sb->s_blocksize / sizeof(uint32_t))); uint32_t 76 fs/udf/partition.c index = block % (sb->s_blocksize / sizeof(uint32_t)); uint32_t 79 fs/udf/partition.c index = vdata->s_start_offset / sizeof(uint32_t) + block; uint32_t 106 fs/udf/partition.c inline uint32_t udf_get_pblock_virt20(struct super_block *sb, uint32_t block, uint32_t 107 fs/udf/partition.c uint16_t partition, uint32_t offset) uint32_t 112 fs/udf/partition.c uint32_t udf_get_pblock_spar15(struct super_block *sb, uint32_t block, uint32_t 113 fs/udf/partition.c uint16_t partition, uint32_t offset) uint32_t 119 fs/udf/partition.c uint32_t packet; uint32_t 157 fs/udf/partition.c uint32_t packet; uint32_t 280 fs/udf/partition.c static uint32_t udf_try_read_meta(struct inode *inode, uint32_t block, uint32_t 281 fs/udf/partition.c uint16_t partition, uint32_t offset) uint32_t 286 fs/udf/partition.c uint32_t elen; uint32_t 289 fs/udf/partition.c uint32_t phyblock; uint32_t 306 fs/udf/partition.c uint32_t udf_get_pblock_meta25(struct super_block *sb, uint32_t block, uint32_t 307 fs/udf/partition.c uint16_t partition, uint32_t offset) uint32_t 312 fs/udf/partition.c uint32_t retblk; uint32_t 113 fs/udf/super.c (2 * sizeof(uint32_t)) < partnum) { uint32_t 119 fs/udf/super.c offset = partnum * 2 * sizeof(uint32_t); uint32_t 1182 fs/udf/super.c uint32_t pos; uint32_t 1334 fs/udf/super.c uint32_t loc; uint32_t 1665 fs/udf/super.c uint32_t vdsn; uint32_t 2423 fs/udf/super.c uint32_t bytes; uint32_t 2472 fs/udf/super.c uint32_t elen; uint32_t 112 fs/udf/symlink.c uint32_t pos; uint32_t 30 fs/udf/truncate.c struct kernel_lb_addr *eloc, int8_t etype, uint32_t elen, uint32_t 31 fs/udf/truncate.c uint32_t nelen) uint32_t 71 fs/udf/truncate.c uint32_t elen, nelen; uint32_t 125 fs/udf/truncate.c uint32_t elen; uint32_t 206 fs/udf/truncate.c uint32_t elen, nelen = 0, indirect_ext_len = 0, lenalloc; uint32_t 7 fs/udf/udf_i.h uint32_t offset; uint32_t 43 fs/udf/udfdecl.h #define UDF_INVALID_ID ((uint32_t)-1) uint32_t 71 fs/udf/udfdecl.h typedef uint32_t udf_pblk_t; uint32_t 97 fs/udf/udfdecl.h uint32_t block; uint32_t 98 fs/udf/udfdecl.h uint32_t volDescSeqNum; uint32_t 159 fs/udf/udfdecl.h struct kernel_lb_addr *, uint32_t *, sector_t *); uint32_t 163 fs/udf/udfdecl.h struct kernel_lb_addr *eloc, uint32_t elen, int inc); uint32_t 165 fs/udf/udfdecl.h struct kernel_lb_addr *, uint32_t, int); uint32_t 167 fs/udf/udfdecl.h struct kernel_lb_addr *, uint32_t, int); uint32_t 170 fs/udf/udfdecl.h struct kernel_lb_addr *, uint32_t *, int); uint32_t 172 fs/udf/udfdecl.h struct kernel_lb_addr *, uint32_t *, int); uint32_t 179 fs/udf/udfdecl.h extern struct genericFormat *udf_add_extendedattr(struct inode *, uint32_t, uint32_t 180 fs/udf/udfdecl.h uint32_t, uint8_t); uint32_t 181 fs/udf/udfdecl.h extern struct genericFormat *udf_get_extendedattr(struct inode *, uint32_t, uint32_t 183 fs/udf/udfdecl.h extern struct buffer_head *udf_read_tagged(struct super_block *, uint32_t, uint32_t 184 fs/udf/udfdecl.h uint32_t, uint16_t *); uint32_t 186 fs/udf/udfdecl.h struct kernel_lb_addr *, uint32_t, uint32_t 189 fs/udf/udfdecl.h extern void udf_new_tag(char *, uint16_t, uint16_t, uint16_t, uint32_t, int); uint32_t 196 fs/udf/udfdecl.h extern uint32_t udf_get_pblock(struct super_block *, uint32_t, uint16_t, uint32_t 197 fs/udf/udfdecl.h uint32_t); uint32_t 198 fs/udf/udfdecl.h extern uint32_t udf_get_pblock_virt15(struct super_block *, uint32_t, uint16_t, uint32_t 199 fs/udf/udfdecl.h uint32_t); uint32_t 200 fs/udf/udfdecl.h extern uint32_t udf_get_pblock_virt20(struct super_block *, uint32_t, uint16_t, uint32_t 201 fs/udf/udfdecl.h uint32_t); uint32_t 202 fs/udf/udfdecl.h extern uint32_t udf_get_pblock_spar15(struct super_block *, uint32_t, uint16_t, uint32_t 203 fs/udf/udfdecl.h uint32_t); uint32_t 204 fs/udf/udfdecl.h extern uint32_t udf_get_pblock_meta25(struct super_block *, uint32_t, uint16_t, uint32_t 205 fs/udf/udfdecl.h uint32_t); uint32_t 208 fs/udf/udfdecl.h static inline uint32_t uint32_t 210 fs/udf/udfdecl.h uint32_t offset) uint32_t 235 fs/udf/udfdecl.h struct kernel_lb_addr *, uint32_t, uint32_t); uint32_t 237 fs/udf/udfdecl.h uint32_t, uint32_t); uint32_t 239 fs/udf/udfdecl.h uint16_t partition, uint32_t goal, int *err); uint32_t 246 fs/udf/udfdecl.h struct kernel_lb_addr *, uint32_t *, uint32_t 250 fs/udf/udfdecl.h extern struct long_ad *udf_get_filelongad(uint8_t *, int, uint32_t *, int); uint32_t 251 fs/udf/udfdecl.h extern struct short_ad *udf_get_fileshortad(uint8_t *, int, uint32_t *, int); uint32_t 156 fs/udf/unicode.c uint32_t c; uint32_t 2113 fs/xfs/libxfs/xfs_alloc.c uint32_t f = be32_to_cpu(agf->agf_flfirst); uint32_t 2114 fs/xfs/libxfs/xfs_alloc.c uint32_t l = be32_to_cpu(agf->agf_fllast); uint32_t 2115 fs/xfs/libxfs/xfs_alloc.c uint32_t c = be32_to_cpu(agf->agf_flcount); uint32_t 125 fs/xfs/libxfs/xfs_attr_leaf.c uint32_t firstused; uint32_t 243 fs/xfs/libxfs/xfs_attr_leaf.c uint32_t end; /* must be 32bit - see below */ uint32_t 299 fs/xfs/libxfs/xfs_attr_leaf.c end = (uint32_t)ichdr.freemap[i].base + ichdr.freemap[i].size; uint32_t 52 fs/xfs/libxfs/xfs_attr_remote.c uint32_t offset, uint32_t 53 fs/xfs/libxfs/xfs_attr_remote.c uint32_t size, uint32_t 227 fs/xfs/libxfs/xfs_attr_remote.c uint32_t offset, uint32_t 228 fs/xfs/libxfs/xfs_attr_remote.c uint32_t size, uint32_t 20 fs/xfs/libxfs/xfs_bit.h static inline uint32_t xfs_mask32lo(int n) uint32_t 22 fs/xfs/libxfs/xfs_bit.h return ((uint32_t)1 << (n)) - 1; uint32_t 30 fs/xfs/libxfs/xfs_bit.h static inline int xfs_highbit32(uint32_t v) uint32_t 42 fs/xfs/libxfs/xfs_bit.h static inline int xfs_lowbit32(uint32_t v) uint32_t 50 fs/xfs/libxfs/xfs_bit.h uint32_t w = (uint32_t)v; uint32_t 56 fs/xfs/libxfs/xfs_bit.h w = (uint32_t)(v >> 32); uint32_t 32 fs/xfs/libxfs/xfs_btree.c static const uint32_t xfs_magics[2][XFS_BTNUM_MAX] = { uint32_t 40 fs/xfs/libxfs/xfs_btree.c uint32_t uint32_t 45 fs/xfs/libxfs/xfs_btree.c uint32_t magic = xfs_magics[crc][btnum]; uint32_t 66 fs/xfs/libxfs/xfs_btree.h uint32_t xfs_btree_magic(int crc, xfs_btnum_t btnum); uint32_t 5 fs/xfs/libxfs/xfs_cksum.h #define XFS_CRC_SEED (~(uint32_t)0) uint32_t 13 fs/xfs/libxfs/xfs_cksum.h static inline uint32_t uint32_t 16 fs/xfs/libxfs/xfs_cksum.h uint32_t zero = 0; uint32_t 17 fs/xfs/libxfs/xfs_cksum.h uint32_t crc; uint32_t 34 fs/xfs/libxfs/xfs_cksum.h static inline uint32_t uint32_t 52 fs/xfs/libxfs/xfs_cksum.h xfs_end_cksum(uint32_t crc) uint32_t 66 fs/xfs/libxfs/xfs_cksum.h uint32_t crc = xfs_start_cksum_update(buffer, length, cksum_offset); uint32_t 77 fs/xfs/libxfs/xfs_cksum.h uint32_t crc = xfs_start_cksum_safe(buffer, length, cksum_offset); uint32_t 102 fs/xfs/libxfs/xfs_da_format.h uint32_t forw; uint32_t 103 fs/xfs/libxfs/xfs_da_format.h uint32_t back; uint32_t 185 fs/xfs/libxfs/xfs_da_format.h typedef uint32_t xfs_dir2_dataptr_t; uint32_t 197 fs/xfs/libxfs/xfs_da_format.h typedef uint32_t xfs_dir2_db_t; uint32_t 438 fs/xfs/libxfs/xfs_da_format.h uint32_t forw; uint32_t 439 fs/xfs/libxfs/xfs_da_format.h uint32_t back; uint32_t 529 fs/xfs/libxfs/xfs_da_format.h uint32_t magic; uint32_t 530 fs/xfs/libxfs/xfs_da_format.h uint32_t firstdb; uint32_t 531 fs/xfs/libxfs/xfs_da_format.h uint32_t nvalid; uint32_t 532 fs/xfs/libxfs/xfs_da_format.h uint32_t nused; uint32_t 716 fs/xfs/libxfs/xfs_da_format.h uint32_t forw; uint32_t 717 fs/xfs/libxfs/xfs_da_format.h uint32_t back; uint32_t 727 fs/xfs/libxfs/xfs_da_format.h uint32_t firstused; uint32_t 97 fs/xfs/libxfs/xfs_format.h uint32_t sb_magicnum; /* magic number == XFS_SB_MAGIC */ uint32_t 98 fs/xfs/libxfs/xfs_format.h uint32_t sb_blocksize; /* logical block size, bytes */ uint32_t 144 fs/xfs/libxfs/xfs_format.h uint32_t sb_unit; /* stripe or raid unit */ uint32_t 145 fs/xfs/libxfs/xfs_format.h uint32_t sb_width; /* stripe or raid width */ uint32_t 149 fs/xfs/libxfs/xfs_format.h uint32_t sb_logsunit; /* stripe unit size for the log */ uint32_t 150 fs/xfs/libxfs/xfs_format.h uint32_t sb_features2; /* additional feature bits */ uint32_t 161 fs/xfs/libxfs/xfs_format.h uint32_t sb_bad_features2; uint32_t 166 fs/xfs/libxfs/xfs_format.h uint32_t sb_features_compat; uint32_t 167 fs/xfs/libxfs/xfs_format.h uint32_t sb_features_ro_compat; uint32_t 168 fs/xfs/libxfs/xfs_format.h uint32_t sb_features_incompat; uint32_t 169 fs/xfs/libxfs/xfs_format.h uint32_t sb_features_log_incompat; uint32_t 171 fs/xfs/libxfs/xfs_format.h uint32_t sb_crc; /* superblock crc */ uint32_t 444 fs/xfs/libxfs/xfs_format.h uint32_t feature) uint32_t 460 fs/xfs/libxfs/xfs_format.h uint32_t feature) uint32_t 477 fs/xfs/libxfs/xfs_format.h uint32_t feature) uint32_t 487 fs/xfs/libxfs/xfs_format.h uint32_t feature) uint32_t 1071 fs/xfs/libxfs/xfs_format.h #define XFS_INO_MASK(k) (uint32_t)((1ULL << (k)) - 1) uint32_t 1403 fs/xfs/libxfs/xfs_format.h #define XFS_RMAP_LEN_MAX ((uint32_t)~0U) uint32_t 202 fs/xfs/libxfs/xfs_fs.h uint32_t sick; /* o: unhealthy fs & rt metadata */ uint32_t 203 fs/xfs/libxfs/xfs_fs.h uint32_t checked; /* o: checked fs & rt metadata */ uint32_t 283 fs/xfs/libxfs/xfs_fs.h uint32_t ag_number; /* i/o: AG number */ uint32_t 284 fs/xfs/libxfs/xfs_fs.h uint32_t ag_length; /* o: length in blocks */ uint32_t 285 fs/xfs/libxfs/xfs_fs.h uint32_t ag_freeblks; /* o: free space */ uint32_t 286 fs/xfs/libxfs/xfs_fs.h uint32_t ag_icount; /* o: inodes allocated */ uint32_t 287 fs/xfs/libxfs/xfs_fs.h uint32_t ag_ifree; /* o: inodes free */ uint32_t 288 fs/xfs/libxfs/xfs_fs.h uint32_t ag_sick; /* o: sick things in ag */ uint32_t 289 fs/xfs/libxfs/xfs_fs.h uint32_t ag_checked; /* o: checked metadata in ag */ uint32_t 290 fs/xfs/libxfs/xfs_fs.h uint32_t ag_flags; /* i/o: flags for this ag */ uint32_t 375 fs/xfs/libxfs/xfs_fs.h uint32_t bs_gen; /* generation count */ uint32_t 376 fs/xfs/libxfs/xfs_fs.h uint32_t bs_uid; /* user id */ uint32_t 377 fs/xfs/libxfs/xfs_fs.h uint32_t bs_gid; /* group id */ uint32_t 378 fs/xfs/libxfs/xfs_fs.h uint32_t bs_projectid; /* project id */ uint32_t 380 fs/xfs/libxfs/xfs_fs.h uint32_t bs_atime_nsec; /* access time, nanoseconds */ uint32_t 381 fs/xfs/libxfs/xfs_fs.h uint32_t bs_mtime_nsec; /* modify time, nanoseconds */ uint32_t 382 fs/xfs/libxfs/xfs_fs.h uint32_t bs_ctime_nsec; /* inode change time, nanoseconds */ uint32_t 383 fs/xfs/libxfs/xfs_fs.h uint32_t bs_btime_nsec; /* creation time, nanoseconds */ uint32_t 385 fs/xfs/libxfs/xfs_fs.h uint32_t bs_blksize; /* block size */ uint32_t 386 fs/xfs/libxfs/xfs_fs.h uint32_t bs_rdev; /* device value */ uint32_t 387 fs/xfs/libxfs/xfs_fs.h uint32_t bs_cowextsize_blks; /* cow extent size hint, blocks */ uint32_t 388 fs/xfs/libxfs/xfs_fs.h uint32_t bs_extsize_blks; /* extent size hint, blocks */ uint32_t 390 fs/xfs/libxfs/xfs_fs.h uint32_t bs_nlink; /* number of links */ uint32_t 391 fs/xfs/libxfs/xfs_fs.h uint32_t bs_extents; /* number of extents */ uint32_t 392 fs/xfs/libxfs/xfs_fs.h uint32_t bs_aextents; /* attribute number of extents */ uint32_t 422 fs/xfs/libxfs/xfs_fs.h static inline uint32_t uint32_t 425 fs/xfs/libxfs/xfs_fs.h return (uint32_t)bs->bs_projid_hi << 16 | bs->bs_projid_lo; uint32_t 462 fs/xfs/libxfs/xfs_fs.h uint32_t flags; /* I/O: operation flags */ uint32_t 463 fs/xfs/libxfs/xfs_fs.h uint32_t icount; /* I: count of entries in buffer */ uint32_t 464 fs/xfs/libxfs/xfs_fs.h uint32_t ocount; /* O: count of entries filled out */ uint32_t 465 fs/xfs/libxfs/xfs_fs.h uint32_t agno; /* I: see comment for IREQ_AGNO */ uint32_t 804 fs/xfs/libxfs/xfs_fs.h #define XFS_IOC_GOINGDOWN _IOR ('X', 125, uint32_t) uint32_t 294 fs/xfs/libxfs/xfs_iext_tree.c uint32_t rec_len = rec->hi & XFS_IEXT_LENGTH_MASK; uint32_t 381 fs/xfs/libxfs/xfs_inode_buf.c uint32_t di_nextents = XFS_DFORK_NEXTENTS(dip, whichfork); uint32_t 589 fs/xfs/libxfs/xfs_inode_buf.c uint32_t crc; uint32_t 730 fs/xfs/libxfs/xfs_inode_buf.c uint32_t extsize, uint32_t 737 fs/xfs/libxfs/xfs_inode_buf.c uint32_t extsize_bytes; uint32_t 738 fs/xfs/libxfs/xfs_inode_buf.c uint32_t blocksize_bytes; uint32_t 787 fs/xfs/libxfs/xfs_inode_buf.c uint32_t cowextsize, uint32_t 794 fs/xfs/libxfs/xfs_inode_buf.c uint32_t cowextsize_bytes; uint32_t 22 fs/xfs/libxfs/xfs_inode_buf.h uint32_t di_uid; /* owner's user id */ uint32_t 23 fs/xfs/libxfs/xfs_inode_buf.h uint32_t di_gid; /* owner's group id */ uint32_t 33 fs/xfs/libxfs/xfs_inode_buf.h uint32_t di_dmevmask; /* DMIG event mask */ uint32_t 38 fs/xfs/libxfs/xfs_inode_buf.h uint32_t di_cowextsize; /* basic cow extent size for file */ uint32_t 76 fs/xfs/libxfs/xfs_inode_buf.h uint32_t extsize, uint16_t mode, uint16_t flags); uint32_t 78 fs/xfs/libxfs/xfs_inode_buf.h uint32_t cowextsize, uint16_t mode, uint16_t flags, uint32_t 22 fs/xfs/libxfs/xfs_log_format.h typedef uint32_t xlog_tid_t; uint32_t 90 fs/xfs/libxfs/xfs_log_format.h uint32_t pad2; /* may as well make it 64 bits */ uint32_t 271 fs/xfs/libxfs/xfs_log_format.h uint32_t ilf_fields; /* flags for fields logged */ uint32_t 274 fs/xfs/libxfs/xfs_log_format.h uint32_t ilf_pad; /* pad for 64 bit boundary */ uint32_t 277 fs/xfs/libxfs/xfs_log_format.h uint32_t ilfu_rdev; /* rdev value for dev inode*/ uint32_t 293 fs/xfs/libxfs/xfs_log_format.h uint32_t ilf_fields; /* flags for fields logged */ uint32_t 298 fs/xfs/libxfs/xfs_log_format.h uint32_t ilfu_rdev; /* rdev value for dev inode*/ uint32_t 386 fs/xfs/libxfs/xfs_log_format.h uint32_t di_uid; /* owner's user id */ uint32_t 387 fs/xfs/libxfs/xfs_log_format.h uint32_t di_gid; /* owner's group id */ uint32_t 388 fs/xfs/libxfs/xfs_log_format.h uint32_t di_nlink; /* number of links to file */ uint32_t 403 fs/xfs/libxfs/xfs_log_format.h uint32_t di_dmevmask; /* DMIG event mask */ uint32_t 406 fs/xfs/libxfs/xfs_log_format.h uint32_t di_gen; /* generation number */ uint32_t 412 fs/xfs/libxfs/xfs_log_format.h uint32_t di_crc; /* CRC of the inode */ uint32_t 416 fs/xfs/libxfs/xfs_log_format.h uint32_t di_cowextsize; /* basic cow extent size for file */ uint32_t 548 fs/xfs/libxfs/xfs_log_format.h uint32_t ext_len; uint32_t 553 fs/xfs/libxfs/xfs_log_format.h uint32_t ext_len; uint32_t 554 fs/xfs/libxfs/xfs_log_format.h uint32_t ext_pad; uint32_t 565 fs/xfs/libxfs/xfs_log_format.h uint32_t efi_nextents; /* # extents to free */ uint32_t 573 fs/xfs/libxfs/xfs_log_format.h uint32_t efi_nextents; /* # extents to free */ uint32_t 581 fs/xfs/libxfs/xfs_log_format.h uint32_t efi_nextents; /* # extents to free */ uint32_t 594 fs/xfs/libxfs/xfs_log_format.h uint32_t efd_nextents; /* # of extents freed */ uint32_t 602 fs/xfs/libxfs/xfs_log_format.h uint32_t efd_nextents; /* # of extents freed */ uint32_t 610 fs/xfs/libxfs/xfs_log_format.h uint32_t efd_nextents; /* # of extents freed */ uint32_t 622 fs/xfs/libxfs/xfs_log_format.h uint32_t me_len; uint32_t 623 fs/xfs/libxfs/xfs_log_format.h uint32_t me_flags; uint32_t 654 fs/xfs/libxfs/xfs_log_format.h uint32_t rui_nextents; /* # extents to free */ uint32_t 675 fs/xfs/libxfs/xfs_log_format.h uint32_t __pad; uint32_t 684 fs/xfs/libxfs/xfs_log_format.h uint32_t pe_len; uint32_t 685 fs/xfs/libxfs/xfs_log_format.h uint32_t pe_flags; uint32_t 702 fs/xfs/libxfs/xfs_log_format.h uint32_t cui_nextents; /* # extents to free */ uint32_t 723 fs/xfs/libxfs/xfs_log_format.h uint32_t __pad; uint32_t 750 fs/xfs/libxfs/xfs_log_format.h uint32_t bui_nextents; /* # extents to free */ uint32_t 771 fs/xfs/libxfs/xfs_log_format.h uint32_t __pad; uint32_t 787 fs/xfs/libxfs/xfs_log_format.h uint32_t qlf_boffset; /* off of dquot in buffer */ uint32_t 17 fs/xfs/libxfs/xfs_log_recover.h ((((uint32_t)tid)>>XLOG_RHASH_SHIFT) & (XLOG_RHASH_SIZE-1)) uint32_t 376 fs/xfs/libxfs/xfs_rmap_btree.c uint32_t x; uint32_t 377 fs/xfs/libxfs/xfs_rmap_btree.c uint32_t y; uint32_t 406 fs/xfs/libxfs/xfs_rmap_btree.c uint32_t x; uint32_t 407 fs/xfs/libxfs/xfs_rmap_btree.c uint32_t y; uint32_t 223 fs/xfs/libxfs/xfs_sb.c uint32_t agcount = 0; uint32_t 224 fs/xfs/libxfs/xfs_sb.c uint32_t rem; uint32_t 255 fs/xfs/libxfs/xfs_sb.c uint32_t align; uint32_t 130 fs/xfs/libxfs/xfs_shared.h int xfs_symlink_hdr_set(struct xfs_mount *mp, xfs_ino_t ino, uint32_t offset, uint32_t 131 fs/xfs/libxfs/xfs_shared.h uint32_t size, struct xfs_buf *bp); uint32_t 132 fs/xfs/libxfs/xfs_shared.h bool xfs_symlink_hdr_ok(xfs_ino_t ino, uint32_t offset, uint32_t 133 fs/xfs/libxfs/xfs_shared.h uint32_t size, struct xfs_buf *bp); uint32_t 39 fs/xfs/libxfs/xfs_symlink_remote.c uint32_t offset, uint32_t 40 fs/xfs/libxfs/xfs_symlink_remote.c uint32_t size, uint32_t 68 fs/xfs/libxfs/xfs_symlink_remote.c uint32_t offset, uint32_t 69 fs/xfs/libxfs/xfs_symlink_remote.c uint32_t size, uint32_t 9 fs/xfs/libxfs/xfs_types.h typedef uint32_t prid_t; /* project ID */ uint32_t 11 fs/xfs/libxfs/xfs_types.h typedef uint32_t xfs_agblock_t; /* blockno in alloc. group */ uint32_t 12 fs/xfs/libxfs/xfs_types.h typedef uint32_t xfs_agino_t; /* inode # within allocation grp */ uint32_t 13 fs/xfs/libxfs/xfs_types.h typedef uint32_t xfs_extlen_t; /* extent length in blocks */ uint32_t 14 fs/xfs/libxfs/xfs_types.h typedef uint32_t xfs_agnumber_t; /* allocation group number */ uint32_t 21 fs/xfs/libxfs/xfs_types.h typedef uint32_t xfs_rtword_t; /* word type for bitmap manipulations */ uint32_t 26 fs/xfs/libxfs/xfs_types.h typedef uint32_t xfs_dablk_t; /* dir/attr block number (in file) */ uint32_t 27 fs/xfs/libxfs/xfs_types.h typedef uint32_t xfs_dahash_t; /* dir/attr hash value */ uint32_t 144 fs/xfs/libxfs/xfs_types.h typedef uint32_t xfs_dqid_t; uint32_t 66 fs/xfs/scrub/agheader.c uint32_t v2_ok; uint32_t 209 fs/xfs/scrub/inode.c uint32_t nextents; uint32_t 764 fs/xfs/scrub/trace.h __field(uint32_t, btnum) uint32_t 780 fs/xfs/scrub/trace.h uint32_t magic, uint16_t level), uint32_t 786 fs/xfs/scrub/trace.h __field(uint32_t, magic) uint32_t 533 fs/xfs/xfs_attr_list.c ((ATTR_ENTBASESIZE + (namelen) + 1 + sizeof(uint32_t)-1) \ uint32_t 534 fs/xfs/xfs_attr_list.c & ~(sizeof(uint32_t)-1)) uint32_t 1773 fs/xfs/xfs_bmap_util.c uint32_t ipnext = XFS_IFORK_NEXTENTS(ip, w); uint32_t 1774 fs/xfs/xfs_bmap_util.c uint32_t tipnext = XFS_IFORK_NEXTENTS(tip, w); uint32_t 14 fs/xfs/xfs_fsmap.h uint32_t fmr_flags; /* mapping flags */ uint32_t 22 fs/xfs/xfs_fsmap.h uint32_t fmh_iflags; /* control flags */ uint32_t 23 fs/xfs/xfs_fsmap.h uint32_t fmh_oflags; /* output flags */ uint32_t 432 fs/xfs/xfs_fsops.c uint32_t inflags) uint32_t 14 fs/xfs/xfs_fsops.h extern int xfs_fs_goingdown(xfs_mount_t *mp, uint32_t inflags); uint32_t 287 fs/xfs/xfs_icache.c uint32_t nlink = inode->i_nlink; uint32_t 288 fs/xfs/xfs_icache.c uint32_t generation = inode->i_generation; uint32_t 792 fs/xfs/xfs_icache.c uint32_t first_index; uint32_t 429 fs/xfs/xfs_ioctl.c uint32_t *len, uint32_t 430 fs/xfs/xfs_ioctl.c uint32_t flags) uint32_t 458 fs/xfs/xfs_ioctl.c uint32_t len, uint32_t 459 fs/xfs/xfs_ioctl.c uint32_t flags) uint32_t 484 fs/xfs/xfs_ioctl.c uint32_t flags) uint32_t 2358 fs/xfs/xfs_ioctl.c uint32_t in; uint32_t 2363 fs/xfs/xfs_ioctl.c if (get_user(in, (uint32_t __user *)arg)) uint32_t 39 fs/xfs/xfs_ioctl.h uint32_t *len, uint32_t 40 fs/xfs/xfs_ioctl.h uint32_t flags); uint32_t 47 fs/xfs/xfs_ioctl.h uint32_t len, uint32_t 48 fs/xfs/xfs_ioctl.h uint32_t flags); uint32_t 54 fs/xfs/xfs_ioctl.h uint32_t flags); uint32_t 172 fs/xfs/xfs_linux.h static inline uint32_t xfs_kuid_to_uid(kuid_t uid) uint32_t 177 fs/xfs/xfs_linux.h static inline kuid_t xfs_uid_to_kuid(uint32_t uid) uint32_t 182 fs/xfs/xfs_linux.h static inline uint32_t xfs_kgid_to_gid(kgid_t gid) uint32_t 187 fs/xfs/xfs_linux.h static inline kgid_t xfs_gid_to_kgid(uint32_t gid) uint32_t 208 fs/xfs/xfs_linux.h static inline uint64_t roundup_64(uint64_t x, uint32_t y) uint32_t 215 fs/xfs/xfs_linux.h static inline uint64_t howmany_64(uint64_t x, uint32_t y) uint32_t 1656 fs/xfs/xfs_log.c uint32_t crc; uint32_t 1795 fs/xfs/xfs_log.c uint32_t cycle = get_unaligned_be32(data + i); uint32_t 1807 fs/xfs/xfs_log.c uint32_t *roundoff) uint32_t 1809 fs/xfs/xfs_log.c uint32_t count_init, count; uint32_t 3246 fs/xfs/xfs_log.c uint32_t sunit_bb = BTOBB(log->l_mp->m_sb.sb_logsunit); uint32_t 403 fs/xfs/xfs_log_priv.h uint32_t l_badcrc_factor; uint32_t 2189 fs/xfs/xfs_log_recover.c uint32_t magic32; uint32_t 2340 fs/xfs/xfs_log_recover.c uint32_t magic32; uint32_t 198 fs/xfs/xfs_mount.h uint32_t m_generation; uint32_t 354 fs/xfs/xfs_mount.h uint32_t pagf_flcount; /* count of blocks in freelist */ uint32_t 357 fs/xfs/xfs_mount.h uint32_t pagf_btreeblks; /* # of blocks held in AGF btrees */ uint32_t 55 fs/xfs/xfs_qm.c uint32_t next_index; uint32_t 90 fs/xfs/xfs_stats.c uint32_t vn_active; uint32_t 44 fs/xfs/xfs_stats.h uint32_t xs_allocx; uint32_t 45 fs/xfs/xfs_stats.h uint32_t xs_allocb; uint32_t 46 fs/xfs/xfs_stats.h uint32_t xs_freex; uint32_t 47 fs/xfs/xfs_stats.h uint32_t xs_freeb; uint32_t 48 fs/xfs/xfs_stats.h uint32_t xs_abt_lookup; uint32_t 49 fs/xfs/xfs_stats.h uint32_t xs_abt_compare; uint32_t 50 fs/xfs/xfs_stats.h uint32_t xs_abt_insrec; uint32_t 51 fs/xfs/xfs_stats.h uint32_t xs_abt_delrec; uint32_t 52 fs/xfs/xfs_stats.h uint32_t xs_blk_mapr; uint32_t 53 fs/xfs/xfs_stats.h uint32_t xs_blk_mapw; uint32_t 54 fs/xfs/xfs_stats.h uint32_t xs_blk_unmap; uint32_t 55 fs/xfs/xfs_stats.h uint32_t xs_add_exlist; uint32_t 56 fs/xfs/xfs_stats.h uint32_t xs_del_exlist; uint32_t 57 fs/xfs/xfs_stats.h uint32_t xs_look_exlist; uint32_t 58 fs/xfs/xfs_stats.h uint32_t xs_cmp_exlist; uint32_t 59 fs/xfs/xfs_stats.h uint32_t xs_bmbt_lookup; uint32_t 60 fs/xfs/xfs_stats.h uint32_t xs_bmbt_compare; uint32_t 61 fs/xfs/xfs_stats.h uint32_t xs_bmbt_insrec; uint32_t 62 fs/xfs/xfs_stats.h uint32_t xs_bmbt_delrec; uint32_t 63 fs/xfs/xfs_stats.h uint32_t xs_dir_lookup; uint32_t 64 fs/xfs/xfs_stats.h uint32_t xs_dir_create; uint32_t 65 fs/xfs/xfs_stats.h uint32_t xs_dir_remove; uint32_t 66 fs/xfs/xfs_stats.h uint32_t xs_dir_getdents; uint32_t 67 fs/xfs/xfs_stats.h uint32_t xs_trans_sync; uint32_t 68 fs/xfs/xfs_stats.h uint32_t xs_trans_async; uint32_t 69 fs/xfs/xfs_stats.h uint32_t xs_trans_empty; uint32_t 70 fs/xfs/xfs_stats.h uint32_t xs_ig_attempts; uint32_t 71 fs/xfs/xfs_stats.h uint32_t xs_ig_found; uint32_t 72 fs/xfs/xfs_stats.h uint32_t xs_ig_frecycle; uint32_t 73 fs/xfs/xfs_stats.h uint32_t xs_ig_missed; uint32_t 74 fs/xfs/xfs_stats.h uint32_t xs_ig_dup; uint32_t 75 fs/xfs/xfs_stats.h uint32_t xs_ig_reclaims; uint32_t 76 fs/xfs/xfs_stats.h uint32_t xs_ig_attrchg; uint32_t 77 fs/xfs/xfs_stats.h uint32_t xs_log_writes; uint32_t 78 fs/xfs/xfs_stats.h uint32_t xs_log_blocks; uint32_t 79 fs/xfs/xfs_stats.h uint32_t xs_log_noiclogs; uint32_t 80 fs/xfs/xfs_stats.h uint32_t xs_log_force; uint32_t 81 fs/xfs/xfs_stats.h uint32_t xs_log_force_sleep; uint32_t 82 fs/xfs/xfs_stats.h uint32_t xs_try_logspace; uint32_t 83 fs/xfs/xfs_stats.h uint32_t xs_sleep_logspace; uint32_t 84 fs/xfs/xfs_stats.h uint32_t xs_push_ail; uint32_t 85 fs/xfs/xfs_stats.h uint32_t xs_push_ail_success; uint32_t 86 fs/xfs/xfs_stats.h uint32_t xs_push_ail_pushbuf; uint32_t 87 fs/xfs/xfs_stats.h uint32_t xs_push_ail_pinned; uint32_t 88 fs/xfs/xfs_stats.h uint32_t xs_push_ail_locked; uint32_t 89 fs/xfs/xfs_stats.h uint32_t xs_push_ail_flushing; uint32_t 90 fs/xfs/xfs_stats.h uint32_t xs_push_ail_restarts; uint32_t 91 fs/xfs/xfs_stats.h uint32_t xs_push_ail_flush; uint32_t 92 fs/xfs/xfs_stats.h uint32_t xs_xstrat_quick; uint32_t 93 fs/xfs/xfs_stats.h uint32_t xs_xstrat_split; uint32_t 94 fs/xfs/xfs_stats.h uint32_t xs_write_calls; uint32_t 95 fs/xfs/xfs_stats.h uint32_t xs_read_calls; uint32_t 96 fs/xfs/xfs_stats.h uint32_t xs_attr_get; uint32_t 97 fs/xfs/xfs_stats.h uint32_t xs_attr_set; uint32_t 98 fs/xfs/xfs_stats.h uint32_t xs_attr_remove; uint32_t 99 fs/xfs/xfs_stats.h uint32_t xs_attr_list; uint32_t 100 fs/xfs/xfs_stats.h uint32_t xs_iflush_count; uint32_t 101 fs/xfs/xfs_stats.h uint32_t xs_icluster_flushcnt; uint32_t 102 fs/xfs/xfs_stats.h uint32_t xs_icluster_flushinode; uint32_t 103 fs/xfs/xfs_stats.h uint32_t vn_active; /* # vnodes not on free lists */ uint32_t 104 fs/xfs/xfs_stats.h uint32_t vn_alloc; /* # times vn_alloc called */ uint32_t 105 fs/xfs/xfs_stats.h uint32_t vn_get; /* # times vn_get called */ uint32_t 106 fs/xfs/xfs_stats.h uint32_t vn_hold; /* # times vn_hold called */ uint32_t 107 fs/xfs/xfs_stats.h uint32_t vn_rele; /* # times vn_rele called */ uint32_t 108 fs/xfs/xfs_stats.h uint32_t vn_reclaim; /* # times vn_reclaim called */ uint32_t 109 fs/xfs/xfs_stats.h uint32_t vn_remove; /* # times vn_remove called */ uint32_t 110 fs/xfs/xfs_stats.h uint32_t vn_free; /* # times vn_free called */ uint32_t 111 fs/xfs/xfs_stats.h uint32_t xb_get; uint32_t 112 fs/xfs/xfs_stats.h uint32_t xb_create; uint32_t 113 fs/xfs/xfs_stats.h uint32_t xb_get_locked; uint32_t 114 fs/xfs/xfs_stats.h uint32_t xb_get_locked_waited; uint32_t 115 fs/xfs/xfs_stats.h uint32_t xb_busy_locked; uint32_t 116 fs/xfs/xfs_stats.h uint32_t xb_miss_locked; uint32_t 117 fs/xfs/xfs_stats.h uint32_t xb_page_retries; uint32_t 118 fs/xfs/xfs_stats.h uint32_t xb_page_found; uint32_t 119 fs/xfs/xfs_stats.h uint32_t xb_get_read; uint32_t 121 fs/xfs/xfs_stats.h uint32_t xs_abtb_2[__XBTS_MAX]; uint32_t 122 fs/xfs/xfs_stats.h uint32_t xs_abtc_2[__XBTS_MAX]; uint32_t 123 fs/xfs/xfs_stats.h uint32_t xs_bmbt_2[__XBTS_MAX]; uint32_t 124 fs/xfs/xfs_stats.h uint32_t xs_ibt_2[__XBTS_MAX]; uint32_t 125 fs/xfs/xfs_stats.h uint32_t xs_fibt_2[__XBTS_MAX]; uint32_t 126 fs/xfs/xfs_stats.h uint32_t xs_rmap_2[__XBTS_MAX]; uint32_t 127 fs/xfs/xfs_stats.h uint32_t xs_refcbt_2[__XBTS_MAX]; uint32_t 128 fs/xfs/xfs_stats.h uint32_t xs_qm_dqreclaims; uint32_t 129 fs/xfs/xfs_stats.h uint32_t xs_qm_dqreclaim_misses; uint32_t 130 fs/xfs/xfs_stats.h uint32_t xs_qm_dquot_dups; uint32_t 131 fs/xfs/xfs_stats.h uint32_t xs_qm_dqcachemisses; uint32_t 132 fs/xfs/xfs_stats.h uint32_t xs_qm_dqcachehits; uint32_t 133 fs/xfs/xfs_stats.h uint32_t xs_qm_dqwants; uint32_t 134 fs/xfs/xfs_stats.h uint32_t xs_qm_dquot; uint32_t 135 fs/xfs/xfs_stats.h uint32_t xs_qm_dquot_unused; uint32_t 142 fs/xfs/xfs_stats.h #define xfsstats_offset(f) (offsetof(struct __xfsstats, f)/sizeof(uint32_t)) uint32_t 147 fs/xfs/xfs_stats.h uint32_t a[xfsstats_offset(xs_qm_dquot)]; uint32_t 155 fs/xfs/xfs_stats.h (offsetof(struct __xfsstats, member) / (int)sizeof(uint32_t)) uint32_t 3338 fs/xfs/xfs_trace.h __field(uint32_t, tid) uint32_t 3339 fs/xfs/xfs_trace.h __field(uint32_t, flags) uint32_t 342 fs/xfs/xfs_trans.c uint32_t flags = (XFS_TRANS_DIRTY|XFS_TRANS_SB_DIRTY); uint32_t 548 fs/xfs/xfs_trans.c uint32_t *field, uint32_t 44 include/asm-generic/div64.h uint32_t __base = (base); \ uint32_t 45 include/asm-generic/div64.h uint32_t __rem; \ uint32_t 81 include/asm-generic/div64.h uint32_t ___p, ___bias; \ uint32_t 128 include/asm-generic/div64.h uint32_t ___bits = -(___m & -___m); \ uint32_t 177 include/asm-generic/div64.h uint32_t m_lo = m; uint32_t 178 include/asm-generic/div64.h uint32_t m_hi = m >> 32; uint32_t 179 include/asm-generic/div64.h uint32_t n_lo = n; uint32_t 180 include/asm-generic/div64.h uint32_t n_hi = n >> 32; uint32_t 182 include/asm-generic/div64.h uint32_t res_lo, res_hi, tmp; uint32_t 217 include/asm-generic/div64.h extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); uint32_t 224 include/asm-generic/div64.h uint32_t __base = (base); \ uint32_t 225 include/asm-generic/div64.h uint32_t __rem; \ uint32_t 234 include/asm-generic/div64.h uint32_t __res_lo, __n_lo = (n); \ uint32_t 240 include/asm-generic/div64.h __rem = (uint32_t)(n) % __base; \ uint32_t 241 include/asm-generic/div64.h (n) = (uint32_t)(n) / __base; \ uint32_t 15 include/crypto/asym_tpm_subtype.h struct tpm_key *tpm_key_create(const void *blob, uint32_t blob_len); uint32_t 82 include/crypto/drbg.h typedef uint32_t drbg_flag_t; uint32_t 90 include/drm/drm_atomic_helper.h uint32_t flags); uint32_t 115 include/drm/drm_atomic_helper.h uint32_t src_x, uint32_t src_y, uint32_t 116 include/drm/drm_atomic_helper.h uint32_t src_w, uint32_t src_h, uint32_t 138 include/drm/drm_atomic_helper.h uint32_t flags, uint32_t 144 include/drm/drm_atomic_helper.h uint32_t flags, uint32_t 145 include/drm/drm_atomic_helper.h uint32_t target, uint32_t 149 include/drm/drm_atomic_helper.h uint32_t size, uint32_t 50 include/drm/drm_auth.h uint32_t kernel_waiters; uint32_t 51 include/drm/drm_auth.h uint32_t user_waiters; uint32_t 32 include/drm/drm_color_mgmt.h uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision); uint32_t 768 include/drm/drm_connector.h int (*fill_modes)(struct drm_connector *connector, uint32_t max_width, uint32_t max_height); uint32_t 1296 include/drm/drm_connector.h uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER]; uint32_t 1455 include/drm/drm_connector.h uint32_t id) uint32_t 425 include/drm/drm_crtc.h uint32_t handle, uint32_t width, uint32_t height); uint32_t 447 include/drm/drm_crtc.h uint32_t handle, uint32_t width, uint32_t height, uint32_t 482 include/drm/drm_crtc.h uint32_t size, uint32_t 567 include/drm/drm_crtc.h uint32_t flags, uint32_t 586 include/drm/drm_crtc.h uint32_t flags, uint32_t target, uint32_t 1011 include/drm/drm_crtc.h uint32_t gamma_size; uint32_t 1134 include/drm/drm_crtc.h uint32_t x; uint32_t 1135 include/drm/drm_crtc.h uint32_t y; uint32_t 1171 include/drm/drm_crtc.h static inline uint32_t drm_crtc_mask(const struct drm_crtc *crtc) uint32_t 1191 include/drm/drm_crtc.h uint32_t id) uint32_t 60 include/drm/drm_damage_helper.h uint32_t num_clips; uint32_t 62 include/drm/drm_damage_helper.h uint32_t curr_clip; uint32_t 35 include/drm/drm_debugfs_crc.h uint32_t frame; uint32_t 36 include/drm/drm_debugfs_crc.h uint32_t crcs[DRM_MAX_CRC_NR]; uint32_t 65 include/drm/drm_debugfs_crc.h uint32_t frame, uint32_t *crcs); uint32_t 68 include/drm/drm_debugfs_crc.h uint32_t frame, uint32_t *crcs) uint32_t 566 include/drm/drm_drv.h uint32_t handle, uint32_t flags, int *prime_fd); uint32_t 577 include/drm/drm_drv.h int prime_fd, uint32_t *handle); uint32_t 696 include/drm/drm_drv.h struct drm_device *dev, uint32_t handle, uint32_t 716 include/drm/drm_drv.h uint32_t handle); uint32_t 150 include/drm/drm_encoder.h uint32_t possible_crtcs; uint32_t 167 include/drm/drm_encoder.h uint32_t possible_clones; uint32_t 236 include/drm/drm_encoder.h uint32_t id) uint32_t 312 include/drm/drm_fourcc.h uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth); uint32_t 313 include/drm/drm_fourcc.h uint32_t drm_driver_legacy_fb_format(struct drm_device *dev, uint32_t 314 include/drm/drm_fourcc.h uint32_t bpp, uint32_t depth); uint32_t 321 include/drm/drm_fourcc.h const char *drm_get_format_name(uint32_t format, struct drm_format_name_buf *buf); uint32_t 223 include/drm/drm_framebuffer.h uint32_t id); uint32_t 257 include/drm/drm_framebuffer.h static inline uint32_t drm_framebuffer_read_refcount(const struct drm_framebuffer *fb) uint32_t 408 include/drm/drm_gem.h uint32_t handle); uint32_t 155 include/drm/drm_gem_shmem_helper.h uint32_t *handle); uint32_t 115 include/drm/drm_gem_vram_helper.h uint32_t handle, uint64_t *offset); uint32_t 23 include/drm/drm_lease.h uint32_t drm_lease_filter_crtcs(struct drm_file *file_priv, uint32_t crtcs); uint32_t 137 include/drm/drm_mipi_dbi.h const uint32_t *formats, unsigned int format_count, uint32_t 859 include/drm/drm_mode_config.h uint32_t preferred_depth, prefer_shadow; uint32_t 918 include/drm/drm_mode_config.h uint32_t cursor_width, cursor_height; uint32_t 56 include/drm/drm_mode_object.h uint32_t id; uint32_t 57 include/drm/drm_mode_object.h uint32_t type; uint32_t 119 include/drm/drm_mode_object.h uint32_t id, uint32_t type); uint32_t 134 include/drm/drm_mode_object.h bool drm_mode_object_lease_required(uint32_t type); uint32_t 92 include/drm/drm_modeset_lock.h uint32_t flags); uint32_t 20 include/drm/drm_of.h uint32_t drm_of_crtc_port_mask(struct drm_device *dev, uint32_t 22 include/drm/drm_of.h uint32_t drm_of_find_possible_crtcs(struct drm_device *dev, uint32_t 39 include/drm/drm_of.h static inline uint32_t drm_of_crtc_port_mask(struct drm_device *dev, uint32_t 45 include/drm/drm_of.h static inline uint32_t drm_of_find_possible_crtcs(struct drm_device *dev, uint32_t 100 include/drm/drm_plane.h uint32_t crtc_w, crtc_h; uint32_t 106 include/drm/drm_plane.h uint32_t src_x; uint32_t 111 include/drm/drm_plane.h uint32_t src_y; uint32_t 114 include/drm/drm_plane.h uint32_t src_h, src_w; uint32_t 268 include/drm/drm_plane.h uint32_t src_x, uint32_t src_y, uint32_t 269 include/drm/drm_plane.h uint32_t src_w, uint32_t src_h, uint32_t 495 include/drm/drm_plane.h bool (*format_mod_supported)(struct drm_plane *plane, uint32_t format, uint32_t 590 include/drm/drm_plane.h uint32_t possible_crtcs; uint32_t 592 include/drm/drm_plane.h uint32_t *format_types; uint32_t 715 include/drm/drm_plane.h uint32_t possible_crtcs, uint32_t 717 include/drm/drm_plane.h const uint32_t *formats, uint32_t 724 include/drm/drm_plane.h uint32_t possible_crtcs, uint32_t 726 include/drm/drm_plane.h const uint32_t *formats, unsigned int format_count, uint32_t 769 include/drm/drm_plane.h uint32_t id) uint32_t 72 include/drm/drm_prime.h struct drm_file *file_priv, int prime_fd, uint32_t *handle); uint32_t 74 include/drm/drm_prime.h struct drm_file *file_priv, uint32_t handle, uint32_t flags, uint32_t 13 include/drm/drm_probe_helper.h *connector, uint32_t maxX, uint32_t 14 include/drm/drm_probe_helper.h uint32_t maxY); uint32_t 159 include/drm/drm_property.h uint32_t flags; uint32_t 169 include/drm/drm_property.h uint32_t num_values; uint32_t 235 include/drm/drm_property.h uint32_t type) uint32_t 263 include/drm/drm_property.h uint32_t type); uint32_t 274 include/drm/drm_property.h uint32_t id); uint32_t 296 include/drm/drm_property.h uint32_t id) uint32_t 177 include/drm/drm_simple_kms_helper.h const uint32_t *formats, unsigned int format_count, uint32_t 126 include/drm/drm_syncobj.h int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags, uint32_t 268 include/drm/gpu_scheduler.h uint32_t hw_submission_limit; uint32_t 288 include/drm/gpu_scheduler.h uint32_t hw_submission, unsigned hang_limit, long timeout, uint32_t 100 include/drm/ttm/ttm_bo_api.h uint32_t page_alignment; uint32_t 101 include/drm/ttm/ttm_bo_api.h uint32_t mem_type; uint32_t 102 include/drm/ttm/ttm_bo_api.h uint32_t placement; uint32_t 278 include/drm/ttm/ttm_bo_api.h uint32_t flags; uint32_t 340 include/drm/ttm/ttm_bo_api.h uint32_t *new_flags); uint32_t 525 include/drm/ttm/ttm_bo_api.h uint32_t page_alignment, uint32_t 572 include/drm/ttm/ttm_bo_api.h uint32_t page_alignment, bool interrubtible, size_t acc_size, uint32_t 597 include/drm/ttm/ttm_bo_api.h uint32_t page_alignment, bool interruptible, uint32_t 179 include/drm/ttm/ttm_bo_driver.h uint32_t flags; uint32_t 182 include/drm/ttm/ttm_bo_driver.h uint32_t available_caching; uint32_t 183 include/drm/ttm/ttm_bo_driver.h uint32_t default_caching; uint32_t 236 include/drm/ttm/ttm_bo_driver.h uint32_t page_flags); uint32_t 271 include/drm/ttm/ttm_bo_driver.h int (*invalidate_caches)(struct ttm_bo_device *bdev, uint32_t flags); uint32_t 272 include/drm/ttm/ttm_bo_driver.h int (*init_mem_type)(struct ttm_bo_device *bdev, uint32_t type, uint32_t 539 include/drm/ttm/ttm_bo_driver.h static inline uint32_t uint32_t 540 include/drm/ttm/ttm_bo_driver.h ttm_flag_masked(uint32_t *old, uint32_t new, uint32_t mask) uint32_t 902 include/drm/ttm/ttm_bo_driver.h pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp); uint32_t 88 include/drm/ttm/ttm_placement.h uint32_t flags; uint32_t 109 include/drm/ttm/ttm_tt.h uint32_t page_flags; uint32_t 162 include/drm/ttm/ttm_tt.h uint32_t page_flags); uint32_t 164 include/drm/ttm/ttm_tt.h uint32_t page_flags); uint32_t 166 include/drm/ttm/ttm_tt.h uint32_t page_flags); uint32_t 229 include/drm/ttm/ttm_tt.h int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement); uint32_t 267 include/drm/ttm/ttm_tt.h uint32_t page_flags); uint32_t 31 include/keys/trusted-type.h uint32_t keyhandle; uint32_t 34 include/keys/trusted-type.h uint32_t pcrinfo_len; uint32_t 37 include/keys/trusted-type.h uint32_t hash; uint32_t 38 include/keys/trusted-type.h uint32_t policydigest_len; uint32_t 40 include/keys/trusted-type.h uint32_t policyhandle; uint32_t 16 include/keys/trusted.h #define LOAD32(buffer, offset) (ntohl(*(uint32_t *)&buffer[offset])) uint32_t 17 include/keys/trusted.h #define LOAD32N(buffer, offset) (*(uint32_t *)&buffer[offset]) uint32_t 28 include/keys/trusted.h uint32_t handle; uint32_t 43 include/keys/trusted.h const uint32_t command, uint32_t 49 include/keys/trusted.h int oiap(struct tpm_buf *tb, uint32_t *handle, unsigned char *nonce); uint32_t 124 include/keys/trusted.h static inline void store32(struct tpm_buf *buf, const uint32_t value) uint32_t 126 include/keys/trusted.h *(uint32_t *) & buf->data[buf->len] = htonl(value); uint32_t 46 include/linux/bch.h uint32_t *mod8_tab; uint32_t 47 include/linux/bch.h uint32_t *ecc_buf; uint32_t 48 include/linux/bch.h uint32_t *ecc_buf2; uint32_t 77 include/linux/cb710.h int reg, uint32_t and, uint32_t xor); uint32_t 154 include/linux/cb710.h uint32_t cb710_sg_dwiter_read_next_block(struct sg_mapping_iter *miter); uint32_t 155 include/linux/cb710.h void cb710_sg_dwiter_write_next_block(struct sg_mapping_iter *miter, uint32_t data); uint32_t 24 include/linux/ceph/osdmap.h uint32_t seed; uint32_t 30 include/linux/consolemap.h #define conv_8bit_to_uni(c) ((uint32_t)(c)) uint32_t 52 include/linux/cs5535.h uint32_t lo, hi; uint32_t 260 include/linux/device-mapper.h uint32_t max_io_len; uint32_t 411 include/linux/device-mapper.h uint32_t dm_get_event_nr(struct mapped_device *md); uint32_t 413 include/linux/device-mapper.h uint32_t dm_next_uevent_seq(struct mapped_device *md); uint32_t 29 include/linux/digsig.h uint32_t timestamp; /* key made, always 0 for now */ uint32_t 37 include/linux/digsig.h uint32_t timestamp; /* signature made */ uint32_t 35 include/linux/dlm.h int num_slots, int our_slot, uint32_t generation); uint32_t 84 include/linux/dlm.h uint32_t flags, int lvblen, uint32_t 136 include/linux/dlm.h uint32_t flags, uint32_t 139 include/linux/dlm.h uint32_t parent_lkid, uint32_t 165 include/linux/dlm.h uint32_t lkid, uint32_t 166 include/linux/dlm.h uint32_t flags, uint32_t 51 include/linux/dm-dirty-log.h uint32_t (*get_region_size)(struct dm_dirty_log *log); uint32_t 41 include/linux/dm-region-hash.h struct dm_dirty_log *log, uint32_t region_size, uint32_t 541 include/linux/dma-fence.h uint32_t count, uint32_t 543 include/linux/dma-fence.h uint32_t *idx); uint32_t 123 include/linux/dma/ipu-dma.h uint32_t in_pixel_fmt; uint32_t 126 include/linux/dma/ipu-dma.h uint32_t out_pixel_fmt; uint32_t 121 include/linux/fscache.h uint32_t version; /* indexing version */ uint32_t 18 include/linux/fsi.h uint32_t addr; uint32_t 19 include/linux/fsi.h uint32_t size; uint32_t 22 include/linux/fsi.h extern int fsi_device_read(struct fsi_device *dev, uint32_t addr, uint32_t 24 include/linux/fsi.h extern int fsi_device_write(struct fsi_device *dev, uint32_t addr, uint32_t 63 include/linux/fsi.h uint32_t addr, uint32_t size); uint32_t 65 include/linux/fsi.h uint32_t addr, uint32_t size); uint32_t 66 include/linux/fsi.h extern int fsi_slave_read(struct fsi_slave *slave, uint32_t addr, uint32_t 68 include/linux/fsi.h extern int fsi_slave_write(struct fsi_slave *slave, uint32_t addr, uint32_t 114 include/linux/iio/imu/adis.h uint32_t val) uint32_t 144 include/linux/iio/imu/adis.h uint32_t *val) uint32_t 32 include/linux/input/matrix_keypad.h const uint32_t *keymap; uint32_t 50 include/linux/intel-ish-client-if.h uint32_t size; uint32_t 91 include/linux/ioc3.h extern void ioc3_write_ireg(struct ioc3_driver_data *idd, uint32_t value, int reg); uint32_t 17 include/linux/jz4740-adc.h int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val); uint32_t 31 include/linux/key.h typedef uint32_t key_perm_t; uint32_t 1340 include/linux/kvm_host.h uint32_t guest_irq, bool set); uint32_t 131 include/linux/lockd/lockd.h uint32_t pid; uint32_t 99 include/linux/lz4.h uint32_t hashTable[LZ4_HASH_SIZE_U32]; uint32_t 100 include/linux/lz4.h uint32_t currentOffset; uint32_t 101 include/linux/lz4.h uint32_t initCheck; uint32_t 104 include/linux/lz4.h uint32_t dictSize; uint32_t 141 include/linux/mtd/cfi.h uint32_t EraseRegionInfo[0]; /* Not host ordered */ uint32_t 158 include/linux/mtd/cfi.h uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature uint32_t 172 include/linux/mtd/cfi.h uint32_t ProtRegAddr; uint32_t 245 include/linux/mtd/cfi.h uint32_t ProtField[1]; /* Not host ordered */ uint32_t 251 include/linux/mtd/cfi.h uint32_t ConfField[1]; /* Not host ordered */ uint32_t 292 include/linux/mtd/cfi.h uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, uint32_t 302 include/linux/mtd/cfi.h uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base, uint32_t 306 include/linux/mtd/cfi.h static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr) uint32_t 322 include/linux/mtd/cfi.h static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr) uint32_t 342 include/linux/mtd/cfi.h int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map, uint32_t 344 include/linux/mtd/cfi.h void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map, uint32_t 38 include/linux/mtd/ftl.h uint32_t EraseCount; uint32_t 44 include/linux/mtd/ftl.h uint32_t FormattedSize; uint32_t 45 include/linux/mtd/ftl.h uint32_t FirstVMAddress; uint32_t 49 include/linux/mtd/ftl.h uint32_t SerialNumber; uint32_t 50 include/linux/mtd/ftl.h uint32_t AltEUHOffset; uint32_t 51 include/linux/mtd/ftl.h uint32_t BAMOffset; uint32_t 330 include/linux/mtd/map.h r.x[0] = get_unaligned((uint32_t *)ptr); uint32_t 37 include/linux/mtd/mtd.h uint32_t erasesize; /* For this region */ uint32_t 38 include/linux/mtd/mtd.h uint32_t numblocks; /* Number of blocks of erasesize in this region */ uint32_t 69 include/linux/mtd/mtd.h uint32_t ooboffs; uint32_t 199 include/linux/mtd/mtd.h uint32_t flags; uint32_t 200 include/linux/mtd/mtd.h uint32_t orig_flags; /* Flags as before running mtd checks */ uint32_t 207 include/linux/mtd/mtd.h uint32_t erasesize; uint32_t 215 include/linux/mtd/mtd.h uint32_t writesize; uint32_t 226 include/linux/mtd/mtd.h uint32_t writebufsize; uint32_t 228 include/linux/mtd/mtd.h uint32_t oobsize; // Amount of OOB data per block (e.g. 16) uint32_t 229 include/linux/mtd/mtd.h uint32_t oobavail; // Available OOB bytes per block uint32_t 464 include/linux/mtd/mtd.h static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd) uint32_t 472 include/linux/mtd/mtd.h static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd) uint32_t 507 include/linux/mtd/mtd.h static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd) uint32_t 515 include/linux/mtd/mtd.h static inline uint32_t mtd_mod_by_ws(uint64_t sz, struct mtd_info *mtd) uint32_t 53 include/linux/mtd/ndfc.h uint32_t ccr_settings; uint32_t 58 include/linux/mtd/ndfc.h uint32_t bank_settings; uint32_t 50 include/linux/mtd/partitions.h uint32_t mask_flags; /* master MTD flags to mask out for this partition */ uint32_t 378 include/linux/mtd/rawnand.h int (*read_subpage)(struct nand_chip *chip, uint32_t offs, uint32_t 379 include/linux/mtd/rawnand.h uint32_t len, uint8_t *buf, int page); uint32_t 380 include/linux/mtd/rawnand.h int (*write_subpage)(struct nand_chip *chip, uint32_t offset, uint32_t 381 include/linux/mtd/rawnand.h uint32_t data_len, const uint8_t *data_buf, uint32_t 145 include/linux/mtd/sh_flctl.h uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */ uint32_t 147 include/linux/mtd/sh_flctl.h uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ uint32_t 148 include/linux/mtd/sh_flctl.h uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ uint32_t 149 include/linux/mtd/sh_flctl.h uint32_t flcmncr_base; /* base value of FLCMNCR */ uint32_t 150 include/linux/mtd/sh_flctl.h uint32_t flintdmacr_base; /* irq enable bits */ uint32_t 28 include/linux/nfs4.h uint32_t type; uint32_t 29 include/linux/nfs4.h uint32_t flag; uint32_t 30 include/linux/nfs4.h uint32_t access_mask; uint32_t 39 include/linux/nfs4.h uint32_t naces; uint32_t 46 include/linux/nfs4.h uint32_t lfs; uint32_t 47 include/linux/nfs4.h uint32_t pi; uint32_t 1295 include/linux/nfs_xdr.h uint32_t major_id_sz; uint32_t 1300 include/linux/nfs_xdr.h uint32_t server_scope_sz; uint32_t 1338 include/linux/nfs_xdr.h uint32_t seqid; uint32_t 1339 include/linux/nfs_xdr.h uint32_t flags; uint32_t 1340 include/linux/nfs_xdr.h uint32_t cb_program; uint32_t 1347 include/linux/nfs_xdr.h uint32_t seqid; uint32_t 1348 include/linux/nfs_xdr.h uint32_t flags; uint32_t 77 include/linux/of.h uint32_t args[MAX_PHANDLE_ARGS]; uint32_t 92 include/linux/of.h uint32_t cur_count; uint32_t 388 include/linux/of.h uint32_t *args, uint32_t 891 include/linux/of.h uint32_t *args, uint32_t 59 include/linux/of_fdt.h extern uint32_t of_get_flat_dt_phandle(unsigned long node); uint32_t 157 include/linux/pe.h uint32_t peaddr; /* address of pe header */ uint32_t 167 include/linux/pe.h uint32_t magic; /* PE magic */ uint32_t 170 include/linux/pe.h uint32_t timestamp; /* time_t */ uint32_t 171 include/linux/pe.h uint32_t symbol_table; /* symbol table offset */ uint32_t 172 include/linux/pe.h uint32_t symbols; /* number of symbols */ uint32_t 184 include/linux/pe.h uint32_t text_size; /* size of text section(s) */ uint32_t 185 include/linux/pe.h uint32_t data_size; /* size of data section(s) */ uint32_t 186 include/linux/pe.h uint32_t bss_size; /* size of bss section(s) */ uint32_t 187 include/linux/pe.h uint32_t entry_point; /* file offset of entry point */ uint32_t 188 include/linux/pe.h uint32_t code_base; /* relative code addr in ram */ uint32_t 189 include/linux/pe.h uint32_t data_base; /* relative data addr in ram */ uint32_t 191 include/linux/pe.h uint32_t image_base; /* preferred load address */ uint32_t 192 include/linux/pe.h uint32_t section_align; /* alignment in bytes */ uint32_t 193 include/linux/pe.h uint32_t file_align; /* file alignment in bytes */ uint32_t 200 include/linux/pe.h uint32_t win32_version; /* reserved, must be 0 */ uint32_t 201 include/linux/pe.h uint32_t image_size; /* image size */ uint32_t 202 include/linux/pe.h uint32_t header_size; /* header size rounded up to uint32_t 204 include/linux/pe.h uint32_t csum; /* checksum */ uint32_t 207 include/linux/pe.h uint32_t stack_size_req;/* amt of stack requested */ uint32_t 208 include/linux/pe.h uint32_t stack_size; /* amt of stack required */ uint32_t 209 include/linux/pe.h uint32_t heap_size_req; /* amt of heap requested */ uint32_t 210 include/linux/pe.h uint32_t heap_size; /* amt of heap required */ uint32_t 211 include/linux/pe.h uint32_t loader_flags; /* reserved, must be 0 */ uint32_t 212 include/linux/pe.h uint32_t data_dirs; /* number of data dir entries */ uint32_t 219 include/linux/pe.h uint32_t text_size; /* size of text section(s) */ uint32_t 220 include/linux/pe.h uint32_t data_size; /* size of data section(s) */ uint32_t 221 include/linux/pe.h uint32_t bss_size; /* size of bss section(s) */ uint32_t 222 include/linux/pe.h uint32_t entry_point; /* file offset of entry point */ uint32_t 223 include/linux/pe.h uint32_t code_base; /* relative code addr in ram */ uint32_t 226 include/linux/pe.h uint32_t section_align; /* alignment in bytes */ uint32_t 227 include/linux/pe.h uint32_t file_align; /* file alignment in bytes */ uint32_t 234 include/linux/pe.h uint32_t win32_version; /* reserved, must be 0 */ uint32_t 235 include/linux/pe.h uint32_t image_size; /* image size */ uint32_t 236 include/linux/pe.h uint32_t header_size; /* header size rounded up to uint32_t 238 include/linux/pe.h uint32_t csum; /* checksum */ uint32_t 245 include/linux/pe.h uint32_t loader_flags; /* reserved, must be 0 */ uint32_t 246 include/linux/pe.h uint32_t data_dirs; /* number of data dir entries */ uint32_t 250 include/linux/pe.h uint32_t virtual_address; /* relative to load address */ uint32_t 251 include/linux/pe.h uint32_t size; uint32_t 275 include/linux/pe.h uint32_t virtual_size; /* size of loaded section in ram */ uint32_t 276 include/linux/pe.h uint32_t virtual_address; /* relative virtual address */ uint32_t 277 include/linux/pe.h uint32_t raw_data_size; /* size of the section */ uint32_t 278 include/linux/pe.h uint32_t data_addr; /* file pointer to first page of sec */ uint32_t 279 include/linux/pe.h uint32_t relocs; /* file pointer to relocation entries */ uint32_t 280 include/linux/pe.h uint32_t line_numbers; /* line numbers! */ uint32_t 283 include/linux/pe.h uint32_t flags; uint32_t 413 include/linux/pe.h uint32_t virtual_address; uint32_t 414 include/linux/pe.h uint32_t symbol_table_index; uint32_t 437 include/linux/pe.h uint32_t length; uint32_t 13 include/linux/platform_data/ata-pxa.h uint32_t dma_dreq; uint32_t 15 include/linux/platform_data/ata-pxa.h uint32_t reg_shift; uint32_t 17 include/linux/platform_data/ata-pxa.h uint32_t irq_flags; uint32_t 28 include/linux/platform_data/cros_ec_chardev.h uint32_t offset; uint32_t 29 include/linux/platform_data/cros_ec_chardev.h uint32_t bytes; uint32_t 935 include/linux/platform_data/cros_ec_commands.h uint32_t version; uint32_t 949 include/linux/platform_data/cros_ec_commands.h uint32_t in_data; uint32_t 957 include/linux/platform_data/cros_ec_commands.h uint32_t out_data; uint32_t 980 include/linux/platform_data/cros_ec_commands.h uint32_t current_image; uint32_t 992 include/linux/platform_data/cros_ec_commands.h uint32_t offset; uint32_t 993 include/linux/platform_data/cros_ec_commands.h uint32_t size; uint32_t 1001 include/linux/platform_data/cros_ec_commands.h uint32_t data[32]; uint32_t 1083 include/linux/platform_data/cros_ec_commands.h uint32_t version_mask; uint32_t 1106 include/linux/platform_data/cros_ec_commands.h uint32_t flags; /* Mask of enum ec_comms_status */ uint32_t 1114 include/linux/platform_data/cros_ec_commands.h uint32_t ec_result; uint32_t 1115 include/linux/platform_data/cros_ec_commands.h uint32_t ret_len; uint32_t 1141 include/linux/platform_data/cros_ec_commands.h uint32_t protocol_versions; uint32_t 1144 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 1161 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 1162 include/linux/platform_data/cros_ec_commands.h uint32_t value; uint32_t 1166 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 1167 include/linux/platform_data/cros_ec_commands.h uint32_t value; uint32_t 1292 include/linux/platform_data/cros_ec_commands.h uint32_t flags[2]; uint32_t 1303 include/linux/platform_data/cros_ec_commands.h uint32_t sku_id; uint32_t 1326 include/linux/platform_data/cros_ec_commands.h uint32_t flash_size; uint32_t 1327 include/linux/platform_data/cros_ec_commands.h uint32_t write_block_size; uint32_t 1328 include/linux/platform_data/cros_ec_commands.h uint32_t erase_block_size; uint32_t 1329 include/linux/platform_data/cros_ec_commands.h uint32_t protect_block_size; uint32_t 1378 include/linux/platform_data/cros_ec_commands.h uint32_t flash_size; uint32_t 1379 include/linux/platform_data/cros_ec_commands.h uint32_t write_block_size; uint32_t 1380 include/linux/platform_data/cros_ec_commands.h uint32_t erase_block_size; uint32_t 1381 include/linux/platform_data/cros_ec_commands.h uint32_t protect_block_size; uint32_t 1384 include/linux/platform_data/cros_ec_commands.h uint32_t write_ideal_size; uint32_t 1385 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 1412 include/linux/platform_data/cros_ec_commands.h uint32_t flash_size; uint32_t 1414 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 1416 include/linux/platform_data/cros_ec_commands.h uint32_t write_ideal_size; uint32_t 1437 include/linux/platform_data/cros_ec_commands.h uint32_t offset; uint32_t 1438 include/linux/platform_data/cros_ec_commands.h uint32_t size; uint32_t 1454 include/linux/platform_data/cros_ec_commands.h uint32_t offset; uint32_t 1455 include/linux/platform_data/cros_ec_commands.h uint32_t size; uint32_t 1468 include/linux/platform_data/cros_ec_commands.h uint32_t offset; uint32_t 1469 include/linux/platform_data/cros_ec_commands.h uint32_t size; uint32_t 1560 include/linux/platform_data/cros_ec_commands.h uint32_t mask; uint32_t 1561 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 1574 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 1575 include/linux/platform_data/cros_ec_commands.h uint32_t valid_flags; uint32_t 1576 include/linux/platform_data/cros_ec_commands.h uint32_t writable_flags; uint32_t 1623 include/linux/platform_data/cros_ec_commands.h uint32_t region; uint32_t 1627 include/linux/platform_data/cros_ec_commands.h uint32_t offset; uint32_t 1628 include/linux/platform_data/cros_ec_commands.h uint32_t size; uint32_t 1642 include/linux/platform_data/cros_ec_commands.h uint32_t op; uint32_t 1688 include/linux/platform_data/cros_ec_commands.h uint32_t rpm; uint32_t 1696 include/linux/platform_data/cros_ec_commands.h uint32_t rpm; uint32_t 1701 include/linux/platform_data/cros_ec_commands.h uint32_t rpm; uint32_t 1727 include/linux/platform_data/cros_ec_commands.h uint32_t percent; uint32_t 1732 include/linux/platform_data/cros_ec_commands.h uint32_t percent; uint32_t 2019 include/linux/platform_data/cros_ec_commands.h uint32_t num; uint32_t 2020 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 2154 include/linux/platform_data/cros_ec_commands.h uint32_t offset; /* Offset in flash to hash */ uint32_t 2155 include/linux/platform_data/cros_ec_commands.h uint32_t size; /* Number of bytes to hash */ uint32_t 2164 include/linux/platform_data/cros_ec_commands.h uint32_t offset; /* Offset in flash which was hashed */ uint32_t 2165 include/linux/platform_data/cros_ec_commands.h uint32_t size; /* Number of bytes hashed */ uint32_t 2399 include/linux/platform_data/cros_ec_commands.h uint32_t timestamp; uint32_t 2418 include/linux/platform_data/cros_ec_commands.h uint32_t timestamp; uint32_t 2426 include/linux/platform_data/cros_ec_commands.h uint32_t number_data; uint32_t 2610 include/linux/platform_data/cros_ec_commands.h uint32_t max_data_vector; uint32_t 2702 include/linux/platform_data/cros_ec_commands.h uint32_t min_frequency; uint32_t 2705 include/linux/platform_data/cros_ec_commands.h uint32_t max_frequency; uint32_t 2708 include/linux/platform_data/cros_ec_commands.h uint32_t fifo_max_event_count; uint32_t 2748 include/linux/platform_data/cros_ec_commands.h uint32_t enabled; uint32_t 2749 include/linux/platform_data/cros_ec_commands.h uint32_t disabled; uint32_t 2825 include/linux/platform_data/cros_ec_commands.h uint32_t pstore_size; uint32_t 2827 include/linux/platform_data/cros_ec_commands.h uint32_t access_size; uint32_t 2838 include/linux/platform_data/cros_ec_commands.h uint32_t offset; /* Byte offset to read */ uint32_t 2839 include/linux/platform_data/cros_ec_commands.h uint32_t size; /* Size to read in bytes */ uint32_t 2846 include/linux/platform_data/cros_ec_commands.h uint32_t offset; /* Byte offset to write */ uint32_t 2847 include/linux/platform_data/cros_ec_commands.h uint32_t size; /* Size to write in bytes */ uint32_t 2856 include/linux/platform_data/cros_ec_commands.h uint32_t time; uint32_t 2860 include/linux/platform_data/cros_ec_commands.h uint32_t time; uint32_t 2893 include/linux/platform_data/cros_ec_commands.h uint32_t offset; uint32_t 2894 include/linux/platform_data/cros_ec_commands.h uint32_t num_entries; uint32_t 2902 include/linux/platform_data/cros_ec_commands.h uint32_t writes; uint32_t 2903 include/linux/platform_data/cros_ec_commands.h uint32_t history_size; uint32_t 2904 include/linux/platform_data/cros_ec_commands.h uint32_t last_boot; uint32_t 2929 include/linux/platform_data/cros_ec_commands.h uint32_t slot_locked; uint32_t 3023 include/linux/platform_data/cros_ec_commands.h uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ uint32_t 3024 include/linux/platform_data/cros_ec_commands.h uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */ uint32_t 3025 include/linux/platform_data/cros_ec_commands.h uint32_t temp_fan_off; /* no active cooling needed */ uint32_t 3026 include/linux/platform_data/cros_ec_commands.h uint32_t temp_fan_max; /* max active cooling needed */ uint32_t 3031 include/linux/platform_data/cros_ec_commands.h uint32_t sensor_num; uint32_t 3040 include/linux/platform_data/cros_ec_commands.h uint32_t sensor_num; uint32_t 3140 include/linux/platform_data/cros_ec_commands.h uint32_t rows; uint32_t 3141 include/linux/platform_data/cros_ec_commands.h uint32_t cols; uint32_t 3202 include/linux/platform_data/cros_ec_commands.h uint32_t keyboard_id; uint32_t 3236 include/linux/platform_data/cros_ec_commands.h uint32_t valid_mask; /* valid fields */ uint32_t 3241 include/linux/platform_data/cros_ec_commands.h uint32_t poll_timeout_us; uint32_t 3301 include/linux/platform_data/cros_ec_commands.h uint32_t time_us; uint32_t 3385 include/linux/platform_data/cros_ec_commands.h uint32_t host_event; uint32_t 3394 include/linux/platform_data/cros_ec_commands.h uint32_t buttons; uint32_t 3396 include/linux/platform_data/cros_ec_commands.h uint32_t switches; uint32_t 3398 include/linux/platform_data/cros_ec_commands.h uint32_t fp_events; uint32_t 3400 include/linux/platform_data/cros_ec_commands.h uint32_t sysrq; uint32_t 3403 include/linux/platform_data/cros_ec_commands.h uint32_t cec_events; uint32_t 3410 include/linux/platform_data/cros_ec_commands.h uint32_t host_event; uint32_t 3419 include/linux/platform_data/cros_ec_commands.h uint32_t buttons; uint32_t 3421 include/linux/platform_data/cros_ec_commands.h uint32_t switches; uint32_t 3423 include/linux/platform_data/cros_ec_commands.h uint32_t fp_events; uint32_t 3425 include/linux/platform_data/cros_ec_commands.h uint32_t sysrq; uint32_t 3428 include/linux/platform_data/cros_ec_commands.h uint32_t cec_events; uint32_t 3532 include/linux/platform_data/cros_ec_commands.h uint32_t mask; uint32_t 3536 include/linux/platform_data/cros_ec_commands.h uint32_t mask; uint32_t 3723 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 3785 include/linux/platform_data/cros_ec_commands.h uint32_t mode; /* enum charge_control_mode */ uint32_t 3885 include/linux/platform_data/cros_ec_commands.h uint32_t usb_dev_type; uint32_t 3973 include/linux/platform_data/cros_ec_commands.h uint32_t flags; uint32_t 4041 include/linux/platform_data/cros_ec_commands.h uint32_t param; /* enum charge_state_param */ uint32_t 4045 include/linux/platform_data/cros_ec_commands.h uint32_t param; /* param to set */ uint32_t 4046 include/linux/platform_data/cros_ec_commands.h uint32_t value; /* value to set */ uint32_t 4062 include/linux/platform_data/cros_ec_commands.h uint32_t value; uint32_t 4076 include/linux/platform_data/cros_ec_commands.h uint32_t limit; /* in mA */ uint32_t 4113 include/linux/platform_data/cros_ec_commands.h uint32_t seconds; uint32_t 4121 include/linux/platform_data/cros_ec_commands.h uint32_t time_g3; uint32_t 4127 include/linux/platform_data/cros_ec_commands.h uint32_t time_remaining; uint32_t 4133 include/linux/platform_data/cros_ec_commands.h uint32_t hibernate_delay; uint32_t 4202 include/linux/platform_data/cros_ec_commands.h uint32_t sleep_transitions; uint32_t 4231 include/linux/platform_data/cros_ec_commands.h uint32_t event_mask; uint32_t 4236 include/linux/platform_data/cros_ec_commands.h uint32_t event_mask; uint32_t 4291 include/linux/platform_data/cros_ec_commands.h uint32_t param; uint32_t 4292 include/linux/platform_data/cros_ec_commands.h uint32_t value; uint32_t 4297 include/linux/platform_data/cros_ec_commands.h uint32_t value; uint32_t 4553 include/linux/platform_data/cros_ec_commands.h uint32_t bclk; uint32_t 4676 include/linux/platform_data/cros_ec_commands.h uint32_t curr_lim_ma; /* input current limit */ uint32_t 4690 include/linux/platform_data/cros_ec_commands.h uint32_t status; /* PD MCU host event status */ uint32_t 4825 include/linux/platform_data/cros_ec_commands.h uint32_t max_power; uint32_t 4853 include/linux/platform_data/cros_ec_commands.h uint32_t size; /* Size to write in bytes */ uint32_t 4869 include/linux/platform_data/cros_ec_commands.h uint32_t current_image; /* One of ec_current_image */ uint32_t 4909 include/linux/platform_data/cros_ec_commands.h uint32_t timestamp; /* relative timestamp in milliseconds */ uint32_t 5003 include/linux/platform_data/cros_ec_commands.h uint32_t vdo[6]; /* Mode VDOs */ uint32_t 5016 include/linux/platform_data/cros_ec_commands.h uint32_t cmd; /* enum pd_mode_cmd */ uint32_t 5100 include/linux/platform_data/cros_ec_commands.h uint32_t status; uint32_t 5112 include/linux/platform_data/cros_ec_commands.h uint32_t action; uint32_t 5153 include/linux/platform_data/cros_ec_commands.h uint32_t tag; /* enum cbi_data_tag */ uint32_t 5154 include/linux/platform_data/cros_ec_commands.h uint32_t flag; /* CBI_GET_* */ uint32_t 5169 include/linux/platform_data/cros_ec_commands.h uint32_t tag; /* enum cbi_data_tag */ uint32_t 5170 include/linux/platform_data/cros_ec_commands.h uint32_t flag; /* CBI_SET_* */ uint32_t 5171 include/linux/platform_data/cros_ec_commands.h uint32_t size; /* Data size */ uint32_t 5189 include/linux/platform_data/cros_ec_commands.h uint32_t time_since_ec_boot_ms; uint32_t 5197 include/linux/platform_data/cros_ec_commands.h uint32_t ap_resets_since_ec_boot; uint32_t 5203 include/linux/platform_data/cros_ec_commands.h uint32_t ec_reset_flags; uint32_t 5221 include/linux/platform_data/cros_ec_commands.h uint32_t reset_time_ms; uint32_t 5361 include/linux/platform_data/cros_ec_commands.h uint32_t mode; /* as defined by FP_MODE_ constants */ uint32_t 5365 include/linux/platform_data/cros_ec_commands.h uint32_t mode; /* as defined by FP_MODE_ constants */ uint32_t 5386 include/linux/platform_data/cros_ec_commands.h uint32_t vendor_id; uint32_t 5387 include/linux/platform_data/cros_ec_commands.h uint32_t product_id; uint32_t 5388 include/linux/platform_data/cros_ec_commands.h uint32_t model_id; uint32_t 5389 include/linux/platform_data/cros_ec_commands.h uint32_t version; uint32_t 5391 include/linux/platform_data/cros_ec_commands.h uint32_t frame_size; uint32_t 5392 include/linux/platform_data/cros_ec_commands.h uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ uint32_t 5401 include/linux/platform_data/cros_ec_commands.h uint32_t vendor_id; uint32_t 5402 include/linux/platform_data/cros_ec_commands.h uint32_t product_id; uint32_t 5403 include/linux/platform_data/cros_ec_commands.h uint32_t model_id; uint32_t 5404 include/linux/platform_data/cros_ec_commands.h uint32_t version; uint32_t 5406 include/linux/platform_data/cros_ec_commands.h uint32_t frame_size; uint32_t 5407 include/linux/platform_data/cros_ec_commands.h uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ uint32_t 5413 include/linux/platform_data/cros_ec_commands.h uint32_t template_size; /* max template size in bytes */ uint32_t 5416 include/linux/platform_data/cros_ec_commands.h uint32_t template_dirty; /* bitmap of templates with MCU side changes */ uint32_t 5417 include/linux/platform_data/cros_ec_commands.h uint32_t template_version; /* version of the template format */ uint32_t 5437 include/linux/platform_data/cros_ec_commands.h #define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t)) uint32_t 5464 include/linux/platform_data/cros_ec_commands.h uint32_t offset; uint32_t 5465 include/linux/platform_data/cros_ec_commands.h uint32_t size; uint32_t 5475 include/linux/platform_data/cros_ec_commands.h uint32_t offset; uint32_t 5476 include/linux/platform_data/cros_ec_commands.h uint32_t size; uint32_t 5484 include/linux/platform_data/cros_ec_commands.h uint32_t userid[FP_CONTEXT_USERID_WORDS]; uint32_t 5493 include/linux/platform_data/cros_ec_commands.h uint32_t capture_time_us; uint32_t 5494 include/linux/platform_data/cros_ec_commands.h uint32_t matching_time_us; uint32_t 5495 include/linux/platform_data/cros_ec_commands.h uint32_t overall_time_us; uint32_t 5497 include/linux/platform_data/cros_ec_commands.h uint32_t lo; uint32_t 5498 include/linux/platform_data/cros_ec_commands.h uint32_t hi; uint32_t 5523 include/linux/platform_data/cros_ec_commands.h uint32_t valid_flags; uint32_t 5525 include/linux/platform_data/cros_ec_commands.h uint32_t status; uint32_t 5538 include/linux/platform_data/cros_ec_commands.h uint32_t n_frames; uint32_t 5539 include/linux/platform_data/cros_ec_commands.h uint32_t frame_sizes[0]; uint32_t 5549 include/linux/platform_data/cros_ec_commands.h uint32_t frame_index; uint32_t 5550 include/linux/platform_data/cros_ec_commands.h uint32_t offset; uint32_t 5551 include/linux/platform_data/cros_ec_commands.h uint32_t size; uint32_t 5591 include/linux/platform_data/cros_ec_commands.h uint32_t cycle_count; uint32_t 67 include/linux/platform_data/cros_ec_proto.h uint32_t version; uint32_t 68 include/linux/platform_data/cros_ec_proto.h uint32_t command; uint32_t 69 include/linux/platform_data/cros_ec_proto.h uint32_t outsize; uint32_t 70 include/linux/platform_data/cros_ec_proto.h uint32_t insize; uint32_t 71 include/linux/platform_data/cros_ec_proto.h uint32_t result; uint32_t 38 include/linux/platform_data/cyttsp4.h uint32_t size; uint32_t 43 include/linux/platform_data/mtd-davinci.h uint32_t mask_ale; uint32_t 44 include/linux/platform_data/mtd-davinci.h uint32_t mask_cle; uint32_t 54 include/linux/platform_data/mtd-davinci.h uint32_t core_chipsel; uint32_t 57 include/linux/platform_data/mtd-davinci.h uint32_t mask_chipsel; uint32_t 12 include/linux/power/bq24735-charger.h uint32_t charge_current; uint32_t 13 include/linux/power/bq24735-charger.h uint32_t charge_voltage; uint32_t 14 include/linux/power/bq24735-charger.h uint32_t input_current; uint32_t 40 include/linux/raid/pq.h typedef uint32_t u32; uint32_t 184 include/linux/raid/pq.h static inline uint32_t raid6_jiffies(void) uint32_t 30 include/linux/sdb.h uint32_t device_id; /* 0x20..0x23 */ uint32_t 31 include/linux/sdb.h uint32_t version; /* 0x24..0x27 */ uint32_t 32 include/linux/sdb.h uint32_t date; /* 0x28..0x2b */ uint32_t 67 include/linux/sdb.h uint32_t sdb_magic; /* 0x00-0x03 */ uint32_t 84 include/linux/sdb.h uint32_t bus_specific; /* 0x04-0x07 */ uint32_t 125 include/linux/sdb.h uint32_t tool_version; /* 0x28-0x2b */ uint32_t 126 include/linux/sdb.h uint32_t date; /* 0x2c-0x2f */ uint32_t 28 include/linux/seqno-fence.h uint32_t seqno_ofs; uint32_t 88 include/linux/seqno-fence.h struct dma_buf *sync_buf, uint32_t context, uint32_t 89 include/linux/seqno-fence.h uint32_t seqno_ofs, uint32_t seqno, uint32_t 44 include/linux/soc/qcom/apr.h uint32_t opcode; uint32_t 45 include/linux/soc/qcom/apr.h uint32_t status; uint32_t 63 include/linux/soc/qcom/apr.h uint32_t token; uint32_t 64 include/linux/soc/qcom/apr.h uint32_t opcode; uint32_t 86 include/linux/soc/qcom/apr.h uint32_t version; uint32_t 28 include/linux/stat.h uint32_t blksize; /* Preferred I/O size */ uint32_t 114 include/linux/string.h extern void *memset32(uint32_t *, uint32_t, __kernel_size_t); uint32_t 125 include/linux/string.h return memset32((uint32_t *)p, v, n); uint32_t 133 include/linux/string.h return memset32((uint32_t *)p, (uintptr_t)v, n); uint32_t 36 include/linux/sunrpc/bc_xprt.h void xprt_complete_bc_request(struct rpc_rqst *req, uint32_t copied); uint32_t 989 include/linux/syscalls.h asmlinkage long sys_rseq(struct rseq __user *rseq, uint32_t rseq_len, uint32_t 990 include/linux/syscalls.h int flags, uint32_t sig); uint32_t 95 include/linux/xxhash.h uint32_t xxh32(const void *input, size_t length, uint32_t seed); uint32_t 147 include/linux/xxhash.h uint32_t total_len_32; uint32_t 148 include/linux/xxhash.h uint32_t large_len; uint32_t 149 include/linux/xxhash.h uint32_t v1; uint32_t 150 include/linux/xxhash.h uint32_t v2; uint32_t 151 include/linux/xxhash.h uint32_t v3; uint32_t 152 include/linux/xxhash.h uint32_t v4; uint32_t 153 include/linux/xxhash.h uint32_t mem32[4]; uint32_t 154 include/linux/xxhash.h uint32_t memsize; uint32_t 167 include/linux/xxhash.h uint32_t memsize; uint32_t 178 include/linux/xxhash.h void xxh32_reset(struct xxh32_state *state, uint32_t seed); uint32_t 204 include/linux/xxhash.h uint32_t xxh32_digest(const struct xxh32_state *state); uint32_t 194 include/linux/xz.h XZ_EXTERN struct xz_dec *xz_dec_init(enum xz_mode mode, uint32_t dict_max); uint32_t 262 include/linux/xz.h XZ_EXTERN uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc); uint32_t 237 include/media/dvb_demux.h uint32_t speed_pkts_cnt; /* for TS speed check */ uint32_t 52 include/media/i2c/smiapp.h uint32_t nvm_size; /* bytes */ uint32_t 53 include/media/i2c/smiapp.h uint32_t ext_clk; /* sensor external clk */ uint32_t 56 include/media/i2c/smiapp.h uint32_t csi_signalling_mode; /* SMIAPP_CSI_SIGNALLING_MODE_* */ uint32_t 5076 include/net/cfg80211.h uint32_t oui; uint32_t 5130 include/net/cfg80211.h uint32_t _bitmap_shifter; uint32_t 332 include/rdma/ib_verbs.h uint32_t rc_odp_caps; uint32_t 333 include/rdma/ib_verbs.h uint32_t uc_odp_caps; uint32_t 334 include/rdma/ib_verbs.h uint32_t ud_odp_caps; uint32_t 335 include/rdma/ib_verbs.h uint32_t xrc_odp_caps; uint32_t 38 include/rdma/rdma_counter.h uint32_t id; uint32_t 93 include/scsi/iscsi_if.h uint32_t type; /* k/u events type */ uint32_t 94 include/scsi/iscsi_if.h uint32_t iferror; /* carries interface or resource errors */ uint32_t 100 include/scsi/iscsi_if.h uint32_t initial_cmdsn; uint32_t 106 include/scsi/iscsi_if.h uint32_t initial_cmdsn; uint32_t 111 include/scsi/iscsi_if.h uint32_t sid; uint32_t 114 include/scsi/iscsi_if.h uint32_t sid; uint32_t 115 include/scsi/iscsi_if.h uint32_t cid; uint32_t 118 include/scsi/iscsi_if.h uint32_t sid; uint32_t 119 include/scsi/iscsi_if.h uint32_t cid; uint32_t 121 include/scsi/iscsi_if.h uint32_t is_leading; uint32_t 124 include/scsi/iscsi_if.h uint32_t sid; uint32_t 125 include/scsi/iscsi_if.h uint32_t cid; uint32_t 128 include/scsi/iscsi_if.h uint32_t sid; uint32_t 129 include/scsi/iscsi_if.h uint32_t cid; uint32_t 130 include/scsi/iscsi_if.h uint32_t hdr_size; uint32_t 131 include/scsi/iscsi_if.h uint32_t data_size; uint32_t 134 include/scsi/iscsi_if.h uint32_t sid; uint32_t 135 include/scsi/iscsi_if.h uint32_t cid; uint32_t 136 include/scsi/iscsi_if.h uint32_t param; /* enum iscsi_param */ uint32_t 137 include/scsi/iscsi_if.h uint32_t len; uint32_t 140 include/scsi/iscsi_if.h uint32_t sid; uint32_t 141 include/scsi/iscsi_if.h uint32_t cid; uint32_t 144 include/scsi/iscsi_if.h uint32_t sid; uint32_t 145 include/scsi/iscsi_if.h uint32_t cid; uint32_t 147 include/scsi/iscsi_if.h uint32_t flag; uint32_t 150 include/scsi/iscsi_if.h uint32_t sid; uint32_t 151 include/scsi/iscsi_if.h uint32_t cid; uint32_t 154 include/scsi/iscsi_if.h uint32_t non_blocking; uint32_t 157 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 158 include/scsi/iscsi_if.h uint32_t non_blocking; uint32_t 162 include/scsi/iscsi_if.h uint32_t timeout_ms; uint32_t 169 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 176 include/scsi/iscsi_if.h uint32_t enable; uint32_t 179 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 180 include/scsi/iscsi_if.h uint32_t param; /* enum iscsi_host_param */ uint32_t 181 include/scsi/iscsi_if.h uint32_t len; uint32_t 184 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 187 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 188 include/scsi/iscsi_if.h uint32_t count; uint32_t 191 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 192 include/scsi/iscsi_if.h uint32_t iface_num; uint32_t 193 include/scsi/iscsi_if.h uint32_t iface_type; uint32_t 194 include/scsi/iscsi_if.h uint32_t payload_size; uint32_t 195 include/scsi/iscsi_if.h uint32_t pid; /* unique ping id associated uint32_t 199 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 200 include/scsi/iscsi_if.h uint32_t num_entries; /* number of CHAP entries uint32_t 207 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 211 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 212 include/scsi/iscsi_if.h uint32_t flashnode_idx; uint32_t 213 include/scsi/iscsi_if.h uint32_t count; uint32_t 216 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 217 include/scsi/iscsi_if.h uint32_t len; uint32_t 220 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 221 include/scsi/iscsi_if.h uint32_t flashnode_idx; uint32_t 224 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 225 include/scsi/iscsi_if.h uint32_t flashnode_idx; uint32_t 228 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 229 include/scsi/iscsi_if.h uint32_t flashnode_idx; uint32_t 232 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 233 include/scsi/iscsi_if.h uint32_t sid; uint32_t 236 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 243 include/scsi/iscsi_if.h uint32_t sid; uint32_t 244 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 247 include/scsi/iscsi_if.h uint32_t sid; uint32_t 248 include/scsi/iscsi_if.h uint32_t cid; uint32_t 251 include/scsi/iscsi_if.h uint32_t sid; uint32_t 252 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 255 include/scsi/iscsi_if.h uint32_t sid; uint32_t 256 include/scsi/iscsi_if.h uint32_t cid; uint32_t 260 include/scsi/iscsi_if.h uint32_t sid; uint32_t 261 include/scsi/iscsi_if.h uint32_t cid; uint32_t 262 include/scsi/iscsi_if.h uint32_t state; /* enum iscsi_conn_state */ uint32_t 265 include/scsi/iscsi_if.h uint32_t sid; uint32_t 266 include/scsi/iscsi_if.h uint32_t cid; uint32_t 267 include/scsi/iscsi_if.h uint32_t error; /* enum iscsi_err */ uint32_t 270 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 271 include/scsi/iscsi_if.h uint32_t sid; uint32_t 277 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 280 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 283 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 284 include/scsi/iscsi_if.h uint32_t data_size; uint32_t 288 include/scsi/iscsi_if.h uint32_t host_no; uint32_t 289 include/scsi/iscsi_if.h uint32_t status; /* enum uint32_t 291 include/scsi/iscsi_if.h uint32_t pid; /* unique ping id associated uint32_t 293 include/scsi/iscsi_if.h uint32_t data_size; uint32_t 296 include/scsi/iscsi_if.h uint32_t flashnode_idx; uint32_t 312 include/scsi/iscsi_if.h uint32_t len; /* Actual length of the param value */ uint32_t 318 include/scsi/iscsi_if.h uint32_t iface_num; /* iface number, 0 - n */ uint32_t 319 include/scsi/iscsi_if.h uint32_t len; /* Actual length of the param */ uint32_t 336 include/scsi/iscsi_if.h uint32_t ip_addr_len; /* 4 or 16 */ uint32_t 698 include/scsi/iscsi_if.h uint32_t len; /* Actual length of the param */ uint32_t 788 include/scsi/iscsi_if.h uint32_t noptx_pdus; uint32_t 789 include/scsi/iscsi_if.h uint32_t scsicmd_pdus; uint32_t 790 include/scsi/iscsi_if.h uint32_t tmfcmd_pdus; uint32_t 791 include/scsi/iscsi_if.h uint32_t login_pdus; uint32_t 792 include/scsi/iscsi_if.h uint32_t text_pdus; uint32_t 793 include/scsi/iscsi_if.h uint32_t dataout_pdus; uint32_t 794 include/scsi/iscsi_if.h uint32_t logout_pdus; uint32_t 795 include/scsi/iscsi_if.h uint32_t snack_pdus; uint32_t 798 include/scsi/iscsi_if.h uint32_t noprx_pdus; uint32_t 799 include/scsi/iscsi_if.h uint32_t scsirsp_pdus; uint32_t 800 include/scsi/iscsi_if.h uint32_t tmfrsp_pdus; uint32_t 801 include/scsi/iscsi_if.h uint32_t textrsp_pdus; uint32_t 802 include/scsi/iscsi_if.h uint32_t datain_pdus; uint32_t 803 include/scsi/iscsi_if.h uint32_t logoutrsp_pdus; uint32_t 804 include/scsi/iscsi_if.h uint32_t r2t_pdus; uint32_t 805 include/scsi/iscsi_if.h uint32_t async_pdus; uint32_t 806 include/scsi/iscsi_if.h uint32_t rjt_pdus; uint32_t 809 include/scsi/iscsi_if.h uint32_t digest_err; uint32_t 810 include/scsi/iscsi_if.h uint32_t timeout_err; uint32_t 817 include/scsi/iscsi_if.h uint32_t custom_length; uint32_t 948 include/scsi/iscsi_if.h uint32_t custom_length; uint32_t 66 include/scsi/iscsi_proto.h typedef uint32_t __bitwise itt_t; uint32_t 70 include/scsi/iscsi_proto.h #define get_itt(itt) ((__force uint32_t)(itt_t)(itt) & ISCSI_ITT_MASK) uint32_t 88 include/scsi/libiscsi.h uint32_t data_length; /* copied from R2T */ uint32_t 89 include/scsi/libiscsi.h uint32_t data_offset; /* copied from R2T */ uint32_t 169 include/scsi/libiscsi.h uint32_t exp_statsn; uint32_t 170 include/scsi/libiscsi.h uint32_t statsn; uint32_t 232 include/scsi/libiscsi.h uint32_t scsicmd_pdus_cnt; uint32_t 233 include/scsi/libiscsi.h uint32_t dataout_pdus_cnt; uint32_t 234 include/scsi/libiscsi.h uint32_t scsirsp_pdus_cnt; uint32_t 235 include/scsi/libiscsi.h uint32_t datain_pdus_cnt; uint32_t 236 include/scsi/libiscsi.h uint32_t r2t_pdus_cnt; uint32_t 237 include/scsi/libiscsi.h uint32_t tmfcmd_pdus_cnt; uint32_t 241 include/scsi/libiscsi.h uint32_t eh_abort_cnt; uint32_t 242 include/scsi/libiscsi.h uint32_t fmr_unalign_cnt; uint32_t 272 include/scsi/libiscsi.h uint32_t cmdsn; uint32_t 273 include/scsi/libiscsi.h uint32_t exp_cmdsn; uint32_t 274 include/scsi/libiscsi.h uint32_t max_cmdsn; uint32_t 277 include/scsi/libiscsi.h uint32_t queued_cmdsn; uint32_t 401 include/scsi/libiscsi.h uint16_t, int, int, uint32_t, unsigned int); uint32_t 416 include/scsi/libiscsi.h int, uint32_t); uint32_t 445 include/scsi/libiscsi.h char *, uint32_t); uint32_t 458 include/scsi/libiscsi.h uint32_t exp_cmdsn, uint32_t max_cmdsn); uint32_t 50 include/scsi/libiscsi_tcp.h uint32_t hdr_buf[64]; uint32_t 69 include/scsi/libiscsi_tcp.h uint32_t exp_datasn; /* expected target's R2TSN/DataSN */ uint32_t 117 include/scsi/libiscsi_tcp.h uint32_t conn_idx); uint32_t 55 include/scsi/scsi_bsg_iscsi.h uint32_t vendor_cmd[0]; uint32_t 62 include/scsi/scsi_bsg_iscsi.h uint32_t vendor_rsp[0]; uint32_t 68 include/scsi/scsi_bsg_iscsi.h uint32_t msgcode; uint32_t 85 include/scsi/scsi_bsg_iscsi.h uint32_t result; uint32_t 88 include/scsi/scsi_bsg_iscsi.h uint32_t reply_payload_rcv_len; uint32_t 81 include/scsi/scsi_transport_iscsi.h uint32_t sn); uint32_t 84 include/scsi/scsi_transport_iscsi.h uint32_t cid); uint32_t 105 include/scsi/scsi_transport_iscsi.h char *data, uint32_t data_size); uint32_t 127 include/scsi/scsi_transport_iscsi.h uint32_t enable, struct sockaddr *dst_addr); uint32_t 130 include/scsi/scsi_transport_iscsi.h uint32_t len); uint32_t 136 include/scsi/scsi_transport_iscsi.h int (*send_ping) (struct Scsi_Host *shost, uint32_t iface_num, uint32_t 137 include/scsi/scsi_transport_iscsi.h uint32_t iface_type, uint32_t payload_size, uint32_t 138 include/scsi/scsi_transport_iscsi.h uint32_t pid, struct sockaddr *dst_addr); uint32_t 140 include/scsi/scsi_transport_iscsi.h uint32_t *num_entries, char *buf); uint32_t 174 include/scsi/scsi_transport_iscsi.h char *data, uint32_t data_size); uint32_t 177 include/scsi/scsi_transport_iscsi.h struct iscsi_transport *transport, uint32_t type, uint32_t 180 include/scsi/scsi_transport_iscsi.h extern void iscsi_post_host_event(uint32_t host_no, uint32_t 183 include/scsi/scsi_transport_iscsi.h uint32_t data_size, uint32_t 186 include/scsi/scsi_transport_iscsi.h extern void iscsi_ping_comp_event(uint32_t host_no, uint32_t 188 include/scsi/scsi_transport_iscsi.h uint32_t status, uint32_t pid, uint32_t 189 include/scsi/scsi_transport_iscsi.h uint32_t data_size, uint8_t *data); uint32_t 195 include/scsi/scsi_transport_iscsi.h uint32_t cid; /* connection id */ uint32_t 264 include/scsi/scsi_transport_iscsi.h uint32_t port_speed; uint32_t 265 include/scsi/scsi_transport_iscsi.h uint32_t port_state; uint32_t 284 include/scsi/scsi_transport_iscsi.h uint32_t iface_type; /* IPv4 or IPv6 */ uint32_t 285 include/scsi/scsi_transport_iscsi.h uint32_t iface_num; /* iface number, 0 - n */ uint32_t 302 include/scsi/scsi_transport_iscsi.h uint32_t exp_statsn; uint32_t 303 include/scsi/scsi_transport_iscsi.h uint32_t statsn; uint32_t 425 include/scsi/scsi_transport_iscsi.h int dd_size, uint32_t cid); uint32_t 436 include/scsi/scsi_transport_iscsi.h uint32_t iface_type, uint32_t 437 include/scsi/scsi_transport_iscsi.h uint32_t iface_num, int dd_size); uint32_t 75 include/soc/tegra/bpmp-abi.h uint32_t mrq; uint32_t 84 include/soc/tegra/bpmp-abi.h uint32_t flags; uint32_t 100 include/soc/tegra/bpmp-abi.h uint32_t flags; uint32_t 225 include/soc/tegra/bpmp-abi.h uint32_t challenge; uint32_t 239 include/soc/tegra/bpmp-abi.h uint32_t reply; uint32_t 266 include/soc/tegra/bpmp-abi.h uint32_t addr; uint32_t 331 include/soc/tegra/bpmp-abi.h uint32_t phys_addr; /* (void *) */ uint32_t 333 include/soc/tegra/bpmp-abi.h uint32_t size; uint32_t 344 include/soc/tegra/bpmp-abi.h uint32_t base; uint32_t 372 include/soc/tegra/bpmp-abi.h uint32_t base; uint32_t 400 include/soc/tegra/bpmp-abi.h uint32_t clr; uint32_t 402 include/soc/tegra/bpmp-abi.h uint32_t set; uint32_t 416 include/soc/tegra/bpmp-abi.h uint32_t mask; uint32_t 454 include/soc/tegra/bpmp-abi.h uint32_t area; uint32_t 456 include/soc/tegra/bpmp-abi.h uint32_t size; uint32_t 473 include/soc/tegra/bpmp-abi.h uint32_t eof; uint32_t 478 include/soc/tegra/bpmp-abi.h uint32_t challenge; uint32_t 483 include/soc/tegra/bpmp-abi.h uint32_t reply; uint32_t 507 include/soc/tegra/bpmp-abi.h uint32_t base; uint32_t 583 include/soc/tegra/bpmp-abi.h uint32_t fnameaddr; uint32_t 585 include/soc/tegra/bpmp-abi.h uint32_t fnamelen; uint32_t 587 include/soc/tegra/bpmp-abi.h uint32_t dataaddr; uint32_t 589 include/soc/tegra/bpmp-abi.h uint32_t datalen; uint32_t 598 include/soc/tegra/bpmp-abi.h uint32_t dataaddr; uint32_t 600 include/soc/tegra/bpmp-abi.h uint32_t datalen; uint32_t 609 include/soc/tegra/bpmp-abi.h uint32_t reserved; uint32_t 611 include/soc/tegra/bpmp-abi.h uint32_t nbytes; uint32_t 620 include/soc/tegra/bpmp-abi.h uint32_t reserved; uint32_t 622 include/soc/tegra/bpmp-abi.h uint32_t nbytes; uint32_t 642 include/soc/tegra/bpmp-abi.h uint32_t cmd; uint32_t 710 include/soc/tegra/bpmp-abi.h uint32_t cmd; uint32_t 712 include/soc/tegra/bpmp-abi.h uint32_t reset_id; uint32_t 722 include/soc/tegra/bpmp-abi.h uint32_t max_id; uint32_t 808 include/soc/tegra/bpmp-abi.h uint32_t bus_id; uint32_t 811 include/soc/tegra/bpmp-abi.h uint32_t data_size; uint32_t 826 include/soc/tegra/bpmp-abi.h uint32_t data_size; uint32_t 836 include/soc/tegra/bpmp-abi.h uint32_t cmd; uint32_t 919 include/soc/tegra/bpmp-abi.h uint32_t parent_id; uint32_t 923 include/soc/tegra/bpmp-abi.h uint32_t parent_id; uint32_t 927 include/soc/tegra/bpmp-abi.h uint32_t parent_id; uint32_t 965 include/soc/tegra/bpmp-abi.h uint32_t flags; uint32_t 966 include/soc/tegra/bpmp-abi.h uint32_t parent; uint32_t 967 include/soc/tegra/bpmp-abi.h uint32_t parents[MRQ_CLK_MAX_PARENTS]; uint32_t 978 include/soc/tegra/bpmp-abi.h uint32_t max_id; uint32_t 1021 include/soc/tegra/bpmp-abi.h uint32_t cmd_and_id; uint32_t 1111 include/soc/tegra/bpmp-abi.h uint32_t mrq; uint32_t 1148 include/soc/tegra/bpmp-abi.h uint32_t partition_id; uint32_t 1158 include/soc/tegra/bpmp-abi.h uint32_t sram_state; uint32_t 1163 include/soc/tegra/bpmp-abi.h uint32_t logic_state; uint32_t 1192 include/soc/tegra/bpmp-abi.h uint32_t partition_id; uint32_t 1200 include/soc/tegra/bpmp-abi.h uint32_t sram_state; uint32_t 1205 include/soc/tegra/bpmp-abi.h uint32_t logic_state; uint32_t 1213 include/soc/tegra/bpmp-abi.h uint32_t clock_state; uint32_t 1309 include/soc/tegra/bpmp-abi.h uint32_t type; uint32_t 1314 include/soc/tegra/bpmp-abi.h uint32_t state; uint32_t 1319 include/soc/tegra/bpmp-abi.h uint32_t state; uint32_t 1327 include/soc/tegra/bpmp-abi.h uint32_t max_id; uint32_t 1348 include/soc/tegra/bpmp-abi.h uint32_t cmd; uint32_t 1349 include/soc/tegra/bpmp-abi.h uint32_t id; uint32_t 1495 include/soc/tegra/bpmp-abi.h uint32_t type; uint32_t 1504 include/soc/tegra/bpmp-abi.h uint32_t zone; uint32_t 1529 include/soc/tegra/bpmp-abi.h uint32_t zone; uint32_t 1532 include/soc/tegra/bpmp-abi.h uint32_t enabled; uint32_t 1541 include/soc/tegra/bpmp-abi.h uint32_t zone; uint32_t 1551 include/soc/tegra/bpmp-abi.h uint32_t num; uint32_t 1563 include/soc/tegra/bpmp-abi.h uint32_t type; uint32_t 1578 include/soc/tegra/bpmp-abi.h uint32_t type; uint32_t 1619 include/soc/tegra/bpmp-abi.h uint32_t addr; uint32_t 1621 include/soc/tegra/bpmp-abi.h uint32_t cluster_id; uint32_t 1631 include/soc/tegra/bpmp-abi.h uint32_t ref_clk_hz; /**< reference frequency in Hz */ uint32_t 1739 include/soc/tegra/bpmp-abi.h uint32_t freq; uint32_t 1741 include/soc/tegra/bpmp-abi.h uint32_t latency; uint32_t 1750 include/soc/tegra/bpmp-abi.h uint32_t num_pairs; uint32_t 1777 include/soc/tegra/bpmp-abi.h uint32_t cluster_id; uint32_t 1785 include/soc/tegra/bpmp-abi.h uint32_t ref_clk_hz; uint32_t 1825 include/soc/tegra/bpmp-abi.h uint32_t cluster_id; uint32_t 1839 include/soc/tegra/bpmp-abi.h uint32_t auto_cc3_config; uint32_t 1870 include/soc/tegra/bpmp-abi.h uint32_t cmd; uint32_t 1946 include/soc/tegra/bpmp-abi.h uint32_t cmd; uint32_t 1993 include/soc/tegra/bpmp-abi.h uint32_t space_avail; uint32_t 2015 include/soc/tegra/bpmp-abi.h uint32_t bpmp_tx_buf_len; uint32_t 2029 include/soc/tegra/bpmp-abi.h uint32_t type; uint32_t 2089 include/soc/tegra/bpmp-abi.h uint32_t cmd; uint32_t 2091 include/soc/tegra/bpmp-abi.h uint32_t id; uint32_t 2093 include/soc/tegra/bpmp-abi.h uint32_t value; uint32_t 2131 include/soc/tegra/bpmp-abi.h uint32_t x; uint32_t 2133 include/soc/tegra/bpmp-abi.h uint32_t y; uint32_t 2135 include/soc/tegra/bpmp-abi.h uint32_t nblks; uint32_t 2140 include/soc/tegra/bpmp-abi.h uint32_t status; uint32_t 2302 include/soc/tegra/bpmp-abi.h uint32_t cmd_and_id; uint32_t 2489 include/soc/tegra/bpmp-abi.h uint32_t fmon_faults; uint32_t 2505 include/soc/tegra/bpmp-abi.h uint32_t vmon_faults; uint32_t 2554 include/soc/tegra/bpmp-abi.h uint32_t ec_hsm_id; uint32_t 2562 include/soc/tegra/bpmp-abi.h uint32_t ec_hsm_id; uint32_t 2568 include/soc/tegra/bpmp-abi.h uint32_t ec_status_flags; uint32_t 2570 include/soc/tegra/bpmp-abi.h uint32_t error_idx; uint32_t 2572 include/soc/tegra/bpmp-abi.h uint32_t error_type; uint32_t 2574 include/soc/tegra/bpmp-abi.h uint32_t error_desc_num; uint32_t 2594 include/soc/tegra/bpmp-abi.h uint32_t cmd_id; uint32_t 2647 include/soc/tegra/bpmp-abi.h uint32_t ready; uint32_t 2649 include/soc/tegra/bpmp-abi.h uint32_t unused; uint32_t 84 include/sound/sof/control.h uint32_t channel; /**< channel map - enum sof_ipc_chmap */ uint32_t 85 include/sound/sof/control.h uint32_t value; uint32_t 90 include/sound/sof/control.h uint32_t index; /**< component source/sink/control index in control */ uint32_t 92 include/sound/sof/control.h uint32_t uvalue; uint32_t 100 include/sound/sof/control.h uint32_t comp_id; uint32_t 103 include/sound/sof/control.h uint32_t type; /**< enum sof_ipc_ctrl_type */ uint32_t 104 include/sound/sof/control.h uint32_t cmd; /**< enum sof_ipc_ctrl_cmd */ uint32_t 105 include/sound/sof/control.h uint32_t index; /**< control index for comps > 1 control */ uint32_t 109 include/sound/sof/control.h uint32_t num_elems; /**< in array elems or bytes for data type */ uint32_t 110 include/sound/sof/control.h uint32_t elems_remaining; /**< elems remaining if sent in parts */ uint32_t 112 include/sound/sof/control.h uint32_t msg_index; /**< for large messages sent in parts */ uint32_t 115 include/sound/sof/control.h uint32_t reserved[6]; uint32_t 142 include/sound/sof/control.h uint32_t src_comp_id; /**< source component id */ uint32_t 143 include/sound/sof/control.h uint32_t event_type; /**< event type - SOF_CTRL_EVENT_* */ uint32_t 144 include/sound/sof/control.h uint32_t num_elems; /**< in array elems or bytes for data type */ uint32_t 147 include/sound/sof/control.h uint32_t reserved[8]; uint32_t 154 include/sound/sof/control.h uint32_t event_value; uint32_t 58 include/sound/sof/dai-intel.h uint32_t mclk_rate; /* mclk frequency in Hz */ uint32_t 59 include/sound/sof/dai-intel.h uint32_t fsync_rate; /* fsync frequency in Hz */ uint32_t 60 include/sound/sof/dai-intel.h uint32_t bclk_rate; /* bclk frequency in Hz */ uint32_t 63 include/sound/sof/dai-intel.h uint32_t tdm_slots; uint32_t 64 include/sound/sof/dai-intel.h uint32_t rx_slots; uint32_t 65 include/sound/sof/dai-intel.h uint32_t tx_slots; uint32_t 68 include/sound/sof/dai-intel.h uint32_t sample_valid_bits; uint32_t 73 include/sound/sof/dai-intel.h uint32_t mclk_direction; uint32_t 77 include/sound/sof/dai-intel.h uint32_t clks_control; uint32_t 78 include/sound/sof/dai-intel.h uint32_t quirks; uint32_t 79 include/sound/sof/dai-intel.h uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK uint32_t 87 include/sound/sof/dai-intel.h uint32_t link_dma_ch; uint32_t 156 include/sound/sof/dai-intel.h uint32_t driver_ipc_version; /**< Version (1..N) */ uint32_t 158 include/sound/sof/dai-intel.h uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */ uint32_t 159 include/sound/sof/dai-intel.h uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */ uint32_t 161 include/sound/sof/dai-intel.h uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */ uint32_t 162 include/sound/sof/dai-intel.h uint32_t reserved_1; /**< Reserved */ uint32_t 169 include/sound/sof/dai-intel.h uint32_t num_pdm_active; /**< Number of active pdm controllers */ uint32_t 171 include/sound/sof/dai-intel.h uint32_t wake_up_time; /**< Time from clock start to data (us) */ uint32_t 172 include/sound/sof/dai-intel.h uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */ uint32_t 173 include/sound/sof/dai-intel.h uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */ uint32_t 176 include/sound/sof/dai-intel.h uint32_t reserved[5]; uint32_t 185 include/sound/sof/dai-intel.h uint32_t stream_id; uint32_t 188 include/sound/sof/dai-intel.h uint32_t reserved[15]; uint32_t 60 include/sound/sof/dai.h uint32_t type; /**< DAI type - enum sof_ipc_dai_type */ uint32_t 61 include/sound/sof/dai.h uint32_t dai_index; /**< index of this type dai */ uint32_t 68 include/sound/sof/dai.h uint32_t reserved[8]; uint32_t 125 include/sound/sof/header.h uint32_t size; /**< size of structure */ uint32_t 136 include/sound/sof/header.h uint32_t size; /**< size of structure */ uint32_t 137 include/sound/sof/header.h uint32_t cmd; /**< SOF_IPC_GLB_ + cmd */ uint32_t 160 include/sound/sof/header.h uint32_t count; /**< count of 0 means end of compound sequence */ uint32_t 167 include/sound/sof/header.h uint32_t arch; /* Identifier of architecture */ uint32_t 168 include/sound/sof/header.h uint32_t totalsize; /* Total size of oops message */ uint32_t 175 include/sound/sof/header.h uint32_t configidhi; /* ConfigID hi 32bits */ uint32_t 176 include/sound/sof/header.h uint32_t configidlo; /* ConfigID lo 32bits */ uint32_t 177 include/sound/sof/header.h uint32_t numaregs; /* Special regs num */ uint32_t 178 include/sound/sof/header.h uint32_t stackoffset; /* Offset to stack pointer from beginning of uint32_t 181 include/sound/sof/header.h uint32_t stackptr; /* Stack ptr */ uint32_t 45 include/sound/sof/info.h uint32_t abi_version; uint32_t 48 include/sound/sof/info.h uint32_t reserved[4]; uint32_t 54 include/sound/sof/info.h uint32_t dspbox_offset; /* dsp initiated IPC mailbox */ uint32_t 55 include/sound/sof/info.h uint32_t hostbox_offset; /* host initiated IPC mailbox */ uint32_t 56 include/sound/sof/info.h uint32_t dspbox_size; uint32_t 57 include/sound/sof/info.h uint32_t hostbox_size; uint32_t 64 include/sound/sof/info.h uint32_t reserved[4]; uint32_t 82 include/sound/sof/info.h uint32_t type; /**< SOF_IPC_EXT_ */ uint32_t 87 include/sound/sof/info.h uint32_t type; /**< SOF_IPC_REGION_ */ uint32_t 88 include/sound/sof/info.h uint32_t id; /**< platform specific - used to map to host memory */ uint32_t 95 include/sound/sof/info.h uint32_t num_buffers; uint32_t 103 include/sound/sof/info.h uint32_t type; /**< SOF_IPC_REGION_ */ uint32_t 104 include/sound/sof/info.h uint32_t id; /**< platform specific - used to map to host memory */ uint32_t 105 include/sound/sof/info.h uint32_t flags; /**< R, W, RW, etc - to define */ uint32_t 106 include/sound/sof/info.h uint32_t size; /**< size of region in bytes */ uint32_t 108 include/sound/sof/info.h uint32_t offset; uint32_t 114 include/sound/sof/info.h uint32_t num_windows; uint32_t 21 include/sound/sof/pm.h uint32_t type; uint32_t 22 include/sound/sof/pm.h uint32_t size; uint32_t 33 include/sound/sof/pm.h uint32_t num_elems; uint32_t 34 include/sound/sof/pm.h uint32_t size; uint32_t 37 include/sound/sof/pm.h uint32_t reserved[8]; uint32_t 45 include/sound/sof/pm.h uint32_t enable_mask; uint32_t 68 include/sound/sof/stream.h uint32_t phy_addr; uint32_t 69 include/sound/sof/stream.h uint32_t pages; uint32_t 70 include/sound/sof/stream.h uint32_t size; uint32_t 71 include/sound/sof/stream.h uint32_t reserved[3]; uint32_t 77 include/sound/sof/stream.h uint32_t direction; /**< enum sof_ipc_stream_direction */ uint32_t 78 include/sound/sof/stream.h uint32_t frame_fmt; /**< enum sof_ipc_frame */ uint32_t 79 include/sound/sof/stream.h uint32_t buffer_fmt; /**< enum sof_ipc_buffer_format */ uint32_t 80 include/sound/sof/stream.h uint32_t rate; uint32_t 87 include/sound/sof/stream.h uint32_t host_period_bytes; uint32_t 89 include/sound/sof/stream.h uint32_t reserved[2]; uint32_t 96 include/sound/sof/stream.h uint32_t comp_id; uint32_t 97 include/sound/sof/stream.h uint32_t flags; /**< generic PCM flags - SOF_PCM_FLAG_ */ uint32_t 98 include/sound/sof/stream.h uint32_t reserved[2]; uint32_t 105 include/sound/sof/stream.h uint32_t comp_id; uint32_t 106 include/sound/sof/stream.h uint32_t posn_offset; uint32_t 112 include/sound/sof/stream.h uint32_t comp_id; uint32_t 135 include/sound/sof/stream.h uint32_t comp_id; /**< host component ID */ uint32_t 136 include/sound/sof/stream.h uint32_t flags; /**< SOF_TIME_ */ uint32_t 137 include/sound/sof/stream.h uint32_t wallclock_hz; /**< frequency of wallclock in Hz */ uint32_t 138 include/sound/sof/stream.h uint32_t timestamp_ns; /**< resolution of timestamp in ns */ uint32_t 144 include/sound/sof/stream.h uint32_t xrun_comp_id; /**< comp ID of XRUN component */ uint32_t 52 include/sound/sof/topology.h uint32_t id; uint32_t 54 include/sound/sof/topology.h uint32_t pipeline_id; uint32_t 57 include/sound/sof/topology.h uint32_t reserved[2]; uint32_t 79 include/sound/sof/topology.h uint32_t size; /**< buffer size in bytes */ uint32_t 80 include/sound/sof/topology.h uint32_t caps; /**< SOF_MEM_CAPS_ */ uint32_t 86 include/sound/sof/topology.h uint32_t periods_sink; /**< 0 means variable */ uint32_t 87 include/sound/sof/topology.h uint32_t periods_source;/**< 0 means variable */ uint32_t 88 include/sound/sof/topology.h uint32_t reserved1; /**< reserved */ uint32_t 89 include/sound/sof/topology.h uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */ uint32_t 90 include/sound/sof/topology.h uint32_t xrun_action; uint32_t 93 include/sound/sof/topology.h uint32_t reserved[2]; uint32_t 100 include/sound/sof/topology.h uint32_t direction; /**< SOF_IPC_STREAM_ */ uint32_t 101 include/sound/sof/topology.h uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */ uint32_t 102 include/sound/sof/topology.h uint32_t dmac_config; /**< DMA engine specific */ uint32_t 109 include/sound/sof/topology.h uint32_t direction; /**< SOF_IPC_STREAM_ */ uint32_t 110 include/sound/sof/topology.h uint32_t dai_index; /**< index of this type dai */ uint32_t 111 include/sound/sof/topology.h uint32_t type; /**< DAI type - SOF_DAI_ */ uint32_t 112 include/sound/sof/topology.h uint32_t reserved; /**< reserved */ uint32_t 133 include/sound/sof/topology.h uint32_t channels; uint32_t 134 include/sound/sof/topology.h uint32_t min_value; uint32_t 135 include/sound/sof/topology.h uint32_t max_value; uint32_t 136 include/sound/sof/topology.h uint32_t ramp; /**< SOF_VOLUME_ */ uint32_t 137 include/sound/sof/topology.h uint32_t initial_ramp; /**< ramp space in ms */ uint32_t 145 include/sound/sof/topology.h uint32_t source_rate; /**< source rate or 0 for variable */ uint32_t 146 include/sound/sof/topology.h uint32_t sink_rate; /**< sink rate or 0 for variable */ uint32_t 147 include/sound/sof/topology.h uint32_t rate_mask; /**< SOF_RATE_ supported rates */ uint32_t 187 include/sound/sof/topology.h uint32_t size; /**< size of bespoke data section in bytes */ uint32_t 188 include/sound/sof/topology.h uint32_t type; /**< sof_ipc_process_type */ uint32_t 191 include/sound/sof/topology.h uint32_t reserved[7]; uint32_t 201 include/sound/sof/topology.h uint32_t id; uint32_t 206 include/sound/sof/topology.h uint32_t id; uint32_t 207 include/sound/sof/topology.h uint32_t offset; uint32_t 223 include/sound/sof/topology.h uint32_t comp_id; /**< component id for pipeline */ uint32_t 224 include/sound/sof/topology.h uint32_t pipeline_id; /**< pipeline id */ uint32_t 225 include/sound/sof/topology.h uint32_t sched_id; /**< Scheduling component id */ uint32_t 226 include/sound/sof/topology.h uint32_t core; /**< core we run on */ uint32_t 227 include/sound/sof/topology.h uint32_t period; /**< execution period in us*/ uint32_t 228 include/sound/sof/topology.h uint32_t priority; /**< priority level 0 (low) to 10 (max) */ uint32_t 229 include/sound/sof/topology.h uint32_t period_mips; /**< worst case instruction count per period */ uint32_t 230 include/sound/sof/topology.h uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */ uint32_t 231 include/sound/sof/topology.h uint32_t xrun_limit_usecs; /**< report xruns greater than limit */ uint32_t 232 include/sound/sof/topology.h uint32_t time_domain; /**< scheduling time domain */ uint32_t 238 include/sound/sof/topology.h uint32_t comp_id; uint32_t 243 include/sound/sof/topology.h uint32_t comp_id; uint32_t 249 include/sound/sof/topology.h uint32_t source_id; uint32_t 250 include/sound/sof/topology.h uint32_t sink_id; uint32_t 26 include/sound/sof/trace.h uint32_t stream_tag; uint32_t 33 include/sound/sof/trace.h uint32_t stream_tag; uint32_t 35 include/sound/sof/trace.h uint32_t reserved[8]; uint32_t 41 include/sound/sof/trace.h uint32_t host_offset; /* Offset of DMA host buffer */ uint32_t 42 include/sound/sof/trace.h uint32_t overflow; /* overflow bytes if any */ uint32_t 43 include/sound/sof/trace.h uint32_t messages; /* total trace messages */ uint32_t 74 include/sound/sof/trace.h uint32_t code; /* SOF_IPC_PANIC_ */ uint32_t 76 include/sound/sof/trace.h uint32_t linenum; uint32_t 22 include/sound/sof/xtensa.h uint32_t exccause; uint32_t 23 include/sound/sof/xtensa.h uint32_t excvaddr; uint32_t 24 include/sound/sof/xtensa.h uint32_t ps; uint32_t 25 include/sound/sof/xtensa.h uint32_t epc1; uint32_t 26 include/sound/sof/xtensa.h uint32_t epc2; uint32_t 27 include/sound/sof/xtensa.h uint32_t epc3; uint32_t 28 include/sound/sof/xtensa.h uint32_t epc4; uint32_t 29 include/sound/sof/xtensa.h uint32_t epc5; uint32_t 30 include/sound/sof/xtensa.h uint32_t epc6; uint32_t 31 include/sound/sof/xtensa.h uint32_t epc7; uint32_t 32 include/sound/sof/xtensa.h uint32_t eps2; uint32_t 33 include/sound/sof/xtensa.h uint32_t eps3; uint32_t 34 include/sound/sof/xtensa.h uint32_t eps4; uint32_t 35 include/sound/sof/xtensa.h uint32_t eps5; uint32_t 36 include/sound/sof/xtensa.h uint32_t eps6; uint32_t 37 include/sound/sof/xtensa.h uint32_t eps7; uint32_t 38 include/sound/sof/xtensa.h uint32_t depc; uint32_t 39 include/sound/sof/xtensa.h uint32_t intenable; uint32_t 40 include/sound/sof/xtensa.h uint32_t interrupt; uint32_t 41 include/sound/sof/xtensa.h uint32_t sar; uint32_t 42 include/sound/sof/xtensa.h uint32_t debugcause; uint32_t 43 include/sound/sof/xtensa.h uint32_t windowbase; uint32_t 44 include/sound/sof/xtensa.h uint32_t windowstart; uint32_t 45 include/sound/sof/xtensa.h uint32_t excsave1; uint32_t 46 include/sound/sof/xtensa.h uint32_t ar[]; uint32_t 120 include/target/target_core_backend.h static inline uint32_t get_unaligned_be24(const uint8_t *const p) uint32_t 13 include/trace/events/fsi.h uint32_t addr, size_t size), uint32_t 40 include/trace/events/fsi.h uint32_t addr, size_t size, const void *data), uint32_t 71 include/trace/events/fsi.h uint32_t addr, size_t size, uint32_t 11 include/trace/events/fsi_master_ast_cf.h TP_PROTO(const struct fsi_master_acf *master, uint32_t op), uint32_t 15 include/trace/events/fsi_master_ast_cf.h __field(uint32_t, op) uint32_t 23 include/trace/events/hswadsp.h TP_PROTO(uint32_t status, uint32_t mask), uint32_t 251 include/trace/events/hswadsp.h __field( uint32_t, id ) uint32_t 252 include/trace/events/hswadsp.h __field( uint32_t, frequency ) uint32_t 253 include/trace/events/hswadsp.h __field( uint32_t, bitdepth ) uint32_t 254 include/trace/events/hswadsp.h __field( uint32_t, map ) uint32_t 255 include/trace/events/hswadsp.h __field( uint32_t, config ) uint32_t 256 include/trace/events/hswadsp.h __field( uint32_t, style ) uint32_t 273 include/trace/events/hswadsp.h (int) __entry->id, (uint32_t)__entry->frequency, uint32_t 274 include/trace/events/hswadsp.h (uint32_t)__entry->bitdepth, (uint32_t)__entry->map, uint32_t 275 include/trace/events/hswadsp.h (uint32_t)__entry->config, (uint32_t)__entry->style, uint32_t 287 include/trace/events/hswadsp.h __field( uint32_t, id ) uint32_t 335 include/trace/events/hswadsp.h __field( uint32_t, channel ) uint32_t 336 include/trace/events/hswadsp.h __field( uint32_t, target_volume ) uint32_t 338 include/trace/events/hswadsp.h __field( uint32_t, curve_type ) uint32_t 350 include/trace/events/hswadsp.h (int) __entry->id, (uint32_t) __entry->channel, uint32_t 351 include/trace/events/hswadsp.h (uint32_t)__entry->target_volume, uint32_t 353 include/trace/events/hswadsp.h (uint32_t)__entry->curve_type) uint32_t 363 include/trace/events/hswadsp.h __field( uint32_t, ssp ) uint32_t 364 include/trace/events/hswadsp.h __field( uint32_t, clock_freq ) uint32_t 365 include/trace/events/hswadsp.h __field( uint32_t, mode ) uint32_t 377 include/trace/events/hswadsp.h (uint32_t)__entry->ssp, uint32_t 378 include/trace/events/hswadsp.h (uint32_t)__entry->clock_freq, (uint32_t)__entry->mode, uint32_t 379 include/trace/events/hswadsp.h (uint32_t)__entry->clock_divider) uint32_t 61 include/uapi/drm/drm.h typedef uint32_t __u32; uint32_t 1152 include/uapi/drm/vmwgfx_drm.h uint32_t svga3d_flags_upper_32_bits; uint32_t 225 include/uapi/linux/fuse.h uint32_t atimensec; uint32_t 226 include/uapi/linux/fuse.h uint32_t mtimensec; uint32_t 227 include/uapi/linux/fuse.h uint32_t ctimensec; uint32_t 228 include/uapi/linux/fuse.h uint32_t mode; uint32_t 229 include/uapi/linux/fuse.h uint32_t nlink; uint32_t 230 include/uapi/linux/fuse.h uint32_t uid; uint32_t 231 include/uapi/linux/fuse.h uint32_t gid; uint32_t 232 include/uapi/linux/fuse.h uint32_t rdev; uint32_t 233 include/uapi/linux/fuse.h uint32_t blksize; uint32_t 234 include/uapi/linux/fuse.h uint32_t padding; uint32_t 243 include/uapi/linux/fuse.h uint32_t bsize; uint32_t 244 include/uapi/linux/fuse.h uint32_t namelen; uint32_t 245 include/uapi/linux/fuse.h uint32_t frsize; uint32_t 246 include/uapi/linux/fuse.h uint32_t padding; uint32_t 247 include/uapi/linux/fuse.h uint32_t spare[6]; uint32_t 253 include/uapi/linux/fuse.h uint32_t type; uint32_t 254 include/uapi/linux/fuse.h uint32_t pid; /* tgid */ uint32_t 498 include/uapi/linux/fuse.h uint32_t entry_valid_nsec; uint32_t 499 include/uapi/linux/fuse.h uint32_t attr_valid_nsec; uint32_t 513 include/uapi/linux/fuse.h uint32_t count; uint32_t 514 include/uapi/linux/fuse.h uint32_t dummy; uint32_t 518 include/uapi/linux/fuse.h uint32_t getattr_flags; uint32_t 519 include/uapi/linux/fuse.h uint32_t dummy; uint32_t 527 include/uapi/linux/fuse.h uint32_t attr_valid_nsec; uint32_t 528 include/uapi/linux/fuse.h uint32_t dummy; uint32_t 535 include/uapi/linux/fuse.h uint32_t mode; uint32_t 536 include/uapi/linux/fuse.h uint32_t rdev; uint32_t 537 include/uapi/linux/fuse.h uint32_t umask; uint32_t 538 include/uapi/linux/fuse.h uint32_t padding; uint32_t 542 include/uapi/linux/fuse.h uint32_t mode; uint32_t 543 include/uapi/linux/fuse.h uint32_t umask; uint32_t 552 include/uapi/linux/fuse.h uint32_t flags; uint32_t 553 include/uapi/linux/fuse.h uint32_t padding; uint32_t 561 include/uapi/linux/fuse.h uint32_t valid; uint32_t 562 include/uapi/linux/fuse.h uint32_t padding; uint32_t 569 include/uapi/linux/fuse.h uint32_t atimensec; uint32_t 570 include/uapi/linux/fuse.h uint32_t mtimensec; uint32_t 571 include/uapi/linux/fuse.h uint32_t ctimensec; uint32_t 572 include/uapi/linux/fuse.h uint32_t mode; uint32_t 573 include/uapi/linux/fuse.h uint32_t unused4; uint32_t 574 include/uapi/linux/fuse.h uint32_t uid; uint32_t 575 include/uapi/linux/fuse.h uint32_t gid; uint32_t 576 include/uapi/linux/fuse.h uint32_t unused5; uint32_t 580 include/uapi/linux/fuse.h uint32_t flags; uint32_t 581 include/uapi/linux/fuse.h uint32_t unused; uint32_t 585 include/uapi/linux/fuse.h uint32_t flags; uint32_t 586 include/uapi/linux/fuse.h uint32_t mode; uint32_t 587 include/uapi/linux/fuse.h uint32_t umask; uint32_t 588 include/uapi/linux/fuse.h uint32_t padding; uint32_t 593 include/uapi/linux/fuse.h uint32_t open_flags; uint32_t 594 include/uapi/linux/fuse.h uint32_t padding; uint32_t 599 include/uapi/linux/fuse.h uint32_t flags; uint32_t 600 include/uapi/linux/fuse.h uint32_t release_flags; uint32_t 606 include/uapi/linux/fuse.h uint32_t unused; uint32_t 607 include/uapi/linux/fuse.h uint32_t padding; uint32_t 614 include/uapi/linux/fuse.h uint32_t size; uint32_t 615 include/uapi/linux/fuse.h uint32_t read_flags; uint32_t 617 include/uapi/linux/fuse.h uint32_t flags; uint32_t 618 include/uapi/linux/fuse.h uint32_t padding; uint32_t 626 include/uapi/linux/fuse.h uint32_t size; uint32_t 627 include/uapi/linux/fuse.h uint32_t write_flags; uint32_t 629 include/uapi/linux/fuse.h uint32_t flags; uint32_t 630 include/uapi/linux/fuse.h uint32_t padding; uint32_t 634 include/uapi/linux/fuse.h uint32_t size; uint32_t 635 include/uapi/linux/fuse.h uint32_t padding; uint32_t 646 include/uapi/linux/fuse.h uint32_t fsync_flags; uint32_t 647 include/uapi/linux/fuse.h uint32_t padding; uint32_t 651 include/uapi/linux/fuse.h uint32_t size; uint32_t 652 include/uapi/linux/fuse.h uint32_t flags; uint32_t 656 include/uapi/linux/fuse.h uint32_t size; uint32_t 657 include/uapi/linux/fuse.h uint32_t padding; uint32_t 661 include/uapi/linux/fuse.h uint32_t size; uint32_t 662 include/uapi/linux/fuse.h uint32_t padding; uint32_t 669 include/uapi/linux/fuse.h uint32_t lk_flags; uint32_t 670 include/uapi/linux/fuse.h uint32_t padding; uint32_t 678 include/uapi/linux/fuse.h uint32_t mask; uint32_t 679 include/uapi/linux/fuse.h uint32_t padding; uint32_t 683 include/uapi/linux/fuse.h uint32_t major; uint32_t 684 include/uapi/linux/fuse.h uint32_t minor; uint32_t 685 include/uapi/linux/fuse.h uint32_t max_readahead; uint32_t 686 include/uapi/linux/fuse.h uint32_t flags; uint32_t 693 include/uapi/linux/fuse.h uint32_t major; uint32_t 694 include/uapi/linux/fuse.h uint32_t minor; uint32_t 695 include/uapi/linux/fuse.h uint32_t max_readahead; uint32_t 696 include/uapi/linux/fuse.h uint32_t flags; uint32_t 699 include/uapi/linux/fuse.h uint32_t max_write; uint32_t 700 include/uapi/linux/fuse.h uint32_t time_gran; uint32_t 703 include/uapi/linux/fuse.h uint32_t unused[8]; uint32_t 709 include/uapi/linux/fuse.h uint32_t major; uint32_t 710 include/uapi/linux/fuse.h uint32_t minor; uint32_t 711 include/uapi/linux/fuse.h uint32_t unused; uint32_t 712 include/uapi/linux/fuse.h uint32_t flags; uint32_t 716 include/uapi/linux/fuse.h uint32_t major; uint32_t 717 include/uapi/linux/fuse.h uint32_t minor; uint32_t 718 include/uapi/linux/fuse.h uint32_t unused; uint32_t 719 include/uapi/linux/fuse.h uint32_t flags; uint32_t 720 include/uapi/linux/fuse.h uint32_t max_read; uint32_t 721 include/uapi/linux/fuse.h uint32_t max_write; uint32_t 722 include/uapi/linux/fuse.h uint32_t dev_major; /* chardev major */ uint32_t 723 include/uapi/linux/fuse.h uint32_t dev_minor; /* chardev minor */ uint32_t 724 include/uapi/linux/fuse.h uint32_t spare[10]; uint32_t 733 include/uapi/linux/fuse.h uint32_t blocksize; uint32_t 734 include/uapi/linux/fuse.h uint32_t padding; uint32_t 743 include/uapi/linux/fuse.h uint32_t flags; uint32_t 744 include/uapi/linux/fuse.h uint32_t cmd; uint32_t 746 include/uapi/linux/fuse.h uint32_t in_size; uint32_t 747 include/uapi/linux/fuse.h uint32_t out_size; uint32_t 757 include/uapi/linux/fuse.h uint32_t flags; uint32_t 758 include/uapi/linux/fuse.h uint32_t in_iovs; uint32_t 759 include/uapi/linux/fuse.h uint32_t out_iovs; uint32_t 765 include/uapi/linux/fuse.h uint32_t flags; uint32_t 766 include/uapi/linux/fuse.h uint32_t events; uint32_t 770 include/uapi/linux/fuse.h uint32_t revents; uint32_t 771 include/uapi/linux/fuse.h uint32_t padding; uint32_t 782 include/uapi/linux/fuse.h uint32_t mode; uint32_t 783 include/uapi/linux/fuse.h uint32_t padding; uint32_t 787 include/uapi/linux/fuse.h uint32_t len; uint32_t 788 include/uapi/linux/fuse.h uint32_t opcode; uint32_t 791 include/uapi/linux/fuse.h uint32_t uid; uint32_t 792 include/uapi/linux/fuse.h uint32_t gid; uint32_t 793 include/uapi/linux/fuse.h uint32_t pid; uint32_t 794 include/uapi/linux/fuse.h uint32_t padding; uint32_t 798 include/uapi/linux/fuse.h uint32_t len; uint32_t 806 include/uapi/linux/fuse.h uint32_t namelen; uint32_t 807 include/uapi/linux/fuse.h uint32_t type; uint32_t 835 include/uapi/linux/fuse.h uint32_t namelen; uint32_t 836 include/uapi/linux/fuse.h uint32_t padding; uint32_t 842 include/uapi/linux/fuse.h uint32_t namelen; uint32_t 843 include/uapi/linux/fuse.h uint32_t padding; uint32_t 849 include/uapi/linux/fuse.h uint32_t size; uint32_t 850 include/uapi/linux/fuse.h uint32_t padding; uint32_t 857 include/uapi/linux/fuse.h uint32_t size; uint32_t 858 include/uapi/linux/fuse.h uint32_t padding; uint32_t 865 include/uapi/linux/fuse.h uint32_t size; uint32_t 866 include/uapi/linux/fuse.h uint32_t dummy2; uint32_t 872 include/uapi/linux/fuse.h #define FUSE_DEV_IOC_CLONE _IOR(229, 0, uint32_t) uint32_t 877 include/uapi/linux/fuse.h uint32_t whence; uint32_t 878 include/uapi/linux/fuse.h uint32_t padding; uint32_t 876 include/uapi/linux/sctp.h uint32_t sack_delay; uint32_t 877 include/uapi/linux/sctp.h uint32_t sack_freq; uint32_t 882 include/uapi/linux/sctp.h uint32_t assoc_value; uint32_t 12 include/video/gbe.h volatile uint32_t ctrlstat; /* general control */ uint32_t 13 include/video/gbe.h volatile uint32_t dotclock; /* dot clock PLL control */ uint32_t 14 include/video/gbe.h volatile uint32_t i2c; /* crt I2C control */ uint32_t 15 include/video/gbe.h volatile uint32_t sysclk; /* system clock PLL control */ uint32_t 16 include/video/gbe.h volatile uint32_t i2cfp; /* flat panel I2C control */ uint32_t 17 include/video/gbe.h volatile uint32_t id; /* device id/chip revision */ uint32_t 18 include/video/gbe.h volatile uint32_t config; /* power on configuration [1] */ uint32_t 19 include/video/gbe.h volatile uint32_t bist; /* internal bist status [1] */ uint32_t 20 include/video/gbe.h uint32_t _pad0[0x010000/4 - 8]; uint32_t 21 include/video/gbe.h volatile uint32_t vt_xy; /* current dot coords */ uint32_t 22 include/video/gbe.h volatile uint32_t vt_xymax; /* maximum dot coords */ uint32_t 23 include/video/gbe.h volatile uint32_t vt_vsync; /* vsync on/off */ uint32_t 24 include/video/gbe.h volatile uint32_t vt_hsync; /* hsync on/off */ uint32_t 25 include/video/gbe.h volatile uint32_t vt_vblank; /* vblank on/off */ uint32_t 26 include/video/gbe.h volatile uint32_t vt_hblank; /* hblank on/off */ uint32_t 27 include/video/gbe.h volatile uint32_t vt_flags; /* polarity of vt signals */ uint32_t 28 include/video/gbe.h volatile uint32_t vt_f2rf_lock; /* f2rf & framelck y coord */ uint32_t 29 include/video/gbe.h volatile uint32_t vt_intr01; /* intr 0,1 y coords */ uint32_t 30 include/video/gbe.h volatile uint32_t vt_intr23; /* intr 2,3 y coords */ uint32_t 31 include/video/gbe.h volatile uint32_t fp_hdrv; /* flat panel hdrv on/off */ uint32_t 32 include/video/gbe.h volatile uint32_t fp_vdrv; /* flat panel vdrv on/off */ uint32_t 33 include/video/gbe.h volatile uint32_t fp_de; /* flat panel de on/off */ uint32_t 34 include/video/gbe.h volatile uint32_t vt_hpixen; /* intrnl horiz pixel on/off */ uint32_t 35 include/video/gbe.h volatile uint32_t vt_vpixen; /* intrnl vert pixel on/off */ uint32_t 36 include/video/gbe.h volatile uint32_t vt_hcmap; /* cmap write (horiz) */ uint32_t 37 include/video/gbe.h volatile uint32_t vt_vcmap; /* cmap write (vert) */ uint32_t 38 include/video/gbe.h volatile uint32_t did_start_xy; /* eol/f did/xy reset val */ uint32_t 39 include/video/gbe.h volatile uint32_t crs_start_xy; /* eol/f crs/xy reset val */ uint32_t 40 include/video/gbe.h volatile uint32_t vc_start_xy; /* eol/f vc/xy reset val */ uint32_t 41 include/video/gbe.h uint32_t _pad1[0xffb0/4]; uint32_t 42 include/video/gbe.h volatile uint32_t ovr_width_tile;/*overlay plane ctrl 0 */ uint32_t 43 include/video/gbe.h volatile uint32_t ovr_inhwctrl; /* overlay plane ctrl 1 */ uint32_t 44 include/video/gbe.h volatile uint32_t ovr_control; /* overlay plane ctrl 1 */ uint32_t 45 include/video/gbe.h uint32_t _pad2[0xfff4/4]; uint32_t 46 include/video/gbe.h volatile uint32_t frm_size_tile;/* normal plane ctrl 0 */ uint32_t 47 include/video/gbe.h volatile uint32_t frm_size_pixel;/*normal plane ctrl 1 */ uint32_t 48 include/video/gbe.h volatile uint32_t frm_inhwctrl; /* normal plane ctrl 2 */ uint32_t 49 include/video/gbe.h volatile uint32_t frm_control; /* normal plane ctrl 3 */ uint32_t 50 include/video/gbe.h uint32_t _pad3[0xfff0/4]; uint32_t 51 include/video/gbe.h volatile uint32_t did_inhwctrl; /* DID control */ uint32_t 52 include/video/gbe.h volatile uint32_t did_control; /* DID shadow */ uint32_t 53 include/video/gbe.h uint32_t _pad4[0x7ff8/4]; uint32_t 54 include/video/gbe.h volatile uint32_t mode_regs[32];/* WID table */ uint32_t 55 include/video/gbe.h uint32_t _pad5[0x7f80/4]; uint32_t 56 include/video/gbe.h volatile uint32_t cmap[6144]; /* color map */ uint32_t 57 include/video/gbe.h uint32_t _pad6[0x2000/4]; uint32_t 58 include/video/gbe.h volatile uint32_t cm_fifo; /* color map fifo status */ uint32_t 59 include/video/gbe.h uint32_t _pad7[0x7ffc/4]; uint32_t 60 include/video/gbe.h volatile uint32_t gmap[256]; /* gamma map */ uint32_t 61 include/video/gbe.h uint32_t _pad8[0x7c00/4]; uint32_t 62 include/video/gbe.h volatile uint32_t gmap10[1024]; /* gamma map */ uint32_t 63 include/video/gbe.h uint32_t _pad9[0x7000/4]; uint32_t 64 include/video/gbe.h volatile uint32_t crs_pos; /* cusror control 0 */ uint32_t 65 include/video/gbe.h volatile uint32_t crs_ctl; /* cusror control 1 */ uint32_t 66 include/video/gbe.h volatile uint32_t crs_cmap[3]; /* crs cmap */ uint32_t 67 include/video/gbe.h uint32_t _pad10[0x7fec/4]; uint32_t 68 include/video/gbe.h volatile uint32_t crs_glyph[64];/* crs glyph */ uint32_t 69 include/video/gbe.h uint32_t _pad11[0x7f00/4]; uint32_t 70 include/video/gbe.h volatile uint32_t vc_0; /* video capture crtl 0 */ uint32_t 71 include/video/gbe.h volatile uint32_t vc_1; /* video capture crtl 1 */ uint32_t 72 include/video/gbe.h volatile uint32_t vc_2; /* video capture crtl 2 */ uint32_t 73 include/video/gbe.h volatile uint32_t vc_3; /* video capture crtl 3 */ uint32_t 74 include/video/gbe.h volatile uint32_t vc_4; /* video capture crtl 4 */ uint32_t 75 include/video/gbe.h volatile uint32_t vc_5; /* video capture crtl 5 */ uint32_t 76 include/video/gbe.h volatile uint32_t vc_6; /* video capture crtl 6 */ uint32_t 77 include/video/gbe.h volatile uint32_t vc_7; /* video capture crtl 7 */ uint32_t 78 include/video/gbe.h volatile uint32_t vc_8; /* video capture crtl 8 */ uint32_t 343 include/video/imx-ipu-v3.h bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format, uint32_t 145 include/video/w100fb.h uint32_t *saved_intmem; uint32_t 146 include/video/w100fb.h uint32_t *saved_extmem; uint32_t 58 include/xen/acpi.h int xen_pcpu_id(uint32_t acpi_id); uint32_t 66 include/xen/arm/hypercall.h int HYPERVISOR_multicall(struct multicall_entry *calls, uint32_t nr); uint32_t 55 include/xen/arm/interface.h DEFINE_GUEST_HANDLE(uint32_t); uint32_t 148 include/xen/grant_table.h uint32_t flags, grant_ref_t ref, domid_t domid) uint32_t 164 include/xen/grant_table.h uint32_t flags, grant_handle_t handle) uint32_t 15 include/xen/interface/event_channel.h typedef uint32_t evtchn_port_t; uint32_t 63 include/xen/interface/event_channel.h uint32_t virq; uint32_t 64 include/xen/interface/event_channel.h uint32_t vcpu; uint32_t 78 include/xen/interface/event_channel.h uint32_t pirq; uint32_t 80 include/xen/interface/event_channel.h uint32_t flags; /* BIND_PIRQ__* */ uint32_t 93 include/xen/interface/event_channel.h uint32_t vcpu; uint32_t 139 include/xen/interface/event_channel.h uint32_t status; uint32_t 140 include/xen/interface/event_channel.h uint32_t vcpu; /* VCPU to which this channel is bound. */ uint32_t 149 include/xen/interface/event_channel.h uint32_t pirq; /* EVTCHNSTAT_pirq */ uint32_t 150 include/xen/interface/event_channel.h uint32_t virq; /* EVTCHNSTAT_virq */ uint32_t 168 include/xen/interface/event_channel.h uint32_t vcpu; uint32_t 201 include/xen/interface/event_channel.h uint32_t offset; uint32_t 202 include/xen/interface/event_channel.h uint32_t vcpu; uint32_t 223 include/xen/interface/event_channel.h uint32_t port; uint32_t 224 include/xen/interface/event_channel.h uint32_t priority; uint32_t 228 include/xen/interface/event_channel.h uint32_t cmd; /* EVTCHNOP_* */ uint32_t 261 include/xen/interface/event_channel.h typedef uint32_t event_word_t; uint32_t 274 include/xen/interface/event_channel.h uint32_t ready; uint32_t 275 include/xen/interface/event_channel.h uint32_t _rsvd; uint32_t 90 include/xen/interface/grant_table.h typedef uint32_t grant_ref_t; uint32_t 112 include/xen/interface/grant_table.h uint32_t frame; uint32_t 201 include/xen/interface/grant_table.h uint32_t pad0; uint32_t 230 include/xen/interface/grant_table.h uint32_t __spacer[4]; /* Pad to a power of two */ uint32_t 242 include/xen/interface/grant_table.h typedef uint32_t grant_handle_t; uint32_t 265 include/xen/interface/grant_table.h uint32_t flags; /* GNTMAP_* */ uint32_t 310 include/xen/interface/grant_table.h uint32_t nr_frames; uint32_t 402 include/xen/interface/grant_table.h uint32_t nr_frames; uint32_t 403 include/xen/interface/grant_table.h uint32_t max_nr_frames; uint32_t 440 include/xen/interface/grant_table.h uint32_t version; uint32_t 459 include/xen/interface/grant_table.h uint32_t nr_frames; uint32_t 477 include/xen/interface/grant_table.h uint32_t version; uint32_t 496 include/xen/interface/grant_table.h uint32_t op; uint32_t 533 include/xen/interface/grant_table.h #define GNTMAP_guest_avail_mask ((uint32_t)~0 << _GNTMAP_guest_avail0) uint32_t 30 include/xen/interface/hvm/hvm_op.h uint32_t index; /* IN */ uint32_t 29 include/xen/interface/hvm/hvm_vcpu.h uint32_t eax; uint32_t 30 include/xen/interface/hvm/hvm_vcpu.h uint32_t ecx; uint32_t 31 include/xen/interface/hvm/hvm_vcpu.h uint32_t edx; uint32_t 32 include/xen/interface/hvm/hvm_vcpu.h uint32_t ebx; uint32_t 33 include/xen/interface/hvm/hvm_vcpu.h uint32_t esp; uint32_t 34 include/xen/interface/hvm/hvm_vcpu.h uint32_t ebp; uint32_t 35 include/xen/interface/hvm/hvm_vcpu.h uint32_t esi; uint32_t 36 include/xen/interface/hvm/hvm_vcpu.h uint32_t edi; uint32_t 37 include/xen/interface/hvm/hvm_vcpu.h uint32_t eip; uint32_t 38 include/xen/interface/hvm/hvm_vcpu.h uint32_t eflags; uint32_t 40 include/xen/interface/hvm/hvm_vcpu.h uint32_t cr0; uint32_t 41 include/xen/interface/hvm/hvm_vcpu.h uint32_t cr3; uint32_t 42 include/xen/interface/hvm/hvm_vcpu.h uint32_t cr4; uint32_t 44 include/xen/interface/hvm/hvm_vcpu.h uint32_t pad1; uint32_t 54 include/xen/interface/hvm/hvm_vcpu.h uint32_t cs_base; uint32_t 55 include/xen/interface/hvm/hvm_vcpu.h uint32_t ds_base; uint32_t 56 include/xen/interface/hvm/hvm_vcpu.h uint32_t ss_base; uint32_t 57 include/xen/interface/hvm/hvm_vcpu.h uint32_t es_base; uint32_t 58 include/xen/interface/hvm/hvm_vcpu.h uint32_t tr_base; uint32_t 59 include/xen/interface/hvm/hvm_vcpu.h uint32_t cs_limit; uint32_t 60 include/xen/interface/hvm/hvm_vcpu.h uint32_t ds_limit; uint32_t 61 include/xen/interface/hvm/hvm_vcpu.h uint32_t ss_limit; uint32_t 62 include/xen/interface/hvm/hvm_vcpu.h uint32_t es_limit; uint32_t 63 include/xen/interface/hvm/hvm_vcpu.h uint32_t tr_limit; uint32_t 121 include/xen/interface/hvm/hvm_vcpu.h uint32_t mode; uint32_t 123 include/xen/interface/hvm/hvm_vcpu.h uint32_t pad; uint32_t 126 include/xen/interface/hvm/start_info.h uint32_t magic; /* Contains the magic value 0x336ec578 */ uint32_t 128 include/xen/interface/hvm/start_info.h uint32_t version; /* Version of this structure. */ uint32_t 129 include/xen/interface/hvm/start_info.h uint32_t flags; /* SIF_xxx flags. */ uint32_t 130 include/xen/interface/hvm/start_info.h uint32_t nr_modules; /* Number of modules passed to the kernel. */ uint32_t 139 include/xen/interface/hvm/start_info.h uint32_t memmap_entries; /* Number of entries in the memmap table. */ uint32_t 142 include/xen/interface/hvm/start_info.h uint32_t reserved; /* Must be zero. */ uint32_t 155 include/xen/interface/hvm/start_info.h uint32_t type; /* Mapping type */ uint32_t 156 include/xen/interface/hvm/start_info.h uint32_t reserved; /* Must be zero for Version 1. */ uint32_t 198 include/xen/interface/io/blkif.h uint32_t _pad1; /* offsetof(blkif_request,u.rw.id) == 8 */ uint32_t 210 include/xen/interface/io/blkif.h uint32_t _pad2; /* offsetof(blkif_req..,u.discard.id)==8*/ uint32_t 222 include/xen/interface/io/blkif.h uint32_t _pad3; /* offsetof(blkif_req..,u.other.id)==8*/ uint32_t 231 include/xen/interface/io/blkif.h uint32_t _pad1; /* offsetof(blkif_...,u.indirect.id) == 8 */ uint32_t 239 include/xen/interface/io/blkif.h uint32_t _pad3; /* make it 64 byte aligned */ uint32_t 13 include/xen/interface/io/console.h typedef uint32_t XENCONS_RING_IDX; uint32_t 503 include/xen/interface/io/displif.h uint32_t width; uint32_t 504 include/xen/interface/io/displif.h uint32_t height; uint32_t 505 include/xen/interface/io/displif.h uint32_t bpp; uint32_t 506 include/xen/interface/io/displif.h uint32_t buffer_sz; uint32_t 507 include/xen/interface/io/displif.h uint32_t flags; uint32_t 622 include/xen/interface/io/displif.h uint32_t width; uint32_t 623 include/xen/interface/io/displif.h uint32_t height; uint32_t 624 include/xen/interface/io/displif.h uint32_t pixel_format; uint32_t 702 include/xen/interface/io/displif.h uint32_t x; uint32_t 703 include/xen/interface/io/displif.h uint32_t y; uint32_t 704 include/xen/interface/io/displif.h uint32_t width; uint32_t 705 include/xen/interface/io/displif.h uint32_t height; uint32_t 706 include/xen/interface/io/displif.h uint32_t bpp; uint32_t 848 include/xen/interface/io/displif.h uint32_t in_cons; uint32_t 849 include/xen/interface/io/displif.h uint32_t in_prod; uint32_t 109 include/xen/interface/io/fbif.h uint32_t in_cons, in_prod; uint32_t 110 include/xen/interface/io/fbif.h uint32_t out_cons, out_prod; uint32_t 114 include/xen/interface/io/fbif.h uint32_t line_length; /* length of a row of pixels (in bytes) */ uint32_t 115 include/xen/interface/io/fbif.h uint32_t mem_length; /* length of the framebuffer (in bytes) */ uint32_t 299 include/xen/interface/io/kbdif.h uint32_t keycode; uint32_t 490 include/xen/interface/io/kbdif.h uint32_t major; /* length of the major axis, pixels */ uint32_t 491 include/xen/interface/io/kbdif.h uint32_t minor; /* length of the minor axis, pixels */ uint32_t 556 include/xen/interface/io/kbdif.h uint32_t in_cons, in_prod; uint32_t 557 include/xen/interface/io/kbdif.h uint32_t out_cons, out_prod; uint32_t 287 include/xen/interface/io/netif.h static uint32_t xen_netif_toeplitz_hash(const uint8_t *key, uint32_t 356 include/xen/interface/io/netif.h uint32_t data[3]; uint32_t 382 include/xen/interface/io/netif.h uint32_t status; uint32_t 389 include/xen/interface/io/netif.h uint32_t data; uint32_t 71 include/xen/interface/io/pciif.h uint32_t cmd; uint32_t 77 include/xen/interface/io/pciif.h uint32_t domain; /* PCI Domain/Segment */ uint32_t 78 include/xen/interface/io/pciif.h uint32_t bus; uint32_t 79 include/xen/interface/io/pciif.h uint32_t devfn; uint32_t 86 include/xen/interface/io/pciif.h uint32_t value; uint32_t 88 include/xen/interface/io/pciif.h uint32_t info; uint32_t 96 include/xen/interface/io/pciif.h uint32_t cmd; uint32_t 101 include/xen/interface/io/pciif.h uint32_t domain; /* PCI Domain/Segment*/ uint32_t 102 include/xen/interface/io/pciif.h uint32_t bus; uint32_t 103 include/xen/interface/io/pciif.h uint32_t devfn; uint32_t 107 include/xen/interface/io/pciif.h uint32_t flags; uint32_t 38 include/xen/interface/io/pvcalls.h uint32_t req_id; /* private to guest, echoed in response */ uint32_t 39 include/xen/interface/io/pvcalls.h uint32_t cmd; /* command to execute */ uint32_t 43 include/xen/interface/io/pvcalls.h uint32_t domain; uint32_t 44 include/xen/interface/io/pvcalls.h uint32_t type; uint32_t 45 include/xen/interface/io/pvcalls.h uint32_t protocol; uint32_t 50 include/xen/interface/io/pvcalls.h uint32_t len; uint32_t 51 include/xen/interface/io/pvcalls.h uint32_t flags; uint32_t 53 include/xen/interface/io/pvcalls.h uint32_t evtchn; uint32_t 62 include/xen/interface/io/pvcalls.h uint32_t len; uint32_t 66 include/xen/interface/io/pvcalls.h uint32_t backlog; uint32_t 72 include/xen/interface/io/pvcalls.h uint32_t evtchn; uint32_t 86 include/xen/interface/io/pvcalls.h uint32_t req_id; uint32_t 87 include/xen/interface/io/pvcalls.h uint32_t cmd; uint32_t 89 include/xen/interface/io/pvcalls.h uint32_t pad; uint32_t 638 include/xen/interface/io/sndif.h uint32_t pcm_rate; uint32_t 642 include/xen/interface/io/sndif.h uint32_t buffer_sz; uint32_t 644 include/xen/interface/io/sndif.h uint32_t period_sz; uint32_t 717 include/xen/interface/io/sndif.h uint32_t offset; uint32_t 718 include/xen/interface/io/sndif.h uint32_t length; uint32_t 896 include/xen/interface/io/sndif.h uint32_t min; uint32_t 897 include/xen/interface/io/sndif.h uint32_t max; uint32_t 900 include/xen/interface/io/sndif.h uint32_t min; uint32_t 901 include/xen/interface/io/sndif.h uint32_t max; uint32_t 904 include/xen/interface/io/sndif.h uint32_t min; uint32_t 905 include/xen/interface/io/sndif.h uint32_t max; uint32_t 908 include/xen/interface/io/sndif.h uint32_t min; uint32_t 909 include/xen/interface/io/sndif.h uint32_t max; uint32_t 1067 include/xen/interface/io/sndif.h uint32_t in_cons; uint32_t 1068 include/xen/interface/io/sndif.h uint32_t in_prod; uint32_t 42 include/xen/interface/io/tpmif.h uint32_t length; /* request/response length in bytes */ uint32_t 49 include/xen/interface/io/tpmif.h uint32_t extra_pages[0]; /* grant IDs; length in nr_extra_pages */ uint32_t 212 include/xen/interface/io/vscsiif.h uint32_t reserved[3]; uint32_t 222 include/xen/interface/io/vscsiif.h uint32_t residual_len; /* request bufflen - uint32_t 224 include/xen/interface/io/vscsiif.h uint32_t reserved[36]; uint32_t 67 include/xen/interface/io/xs_wire.h uint32_t type; /* XS_??? */ uint32_t 68 include/xen/interface/io/xs_wire.h uint32_t req_id;/* Request identifier, echoed in daemon's response. */ uint32_t 69 include/xen/interface/io/xs_wire.h uint32_t tx_id; /* Transaction id (0 if not related to a transaction). */ uint32_t 70 include/xen/interface/io/xs_wire.h uint32_t len; /* Length of data following this. */ uint32_t 83 include/xen/interface/io/xs_wire.h typedef uint32_t XENSTORE_RING_IDX; uint32_t 283 include/xen/interface/memory.h uint32_t id; uint32_t 293 include/xen/interface/memory.h uint32_t nr_frames; uint32_t 298 include/xen/interface/memory.h uint32_t flags; uint32_t 38 include/xen/interface/physdev.h uint32_t irq; uint32_t 69 include/xen/interface/physdev.h uint32_t irq; uint32_t 71 include/xen/interface/physdev.h uint32_t flags; /* XENIRQSTAT_* */ uint32_t 89 include/xen/interface/physdev.h uint32_t iopl; uint32_t 100 include/xen/interface/physdev.h uint32_t nr_ports; uint32_t 112 include/xen/interface/physdev.h uint32_t reg; uint32_t 114 include/xen/interface/physdev.h uint32_t value; uint32_t 125 include/xen/interface/physdev.h uint32_t irq; uint32_t 127 include/xen/interface/physdev.h uint32_t vector; uint32_t 200 include/xen/interface/physdev.h uint32_t cmd; uint32_t 223 include/xen/interface/physdev.h uint32_t nr_pirqs; uint32_t 233 include/xen/interface/physdev.h uint32_t pirq; uint32_t 248 include/xen/interface/physdev.h uint32_t flags; uint32_t 257 include/xen/interface/physdev.h uint32_t flags; uint32_t 263 include/xen/interface/physdev.h uint32_t optarr[]; uint32_t 265 include/xen/interface/physdev.h uint32_t optarr[0]; uint32_t 41 include/xen/interface/platform.h uint32_t secs; uint32_t 42 include/xen/interface/platform.h uint32_t nsecs; uint32_t 50 include/xen/interface/platform.h uint32_t nsecs; uint32_t 51 include/xen/interface/platform.h uint32_t mbz; uint32_t 68 include/xen/interface/platform.h uint32_t type; uint32_t 70 include/xen/interface/platform.h uint32_t handle; uint32_t 71 include/xen/interface/platform.h uint32_t reg; uint32_t 85 include/xen/interface/platform.h uint32_t handle; uint32_t 86 include/xen/interface/platform.h uint32_t reg; uint32_t 94 include/xen/interface/platform.h uint32_t reg; uint32_t 98 include/xen/interface/platform.h uint32_t type; uint32_t 106 include/xen/interface/platform.h uint32_t length; /* Length of microcode data. */ uint32_t 116 include/xen/interface/platform.h uint32_t quirk_id; uint32_t 134 include/xen/interface/platform.h uint32_t function; uint32_t 140 include/xen/interface/platform.h uint32_t misc; uint32_t 152 include/xen/interface/platform.h uint32_t ns; uint32_t 156 include/xen/interface/platform.h uint32_t resolution; uint32_t 157 include/xen/interface/platform.h uint32_t accuracy; uint32_t 178 include/xen/interface/platform.h uint32_t data1; uint32_t 192 include/xen/interface/platform.h uint32_t attr; uint32_t 202 include/xen/interface/platform.h uint32_t reset_type; uint32_t 229 include/xen/interface/platform.h uint32_t type; uint32_t 230 include/xen/interface/platform.h uint32_t index; uint32_t 248 include/xen/interface/platform.h uint32_t mbr_signature; /* offset 0x1b8 in mbr */ uint32_t 259 include/xen/interface/platform.h uint32_t version; uint32_t 262 include/xen/interface/platform.h uint32_t nent; uint32_t 265 include/xen/interface/platform.h uint32_t revision; uint32_t 266 include/xen/interface/platform.h uint32_t bufsz; /* input, in bytes */ uint32_t 274 include/xen/interface/platform.h uint32_t type; uint32_t 288 include/xen/interface/platform.h uint32_t sleep_state; /* Which state to enter (Sn). */ uint32_t 290 include/xen/interface/platform.h uint32_t flags; /* XENPF_ACPI_SLEEP_*. */ uint32_t 297 include/xen/interface/platform.h uint32_t flags; /* Must be zero. */ uint32_t 298 include/xen/interface/platform.h uint32_t cpu; /* Physical cpu. */ uint32_t 318 include/xen/interface/platform.h uint32_t cpumap_nr_cpus; uint32_t 346 include/xen/interface/platform.h uint32_t space_id; uint32_t 347 include/xen/interface/platform.h uint32_t bit_width; uint32_t 348 include/xen/interface/platform.h uint32_t bit_offset; uint32_t 349 include/xen/interface/platform.h uint32_t access_size; uint32_t 354 include/xen/interface/platform.h uint32_t domain; /* domain number of one dependent group */ uint32_t 355 include/xen/interface/platform.h uint32_t coord_type; /* coordination type */ uint32_t 356 include/xen/interface/platform.h uint32_t num; /* number of processors in same domain */ uint32_t 363 include/xen/interface/platform.h uint32_t latency; /* worst latency (ms) to enter/exit this cstate */ uint32_t 364 include/xen/interface/platform.h uint32_t power; /* average power consumption(mW) */ uint32_t 365 include/xen/interface/platform.h uint32_t dpcnt; /* number of dependency entries */ uint32_t 371 include/xen/interface/platform.h uint32_t bm_control:1; uint32_t 372 include/xen/interface/platform.h uint32_t bm_check:1; uint32_t 373 include/xen/interface/platform.h uint32_t has_cst:1; uint32_t 374 include/xen/interface/platform.h uint32_t power_setup_done:1; uint32_t 375 include/xen/interface/platform.h uint32_t bm_rld_set:1; uint32_t 379 include/xen/interface/platform.h uint32_t count; /* number of C state entries in array below */ uint32_t 413 include/xen/interface/platform.h uint32_t flags; /* flag for Px sub info type */ uint32_t 414 include/xen/interface/platform.h uint32_t platform_limit; /* Platform limitation on freq usage */ uint32_t 417 include/xen/interface/platform.h uint32_t state_count; /* total available performance states */ uint32_t 420 include/xen/interface/platform.h uint32_t shared_type; /* coordination type of this processor */ uint32_t 426 include/xen/interface/platform.h uint32_t id; /* ACPI CPU ID */ uint32_t 427 include/xen/interface/platform.h uint32_t type; /* {XEN_PM_CX, XEN_PM_PX} */ uint32_t 431 include/xen/interface/platform.h GUEST_HANDLE(uint32_t) pdc; uint32_t 439 include/xen/interface/platform.h uint32_t xen_cpuid; uint32_t 442 include/xen/interface/platform.h uint32_t max_present; uint32_t 446 include/xen/interface/platform.h uint32_t flags; uint32_t 447 include/xen/interface/platform.h uint32_t apic_id; uint32_t 448 include/xen/interface/platform.h uint32_t acpi_id; uint32_t 455 include/xen/interface/platform.h uint32_t cpuid; uint32_t 461 include/xen/interface/platform.h uint32_t apic_id; uint32_t 462 include/xen/interface/platform.h uint32_t acpi_id; uint32_t 463 include/xen/interface/platform.h uint32_t pxm; uint32_t 470 include/xen/interface/platform.h uint32_t pxm; uint32_t 471 include/xen/interface/platform.h uint32_t flags; uint32_t 479 include/xen/interface/platform.h uint32_t type; uint32_t 482 include/xen/interface/platform.h uint32_t idle_nums; uint32_t 489 include/xen/interface/platform.h uint32_t namelen; /* size of 'name' buffer */ uint32_t 492 include/xen/interface/platform.h uint32_t symnum; /* IN: Symbol to read */ uint32_t 504 include/xen/interface/platform.h uint32_t cmd; uint32_t 505 include/xen/interface/platform.h uint32_t interface_version; /* XENPF_INTERFACE_VERSION */ uint32_t 152 include/xen/interface/sched.h uint32_t id; /* watchdog ID */ uint32_t 153 include/xen/interface/sched.h uint32_t timeout; /* timeout */ uint32_t 155 include/xen/interface/vcpu.h uint32_t flags; /* VCPU_SSHOTTMR_??? */ uint32_t 174 include/xen/interface/vcpu.h uint32_t offset; /* offset within page */ uint32_t 175 include/xen/interface/vcpu.h uint32_t rsvd; /* unused */ uint32_t 193 include/xen/interface/vcpu.h #define xen_vcpu_physid_to_x86_apicid(physid) ((uint32_t)(physid)) uint32_t 194 include/xen/interface/vcpu.h #define xen_vcpu_physid_to_x86_acpiid(physid) ((uint32_t)((physid) >> 32)) uint32_t 55 include/xen/interface/version.h uint32_t submap; /* OUT: 32-bit submap */ uint32_t 78 include/xen/interface/version.h uint32_t len; /* IN: size of buf[]. */ uint32_t 86 include/xen/interface/xen-mca.h uint32_t mc_socketid; /* physical socket of the physical core */ uint32_t 89 include/xen/interface/xen-mca.h uint32_t mc_apicid; uint32_t 90 include/xen/interface/xen-mca.h uint32_t mc_flags; uint32_t 115 include/xen/interface/xen-mca.h uint32_t mc_msrs; /* Number of msr with valid values. */ uint32_t 157 include/xen/interface/xen-mca.h uint32_t mc_socketid; uint32_t 179 include/xen/interface/xen-mca.h uint32_t mi_nentries; uint32_t 180 include/xen/interface/xen-mca.h uint32_t flags; uint32_t 190 include/xen/interface/xen-mca.h uint32_t mc_cpunr; uint32_t 191 include/xen/interface/xen-mca.h uint32_t mc_chipid; uint32_t 194 include/xen/interface/xen-mca.h uint32_t mc_apicid; uint32_t 195 include/xen/interface/xen-mca.h uint32_t mc_clusterid; uint32_t 196 include/xen/interface/xen-mca.h uint32_t mc_ncores; uint32_t 197 include/xen/interface/xen-mca.h uint32_t mc_ncores_active; uint32_t 198 include/xen/interface/xen-mca.h uint32_t mc_nthreads; uint32_t 199 include/xen/interface/xen-mca.h uint32_t mc_cpuid_level; uint32_t 200 include/xen/interface/xen-mca.h uint32_t mc_family; uint32_t 201 include/xen/interface/xen-mca.h uint32_t mc_vendor; uint32_t 202 include/xen/interface/xen-mca.h uint32_t mc_model; uint32_t 203 include/xen/interface/xen-mca.h uint32_t mc_step; uint32_t 206 include/xen/interface/xen-mca.h uint32_t mc_cpu_caps[MC_NCAPS]; uint32_t 207 include/xen/interface/xen-mca.h uint32_t mc_cache_size; uint32_t 208 include/xen/interface/xen-mca.h uint32_t mc_cache_alignment; uint32_t 209 include/xen/interface/xen-mca.h uint32_t mc_nmsrvals; uint32_t 240 include/xen/interface/xen-mca.h uint32_t i; uint32_t 269 include/xen/interface/xen-mca.h uint32_t flags; uint32_t 270 include/xen/interface/xen-mca.h uint32_t _pad0; uint32_t 290 include/xen/interface/xen-mca.h uint32_t flags; uint32_t 297 include/xen/interface/xen-mca.h uint32_t ncpus; uint32_t 298 include/xen/interface/xen-mca.h uint32_t _pad0; uint32_t 307 include/xen/interface/xen-mca.h uint32_t mcinj_cpunr; /* target processor id */ uint32_t 308 include/xen/interface/xen-mca.h uint32_t mcinj_flags; /* see MC_MSRINJ_F_* below */ uint32_t 309 include/xen/interface/xen-mca.h uint32_t mcinj_count; /* 0 .. count-1 in array are valid */ uint32_t 310 include/xen/interface/xen-mca.h uint32_t _pad0; uint32_t 323 include/xen/interface/xen-mca.h uint32_t cmd; uint32_t 324 include/xen/interface/xen-mca.h uint32_t interface_version; /* XEN_MCA_INTERFACE_VERSION */ uint32_t 507 include/xen/interface/xen.h uint32_t version; uint32_t 508 include/xen/interface/xen.h uint32_t pad0; uint32_t 517 include/xen/interface/xen.h uint32_t tsc_to_system_mul; uint32_t 640 include/xen/interface/xen.h uint32_t flags; /* SIF_xxx flags. */ uint32_t 642 include/xen/interface/xen.h uint32_t store_evtchn; /* Event channel for store communication. */ uint32_t 646 include/xen/interface/xen.h uint32_t evtchn; /* Event channel for console page. */ uint32_t 649 include/xen/interface/xen.h uint32_t info_off; /* Offset of console_info struct. */ uint32_t 650 include/xen/interface/xen.h uint32_t info_size; /* Size of console_info struct from start.*/ uint32_t 690 include/xen/interface/xen.h uint32_t mod_start; uint32_t 692 include/xen/interface/xen.h uint32_t mod_end; uint32_t 694 include/xen/interface/xen.h uint32_t cmdline; uint32_t 696 include/xen/interface/xen.h uint32_t pad; uint32_t 728 include/xen/interface/xen.h uint32_t lfb_base; uint32_t 729 include/xen/interface/xen.h uint32_t lfb_size; uint32_t 737 include/xen/interface/xen.h uint32_t gbl_caps; uint32_t 755 include/xen/interface/xen.h uint32_t cmd; uint32_t 760 include/xen/interface/xen.h uint32_t flags; uint32_t 764 include/xen/interface/xen.h uint32_t index; uint32_t 765 include/xen/interface/xen.h uint32_t tmem_offset; uint32_t 766 include/xen/interface/xen.h uint32_t pfn_offset; uint32_t 767 include/xen/interface/xen.h uint32_t len; uint32_t 33 include/xen/interface/xenpmu.h uint32_t maj; uint32_t 34 include/xen/interface/xenpmu.h uint32_t min; uint32_t 39 include/xen/interface/xenpmu.h uint32_t vcpu; uint32_t 40 include/xen/interface/xenpmu.h uint32_t pad; uint32_t 73 include/xen/interface/xenpmu.h uint32_t vcpu_id; uint32_t 79 include/xen/interface/xenpmu.h uint32_t pcpu_id; uint32_t 14 include/xen/xen-ops.h DECLARE_PER_CPU(uint32_t, xen_vcpu_id); uint32_t 15 include/xen/xen-ops.h static inline uint32_t xen_vcpu_nr(int cpu) uint32_t 30 include/xen/xen.h extern uint32_t xen_start_flags; uint32_t 39 kernel/kexec_elf.c static uint32_t elf32_to_cpu(const struct elfhdr *ehdr, uint32_t value) uint32_t 1209 kernel/relay.c uint32_t alloc_size = (uint32_t) rbuf->chan->alloc_size; uint32_t 28 kernel/time/test_udelay.c static int udelay_test_single(struct seq_file *s, int usecs, uint32_t iters) uint32_t 122 lib/bch.c uint32_t *ecc) uint32_t 125 lib/bch.c const uint32_t *p; uint32_t 141 lib/bch.c static void load_ecc8(struct bch_control *bch, uint32_t *dst, uint32_t 158 lib/bch.c const uint32_t *src) uint32_t 196 lib/bch.c uint32_t w, r[BCH_ECC_MAX_WORDS]; uint32_t 198 lib/bch.c const uint32_t * const tab0 = bch->mod8_tab; uint32_t 199 lib/bch.c const uint32_t * const tab1 = tab0 + 256*(l+1); uint32_t 200 lib/bch.c const uint32_t * const tab2 = tab1 + 256*(l+1); uint32_t 201 lib/bch.c const uint32_t * const tab3 = tab2 + 256*(l+1); uint32_t 202 lib/bch.c const uint32_t *pdata, *p0, *p1, *p2, *p3; uint32_t 224 lib/bch.c pdata = (uint32_t *)data; uint32_t 347 lib/bch.c static void compute_syndromes(struct bch_control *bch, uint32_t *ecc, uint32_t 352 lib/bch.c uint32_t poly; uint32_t 1003 lib/bch.c uint32_t sum; uint32_t 1089 lib/bch.c static void build_mod8_tables(struct bch_control *bch, const uint32_t *g) uint32_t 1092 lib/bch.c uint32_t data, hi, lo, *tab; uint32_t 1174 lib/bch.c static uint32_t *compute_generator_polynomial(struct bch_control *bch) uint32_t 1181 lib/bch.c uint32_t *genpoly; uint32_t 1263 lib/bch.c uint32_t *genpoly; uint32_t 73 lib/decompress_unlzma.c uint32_t code; uint32_t 74 lib/decompress_unlzma.c uint32_t range; uint32_t 75 lib/decompress_unlzma.c uint32_t bound; uint32_t 148 lib/decompress_unlzma.c static inline uint32_t INIT rc_is_bit_0_helper(struct rc *rc, uint16_t *p) uint32_t 156 lib/decompress_unlzma.c uint32_t t = rc_is_bit_0_helper(rc, p); uint32_t 223 lib/decompress_unlzma.c uint32_t dict_size; uint32_t 289 lib/decompress_unlzma.c uint32_t rep0, rep1, rep2, rep3; uint32_t 299 lib/decompress_unlzma.c uint32_t offs) uint32_t 308 lib/decompress_unlzma.c uint32_t pos = wr->buffer_pos - offs; uint32_t 330 lib/decompress_unlzma.c static inline int INIT copy_byte(struct writer *wr, uint32_t offs) uint32_t 336 lib/decompress_unlzma.c uint32_t rep0, int len) uint32_t 350 lib/decompress_unlzma.c int lc, uint32_t literal_pos_mask) { uint32_t 427 lib/decompress_unlzma.c uint32_t distance; uint32_t 547 lib/decompress_unlzma.c uint32_t pos_state_mask; uint32_t 548 lib/decompress_unlzma.c uint32_t literal_pos_mask; uint32_t 272 lib/decompress_unxz.c s = xz_dec_init(XZ_DYNALLOC, (uint32_t)-1); uint32_t 26 lib/gen_crc32table.c static uint32_t crc32table_le[LE_TABLE_ROWS][256]; uint32_t 27 lib/gen_crc32table.c static uint32_t crc32table_be[BE_TABLE_ROWS][256]; uint32_t 28 lib/gen_crc32table.c static uint32_t crc32ctable_le[LE_TABLE_ROWS][256]; uint32_t 37 lib/gen_crc32table.c static void crc32init_le_generic(const uint32_t polynomial, uint32_t 38 lib/gen_crc32table.c uint32_t (*tab)[256]) uint32_t 41 lib/gen_crc32table.c uint32_t crc = 1; uint32_t 75 lib/gen_crc32table.c uint32_t crc = 0x80000000; uint32_t 93 lib/gen_crc32table.c static void output_table(uint32_t (*table)[256], int rows, int len, char *trans) uint32_t 50 lib/lz4/lz4defs.h typedef uint32_t U32; uint32_t 29 lib/math/div64.c uint32_t __attribute__((weak)) __div64_32(uint64_t *n, uint32_t base) uint32_t 34 lib/math/div64.c uint32_t high = rem >> 32; uint32_t 784 lib/string.c void *memset32(uint32_t *s, uint32_t v, size_t count) uint32_t 786 lib/string.c uint32_t *xs = s; uint32_t 289 lib/vsprintf.c uint32_t q = (x * (uint64_t)0x346DC5D7) >> 43; uint32_t 303 lib/vsprintf.c uint32_t d3, d2, d1, q, h; uint32_t 308 lib/vsprintf.c d1 = ((uint32_t)n >> 16); /* implicit "& 0xffff" */ uint32_t 315 lib/vsprintf.c q = 656 * d3 + 7296 * d2 + 5536 * d1 + ((uint32_t)n & 0xffff); uint32_t 64 lib/xxhash.c static const uint32_t PRIME32_1 = 2654435761U; uint32_t 65 lib/xxhash.c static const uint32_t PRIME32_2 = 2246822519U; uint32_t 66 lib/xxhash.c static const uint32_t PRIME32_3 = 3266489917U; uint32_t 67 lib/xxhash.c static const uint32_t PRIME32_4 = 668265263U; uint32_t 68 lib/xxhash.c static const uint32_t PRIME32_5 = 374761393U; uint32_t 94 lib/xxhash.c static uint32_t xxh32_round(uint32_t seed, const uint32_t input) uint32_t 102 lib/xxhash.c uint32_t xxh32(const void *input, const size_t len, const uint32_t seed) uint32_t 106 lib/xxhash.c uint32_t h32; uint32_t 110 lib/xxhash.c uint32_t v1 = seed + PRIME32_1 + PRIME32_2; uint32_t 111 lib/xxhash.c uint32_t v2 = seed + PRIME32_2; uint32_t 112 lib/xxhash.c uint32_t v3 = seed + 0; uint32_t 113 lib/xxhash.c uint32_t v4 = seed - PRIME32_1; uint32_t 132 lib/xxhash.c h32 += (uint32_t)len; uint32_t 242 lib/xxhash.c void xxh32_reset(struct xxh32_state *statePtr, const uint32_t seed) uint32_t 278 lib/xxhash.c state->total_len_32 += (uint32_t)len; uint32_t 283 lib/xxhash.c state->memsize += (uint32_t)len; uint32_t 288 lib/xxhash.c const uint32_t *p32 = state->mem32; uint32_t 308 lib/xxhash.c uint32_t v1 = state->v1; uint32_t 309 lib/xxhash.c uint32_t v2 = state->v2; uint32_t 310 lib/xxhash.c uint32_t v3 = state->v3; uint32_t 311 lib/xxhash.c uint32_t v4 = state->v4; uint32_t 332 lib/xxhash.c state->memsize = (uint32_t)(b_end-p); uint32_t 339 lib/xxhash.c uint32_t xxh32_digest(const struct xxh32_state *state) uint32_t 344 lib/xxhash.c uint32_t h32; uint32_t 389 lib/xxhash.c state->memsize += (uint32_t)len; uint32_t 437 lib/xxhash.c state->memsize = (uint32_t)(b_end - p); uint32_t 28 lib/xz/xz_crc32.c STATIC_RW_DATA uint32_t xz_crc32_table[256]; uint32_t 32 lib/xz/xz_crc32.c const uint32_t poly = CRC32_POLY_LE; uint32_t 34 lib/xz/xz_crc32.c uint32_t i; uint32_t 35 lib/xz/xz_crc32.c uint32_t j; uint32_t 36 lib/xz/xz_crc32.c uint32_t r; uint32_t 49 lib/xz/xz_crc32.c XZ_EXTERN uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc) uint32_t 45 lib/xz/xz_dec_bcj.c uint32_t pos; uint32_t 48 lib/xz/xz_dec_bcj.c uint32_t x86_prev_mask; uint32_t 97 lib/xz/xz_dec_bcj.c uint32_t prev_mask = s->x86_prev_mask; uint32_t 98 lib/xz/xz_dec_bcj.c uint32_t src; uint32_t 99 lib/xz/xz_dec_bcj.c uint32_t dest; uint32_t 100 lib/xz/xz_dec_bcj.c uint32_t j; uint32_t 132 lib/xz/xz_dec_bcj.c dest = src - (s->pos + (uint32_t)i + 5); uint32_t 141 lib/xz/xz_dec_bcj.c src = dest ^ (((uint32_t)1 << (32 - j)) - 1); uint32_t 145 lib/xz/xz_dec_bcj.c dest |= (uint32_t)0 - (dest & 0x01000000); uint32_t 163 lib/xz/xz_dec_bcj.c uint32_t instr; uint32_t 169 lib/xz/xz_dec_bcj.c instr -= s->pos + (uint32_t)i; uint32_t 201 lib/xz/xz_dec_bcj.c uint32_t slot; uint32_t 204 lib/xz/xz_dec_bcj.c uint32_t bit_pos; uint32_t 207 lib/xz/xz_dec_bcj.c uint32_t byte_pos; uint32_t 208 lib/xz/xz_dec_bcj.c uint32_t bit_res; uint32_t 211 lib/xz/xz_dec_bcj.c uint32_t addr; uint32_t 214 lib/xz/xz_dec_bcj.c uint32_t mask; uint32_t 240 lib/xz/xz_dec_bcj.c addr |= ((uint32_t)(norm >> 36) & 1) << 20; uint32_t 242 lib/xz/xz_dec_bcj.c addr -= s->pos + (uint32_t)i; uint32_t 268 lib/xz/xz_dec_bcj.c uint32_t addr; uint32_t 272 lib/xz/xz_dec_bcj.c addr = (uint32_t)buf[i] | ((uint32_t)buf[i + 1] << 8) uint32_t 273 lib/xz/xz_dec_bcj.c | ((uint32_t)buf[i + 2] << 16); uint32_t 275 lib/xz/xz_dec_bcj.c addr -= s->pos + (uint32_t)i + 8; uint32_t 291 lib/xz/xz_dec_bcj.c uint32_t addr; uint32_t 296 lib/xz/xz_dec_bcj.c addr = (((uint32_t)buf[i + 1] & 0x07) << 19) uint32_t 297 lib/xz/xz_dec_bcj.c | ((uint32_t)buf[i] << 11) uint32_t 298 lib/xz/xz_dec_bcj.c | (((uint32_t)buf[i + 3] & 0x07) << 8) uint32_t 299 lib/xz/xz_dec_bcj.c | (uint32_t)buf[i + 2]; uint32_t 301 lib/xz/xz_dec_bcj.c addr -= s->pos + (uint32_t)i + 4; uint32_t 319 lib/xz/xz_dec_bcj.c uint32_t instr; uint32_t 325 lib/xz/xz_dec_bcj.c instr -= s->pos + (uint32_t)i; uint32_t 327 lib/xz/xz_dec_bcj.c instr = ((uint32_t)0x40000000 - (instr & 0x400000)) uint32_t 75 lib/xz/xz_dec_lzma2.c uint32_t size; uint32_t 81 lib/xz/xz_dec_lzma2.c uint32_t size_max; uint32_t 88 lib/xz/xz_dec_lzma2.c uint32_t allocated; uint32_t 96 lib/xz/xz_dec_lzma2.c uint32_t range; uint32_t 97 lib/xz/xz_dec_lzma2.c uint32_t code; uint32_t 103 lib/xz/xz_dec_lzma2.c uint32_t init_bytes_left; uint32_t 134 lib/xz/xz_dec_lzma2.c uint32_t rep0; uint32_t 135 lib/xz/xz_dec_lzma2.c uint32_t rep1; uint32_t 136 lib/xz/xz_dec_lzma2.c uint32_t rep2; uint32_t 137 lib/xz/xz_dec_lzma2.c uint32_t rep3; uint32_t 146 lib/xz/xz_dec_lzma2.c uint32_t len; uint32_t 154 lib/xz/xz_dec_lzma2.c uint32_t lc; uint32_t 155 lib/xz/xz_dec_lzma2.c uint32_t literal_pos_mask; /* (1 << lp) - 1 */ uint32_t 156 lib/xz/xz_dec_lzma2.c uint32_t pos_mask; /* (1 << pb) - 1 */ uint32_t 232 lib/xz/xz_dec_lzma2.c uint32_t uncompressed; uint32_t 238 lib/xz/xz_dec_lzma2.c uint32_t compressed; uint32_t 273 lib/xz/xz_dec_lzma2.c uint32_t size; uint32_t 320 lib/xz/xz_dec_lzma2.c static inline uint32_t dict_get(const struct dictionary *dict, uint32_t dist) uint32_t 346 lib/xz/xz_dec_lzma2.c static bool dict_repeat(struct dictionary *dict, uint32_t *len, uint32_t dist) uint32_t 349 lib/xz/xz_dec_lzma2.c uint32_t left; uint32_t 375 lib/xz/xz_dec_lzma2.c uint32_t *left) uint32_t 416 lib/xz/xz_dec_lzma2.c static uint32_t dict_flush(struct dictionary *dict, struct xz_buf *b) uint32_t 440 lib/xz/xz_dec_lzma2.c rc->range = (uint32_t)-1; uint32_t 499 lib/xz/xz_dec_lzma2.c uint32_t bound; uint32_t 519 lib/xz/xz_dec_lzma2.c static __always_inline uint32_t rc_bittree(struct rc_dec *rc, uint32_t 520 lib/xz/xz_dec_lzma2.c uint16_t *probs, uint32_t limit) uint32_t 522 lib/xz/xz_dec_lzma2.c uint32_t symbol = 1; uint32_t 537 lib/xz/xz_dec_lzma2.c uint32_t *dest, uint32_t limit) uint32_t 539 lib/xz/xz_dec_lzma2.c uint32_t symbol = 1; uint32_t 540 lib/xz/xz_dec_lzma2.c uint32_t i = 0; uint32_t 553 lib/xz/xz_dec_lzma2.c static inline void rc_direct(struct rc_dec *rc, uint32_t *dest, uint32_t limit) uint32_t 555 lib/xz/xz_dec_lzma2.c uint32_t mask; uint32_t 561 lib/xz/xz_dec_lzma2.c mask = (uint32_t)0 - (rc->code >> 31); uint32_t 574 lib/xz/xz_dec_lzma2.c uint32_t prev_byte = dict_get(&s->dict, 0); uint32_t 575 lib/xz/xz_dec_lzma2.c uint32_t low = prev_byte >> (8 - s->lzma.lc); uint32_t 576 lib/xz/xz_dec_lzma2.c uint32_t high = (s->dict.pos & s->lzma.literal_pos_mask) << s->lzma.lc; uint32_t 584 lib/xz/xz_dec_lzma2.c uint32_t symbol; uint32_t 585 lib/xz/xz_dec_lzma2.c uint32_t match_byte; uint32_t 586 lib/xz/xz_dec_lzma2.c uint32_t match_bit; uint32_t 587 lib/xz/xz_dec_lzma2.c uint32_t offset; uint32_t 588 lib/xz/xz_dec_lzma2.c uint32_t i; uint32_t 620 lib/xz/xz_dec_lzma2.c uint32_t pos_state) uint32_t 623 lib/xz/xz_dec_lzma2.c uint32_t limit; uint32_t 646 lib/xz/xz_dec_lzma2.c static void lzma_match(struct xz_dec_lzma2 *s, uint32_t pos_state) uint32_t 649 lib/xz/xz_dec_lzma2.c uint32_t dist_slot; uint32_t 650 lib/xz/xz_dec_lzma2.c uint32_t limit; uint32_t 688 lib/xz/xz_dec_lzma2.c static void lzma_rep_match(struct xz_dec_lzma2 *s, uint32_t pos_state) uint32_t 690 lib/xz/xz_dec_lzma2.c uint32_t tmp; uint32_t 724 lib/xz/xz_dec_lzma2.c uint32_t pos_state; uint32_t 849 lib/xz/xz_dec_lzma2.c uint32_t tmp; uint32_t 934 lib/xz/xz_dec_lzma2.c uint32_t tmp; uint32_t 1018 lib/xz/xz_dec_lzma2.c += (uint32_t)b->in[b->in_pos++] << 8; uint32_t 1024 lib/xz/xz_dec_lzma2.c += (uint32_t)b->in[b->in_pos++] + 1; uint32_t 1030 lib/xz/xz_dec_lzma2.c = (uint32_t)b->in[b->in_pos++] << 8; uint32_t 1036 lib/xz/xz_dec_lzma2.c += (uint32_t)b->in[b->in_pos++] + 1; uint32_t 1109 lib/xz/xz_dec_lzma2.c uint32_t dict_max) uint32_t 17 lib/xz/xz_dec_stream.c uint32_t crc32; uint32_t 36 lib/xz/xz_dec_stream.c uint32_t pos; uint32_t 46 lib/xz/xz_dec_stream.c uint32_t crc32; uint32_t 75 lib/xz/xz_dec_stream.c uint32_t size; uint32_t 605 lib/xz/xz_dec_stream.c = ((uint32_t)b->in[b->in_pos] + 1) * 4; uint32_t 786 lib/xz/xz_dec_stream.c XZ_EXTERN struct xz_dec *xz_dec_init(enum xz_mode mode, uint32_t dict_max) uint32_t 62 lib/xz/xz_dec_test.c static uint32_t crc; uint32_t 147 lib/xz/xz_lzma2.h static inline uint32_t lzma_get_dist_state(uint32_t len) uint32_t 43 lib/xz/xz_private.h # define get_le32(p) le32_to_cpup((const uint32_t *)(p)) uint32_t 114 lib/xz/xz_private.h uint32_t dict_max); uint32_t 17 lib/xz/xz_stream.h (~crc32_le(~(uint32_t)(crc), buf, size)) uint32_t 38 lib/zstd/mem.h typedef uint32_t U32; uint32_t 214 net/9p/protocol.c uint32_t *count = va_arg(ap, uint32_t *); uint32_t 221 net/9p/protocol.c min_t(uint32_t, *count, uint32_t 434 net/9p/protocol.c uint32_t count = va_arg(ap, uint32_t); uint32_t 50 net/9p/trans_xen.c uint32_t size; uint32_t 378 net/atm/mpc.c uint32_t type; uint32_t 23 net/atm/mpoa_caches.h uint32_t packets_fwded; uint32_t 25 net/atm/mpoa_caches.h uint32_t retry_time; uint32_t 26 net/atm/mpoa_caches.h uint32_t refresh_time; uint32_t 27 net/atm/mpoa_caches.h uint32_t count; uint32_t 60 net/atm/mpoa_caches.h uint32_t packets_rcvd; uint32_t 991 net/bluetooth/hci_request.c static bool adv_use_rpa(struct hci_dev *hdev, uint32_t flags) uint32_t 29 net/bridge/netfilter/ebt_among.c uint32_t cmp[2] = { 0, 0 }; uint32_t 63 net/dccp/dccp.h #define MAX_DCCP_SPECIFIC_HEADER (255 * sizeof(uint32_t)) uint32_t 69 net/dccp/dccp.h #define DCCP_FEATNEG_OVERHEAD (32 * sizeof(uint32_t)) uint32_t 142 net/dsa/master.c static void dsa_master_get_strings(struct net_device *dev, uint32_t stringset, uint32_t 640 net/dsa/slave.c uint32_t stringset, uint8_t *data) uint32_t 33 net/ieee802154/nl-phy.c uint32_t *buf = kcalloc(32, sizeof(uint32_t), GFP_KERNEL); uint32_t 56 net/ieee802154/nl-phy.c pages * sizeof(uint32_t), buf)) uint32_t 53 net/key/af_key.c uint32_t msg_portid; uint32_t 3495 net/key/af_key.c uint32_t reqid, uint8_t family, uint32_t 4271 net/netfilter/nf_tables_api.c uint32_t flags = 0; uint32_t 20 net/netfilter/xt_limit.c uint32_t credit; uint32_t 913 net/openvswitch/actions.c uint32_t cutlen) uint32_t 127 net/openvswitch/datapath.c uint32_t cutlen); uint32_t 131 net/openvswitch/datapath.c uint32_t cutlen); uint32_t 267 net/openvswitch/datapath.c uint32_t cutlen) uint32_t 299 net/openvswitch/datapath.c uint32_t cutlen) uint32_t 386 net/openvswitch/datapath.c uint32_t cutlen) uint32_t 685 net/openvswitch/datapath.c static bool should_fill_key(const struct sw_flow_id *sfid, uint32_t ufid_flags) uint32_t 691 net/openvswitch/datapath.c static bool should_fill_mask(uint32_t ufid_flags) uint32_t 696 net/openvswitch/datapath.c static bool should_fill_actions(uint32_t ufid_flags) uint32_t 703 net/openvswitch/datapath.c uint32_t ufid_flags) uint32_t 856 net/openvswitch/datapath.c uint32_t ufid_flags) uint32_t 227 net/openvswitch/datapath.h uint32_t cutlen); uint32_t 1186 net/openvswitch/flow_netlink.c uint32_t mark = nla_get_u32(a[OVS_KEY_ATTR_SKB_MARK]); uint32_t 426 net/rxrpc/sendmsg.c uint32_t seq; uint32_t 357 net/sunrpc/backchannel_rqst.c void xprt_complete_bc_request(struct rpc_rqst *req, uint32_t copied) uint32_t 124 net/sunrpc/clnt.c static uint32_t clntid; uint32_t 129 net/wireless/radiotap.c (unsigned long)iterator->_rtheader + sizeof(uint32_t) > uint32_t 134 net/wireless/radiotap.c iterator->_arg += sizeof(uint32_t); uint32_t 144 net/wireless/radiotap.c sizeof(uint32_t) > uint32_t 149 net/wireless/radiotap.c iterator->_arg += sizeof(uint32_t); uint32_t 167 net/wireless/radiotap.c uint32_t oui, uint8_t subns) uint32_t 218 net/wireless/radiotap.c uint32_t oui; uint32_t 1654 net/wireless/reg.c static uint32_t reg_rule_to_chan_bw_flags(const struct ieee80211_regdomain *regd, uint32_t 59 samples/bpf/cookie_uid_helper_example.c uint32_t uid; uint32_t 70 samples/bpf/cookie_uid_helper_example.c map_fd = bpf_create_map(BPF_MAP_TYPE_HASH, sizeof(uint32_t), uint32_t 190 samples/bpf/cookie_uid_helper_example.c uint32_t curN = UINT32_MAX; uint32_t 191 samples/bpf/cookie_uid_helper_example.c uint32_t nextN; uint32_t 49 samples/bpf/fds_example.c return bpf_create_map(BPF_MAP_TYPE_ARRAY, sizeof(uint32_t), uint32_t 50 samples/bpf/fds_example.c sizeof(uint32_t), 1024, 0); uint32_t 75 samples/bpf/fds_example.c static int bpf_do_map(const char *file, uint32_t flags, uint32_t key, uint32_t 76 samples/bpf/fds_example.c uint32_t value) uint32_t 109 samples/bpf/fds_example.c static int bpf_do_prog(const char *file, uint32_t flags, const char *object) uint32_t 141 samples/bpf/fds_example.c uint32_t key = 0, value = 0, flags = 0; uint32_t 65 samples/bpf/map_perf_test_user.c static uint32_t num_map_entries; uint32_t 66 samples/bpf/map_perf_test_user.c static uint32_t inner_lru_hash_size; uint32_t 71 samples/bpf/map_perf_test_user.c static uint32_t max_cnt = 1000000; uint32_t 93 samples/bpf/map_perf_test_user.c uint32_t key; uint32_t 138 samples/bpf/map_perf_test_user.c sizeof(uint32_t), uint32_t 38 samples/bpf/sockex3_user.c uint32_t info_len = sizeof(info); uint32_t 68 samples/bpf/test_cgrp2_array_pin.c sizeof(uint32_t), sizeof(uint32_t), uint32_t 35 samples/bpf/test_cgrp2_tc_kern.c .size_key = sizeof(uint32_t), uint32_t 36 samples/bpf/test_cgrp2_tc_kern.c .size_value = sizeof(uint32_t), uint32_t 92 samples/bpf/test_lwt_bpf.c static inline int rewrite(struct __sk_buff *skb, uint32_t old_ip, uint32_t 93 samples/bpf/test_lwt_bpf.c uint32_t new_ip, int rw_daddr) uint32_t 151 samples/bpf/test_lwt_bpf.c uint32_t old_ip, new_ip = 0x3fea8c0; uint32_t 32 samples/bpf/test_map_in_map_user.c static void check_map_id(int inner_map_fd, int map_in_map_fd, uint32_t key) uint32_t 35 samples/bpf/test_map_in_map_user.c uint32_t info_len = sizeof(info); uint32_t 46 samples/bpf/test_map_in_map_user.c static void populate_map(uint32_t port_key, int magic_result) uint32_t 73 samples/bpf/test_map_in_map_user.c uint32_t result_key = 0, port_key; uint32_t 252 samples/mei/mei-amt-version.c uint32_t count; uint32_t 263 samples/mei/mei-amt-version.c uint32_t command; uint32_t 264 samples/mei/mei-amt-version.c uint32_t length; uint32_t 269 samples/mei/mei-amt-version.c uint32_t status; uint32_t 308 samples/mei/mei-amt-version.c static uint32_t amt_verify_code_versions(const struct amt_host_if_resp_header *resp) uint32_t 310 samples/mei/mei-amt-version.c uint32_t status = AMT_STATUS_SUCCESS; uint32_t 313 samples/mei/mei-amt-version.c uint32_t ver_type_cnt; uint32_t 314 samples/mei/mei-amt-version.c uint32_t len; uint32_t 315 samples/mei/mei-amt-version.c uint32_t i; uint32_t 319 samples/mei/mei-amt-version.c code_ver_len = resp->header.length - sizeof(uint32_t); uint32_t 347 samples/mei/mei-amt-version.c static uint32_t amt_verify_response_header(uint32_t command, uint32_t 349 samples/mei/mei-amt-version.c uint32_t response_size) uint32_t 367 samples/mei/mei-amt-version.c static uint32_t amt_host_if_call(struct amt_host_if *acmd, uint32_t 369 samples/mei/mei-amt-version.c uint8_t **read_buf, uint32_t rcmd, uint32_t 372 samples/mei/mei-amt-version.c uint32_t in_buf_sz; uint32_t 375 samples/mei/mei-amt-version.c uint32_t status; uint32_t 410 samples/mei/mei-amt-version.c static uint32_t amt_get_code_versions(struct amt_host_if *cmd, uint32_t 414 samples/mei/mei-amt-version.c uint32_t status; uint32_t 443 samples/mei/mei-amt-version.c uint32_t status; uint32_t 159 samples/vfio-mdev/mtty.c static void dump_buffer(u8 *buf, uint32_t count) uint32_t 915 samples/vfio-mdev/mtty.c static int mtty_set_irqs(struct mdev_device *mdev, uint32_t flags, uint32_t 1022 scripts/dtc/checks.c uint32_t reg = 0; uint32_t 1104 scripts/dtc/checks.c uint32_t reg = 0; uint32_t 52 scripts/dtc/dtc.h typedef uint32_t cell_t; uint32_t 237 scripts/dtc/dtc.h uint32_t guess_boot_cpuid(struct node *tree); uint32_t 259 scripts/dtc/dtc.h uint32_t boot_cpuid_phys; uint32_t 270 scripts/dtc/dtc.h struct node *tree, uint32_t boot_cpuid_phys); uint32_t 19 scripts/dtc/fdtdump.c #define GET_CELL(p) (p += 4, *((const uint32_t *)(p-4))) uint32_t 49 scripts/dtc/fdtdump.c uint32_t off_mem_rsvmap = fdt32_to_cpu(bph->off_mem_rsvmap); uint32_t 50 scripts/dtc/fdtdump.c uint32_t off_dt = fdt32_to_cpu(bph->off_dt_struct); uint32_t 51 scripts/dtc/fdtdump.c uint32_t off_str = fdt32_to_cpu(bph->off_dt_strings); uint32_t 56 scripts/dtc/fdtdump.c uint32_t version = fdt32_to_cpu(bph->version); uint32_t 57 scripts/dtc/fdtdump.c uint32_t totalsize = fdt32_to_cpu(bph->totalsize); uint32_t 58 scripts/dtc/fdtdump.c uint32_t tag; uint32_t 94 scripts/dtc/fdtget.c value = size == 4 ? fdt32_to_cpu(*(const uint32_t *)p) : uint32_t 139 scripts/dtc/fdtget.c uint32_t tag; /* current tag */ uint32_t 158 scripts/dtc/flattree.c while ((d.len - off) >= sizeof(uint32_t)) { uint32_t 160 scripts/dtc/flattree.c off += sizeof(uint32_t); uint32_t 586 scripts/dtc/flattree.c static uint32_t flat_read_word(struct inbuf *inb) uint32_t 622 scripts/dtc/flattree.c flat_realign(inb, sizeof(uint32_t)); uint32_t 639 scripts/dtc/flattree.c flat_realign(inb, sizeof(uint32_t)); uint32_t 666 scripts/dtc/flattree.c uint32_t proplen, stroff; uint32_t 736 scripts/dtc/flattree.c uint32_t val; uint32_t 799 scripts/dtc/flattree.c uint32_t magic, totalsize, version, size_dt, boot_cpuid_phys; uint32_t 800 scripts/dtc/flattree.c uint32_t off_dt, off_str, off_mem_rsvmap; uint32_t 810 scripts/dtc/flattree.c uint32_t val; uint32_t 883 scripts/dtc/flattree.c uint32_t size_str = fdt32_to_cpu(fdt->size_dt_strings); uint32_t 37 scripts/dtc/libfdt/fdt.c static int check_off_(uint32_t hdrsize, uint32_t totalsize, uint32_t off) uint32_t 42 scripts/dtc/libfdt/fdt.c static int check_block_(uint32_t hdrsize, uint32_t totalsize, uint32_t 43 scripts/dtc/libfdt/fdt.c uint32_t base, uint32_t size) uint32_t 54 scripts/dtc/libfdt/fdt.c size_t fdt_header_size_(uint32_t version) uint32_t 126 scripts/dtc/libfdt/fdt.c uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset) uint32_t 129 scripts/dtc/libfdt/fdt.c uint32_t tag; uint32_t 200 scripts/dtc/libfdt/fdt.c uint32_t tag; uint32_t 77 scripts/dtc/libfdt/fdt_addresses.c fdt32_st(prop, (uint32_t)addr); uint32_t 90 scripts/dtc/libfdt/fdt_addresses.c fdt32_st(prop, (uint32_t)size); uint32_t 28 scripts/dtc/libfdt/fdt_overlay.c static uint32_t overlay_get_target_phandle(const void *fdto, int fragment) uint32_t 37 scripts/dtc/libfdt/fdt_overlay.c if ((len != sizeof(*val)) || (fdt32_to_cpu(*val) == (uint32_t)-1)) uint32_t 38 scripts/dtc/libfdt/fdt_overlay.c return (uint32_t)-1; uint32_t 61 scripts/dtc/libfdt/fdt_overlay.c uint32_t phandle; uint32_t 67 scripts/dtc/libfdt/fdt_overlay.c if (phandle == (uint32_t)-1) uint32_t 117 scripts/dtc/libfdt/fdt_overlay.c const char *name, uint32_t delta) uint32_t 120 scripts/dtc/libfdt/fdt_overlay.c uint32_t adj_val; uint32_t 135 scripts/dtc/libfdt/fdt_overlay.c if (adj_val == (uint32_t)-1) uint32_t 157 scripts/dtc/libfdt/fdt_overlay.c uint32_t delta) uint32_t 193 scripts/dtc/libfdt/fdt_overlay.c static int overlay_adjust_local_phandles(void *fdto, uint32_t delta) uint32_t 223 scripts/dtc/libfdt/fdt_overlay.c uint32_t delta) uint32_t 242 scripts/dtc/libfdt/fdt_overlay.c if (fixup_len % sizeof(uint32_t)) uint32_t 253 scripts/dtc/libfdt/fdt_overlay.c for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) { uint32_t 255 scripts/dtc/libfdt/fdt_overlay.c uint32_t poffset; uint32_t 324 scripts/dtc/libfdt/fdt_overlay.c static int overlay_update_local_references(void *fdto, uint32_t delta) uint32_t 369 scripts/dtc/libfdt/fdt_overlay.c const char *path, uint32_t path_len, uint32_t 370 scripts/dtc/libfdt/fdt_overlay.c const char *name, uint32_t name_len, uint32_t 374 scripts/dtc/libfdt/fdt_overlay.c uint32_t phandle; uint32_t 446 scripts/dtc/libfdt/fdt_overlay.c uint32_t path_len, name_len; uint32_t 447 scripts/dtc/libfdt/fdt_overlay.c uint32_t fixup_len; uint32_t 821 scripts/dtc/libfdt/fdt_overlay.c uint32_t delta; uint32_t 36 scripts/dtc/libfdt/fdt_ro.c uint32_t absoffset = stroffset + fdt_off_dt_strings(fdt); uint32_t 102 scripts/dtc/libfdt/fdt_ro.c int fdt_find_max_phandle(const void *fdt, uint32_t *phandle) uint32_t 104 scripts/dtc/libfdt/fdt_ro.c uint32_t max = 0; uint32_t 108 scripts/dtc/libfdt/fdt_ro.c uint32_t value; uint32_t 130 scripts/dtc/libfdt/fdt_ro.c int fdt_generate_phandle(const void *fdt, uint32_t *phandle) uint32_t 132 scripts/dtc/libfdt/fdt_ro.c uint32_t max; uint32_t 188 scripts/dtc/libfdt/fdt_ro.c uint32_t tag; uint32_t 486 scripts/dtc/libfdt/fdt_ro.c uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) uint32_t 656 scripts/dtc/libfdt/fdt_ro.c int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle) uint32_t 841 scripts/dtc/libfdt/fdt_ro.c uint32_t tag; uint32_t 325 scripts/dtc/libfdt/fdt_rw.c uint32_t tag; uint32_t 79 scripts/dtc/libfdt/fdt_sw.c static inline uint32_t sw_flags(void *fdt) uint32_t 105 scripts/dtc/libfdt/fdt_sw.c int fdt_create_with_flags(void *buf, int bufsize, uint32_t flags) uint32_t 334 scripts/dtc/libfdt/fdt_sw.c uint32_t tag; uint32_t 15 scripts/dtc/libfdt/fdt_wip.c uint32_t idx, const void *val, uint32_t 118 scripts/dtc/libfdt/libfdt.h uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); uint32_t 127 scripts/dtc/libfdt/libfdt.h static inline uint32_t fdt32_ld(const fdt32_t *p) uint32_t 131 scripts/dtc/libfdt/libfdt.h return ((uint32_t)bp[0] << 24) uint32_t 132 scripts/dtc/libfdt/libfdt.h | ((uint32_t)bp[1] << 16) uint32_t 133 scripts/dtc/libfdt/libfdt.h | ((uint32_t)bp[2] << 8) uint32_t 137 scripts/dtc/libfdt/libfdt.h static inline void fdt32_st(void *property, uint32_t value) uint32_t 248 scripts/dtc/libfdt/libfdt.h static inline void fdt_set_##name(void *fdt, uint32_t val) \ uint32_t 269 scripts/dtc/libfdt/libfdt.h size_t fdt_header_size_(uint32_t version); uint32_t 363 scripts/dtc/libfdt/libfdt.h int fdt_find_max_phandle(const void *fdt, uint32_t *phandle); uint32_t 380 scripts/dtc/libfdt/libfdt.h static inline uint32_t fdt_get_max_phandle(const void *fdt) uint32_t 382 scripts/dtc/libfdt/libfdt.h uint32_t phandle; uint32_t 387 scripts/dtc/libfdt/libfdt.h return (uint32_t)-1; uint32_t 405 scripts/dtc/libfdt/libfdt.h int fdt_generate_phandle(const void *fdt, uint32_t *phandle); uint32_t 804 scripts/dtc/libfdt/libfdt.h uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); uint32_t 999 scripts/dtc/libfdt/libfdt.h int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); uint32_t 1219 scripts/dtc/libfdt/libfdt.h uint32_t idx, const void *val, uint32_t 1285 scripts/dtc/libfdt/libfdt.h const char *name, uint32_t val) uint32_t 1332 scripts/dtc/libfdt/libfdt.h const char *name, uint32_t val) uint32_t 1415 scripts/dtc/libfdt/libfdt.h int fdt_create_with_flags(void *buf, int bufsize, uint32_t flags); uint32_t 1435 scripts/dtc/libfdt/libfdt.h static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) uint32_t 1447 scripts/dtc/libfdt/libfdt.h static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) uint32_t 1646 scripts/dtc/libfdt/libfdt.h uint32_t val) uint32_t 1693 scripts/dtc/libfdt/libfdt.h uint32_t val) uint32_t 1818 scripts/dtc/libfdt/libfdt.h const char *name, uint32_t val) uint32_t 1865 scripts/dtc/libfdt/libfdt.h const char *name, uint32_t val) uint32_t 26 scripts/dtc/libfdt/libfdt_env.h typedef uint32_t FDT_BITWISE fdt32_t; uint32_t 47 scripts/dtc/libfdt/libfdt_env.h static inline uint32_t fdt32_to_cpu(fdt32_t x) uint32_t 49 scripts/dtc/libfdt/libfdt_env.h return (FDT_FORCE uint32_t)CPU_TO_FDT32(x); uint32_t 51 scripts/dtc/libfdt/libfdt_env.h static inline fdt32_t cpu_to_fdt32(uint32_t x) uint32_t 399 scripts/dtc/livetree.c struct node *tree, uint32_t boot_cpuid_phys) uint32_t 624 scripts/dtc/livetree.c uint32_t guess_boot_cpuid(struct node *tree) uint32_t 639 scripts/dtc/livetree.c if (!reg || (reg->val.len != sizeof(uint32_t))) uint32_t 34 scripts/mod/file2alias.c typedef uint32_t __u32; uint32_t 41 scripts/mod/sumversion.c uint32_t hash[MD4_HASH_WORDS]; uint32_t 42 scripts/mod/sumversion.c uint32_t block[MD4_BLOCK_WORDS]; uint32_t 46 scripts/mod/sumversion.c static inline uint32_t lshift(uint32_t x, unsigned int s) uint32_t 52 scripts/mod/sumversion.c static inline uint32_t F(uint32_t x, uint32_t y, uint32_t z) uint32_t 57 scripts/mod/sumversion.c static inline uint32_t G(uint32_t x, uint32_t y, uint32_t z) uint32_t 62 scripts/mod/sumversion.c static inline uint32_t H(uint32_t x, uint32_t y, uint32_t z) uint32_t 68 scripts/mod/sumversion.c #define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (uint32_t)0x5A827999,s)) uint32_t 69 scripts/mod/sumversion.c #define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (uint32_t)0x6ED9EBA1,s)) uint32_t 72 scripts/mod/sumversion.c static inline void le32_to_cpu_array(uint32_t *buf, unsigned int words) uint32_t 80 scripts/mod/sumversion.c static inline void cpu_to_le32_array(uint32_t *buf, unsigned int words) uint32_t 88 scripts/mod/sumversion.c static void md4_transform(uint32_t *hash, uint32_t const *in) uint32_t 90 scripts/mod/sumversion.c uint32_t a, b, c, d; uint32_t 156 scripts/mod/sumversion.c le32_to_cpu_array(ctx->block, sizeof(ctx->block) / sizeof(uint32_t)); uint32_t 172 scripts/mod/sumversion.c const uint32_t avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f); uint32_t 217 scripts/mod/sumversion.c sizeof(uint64_t)) / sizeof(uint32_t)); uint32_t 219 scripts/mod/sumversion.c cpu_to_le32_array(mctx->hash, sizeof(mctx->hash) / sizeof(uint32_t)); uint32_t 222 scripts/recordmcount.c uint32_t *ptr; uint32_t 300 scripts/recordmcount.c uint32_t *ptr; uint32_t 371 scripts/recordmcount.c static uint32_t w4rev(uint32_t const x) uint32_t 379 scripts/recordmcount.c static uint32_t w2rev(uint16_t const x) uint32_t 390 scripts/recordmcount.c static uint32_t w4nat(uint32_t const x) uint32_t 395 scripts/recordmcount.c static uint32_t w2nat(uint16_t const x) uint32_t 401 scripts/recordmcount.c static uint32_t (*w)(uint32_t); uint32_t 402 scripts/recordmcount.c static uint32_t (*w2)(uint16_t); uint32_t 115 scripts/recordmcount.h # define uint_t uint32_t uint32_t 62 scripts/sign-file.c uint32_t sig_len; /* Length of signature data */ uint32_t 116 scripts/sortextable.c static uint32_t rbe(const uint32_t *x) uint32_t 128 scripts/sortextable.c static uint32_t rle(const uint32_t *x) uint32_t 141 scripts/sortextable.c static void wbe(uint32_t val, uint32_t *x) uint32_t 153 scripts/sortextable.c static void wle(uint32_t val, uint32_t *x) uint32_t 163 scripts/sortextable.c static uint32_t (*r)(const uint32_t *); uint32_t 166 scripts/sortextable.c static void (*w)(uint32_t, uint32_t *); uint32_t 218 scripts/sortextable.c uint32_t *loc = (uint32_t *)(extab_image + i); uint32_t 224 scripts/sortextable.c i += sizeof(uint32_t) * 3; uint32_t 231 scripts/sortextable.c uint32_t *loc = (uint32_t *)(extab_image + i); uint32_t 237 scripts/sortextable.c i += sizeof(uint32_t) * 3; uint32_t 251 scripts/sortextable.c uint32_t *loc = (uint32_t *)(extab_image + i); uint32_t 261 scripts/sortextable.c uint32_t *loc = (uint32_t *)(extab_image + i); uint32_t 73 scripts/sortextable.h # define uint_t uint32_t uint32_t 105 scripts/sortextable.h uint32_t *sort_done_location; uint32_t 24 security/integrity/digsig_asymmetric.c static struct key *request_asymmetric_key(struct key *keyring, uint32_t keyid) uint32_t 178 security/keys/trusted.c const uint32_t command, uint32_t 183 security/keys/trusted.c uint32_t bufsize; uint32_t 185 security/keys/trusted.c uint32_t ordinal; uint32_t 186 security/keys/trusted.c uint32_t result; uint32_t 263 security/keys/trusted.c const uint32_t command, uint32_t 270 security/keys/trusted.c uint32_t bufsize; uint32_t 272 security/keys/trusted.c uint32_t ordinal; uint32_t 273 security/keys/trusted.c uint32_t result; uint32_t 399 security/keys/trusted.c const unsigned char *key, uint16_t type, uint32_t handle) uint32_t 422 security/keys/trusted.c memcpy(s->enonce, &(tb->data[TPM_DATA_OFFSET + sizeof(uint32_t)]), uint32_t 424 security/keys/trusted.c memcpy(enonce, &(tb->data[TPM_DATA_OFFSET + sizeof(uint32_t) + uint32_t 433 security/keys/trusted.c int oiap(struct tpm_buf *tb, uint32_t *handle, unsigned char *nonce) uint32_t 449 security/keys/trusted.c memcpy(nonce, &tb->data[TPM_DATA_OFFSET + sizeof(uint32_t)], uint32_t 468 security/keys/trusted.c uint32_t keyhandle, const unsigned char *keyauth, uint32_t 469 security/keys/trusted.c const unsigned char *data, uint32_t datalen, uint32_t 470 security/keys/trusted.c unsigned char *blob, uint32_t *bloblen, uint32_t 472 security/keys/trusted.c const unsigned char *pcrinfo, uint32_t pcrinfosize) uint32_t 477 security/keys/trusted.c uint32_t ordinal; uint32_t 478 security/keys/trusted.c uint32_t pcrsize; uint32_t 479 security/keys/trusted.c uint32_t datsize; uint32_t 521 security/keys/trusted.c sizeof(uint32_t), &ordinal, SHA1_DIGEST_SIZE, uint32_t 522 security/keys/trusted.c td->encauth, sizeof(uint32_t), &pcrsize, uint32_t 523 security/keys/trusted.c sizeof(uint32_t), &datsize, datalen, data, 0, uint32_t 529 security/keys/trusted.c sizeof(uint32_t), &ordinal, SHA1_DIGEST_SIZE, uint32_t 530 security/keys/trusted.c td->encauth, sizeof(uint32_t), &pcrsize, uint32_t 531 security/keys/trusted.c pcrinfosize, pcrinfo, sizeof(uint32_t), uint32_t 558 security/keys/trusted.c sealinfosize = LOAD32(tb->data, TPM_DATA_OFFSET + sizeof(uint32_t)); uint32_t 559 security/keys/trusted.c encdatasize = LOAD32(tb->data, TPM_DATA_OFFSET + sizeof(uint32_t) + uint32_t 560 security/keys/trusted.c sizeof(uint32_t) + sealinfosize); uint32_t 561 security/keys/trusted.c storedsize = sizeof(uint32_t) + sizeof(uint32_t) + sealinfosize + uint32_t 562 security/keys/trusted.c sizeof(uint32_t) + encdatasize; uint32_t 583 security/keys/trusted.c uint32_t keyhandle, const unsigned char *keyauth, uint32_t 593 security/keys/trusted.c uint32_t authhandle1 = 0; uint32_t 594 security/keys/trusted.c uint32_t authhandle2 = 0; uint32_t 596 security/keys/trusted.c uint32_t ordinal; uint32_t 597 security/keys/trusted.c uint32_t keyhndl; uint32_t 620 security/keys/trusted.c enonce1, nonceodd, cont, sizeof(uint32_t), uint32_t 625 security/keys/trusted.c enonce2, nonceodd, cont, sizeof(uint32_t), uint32_t 656 security/keys/trusted.c sizeof(uint32_t), TPM_DATA_OFFSET, uint32_t 657 security/keys/trusted.c *datalen, TPM_DATA_OFFSET + sizeof(uint32_t), 0, uint32_t 663 security/keys/trusted.c memcpy(data, tb->data + TPM_DATA_OFFSET + sizeof(uint32_t), *datalen); uint32_t 2926 security/selinux/ss/policydb.c rc = put_entry(buf, sizeof(uint32_t), 3, fp); uint32_t 2933 security/selinux/ss/policydb.c rc = put_entry(buf, sizeof(uint32_t), 1, fp); uint32_t 111 sound/ppc/snd_ps3.c uint32_t status; uint32_t 220 sound/ppc/snd_ps3.c uint32_t dma_addr; uint32_t 223 sound/ppc/snd_ps3.c uint32_t ch0_kick_event = 0; /* initialize to mute gcc */ uint32_t 303 sound/ppc/snd_ps3.c uint32_t port_intr; uint32_t 37 sound/ppc/snd_ps3.h uint32_t avs_audio_ch; /* fixed */ uint32_t 38 sound/ppc/snd_ps3.h uint32_t avs_audio_rate; uint32_t 39 sound/ppc/snd_ps3.h uint32_t avs_audio_width; uint32_t 40 sound/ppc/snd_ps3.h uint32_t avs_audio_format; /* fixed */ uint32_t 41 sound/ppc/snd_ps3.h uint32_t avs_audio_source; /* fixed */ uint32_t 48 sound/sh/aica.h uint32_t cmd; /* Command ID */ uint32_t 49 sound/sh/aica.h uint32_t pos; /* Sample position */ uint32_t 50 sound/sh/aica.h uint32_t length; /* Sample length */ uint32_t 51 sound/sh/aica.h uint32_t freq; /* Frequency */ uint32_t 52 sound/sh/aica.h uint32_t vol; /* Volume 0-255 */ uint32_t 53 sound/sh/aica.h uint32_t pan; /* Pan 0-255 */ uint32_t 54 sound/sh/aica.h uint32_t sfmt; /* Sound format */ uint32_t 55 sound/sh/aica.h uint32_t flags; /* Bit flags */ uint32_t 110 sound/soc/adi/axi-i2s.c uint32_t mask; uint32_t 157 sound/soc/bcm/bcm2835-i2s.c uint32_t syncval; uint32_t 158 sound/soc/bcm/bcm2835-i2s.c uint32_t csreg; uint32_t 159 sound/soc/bcm/bcm2835-i2s.c uint32_t i2s_active_state; uint32_t 161 sound/soc/bcm/bcm2835-i2s.c uint32_t off; uint32_t 162 sound/soc/bcm/bcm2835-i2s.c uint32_t clr; uint32_t 343 sound/soc/bcm/bcm2835-i2s.c uint32_t csreg; uint32_t 621 sound/soc/bcm/bcm2835-i2s.c uint32_t cs_reg; uint32_t 645 sound/soc/bcm/bcm2835-i2s.c uint32_t mask; uint32_t 664 sound/soc/bcm/bcm2835-i2s.c uint32_t mask; uint32_t 163 sound/soc/codecs/cros_ec_codec.c static int set_i2s_bclk(struct snd_soc_component *component, uint32_t bclk) uint32_t 154 sound/soc/codecs/jz4740.c uint32_t val; uint32_t 378 sound/soc/codecs/msm8916-wcd-digital.c static uint32_t get_iir_band_coeff(struct snd_soc_component *component, uint32_t 382 sound/soc/codecs/msm8916-wcd-digital.c uint32_t value = 0; uint32_t 388 sound/soc/codecs/msm8916-wcd-digital.c * sizeof(uint32_t)) & 0x7F); uint32_t 396 sound/soc/codecs/msm8916-wcd-digital.c * sizeof(uint32_t) + 1) & 0x7F); uint32_t 404 sound/soc/codecs/msm8916-wcd-digital.c * sizeof(uint32_t) + 2) & 0x7F); uint32_t 412 sound/soc/codecs/msm8916-wcd-digital.c * sizeof(uint32_t) + 3) & 0x7F); uint32_t 448 sound/soc/codecs/msm8916-wcd-digital.c uint32_t value) uint32_t 487 sound/soc/codecs/msm8916-wcd-digital.c (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); uint32_t 29 sound/soc/codecs/sigmadsp.c uint32_t samplerates; uint32_t 40 sound/soc/codecs/sigmadsp.c uint32_t samplerates; uint32_t 151 sound/soc/codecs/tas571x.c size_t send_size = 1 + len * sizeof(uint32_t); uint32_t 158 sound/soc/codecs/tas571x.c for (i = 0, p = buf + 1; i < len; i++, p += sizeof(uint32_t)) uint32_t 183 sound/soc/codecs/tas571x.c unsigned int recv_size = len * sizeof(uint32_t); uint32_t 210 sound/soc/codecs/tas571x.c for (i = 0, p = recv_buf; i < len; i++, p += sizeof(uint32_t)) uint32_t 890 sound/soc/fsl/fsl_dma.c const uint32_t *iprop; uint32_t 190 sound/soc/fsl/fsl_ssi.c .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1, uint32_t 1499 sound/soc/fsl/fsl_ssi.c REG_SSI_SRMSK / sizeof(uint32_t) + 1; uint32_t 342 sound/soc/fsl/imx-ssi.c uint32_t val; uint32_t 395 sound/soc/intel/baytrail/sst-baytrail-ipc.c uint32_t buffer_addr, uint32_t buffer_size) uint32_t 29 sound/soc/intel/baytrail/sst-baytrail-ipc.h uint32_t (*get_write_position)(struct sst_byt_stream *stream, uint32_t 43 sound/soc/intel/baytrail/sst-baytrail-ipc.h uint32_t buffer_addr, uint32_t buffer_size); uint32_t 187 sound/soc/intel/haswell/sst-haswell-ipc.h uint32_t destination; /* destination address */ uint32_t 188 sound/soc/intel/haswell/sst-haswell-ipc.h uint32_t reverse:1; /* if 1 data flows from destination */ uint32_t 189 sound/soc/intel/haswell/sst-haswell-ipc.h uint32_t size:31; /* transfer size in bytes.*/ uint32_t 195 sound/soc/intel/haswell/sst-haswell-ipc.h uint32_t transfers_count; uint32_t 200 sound/soc/intel/haswell/sst-haswell-ipc.h uint32_t parameter_id; uint32_t 201 sound/soc/intel/haswell/sst-haswell-ipc.h uint32_t data_size; uint32_t 110 sound/soc/jz4740/jz4740-i2s.c static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, uint32_t 117 sound/soc/jz4740/jz4740-i2s.c unsigned int reg, uint32_t value) uint32_t 126 sound/soc/jz4740/jz4740-i2s.c uint32_t conf, ctrl; uint32_t 151 sound/soc/jz4740/jz4740-i2s.c uint32_t conf; uint32_t 168 sound/soc/jz4740/jz4740-i2s.c uint32_t ctrl; uint32_t 169 sound/soc/jz4740/jz4740-i2s.c uint32_t mask; uint32_t 202 sound/soc/jz4740/jz4740-i2s.c uint32_t format = 0; uint32_t 203 sound/soc/jz4740/jz4740-i2s.c uint32_t conf; uint32_t 254 sound/soc/jz4740/jz4740-i2s.c uint32_t ctrl, div_reg; uint32_t 330 sound/soc/jz4740/jz4740-i2s.c uint32_t conf; uint32_t 348 sound/soc/jz4740/jz4740-i2s.c uint32_t conf; uint32_t 390 sound/soc/jz4740/jz4740-i2s.c uint32_t conf; uint32_t 102 sound/soc/kirkwood/kirkwood-i2s.c uint32_t clks_ctrl; uint32_t 138 sound/soc/kirkwood/kirkwood-i2s.c uint32_t ctl_play, ctl_rec; uint32_t 233 sound/soc/kirkwood/kirkwood-i2s.c uint32_t ctl, value; uint32_t 320 sound/soc/kirkwood/kirkwood-i2s.c uint32_t ctl, value; uint32_t 136 sound/soc/kirkwood/kirkwood.h uint32_t ctl_play; uint32_t 137 sound/soc/kirkwood/kirkwood.h uint32_t ctl_rec; uint32_t 46 sound/soc/pxa/pxa-ssp.c uint32_t cr0; uint32_t 47 sound/soc/pxa/pxa-ssp.c uint32_t cr1; uint32_t 48 sound/soc/pxa/pxa-ssp.c uint32_t to; uint32_t 49 sound/soc/pxa/pxa-ssp.c uint32_t psp; uint32_t 66 sound/soc/pxa/pxa-ssp.c uint32_t sscr0; uint32_t 74 sound/soc/pxa/pxa-ssp.c uint32_t sscr0; uint32_t 158 sound/soc/pxa/pxa-ssp.c uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; uint32_t 702 sound/soc/pxa/pxa-ssp.c uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0); uint32_t 703 sound/soc/pxa/pxa-ssp.c uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1); uint32_t 704 sound/soc/pxa/pxa-ssp.c uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP); uint32_t 705 sound/soc/pxa/pxa-ssp.c uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR); uint32_t 238 sound/soc/qcom/qdsp6/q6adm.c struct apr_pkt *pkt, uint32_t rsp_opcode) uint32_t 241 sound/soc/qcom/qdsp6/q6adm.c uint32_t opcode = pkt->hdr.opcode; uint32_t 474 sound/soc/qcom/qdsp6/q6adm.c (sizeof(uint32_t) * payload_map.num_copps)); uint32_t 59 sound/soc/qcom/qdsp6/q6afe-dai.c uint32_t sd_line_mask; uint32_t 60 sound/soc/qcom/qdsp6/q6afe-dai.c uint32_t sync_mode; uint32_t 61 sound/soc/qcom/qdsp6/q6afe-dai.c uint32_t sync_src; uint32_t 62 sound/soc/qcom/qdsp6/q6afe-dai.c uint32_t data_out_enable; uint32_t 63 sound/soc/qcom/qdsp6/q6afe-dai.c uint32_t invert_sync; uint32_t 64 sound/soc/qcom/qdsp6/q6afe-dai.c uint32_t data_delay; uint32_t 65 sound/soc/qcom/qdsp6/q6afe-dai.c uint32_t data_align; uint32_t 341 sound/soc/qcom/qdsp6/q6afe.c uint32_t payload_size; uint32_t 342 sound/soc/qcom/qdsp6/q6afe.c uint32_t payload_address_lsw; uint32_t 343 sound/soc/qcom/qdsp6/q6afe.c uint32_t payload_address_msw; uint32_t 344 sound/soc/qcom/qdsp6/q6afe.c uint32_t mem_map_handle; uint32_t 460 sound/soc/qcom/qdsp6/q6afe.c uint32_t clk_set_minor_version; uint32_t 461 sound/soc/qcom/qdsp6/q6afe.c uint32_t clk_id; uint32_t 462 sound/soc/qcom/qdsp6/q6afe.c uint32_t clk_freq_in_hz; uint32_t 465 sound/soc/qcom/qdsp6/q6afe.c uint32_t enable; uint32_t 173 sound/soc/qcom/qdsp6/q6asm-dai.c static void event_handler(uint32_t opcode, uint32_t token, uint32_t 174 sound/soc/qcom/qdsp6/q6asm-dai.c uint32_t *payload, void *priv) uint32_t 496 sound/soc/qcom/qdsp6/q6asm-dai.c static void compress_event_handler(uint32_t opcode, uint32_t token, uint32_t 497 sound/soc/qcom/qdsp6/q6asm-dai.c uint32_t *payload, void *priv) uint32_t 107 sound/soc/qcom/qdsp6/q6asm.c uint32_t sample_rate; uint32_t 148 sound/soc/qcom/qdsp6/q6asm.c uint32_t mode_flags; uint32_t 151 sound/soc/qcom/qdsp6/q6asm.c uint32_t postprocopo_id; uint32_t 152 sound/soc/qcom/qdsp6/q6asm.c uint32_t dec_fmt_id; uint32_t 163 sound/soc/qcom/qdsp6/q6asm.c uint32_t size; /* size of buffer */ uint32_t 168 sound/soc/qcom/qdsp6/q6asm.c uint32_t num_periods; uint32_t 169 sound/soc/qcom/qdsp6/q6asm.c uint32_t dsp_buf; uint32_t 170 sound/soc/qcom/qdsp6/q6asm.c uint32_t mem_map_handle; uint32_t 186 sound/soc/qcom/qdsp6/q6asm.c uint32_t io_mode; uint32_t 202 sound/soc/qcom/qdsp6/q6asm.c uint32_t pkt_size, bool cmd_flg, uint32_t 203 sound/soc/qcom/qdsp6/q6asm.c uint32_t stream_id) uint32_t 214 sound/soc/qcom/qdsp6/q6asm.c struct apr_pkt *pkt, uint32_t rsp_opcode) uint32_t 355 sound/soc/qcom/qdsp6/q6asm.c uint32_t num_regions, buf_sz; uint32_t 531 sound/soc/qcom/qdsp6/q6asm.c uint32_t client_event = 0; uint32_t 674 sound/soc/qcom/qdsp6/q6asm.c uint32_t sid = 0; uint32_t 675 sound/soc/qcom/qdsp6/q6asm.c uint32_t dir = 0; uint32_t 845 sound/soc/qcom/qdsp6/q6asm.c int q6asm_open_write(struct audio_client *ac, uint32_t format, uint32_t 897 sound/soc/qcom/qdsp6/q6asm.c static int __q6asm_run(struct audio_client *ac, uint32_t flags, uint32_t 898 sound/soc/qcom/qdsp6/q6asm.c uint32_t msw_ts, uint32_t lsw_ts, bool wait) uint32_t 941 sound/soc/qcom/qdsp6/q6asm.c int q6asm_run(struct audio_client *ac, uint32_t flags, uint32_t 942 sound/soc/qcom/qdsp6/q6asm.c uint32_t msw_ts, uint32_t lsw_ts) uint32_t 958 sound/soc/qcom/qdsp6/q6asm.c int q6asm_run_nowait(struct audio_client *ac, uint32_t flags, uint32_t 959 sound/soc/qcom/qdsp6/q6asm.c uint32_t msw_ts, uint32_t lsw_ts) uint32_t 977 sound/soc/qcom/qdsp6/q6asm.c uint32_t rate, uint32_t channels, uint32_t 1035 sound/soc/qcom/qdsp6/q6asm.c uint32_t rate, uint32_t channels, uint16_t bits_per_sample) uint32_t 1135 sound/soc/qcom/qdsp6/q6asm.c uint32_t format, uint16_t bits_per_sample) uint32_t 1186 sound/soc/qcom/qdsp6/q6asm.c int q6asm_open_read(struct audio_client *ac, uint32_t format, uint32_t 1204 sound/soc/qcom/qdsp6/q6asm.c int q6asm_write_async(struct audio_client *ac, uint32_t len, uint32_t msw_ts, uint32_t 1205 sound/soc/qcom/qdsp6/q6asm.c uint32_t lsw_ts, uint32_t wflags) uint32_t 35 sound/soc/qcom/qdsp6/q6asm.h typedef void (*q6asm_cb) (uint32_t opcode, uint32_t token, uint32_t 42 sound/soc/qcom/qdsp6/q6asm.h int q6asm_write_async(struct audio_client *ac, uint32_t len, uint32_t msw_ts, uint32_t 43 sound/soc/qcom/qdsp6/q6asm.h uint32_t lsw_ts, uint32_t flags); uint32_t 44 sound/soc/qcom/qdsp6/q6asm.h int q6asm_open_write(struct audio_client *ac, uint32_t format, uint32_t 47 sound/soc/qcom/qdsp6/q6asm.h int q6asm_open_read(struct audio_client *ac, uint32_t format, uint32_t 50 sound/soc/qcom/qdsp6/q6asm.h uint32_t rate, uint32_t channels, uint16_t bits_per_sample); uint32_t 54 sound/soc/qcom/qdsp6/q6asm.h uint32_t rate, uint32_t channels, uint32_t 57 sound/soc/qcom/qdsp6/q6asm.h int q6asm_run(struct audio_client *ac, uint32_t flags, uint32_t msw_ts, uint32_t 58 sound/soc/qcom/qdsp6/q6asm.h uint32_t lsw_ts); uint32_t 59 sound/soc/qcom/qdsp6/q6asm.h int q6asm_run_nowait(struct audio_client *ac, uint32_t flags, uint32_t msw_ts, uint32_t 60 sound/soc/qcom/qdsp6/q6asm.h uint32_t lsw_ts); uint32_t 27 sound/soc/qcom/qdsp6/q6core.c uint32_t service_id; uint32_t 28 sound/soc/qcom/qdsp6/q6core.c uint32_t version; uint32_t 32 sound/soc/qcom/qdsp6/q6core.c uint32_t build_id; uint32_t 33 sound/soc/qcom/qdsp6/q6core.c uint32_t num_services; uint32_t 39 sound/soc/qcom/qdsp6/q6core.c uint32_t service_id; uint32_t 40 sound/soc/qcom/qdsp6/q6core.c uint32_t api_version; uint32_t 41 sound/soc/qcom/qdsp6/q6core.c uint32_t api_branch_version; uint32_t 45 sound/soc/qcom/qdsp6/q6core.c uint32_t build_major_version; uint32_t 46 sound/soc/qcom/qdsp6/q6core.c uint32_t build_minor_version; uint32_t 47 sound/soc/qcom/qdsp6/q6core.c uint32_t build_branch_version; uint32_t 48 sound/soc/qcom/qdsp6/q6core.c uint32_t build_subbranch_version; uint32_t 49 sound/soc/qcom/qdsp6/q6core.c uint32_t num_services; uint32_t 56 sound/soc/qcom/qdsp6/q6core.c uint32_t avcs_state; uint32_t 59 sound/soc/qcom/qdsp6/q6core.c uint32_t num_services; uint32_t 7 sound/soc/qcom/qdsp6/q6core.h uint32_t service_id; uint32_t 8 sound/soc/qcom/qdsp6/q6core.h uint32_t api_version; uint32_t 9 sound/soc/qcom/qdsp6/q6core.h uint32_t api_branch_version; uint32_t 32 sound/soc/qcom/sdm845.c uint32_t pri_mi2s_clk_count; uint32_t 33 sound/soc/qcom/sdm845.c uint32_t sec_mi2s_clk_count; uint32_t 34 sound/soc/qcom/sdm845.c uint32_t quat_tdm_clk_count; uint32_t 415 sound/soc/sh/rcar/adg.c uint32_t count = 0; uint32_t 124 sound/soc/sof/intel/hda-ipc.c static bool hda_dsp_ipc_is_sof(uint32_t msg) uint32_t 74 sound/usb/card.h uint32_t packet_size[MAX_PACKS_HS]; uint32_t 102 tools/bpf/bpf_dbg.c uint32_t magic; uint32_t 106 tools/bpf/bpf_dbg.c uint32_t sigfigs; uint32_t 107 tools/bpf/bpf_dbg.c uint32_t snaplen; uint32_t 108 tools/bpf/bpf_dbg.c uint32_t linktype; uint32_t 118 tools/bpf/bpf_dbg.c uint32_t caplen; uint32_t 119 tools/bpf/bpf_dbg.c uint32_t len; uint32_t 123 tools/bpf/bpf_dbg.c uint32_t A; uint32_t 124 tools/bpf/bpf_dbg.c uint32_t X; uint32_t 125 tools/bpf/bpf_dbg.c uint32_t M[BPF_MEMWORDS]; uint32_t 126 tools/bpf/bpf_dbg.c uint32_t R; uint32_t 470 tools/bpf/bpf_dbg.c static void bpf_dump_pkt(uint8_t *pkt, uint32_t pkt_caplen, uint32_t pkt_len) uint32_t 603 tools/bpf/bpf_dbg.c static uint32_t extract_u32(uint8_t *pkt, uint32_t off) uint32_t 605 tools/bpf/bpf_dbg.c uint32_t r; uint32_t 612 tools/bpf/bpf_dbg.c static uint16_t extract_u16(uint8_t *pkt, uint32_t off) uint32_t 621 tools/bpf/bpf_dbg.c static uint8_t extract_u8(uint8_t *pkt, uint32_t off) uint32_t 633 tools/bpf/bpf_dbg.c uint8_t *pkt, uint32_t pkt_caplen, uint32_t 634 tools/bpf/bpf_dbg.c uint32_t pkt_len) uint32_t 636 tools/bpf/bpf_dbg.c uint32_t K = f->k; uint32_t 666 tools/bpf/bpf_dbg.c if (d >= sizeof(uint32_t)) uint32_t 687 tools/bpf/bpf_dbg.c if (d >= sizeof(uint32_t)) uint32_t 855 tools/bpf/bpf_dbg.c uint8_t *pkt, uint32_t pkt_caplen, uint32_t 856 tools/bpf/bpf_dbg.c uint32_t pkt_len) uint32_t 867 tools/bpf/bpf_dbg.c uint32_t pkt_caplen, uint32_t pkt_len) uint32_t 887 tools/bpf/bpf_dbg.c uint8_t *pkt, uint32_t pkt_caplen, uint32_t 888 tools/bpf/bpf_dbg.c uint32_t pkt_len, int next) uint32_t 1178 tools/bpf/bpf_dbg.c static uint32_t pass, fail; uint32_t 43 tools/bpf/bpf_exp.y static void bpf_set_curr_instr(uint16_t op, uint8_t jt, uint8_t jf, uint32_t k); uint32_t 51 tools/bpf/bpf_exp.y uint32_t number; uint32_t 480 tools/bpf/bpf_exp.y uint32_t k) uint32_t 543 tools/bpf/bpf_exp.y out[i].k = (uint32_t) (off - i - 1); uint32_t 136 tools/firewire/decode-fcp.c uint32_t operand0:8; uint32_t 137 tools/firewire/decode-fcp.c uint32_t opcode:8; uint32_t 138 tools/firewire/decode-fcp.c uint32_t subunit_id:3; uint32_t 139 tools/firewire/decode-fcp.c uint32_t subunit_type:5; uint32_t 140 tools/firewire/decode-fcp.c uint32_t ctype:4; uint32_t 141 tools/firewire/decode-fcp.c uint32_t cts:4; uint32_t 33 tools/firewire/nosy-dump.c static void print_packet(uint32_t *data, size_t length); uint32_t 134 tools/firewire/nosy-dump.c subaction_create(uint32_t *data, size_t length) uint32_t 240 tools/firewire/nosy-dump.c print_packet((uint32_t *) &sa->packet, sa->length); uint32_t 242 tools/firewire/nosy-dump.c print_packet((uint32_t *) &sa->packet, sa->length); uint32_t 482 tools/firewire/nosy-dump.c handle_request_packet(uint32_t *data, size_t length) uint32_t 547 tools/firewire/nosy-dump.c handle_response_packet(uint32_t *data, size_t length) uint32_t 619 tools/firewire/nosy-dump.c handle_packet(uint32_t *data, size_t length) uint32_t 646 tools/firewire/nosy-dump.c uint32_t *data = (uint32_t *) packet; uint32_t 647 tools/firewire/nosy-dump.c uint32_t index, shift, mask; uint32_t 708 tools/firewire/nosy-dump.c uint32_t bits; uint32_t 744 tools/firewire/nosy-dump.c print_packet(uint32_t *data, size_t length) uint32_t 827 tools/firewire/nosy-dump.c print_stats(uint32_t *data, size_t length) uint32_t 897 tools/firewire/nosy-dump.c uint32_t buf[128 * 1024]; uint32_t 898 tools/firewire/nosy-dump.c uint32_t filter; uint32_t 15 tools/firewire/nosy-dump.h uint32_t timestamp; uint32_t 18 tools/firewire/nosy-dump.h uint32_t zero:24; uint32_t 19 tools/firewire/nosy-dump.h uint32_t phy_id:6; uint32_t 20 tools/firewire/nosy-dump.h uint32_t identifier:2; uint32_t 24 tools/firewire/nosy-dump.h uint32_t zero:16; uint32_t 25 tools/firewire/nosy-dump.h uint32_t gap_count:6; uint32_t 26 tools/firewire/nosy-dump.h uint32_t set_gap_count:1; uint32_t 27 tools/firewire/nosy-dump.h uint32_t set_root:1; uint32_t 28 tools/firewire/nosy-dump.h uint32_t root_id:6; uint32_t 29 tools/firewire/nosy-dump.h uint32_t identifier:2; uint32_t 33 tools/firewire/nosy-dump.h uint32_t more_packets:1; uint32_t 34 tools/firewire/nosy-dump.h uint32_t initiated_reset:1; uint32_t 35 tools/firewire/nosy-dump.h uint32_t port2:2; uint32_t 36 tools/firewire/nosy-dump.h uint32_t port1:2; uint32_t 37 tools/firewire/nosy-dump.h uint32_t port0:2; uint32_t 38 tools/firewire/nosy-dump.h uint32_t power_class:3; uint32_t 39 tools/firewire/nosy-dump.h uint32_t contender:1; uint32_t 40 tools/firewire/nosy-dump.h uint32_t phy_delay:2; uint32_t 41 tools/firewire/nosy-dump.h uint32_t phy_speed:2; uint32_t 42 tools/firewire/nosy-dump.h uint32_t gap_count:6; uint32_t 43 tools/firewire/nosy-dump.h uint32_t link_active:1; uint32_t 44 tools/firewire/nosy-dump.h uint32_t extended:1; uint32_t 45 tools/firewire/nosy-dump.h uint32_t phy_id:6; uint32_t 46 tools/firewire/nosy-dump.h uint32_t identifier:2; uint32_t 50 tools/firewire/nosy-dump.h uint32_t more_packets:1; uint32_t 51 tools/firewire/nosy-dump.h uint32_t reserved1:1; uint32_t 52 tools/firewire/nosy-dump.h uint32_t porth:2; uint32_t 53 tools/firewire/nosy-dump.h uint32_t portg:2; uint32_t 54 tools/firewire/nosy-dump.h uint32_t portf:2; uint32_t 55 tools/firewire/nosy-dump.h uint32_t porte:2; uint32_t 56 tools/firewire/nosy-dump.h uint32_t portd:2; uint32_t 57 tools/firewire/nosy-dump.h uint32_t portc:2; uint32_t 58 tools/firewire/nosy-dump.h uint32_t portb:2; uint32_t 59 tools/firewire/nosy-dump.h uint32_t porta:2; uint32_t 60 tools/firewire/nosy-dump.h uint32_t reserved0:2; uint32_t 61 tools/firewire/nosy-dump.h uint32_t sequence:3; uint32_t 62 tools/firewire/nosy-dump.h uint32_t extended:1; uint32_t 63 tools/firewire/nosy-dump.h uint32_t phy_id:6; uint32_t 64 tools/firewire/nosy-dump.h uint32_t identifier:2; uint32_t 67 tools/firewire/nosy-dump.h uint32_t inverted; uint32_t 68 tools/firewire/nosy-dump.h uint32_t ack; uint32_t 78 tools/firewire/nosy-dump.h uint32_t timestamp; uint32_t 81 tools/firewire/nosy-dump.h uint32_t priority:4; uint32_t 82 tools/firewire/nosy-dump.h uint32_t tcode:4; uint32_t 83 tools/firewire/nosy-dump.h uint32_t rt:2; uint32_t 84 tools/firewire/nosy-dump.h uint32_t tlabel:6; uint32_t 85 tools/firewire/nosy-dump.h uint32_t destination:16; uint32_t 87 tools/firewire/nosy-dump.h uint32_t offset_high:16; uint32_t 88 tools/firewire/nosy-dump.h uint32_t source:16; uint32_t 90 tools/firewire/nosy-dump.h uint32_t offset_low; uint32_t 94 tools/firewire/nosy-dump.h uint32_t common[3]; uint32_t 95 tools/firewire/nosy-dump.h uint32_t crc; uint32_t 99 tools/firewire/nosy-dump.h uint32_t common[3]; uint32_t 100 tools/firewire/nosy-dump.h uint32_t data; uint32_t 101 tools/firewire/nosy-dump.h uint32_t crc; uint32_t 105 tools/firewire/nosy-dump.h uint32_t common[3]; uint32_t 106 tools/firewire/nosy-dump.h uint32_t extended_tcode:16; uint32_t 107 tools/firewire/nosy-dump.h uint32_t data_length:16; uint32_t 108 tools/firewire/nosy-dump.h uint32_t crc; uint32_t 112 tools/firewire/nosy-dump.h uint32_t common[3]; uint32_t 113 tools/firewire/nosy-dump.h uint32_t extended_tcode:16; uint32_t 114 tools/firewire/nosy-dump.h uint32_t data_length:16; uint32_t 115 tools/firewire/nosy-dump.h uint32_t crc; uint32_t 116 tools/firewire/nosy-dump.h uint32_t data[0]; uint32_t 121 tools/firewire/nosy-dump.h uint32_t common[3]; uint32_t 122 tools/firewire/nosy-dump.h uint32_t data; uint32_t 123 tools/firewire/nosy-dump.h uint32_t crc; uint32_t 127 tools/firewire/nosy-dump.h uint32_t common[3]; uint32_t 128 tools/firewire/nosy-dump.h uint32_t extended_tcode:16; uint32_t 129 tools/firewire/nosy-dump.h uint32_t data_length:16; uint32_t 130 tools/firewire/nosy-dump.h uint32_t crc; uint32_t 131 tools/firewire/nosy-dump.h uint32_t data[0]; uint32_t 136 tools/firewire/nosy-dump.h uint32_t common[3]; uint32_t 137 tools/firewire/nosy-dump.h uint32_t crc; uint32_t 141 tools/firewire/nosy-dump.h uint32_t common[3]; uint32_t 142 tools/firewire/nosy-dump.h uint32_t data; uint32_t 143 tools/firewire/nosy-dump.h uint32_t crc; uint32_t 147 tools/firewire/nosy-dump.h uint32_t sy:4; uint32_t 148 tools/firewire/nosy-dump.h uint32_t tcode:4; uint32_t 149 tools/firewire/nosy-dump.h uint32_t channel:6; uint32_t 150 tools/firewire/nosy-dump.h uint32_t tag:2; uint32_t 151 tools/firewire/nosy-dump.h uint32_t data_length:16; uint32_t 153 tools/firewire/nosy-dump.h uint32_t crc; uint32_t 159 tools/firewire/nosy-dump.h uint32_t ack; uint32_t 30 tools/firmware/ihex2fw.c uint32_t addr; uint32_t 136 tools/firmware/ihex2fw.c uint32_t offset = 0; uint32_t 137 tools/firmware/ihex2fw.c uint32_t data32; uint32_t 29 tools/gpio/gpio-event-mon.c uint32_t handleflags, uint32_t 30 tools/gpio/gpio-event-mon.c uint32_t eventflags, uint32_t 147 tools/gpio/gpio-event-mon.c uint32_t handleflags = GPIOHANDLE_REQUEST_INPUT; uint32_t 148 tools/gpio/gpio-event-mon.c uint32_t eventflags = 0; uint32_t 111 tools/iio/iio_generic_buffer.c void print4byte(uint32_t input, struct iio_channel_info *info) uint32_t 188 tools/iio/iio_generic_buffer.c print4byte(*(uint32_t *)(data + channels[k].location), uint32_t 184 tools/include/nolibc/nolibc.h typedef struct { uint32_t fd32[FD_SETSIZE/32]; } fd_set; uint32_t 12 tools/include/tools/be_byteshift.h static inline uint32_t __get_unaligned_be32(const uint8_t *p) uint32_t 29 tools/include/tools/be_byteshift.h static inline void __put_unaligned_be32(uint32_t val, uint8_t *p) uint32_t 46 tools/include/tools/be_byteshift.h static inline uint32_t get_unaligned_be32(const void *p) uint32_t 61 tools/include/tools/be_byteshift.h static inline void put_unaligned_be32(uint32_t val, void *p) uint32_t 12 tools/include/tools/le_byteshift.h static inline uint32_t __get_unaligned_le32(const uint8_t *p) uint32_t 29 tools/include/tools/le_byteshift.h static inline void __put_unaligned_le32(uint32_t val, uint8_t *p) uint32_t 46 tools/include/tools/le_byteshift.h static inline uint32_t get_unaligned_le32(const void *p) uint32_t 61 tools/include/tools/le_byteshift.h static inline void put_unaligned_le32(uint32_t val, void *p) uint32_t 61 tools/include/uapi/drm/drm.h typedef uint32_t __u32; uint32_t 2089 tools/lib/bpf/btf.c static inline bool is_type_mapped(struct btf_dedup *d, uint32_t type_id) uint32_t 2110 tools/lib/bpf/btf.c static uint32_t resolve_fwd_id(struct btf_dedup *d, uint32_t type_id) uint32_t 5587 tools/lib/bpf/libbpf.c uint32_t size; uint32_t 18 tools/lib/bpf/nlattr.c [LIBBPF_NLA_U32] = sizeof(uint32_t), uint32_t 79 tools/lib/bpf/nlattr.h static inline uint32_t libbpf_nla_getattr_u32(const struct nlattr *nla) uint32_t 81 tools/lib/bpf/nlattr.h return *(uint32_t *)libbpf_nla_data(nla); uint32_t 4114 tools/lib/traceevent/event-parse.c trace_seq_printf(s, "%u", *(uint32_t *)num); uint32_t 738 tools/perf/bench/numa.c static inline uint32_t lfsr_32(uint32_t lfsr) uint32_t 740 tools/perf/bench/numa.c const uint32_t taps = BIT(1) | BIT(5) | BIT(6) | BIT(31); uint32_t 98 tools/perf/util/arm-spe-pkt-decoder.c case 4: packet->payload = le32_to_cpu(*(uint32_t *)buf); break; uint32_t 32 tools/perf/util/genelf_debug.c typedef uint32_t uword; uint32_t 127 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t last_mtc; uint32_t 128 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t tsc_ctc_ratio_n; uint32_t 129 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t tsc_ctc_ratio_d; uint32_t 130 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t tsc_ctc_mult; uint32_t 131 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t tsc_slip; uint32_t 132 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t ctc_rem_mask; uint32_t 213 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c static uint64_t multdiv(uint64_t t, uint32_t n, uint32_t d) uint32_t 643 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t last_mtc; uint32_t 661 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c static void intel_pt_fixup_last_mtc(uint32_t mtc, int mtc_shift, uint32_t 662 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t *last_mtc) uint32_t 664 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t first_missing_bit = 1U << (16 - mtc_shift); uint32_t 665 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t mask = ~(first_missing_bit - 1); uint32_t 681 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t mtc, mtc_delta, ctc, fc, ctc_rem; uint32_t 1497 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t ctc = decoder->packet.payload; uint32_t 1498 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t fc = decoder->packet.count; uint32_t 1499 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t ctc_rem = ctc & decoder->ctc_rem_mask; uint32_t 1528 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t mtc, mtc_delta; uint32_t 1647 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t id = decoder->packet.count; uint32_t 1648 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t bit = 1 << id; uint32_t 118 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t mask[INTEL_PT_BLK_TYPE_CNT]; uint32_t 120 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rflags:1; uint32_t 121 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rip:1; uint32_t 122 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rax:1; uint32_t 123 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rcx:1; uint32_t 124 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rdx:1; uint32_t 125 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rbx:1; uint32_t 126 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rsp:1; uint32_t 127 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rbp:1; uint32_t 128 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rsi:1; uint32_t 129 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_rdi:1; uint32_t 130 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_r8:1; uint32_t 131 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_r9:1; uint32_t 132 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_r10:1; uint32_t 133 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_r11:1; uint32_t 134 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_r12:1; uint32_t 135 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_r13:1; uint32_t 136 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_r14:1; uint32_t 137 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_r15:1; uint32_t 138 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_unused_0:14; uint32_t 139 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_ip:1; uint32_t 140 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_applicable_counters:1; uint32_t 141 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_timestamp:1; uint32_t 142 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_unused_1:29; uint32_t 143 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_mem_access_address:1; uint32_t 144 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_mem_aux_info:1; uint32_t 145 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_mem_access_latency:1; uint32_t 146 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_tsx_aux_info:1; uint32_t 147 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_unused_2:28; uint32_t 148 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_lbr_0; uint32_t 149 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_lbr_1; uint32_t 150 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_lbr_2; uint32_t 151 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t has_xmm; uint32_t 216 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t cbr; uint32_t 217 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t flags; uint32_t 250 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t tsc_ctc_ratio_n; uint32_t 251 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t tsc_ctc_ratio_d; uint32_t 233 tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c packet->payload = le32_to_cpu(*(uint32_t *)(buf + 2)); uint32_t 449 tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c packet->payload = le32_to_cpu(*(uint32_t *)(buf + 1)); uint32_t 50 tools/perf/util/jitdump.c uint32_t code_load_count; uint32_t 82 tools/perf/util/jitdump.c uint32_t unwinding_header_size, uint32_t 83 tools/perf/util/jitdump.c uint32_t unwinding_size) uint32_t 621 tools/perf/util/jitdump.c uint32_t unwinding_data_size; uint32_t 38 tools/perf/util/jitdump.h uint32_t magic; /* characters "jItD" */ uint32_t 39 tools/perf/util/jitdump.h uint32_t version; /* header version */ uint32_t 40 tools/perf/util/jitdump.h uint32_t total_size; /* total size of header */ uint32_t 41 tools/perf/util/jitdump.h uint32_t elf_mach; /* elf mach target */ uint32_t 42 tools/perf/util/jitdump.h uint32_t pad1; /* reserved */ uint32_t 43 tools/perf/util/jitdump.h uint32_t pid; /* JIT process id */ uint32_t 60 tools/perf/util/jitdump.h uint32_t id; uint32_t 61 tools/perf/util/jitdump.h uint32_t total_size; uint32_t 68 tools/perf/util/jitdump.h uint32_t pid; uint32_t 69 tools/perf/util/jitdump.h uint32_t tid; uint32_t 83 tools/perf/util/jitdump.h uint32_t pid; uint32_t 84 tools/perf/util/jitdump.h uint32_t tid; uint32_t 1858 tools/perf/util/session.c uint32_t size, cur_size = 0; uint32_t 283 tools/perf/util/symbol-elf.c uint32_t nr_rel_entries, idx; uint32_t 957 tools/perf/util/symbol-elf.c uint32_t nr_syms; uint32_t 959 tools/perf/util/symbol-elf.c uint32_t idx; uint32_t 53 tools/power/cpupower/debug/i386/centrino-decode.c *lo = (uint32_t )(val & 0xffffffffull); uint32_t 54 tools/power/cpupower/debug/i386/centrino-decode.c *hi = (uint32_t )(val>>32 & 0xffffffffull); uint32_t 27 tools/power/cpupower/debug/i386/powernow-k8-decode.c static int get_fidvid(uint32_t cpu, uint32_t *fid, uint32_t *vid) uint32_t 46 tools/power/cpupower/debug/i386/powernow-k8-decode.c *fid = ((uint32_t )(msr & 0xffffffffull)) & MSR_S_LO_CURRENT_FID; uint32_t 47 tools/power/cpupower/debug/i386/powernow-k8-decode.c *vid = ((uint32_t )(msr>>32 & 0xffffffffull)) & MSR_S_HI_CURRENT_VID; uint32_t 57 tools/power/cpupower/debug/i386/powernow-k8-decode.c static uint32_t find_freq_from_fid(uint32_t fid) uint32_t 63 tools/power/cpupower/debug/i386/powernow-k8-decode.c static uint32_t find_millivolts_from_vid(uint32_t vid) uint32_t 72 tools/power/cpupower/debug/i386/powernow-k8-decode.c uint32_t fid, vid; uint32_t 127 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c uint32_t val; uint32_t 162 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c uint32_t val; uint32_t 271 tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c uint32_t val; uint32_t 34 tools/spi/spidev_test.c static uint32_t mode; uint32_t 38 tools/spi/spidev_test.c static uint32_t speed = 500000; uint32_t 61 tools/testing/selftests/android/ion/ionmap_test.c int import_vgem_fd(int vgem_fd, int dma_buf_fd, uint32_t *handle) uint32_t 76 tools/testing/selftests/android/ion/ionmap_test.c void close_handle(int vgem_fd, uint32_t handle) uint32_t 88 tools/testing/selftests/android/ion/ionmap_test.c uint32_t handle = 0; uint32_t 11 tools/testing/selftests/bpf/bpf_rand.h return (((uint64_t)(uint32_t)rand()) | uint32_t 12 tools/testing/selftests/bpf/bpf_rand.h ((uint64_t)(uint32_t)rand() << 32)) & mask; uint32_t 15 tools/testing/selftests/bpf/prog_tests/global_data.c uint32_t key; uint32_t 50 tools/testing/selftests/bpf/prog_tests/global_data.c uint32_t key; uint32_t 85 tools/testing/selftests/bpf/prog_tests/global_data.c uint32_t key; uint32_t 554 tools/testing/selftests/bpf/progs/core_reloc_types.h uint32_t u32_field; uint32_t 567 tools/testing/selftests/bpf/progs/core_reloc_types.h uint32_t s32_field; uint32_t 577 tools/testing/selftests/bpf/progs/core_reloc_types.h uint32_t u32_field; uint32_t 588 tools/testing/selftests/bpf/progs/core_reloc_types.h uint32_t u32_field: 32; /* bitfields are not supported */ uint32_t 600 tools/testing/selftests/bpf/progs/core_reloc_types.h uint32_t u32_field; uint32_t 610 tools/testing/selftests/bpf/progs/core_reloc_types.h uint32_t u16_field; /* not 16-bit anymore */ uint32_t 613 tools/testing/selftests/bpf/progs/core_reloc_types.h uint32_t u32_field; uint32_t 637 tools/testing/selftests/bpf/progs/core_reloc_types.h uint32_t u32_field; uint32_t 640 tools/testing/selftests/bpf/progs/core_reloc_types.h uint32_t u64_field; /* not 64-bit anymore */ uint32_t 35 tools/testing/selftests/bpf/progs/pyperf.h uint32_t success; uint32_t 44 tools/testing/selftests/bpf/progs/pyperf.h uint32_t pid; uint32_t 45 tools/testing/selftests/bpf/progs/pyperf.h uint32_t tid; uint32_t 13 tools/testing/selftests/bpf/progs/strobemeta.h typedef uint32_t pid_t; uint32_t 217 tools/testing/selftests/bpf/progs/strobemeta.h __uint(key_size, sizeof(uint32_t)); uint32_t 224 tools/testing/selftests/bpf/progs/strobemeta.h __uint(key_size, sizeof(uint32_t)); uint32_t 231 tools/testing/selftests/bpf/progs/strobemeta.h __type(key, uint32_t); uint32_t 352 tools/testing/selftests/bpf/progs/strobemeta.h uint32_t len; uint32_t 384 tools/testing/selftests/bpf/progs/strobemeta.h uint32_t len; uint32_t 500 tools/testing/selftests/bpf/progs/strobemeta.h uint32_t zero = 0; uint32_t 20 tools/testing/selftests/bpf/progs/test_core_reloc_ints.c uint32_t u32_field; uint32_t 88 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c int update_tlv_pad(struct __sk_buff *skb, uint32_t new_pad, uint32_t 89 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t old_pad, uint32_t pad_off) uint32_t 119 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t *tlv_off, uint32_t *pad_size, uint32_t 120 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t *pad_off) uint32_t 122 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t srh_off, cur_off; uint32_t 177 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c int add_tlv(struct __sk_buff *skb, struct ip6_srh_t *srh, uint32_t tlv_off, uint32_t 180 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t srh_off = (char *)srh - (char *)(long)skb->data; uint32_t 182 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t pad_off = 0; uint32_t 183 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t pad_size = 0; uint32_t 184 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t partial_srh_len; uint32_t 222 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t tlv_off) uint32_t 224 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t srh_off = (char *)srh - (char *)(long)skb->data; uint32_t 226 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t partial_srh_len; uint32_t 227 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t pad_off = 0; uint32_t 228 tools/testing/selftests/bpf/progs/test_lwt_seg6local.c uint32_t pad_size = 0; uint32_t 88 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t new_pad, uint32_t old_pad, uint32_t 89 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t pad_off) uint32_t 119 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t *tlv_off, uint32_t 120 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t *pad_size, uint32_t 121 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t *pad_off) uint32_t 123 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t srh_off, cur_off; uint32_t 180 tools/testing/selftests/bpf/progs/test_seg6_loop.c struct ip6_srh_t *srh, uint32_t tlv_off, uint32_t 183 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t srh_off = (char *)srh - (char *)(long)skb->data; uint32_t 185 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t pad_off = 0; uint32_t 186 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t pad_size = 0; uint32_t 187 tools/testing/selftests/bpf/progs/test_seg6_loop.c uint32_t partial_srh_len; uint32_t 22 tools/testing/selftests/bpf/progs/test_tc_edt.c .key_size = sizeof(uint32_t), uint32_t 84 tools/testing/selftests/bpf/progs/test_tc_edt.c uint32_t ihl; uint32_t 32 tools/testing/selftests/bpf/test_btf.c static uint32_t pass_cnt; uint32_t 33 tools/testing/selftests/bpf/test_btf.c static uint32_t error_cnt; uint32_t 34 tools/testing/selftests/bpf/test_btf.c static uint32_t skip_cnt; uint32_t 3541 tools/testing/selftests/bpf/test_btf.c uint32_t *ret_types; uint32_t 3791 tools/testing/selftests/bpf/test_btf.c uint32_t info_len; uint32_t 3874 tools/testing/selftests/bpf/test_btf.c uint32_t info_len; uint32_t 4007 tools/testing/selftests/bpf/test_btf.c uint32_t info_len; uint32_t 4300 tools/testing/selftests/bpf/test_btf.c uint32_t ui32; uint32_t 4304 tools/testing/selftests/bpf/test_btf.c uint32_t unused_bits2a:2, uint32_t 4317 tools/testing/selftests/bpf/test_btf.c uint32_t ui32b; uint32_t 4318 tools/testing/selftests/bpf/test_btf.c uint32_t bits2c:2; uint32_t 4641 tools/testing/selftests/bpf/test_btf.c void *mapv, uint32_t i, uint32_t 166 tools/testing/selftests/bpf/test_flow_dissector.c uint32_t src, uint32_t dst, uint32_t 679 tools/testing/selftests/bpf/test_sock_addr.c uint32_t u4_addr32; uint32_t 1405 tools/testing/selftests/bpf/test_sysctl.c prog[insn_num].imm = (uint32_t)value.num; uint32_t 1406 tools/testing/selftests/bpf/test_sysctl.c prog[insn_num + 1].imm = (uint32_t)(value.num >> 32); uint32_t 91 tools/testing/selftests/bpf/test_tag.c static void tag_from_fdinfo(int fd_prog, uint8_t *tag, uint32_t len) uint32_t 114 tools/testing/selftests/bpf/test_tag.c static void tag_from_alg(int insns, uint8_t *tag, uint32_t len) uint32_t 144 tools/testing/selftests/bpf/test_tag.c static void tag_dump(const char *prefix, uint8_t *tag, uint32_t len) uint32_t 155 tools/testing/selftests/bpf/test_tag.c uint8_t *atag, uint32_t len) uint32_t 165 tools/testing/selftests/bpf/test_tag.c static void do_test(uint32_t *tests, int start_insns, int fd_map, uint32_t 187 tools/testing/selftests/bpf/test_tag.c uint32_t tests = 0; uint32_t 91 tools/testing/selftests/bpf/test_verifier.c uint32_t insn_processed; uint32_t 105 tools/testing/selftests/bpf/test_verifier.c uint32_t retval, retval_unpriv; \ uint32_t 224 tools/testing/selftests/bpf/test_verifier.c self->retval = (uint32_t)res; uint32_t 377 tools/testing/selftests/bpf/test_verifier.c static int __create_map(uint32_t type, uint32_t size_key, uint32_t 378 tools/testing/selftests/bpf/test_verifier.c uint32_t size_value, uint32_t max_elem, uint32_t 379 tools/testing/selftests/bpf/test_verifier.c uint32_t extra_flags) uint32_t 395 tools/testing/selftests/bpf/test_verifier.c static int create_map(uint32_t type, uint32_t size_key, uint32_t 396 tools/testing/selftests/bpf/test_verifier.c uint32_t size_value, uint32_t max_elem) uint32_t 437 tools/testing/selftests/bpf/test_verifier.c static int create_prog_array(enum bpf_prog_type prog_type, uint32_t max_elem, uint32_t 837 tools/testing/selftests/bpf/test_verifier.c static int do_prog_test_run(int fd_prog, bool unpriv, uint32_t expected_val, uint32_t 842 tools/testing/selftests/bpf/test_verifier.c uint32_t retval; uint32_t 984 tools/testing/selftests/bpf/test_verifier.c uint32_t insn_processed; uint32_t 1002 tools/testing/selftests/bpf/test_verifier.c uint32_t expected_val; uint32_t 65 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c *(uint32_t *)addr = 47; uint32_t 85 tools/testing/selftests/efivarfs/open-unlink.c *(uint32_t *)buf = 0x7; uint32_t 249 tools/testing/selftests/kvm/dirty_log_test.c static struct kvm_vm *create_vm(enum vm_guest_mode mode, uint32_t vcpuid, uint32_t 39 tools/testing/selftests/kvm/include/aarch64/processor.h static inline void get_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id, uint64_t *addr) uint32_t 47 tools/testing/selftests/kvm/include/aarch64/processor.h static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id, uint64_t val) uint32_t 56 tools/testing/selftests/kvm/include/aarch64/processor.h void aarch64_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 16 tools/testing/selftests/kvm/include/evmcs.h #define u32 uint32_t uint32_t 78 tools/testing/selftests/kvm/include/kvm_util.h uint64_t first_page, uint32_t num_pages); uint32_t 84 tools/testing/selftests/kvm/include/kvm_util.h uint32_t data_memslot, uint32_t pgd_memslot); uint32_t 87 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint32_t 94 tools/testing/selftests/kvm/include/kvm_util.h uint64_t guest_paddr, uint32_t slot, uint64_t npages, uint32_t 95 tools/testing/selftests/kvm/include/kvm_util.h uint32_t flags); uint32_t 97 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_ioctl(struct kvm_vm *vm, uint32_t vcpuid, unsigned long ioctl, uint32_t 99 tools/testing/selftests/kvm/include/kvm_util.h int _vcpu_ioctl(struct kvm_vm *vm, uint32_t vcpuid, unsigned long ioctl, uint32_t 102 tools/testing/selftests/kvm/include/kvm_util.h void vm_mem_region_set_flags(struct kvm_vm *vm, uint32_t slot, uint32_t flags); uint32_t 103 tools/testing/selftests/kvm/include/kvm_util.h void vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpuid); uint32_t 105 tools/testing/selftests/kvm/include/kvm_util.h uint32_t data_memslot, uint32_t pgd_memslot); uint32_t 107 tools/testing/selftests/kvm/include/kvm_util.h size_t size, uint32_t pgd_memslot); uint32_t 113 tools/testing/selftests/kvm/include/kvm_util.h struct kvm_run *vcpu_state(struct kvm_vm *vm, uint32_t vcpuid); uint32_t 114 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_run(struct kvm_vm *vm, uint32_t vcpuid); uint32_t 115 tools/testing/selftests/kvm/include/kvm_util.h int _vcpu_run(struct kvm_vm *vm, uint32_t vcpuid); uint32_t 116 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_run_complete_io(struct kvm_vm *vm, uint32_t vcpuid); uint32_t 117 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_set_mp_state(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 119 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_regs_get(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_regs *regs); uint32_t 120 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_regs_set(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_regs *regs); uint32_t 121 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_args_set(struct kvm_vm *vm, uint32_t vcpuid, unsigned int num, ...); uint32_t 122 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_sregs_get(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 124 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_sregs_set(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 126 tools/testing/selftests/kvm/include/kvm_util.h int _vcpu_sregs_set(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 129 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_events_get(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 131 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_events_set(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 135 tools/testing/selftests/kvm/include/kvm_util.h void vcpu_nested_state_get(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 137 tools/testing/selftests/kvm/include/kvm_util.h int vcpu_nested_state_set(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 143 tools/testing/selftests/kvm/include/kvm_util.h void virt_pgd_alloc(struct kvm_vm *vm, uint32_t pgd_memslot); uint32_t 145 tools/testing/selftests/kvm/include/kvm_util.h uint32_t pgd_memslot); uint32_t 147 tools/testing/selftests/kvm/include/kvm_util.h uint32_t memslot); uint32_t 149 tools/testing/selftests/kvm/include/kvm_util.h vm_paddr_t paddr_min, uint32_t memslot); uint32_t 151 tools/testing/selftests/kvm/include/kvm_util.h struct kvm_vm *vm_create_default(uint32_t vcpuid, uint64_t extra_mem_size, uint32_t 153 tools/testing/selftests/kvm/include/kvm_util.h void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code); uint32_t 198 tools/testing/selftests/kvm/include/kvm_util.h uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc); uint32_t 62 tools/testing/selftests/kvm/include/x86_64/processor.h uint32_t base3; uint32_t 63 tools/testing/selftests/kvm/include/x86_64/processor.h uint32_t zero1; uint32_t 79 tools/testing/selftests/kvm/include/x86_64/processor.h uint32_t eax, edx; uint32_t 89 tools/testing/selftests/kvm/include/x86_64/processor.h static inline uint64_t rdtscp(uint32_t *aux) uint32_t 91 tools/testing/selftests/kvm/include/x86_64/processor.h uint32_t eax, edx; uint32_t 97 tools/testing/selftests/kvm/include/x86_64/processor.h static inline uint64_t rdmsr(uint32_t msr) uint32_t 99 tools/testing/selftests/kvm/include/x86_64/processor.h uint32_t a, d; uint32_t 106 tools/testing/selftests/kvm/include/x86_64/processor.h static inline void wrmsr(uint32_t msr, uint64_t value) uint32_t 108 tools/testing/selftests/kvm/include/x86_64/processor.h uint32_t a = value; uint32_t 109 tools/testing/selftests/kvm/include/x86_64/processor.h uint32_t d = value >> 32; uint32_t 307 tools/testing/selftests/kvm/include/x86_64/processor.h struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid); uint32_t 308 tools/testing/selftests/kvm/include/x86_64/processor.h void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 312 tools/testing/selftests/kvm/include/x86_64/processor.h void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 316 tools/testing/selftests/kvm/include/x86_64/processor.h kvm_get_supported_cpuid_index(uint32_t function, uint32_t index); uint32_t 319 tools/testing/selftests/kvm/include/x86_64/processor.h kvm_get_supported_cpuid_entry(uint32_t function) uint32_t 324 tools/testing/selftests/kvm/include/x86_64/processor.h uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index); uint32_t 325 tools/testing/selftests/kvm/include/x86_64/processor.h void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index, uint32_t 328 tools/testing/selftests/kvm/include/x86_64/processor.h uint32_t kvm_get_cpuid_max(void); uint32_t 335 tools/testing/selftests/kvm/include/x86_64/vmx.h uint32_t index; uint32_t 336 tools/testing/selftests/kvm/include/x86_64/vmx.h uint32_t reserved; uint32_t 535 tools/testing/selftests/kvm/include/x86_64/vmx.h static inline uint32_t vmcs_revision(void) uint32_t 586 tools/testing/selftests/kvm/include/x86_64/vmx.h uint64_t nested_paddr, uint64_t paddr, uint32_t eptp_memslot); uint32_t 589 tools/testing/selftests/kvm/include/x86_64/vmx.h uint32_t eptp_memslot); uint32_t 591 tools/testing/selftests/kvm/include/x86_64/vmx.h uint32_t memslot, uint32_t eptp_memslot); uint32_t 593 tools/testing/selftests/kvm/include/x86_64/vmx.h uint32_t eptp_memslot); uint32_t 77 tools/testing/selftests/kvm/lib/aarch64/processor.c void virt_pgd_alloc(struct kvm_vm *vm, uint32_t pgd_memslot) uint32_t 89 tools/testing/selftests/kvm/lib/aarch64/processor.c uint32_t pgd_memslot, uint64_t flags) uint32_t 141 tools/testing/selftests/kvm/lib/aarch64/processor.c uint32_t pgd_memslot) uint32_t 223 tools/testing/selftests/kvm/lib/aarch64/processor.c struct kvm_vm *vm_create_default(uint32_t vcpuid, uint64_t extra_mem_pages, uint32_t 305 tools/testing/selftests/kvm/lib/aarch64/processor.c void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent) uint32_t 316 tools/testing/selftests/kvm/lib/aarch64/processor.c void aarch64_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 332 tools/testing/selftests/kvm/lib/aarch64/processor.c void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code) uint32_t 92 tools/testing/selftests/kvm/lib/aarch64/ucall.c uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc) uint32_t 115 tools/testing/selftests/kvm/lib/elf.c uint32_t data_memslot, uint32_t pgd_memslot) uint32_t 288 tools/testing/selftests/kvm/lib/kvm_util.c uint64_t first_page, uint32_t num_pages) uint32_t 381 tools/testing/selftests/kvm/lib/kvm_util.c struct vcpu *vcpu_find(struct kvm_vm *vm, uint32_t vcpuid) uint32_t 406 tools/testing/selftests/kvm/lib/kvm_util.c static void vm_vcpu_rm(struct kvm_vm *vm, uint32_t vcpuid) uint32_t 577 tools/testing/selftests/kvm/lib/kvm_util.c uint64_t guest_paddr, uint32_t slot, uint64_t npages, uint32_t 578 tools/testing/selftests/kvm/lib/kvm_util.c uint32_t flags) uint32_t 709 tools/testing/selftests/kvm/lib/kvm_util.c memslot2region(struct kvm_vm *vm, uint32_t memslot) uint32_t 743 tools/testing/selftests/kvm/lib/kvm_util.c void vm_mem_region_set_flags(struct kvm_vm *vm, uint32_t slot, uint32_t flags) uint32_t 804 tools/testing/selftests/kvm/lib/kvm_util.c void vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpuid) uint32_t 949 tools/testing/selftests/kvm/lib/kvm_util.c uint32_t data_memslot, uint32_t pgd_memslot) uint32_t 996 tools/testing/selftests/kvm/lib/kvm_util.c size_t size, uint32_t pgd_memslot) uint32_t 1117 tools/testing/selftests/kvm/lib/kvm_util.c struct kvm_run *vcpu_state(struct kvm_vm *vm, uint32_t vcpuid) uint32_t 1139 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_run(struct kvm_vm *vm, uint32_t vcpuid) uint32_t 1146 tools/testing/selftests/kvm/lib/kvm_util.c int _vcpu_run(struct kvm_vm *vm, uint32_t vcpuid) uint32_t 1158 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_run_complete_io(struct kvm_vm *vm, uint32_t vcpuid) uint32_t 1189 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_set_mp_state(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 1217 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_regs_get(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_regs *regs) uint32_t 1244 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_regs_set(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_regs *regs) uint32_t 1257 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_events_get(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 1270 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_events_set(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 1285 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_nested_state_get(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 1299 tools/testing/selftests/kvm/lib/kvm_util.c int vcpu_nested_state_set(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 1333 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_sregs_get(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_sregs *sregs) uint32_t 1360 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_sregs_set(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_sregs *sregs) uint32_t 1367 tools/testing/selftests/kvm/lib/kvm_util.c int _vcpu_sregs_set(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_sregs *sregs) uint32_t 1389 tools/testing/selftests/kvm/lib/kvm_util.c void vcpu_ioctl(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 1399 tools/testing/selftests/kvm/lib/kvm_util.c int _vcpu_ioctl(struct kvm_vm *vm, uint32_t vcpuid, uint32_t 1558 tools/testing/selftests/kvm/lib/kvm_util.c vm_paddr_t paddr_min, uint32_t memslot) uint32_t 1598 tools/testing/selftests/kvm/lib/kvm_util.c uint32_t memslot) uint32_t 39 tools/testing/selftests/kvm/lib/kvm_util_internal.h uint32_t id; uint32_t 66 tools/testing/selftests/kvm/lib/kvm_util_internal.h struct vcpu *vcpu_find(struct kvm_vm *vm, uint32_t vcpuid); uint32_t 72 tools/testing/selftests/kvm/lib/kvm_util_internal.h memslot2region(struct kvm_vm *vm, uint32_t memslot); uint32_t 18 tools/testing/selftests/kvm/lib/s390x/processor.c void virt_pgd_alloc(struct kvm_vm *vm, uint32_t memslot) uint32_t 41 tools/testing/selftests/kvm/lib/s390x/processor.c static uint64_t virt_alloc_region(struct kvm_vm *vm, int ri, uint32_t memslot) uint32_t 71 tools/testing/selftests/kvm/lib/s390x/processor.c uint32_t memslot) uint32_t 214 tools/testing/selftests/kvm/lib/s390x/processor.c struct kvm_vm *vm_create_default(uint32_t vcpuid, uint64_t extra_mem_pages, uint32_t 241 tools/testing/selftests/kvm/lib/s390x/processor.c void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code) uint32_t 272 tools/testing/selftests/kvm/lib/s390x/processor.c void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent) uint32_t 36 tools/testing/selftests/kvm/lib/s390x/ucall.c uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc) uint32_t 165 tools/testing/selftests/kvm/lib/sparsebit.c typedef uint32_t mask_t; uint32_t 229 tools/testing/selftests/kvm/lib/x86_64/processor.c void virt_pgd_alloc(struct kvm_vm *vm, uint32_t pgd_memslot) uint32_t 259 tools/testing/selftests/kvm/lib/x86_64/processor.c uint32_t pgd_memslot) uint32_t 649 tools/testing/selftests/kvm/lib/x86_64/processor.c void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code) uint32_t 749 tools/testing/selftests/kvm/lib/x86_64/processor.c kvm_get_supported_cpuid_index(uint32_t function, uint32_t index) uint32_t 783 tools/testing/selftests/kvm/lib/x86_64/processor.c uint32_t vcpuid, struct kvm_cpuid2 *cpuid) uint32_t 810 tools/testing/selftests/kvm/lib/x86_64/processor.c struct kvm_vm *vm_create_default(uint32_t vcpuid, uint64_t extra_mem_pages, uint32_t 853 tools/testing/selftests/kvm/lib/x86_64/processor.c uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index) uint32_t 886 tools/testing/selftests/kvm/lib/x86_64/processor.c void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index, uint32_t 922 tools/testing/selftests/kvm/lib/x86_64/processor.c void vcpu_args_set(struct kvm_vm *vm, uint32_t vcpuid, unsigned int num, ...) uint32_t 972 tools/testing/selftests/kvm/lib/x86_64/processor.c void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent) uint32_t 1016 tools/testing/selftests/kvm/lib/x86_64/processor.c struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid) uint32_t 1099 tools/testing/selftests/kvm/lib/x86_64/processor.c void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_x86_state *state) uint32_t 1148 tools/testing/selftests/kvm/lib/x86_64/processor.c const uint32_t *chunk; uint32_t 1157 tools/testing/selftests/kvm/lib/x86_64/processor.c chunk = (const uint32_t *)("GenuineIntel"); uint32_t 1161 tools/testing/selftests/kvm/lib/x86_64/processor.c uint32_t kvm_get_cpuid_max(void) uint32_t 38 tools/testing/selftests/kvm/lib/x86_64/ucall.c uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc) uint32_t 170 tools/testing/selftests/kvm/lib/x86_64/vmx.c *(uint32_t *)(vmx->vmxon) = vmcs_revision(); uint32_t 181 tools/testing/selftests/kvm/lib/x86_64/vmx.c *(uint32_t *)(vmx->vmcs) = vmcs_revision(); uint32_t 189 tools/testing/selftests/kvm/lib/x86_64/vmx.c *(uint32_t *)(vmx->shadow_vmcs) = uint32_t 208 tools/testing/selftests/kvm/lib/x86_64/vmx.c uint32_t sec_exec_ctl = 0; uint32_t 268 tools/testing/selftests/kvm/lib/x86_64/vmx.c uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS); uint32_t 393 tools/testing/selftests/kvm/lib/x86_64/vmx.c uint64_t nested_paddr, uint64_t paddr, uint32_t eptp_memslot) uint32_t 493 tools/testing/selftests/kvm/lib/x86_64/vmx.c uint32_t eptp_memslot) uint32_t 512 tools/testing/selftests/kvm/lib/x86_64/vmx.c uint32_t memslot, uint32_t eptp_memslot) uint32_t 534 tools/testing/selftests/kvm/lib/x86_64/vmx.c uint32_t eptp_memslot) uint32_t 29 tools/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c uint32_t eax, ebx, ecx, edx; uint32_t 87 tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c uint32_t control; uint32_t 48 tools/testing/selftests/net/ip_defrag.c static uint32_t ip_id = 0xabcd; uint32_t 82 tools/testing/selftests/net/ip_defrag.c static uint32_t raw_checksum(uint8_t *buf, int len, uint32_t sum) uint32_t 103 tools/testing/selftests/net/ip_defrag.c uint32_t sum = 0; uint32_t 107 tools/testing/selftests/net/ip_defrag.c IPPROTO_UDP + (uint32_t)(UDP_HLEN + payload_len)); uint32_t 119 tools/testing/selftests/net/ip_defrag.c uint32_t sum = 0; uint32_t 33 tools/testing/selftests/net/ipv6_flowlabel.c #define FLOWLABEL_WILDCARD ((uint32_t) -1) uint32_t 36 tools/testing/selftests/net/ipv6_flowlabel.c static uint32_t cfg_label = 1; uint32_t 38 tools/testing/selftests/net/ipv6_flowlabel.c static void do_send(int fd, bool with_flowlabel, uint32_t flowlabel) uint32_t 58 tools/testing/selftests/net/ipv6_flowlabel.c *(uint32_t *)CMSG_DATA(cm) = htonl(flowlabel); uint32_t 74 tools/testing/selftests/net/ipv6_flowlabel.c static void do_recv(int fd, bool with_flowlabel, uint32_t expect) uint32_t 81 tools/testing/selftests/net/ipv6_flowlabel.c uint32_t flowlabel; uint32_t 114 tools/testing/selftests/net/ipv6_flowlabel.c flowlabel = ntohl(*(uint32_t *)CMSG_DATA(cm)); uint32_t 147 tools/testing/selftests/net/ipv6_flowlabel.c static void flowlabel_get(int fd, uint32_t label, uint8_t share, uint16_t flags) uint32_t 48 tools/testing/selftests/net/ipv6_flowlabel_mgr.c static int flowlabel_get(int fd, uint32_t label, uint8_t share, uint16_t flags) uint32_t 64 tools/testing/selftests/net/ipv6_flowlabel_mgr.c static int flowlabel_put(int fd, uint32_t label) uint32_t 97 tools/testing/selftests/net/msg_zerocopy.c static uint32_t next_completion; uint32_t 171 tools/testing/selftests/net/msg_zerocopy.c static void add_zcopy_cookie(struct msghdr *msg, uint32_t cookie) uint32_t 187 tools/testing/selftests/net/msg_zerocopy.c static uint32_t cookie; uint32_t 347 tools/testing/selftests/net/msg_zerocopy.c static uint32_t do_process_zerocopy_cookies(struct rds_zcopy_cookies *ck) uint32_t 398 tools/testing/selftests/net/msg_zerocopy.c uint32_t hi, lo, range; uint32_t 422 tools/testing/selftests/net/nettest.c static int set_membership(int sd, uint32_t grp, uint32_t addr, int ifindex) uint32_t 424 tools/testing/selftests/net/nettest.c uint32_t if_addr = addr; uint32_t 777 tools/testing/selftests/net/nettest.c const uint32_t *pa = (uint32_t *) &in6->s6_addr; uint32_t 1009 tools/testing/selftests/net/nettest.c uint32_t if_addr = htonl(INADDR_ANY); uint32_t 136 tools/testing/selftests/net/psock_snd.c const int alen = sizeof(uint32_t); uint32_t 80 tools/testing/selftests/net/psock_tpacket.c uint32_t version; uint32_t 81 tools/testing/selftests/net/psock_tpacket.c uint32_t offset_to_priv; uint32_t 523 tools/testing/selftests/net/psock_tpacket.c static void __v3_test_block_len(struct block_desc *pbd, uint32_t bytes, int block_num) uint32_t 220 tools/testing/selftests/net/reuseport_bpf.c uint32_t data, ndata; uint32_t 51 tools/testing/selftests/net/tcp_fastopen_backup_key.c static void get_keys(int fd, uint32_t *keys) uint32_t 69 tools/testing/selftests/net/tcp_fastopen_backup_key.c static void set_keys(int fd, uint32_t *keys) uint32_t 98 tools/testing/selftests/net/tcp_fastopen_backup_key.c uint32_t keys[8]; uint32_t 216 tools/testing/selftests/net/tcp_fastopen_backup_key.c static uint32_t new_key[4]; uint32_t 217 tools/testing/selftests/net/tcp_fastopen_backup_key.c uint32_t keys[8]; uint32_t 218 tools/testing/selftests/net/tcp_fastopen_backup_key.c uint32_t tmp_key[4]; uint32_t 68 tools/testing/selftests/net/udpgso_bench_tx.c static uint32_t cfg_tx_ts = SOF_TIMESTAMPING_TX_SOFTWARE; uint32_t 300 tools/testing/selftests/net/udpgso_bench_tx.c uint32_t *valp; uint32_t 123 tools/testing/selftests/networking/timestamping/txtimestamp.c uint32_t key, int payload_len) uint32_t 387 tools/testing/selftests/networking/timestamping/txtimestamp.c char control[CMSG_SPACE(sizeof(uint32_t))]; uint32_t 518 tools/testing/selftests/networking/timestamping/txtimestamp.c cmsg->cmsg_len = CMSG_LEN(sizeof(uint32_t)); uint32_t 520 tools/testing/selftests/networking/timestamping/txtimestamp.c *((uint32_t *) CMSG_DATA(cmsg)) = report_opt; uint32_t 31 tools/testing/selftests/powerpc/cache_shape/cache_shape.c static void print_size(const char *label, uint32_t val) uint32_t 36 tools/testing/selftests/powerpc/cache_shape/cache_shape.c static void print_geo(const char *label, uint32_t val) uint32_t 64 tools/testing/selftests/powerpc/cache_shape/cache_shape.c print_size("L1I ", (uint32_t)p->a_un.a_val); uint32_t 70 tools/testing/selftests/powerpc/cache_shape/cache_shape.c print_geo("L1I ", (uint32_t)p->a_un.a_val); uint32_t 76 tools/testing/selftests/powerpc/cache_shape/cache_shape.c print_size("L1D ", (uint32_t)p->a_un.a_val); uint32_t 82 tools/testing/selftests/powerpc/cache_shape/cache_shape.c print_geo("L1D ", (uint32_t)p->a_un.a_val); uint32_t 88 tools/testing/selftests/powerpc/cache_shape/cache_shape.c print_size("L2 ", (uint32_t)p->a_un.a_val); uint32_t 94 tools/testing/selftests/powerpc/cache_shape/cache_shape.c print_geo("L2 ", (uint32_t)p->a_un.a_val); uint32_t 100 tools/testing/selftests/powerpc/cache_shape/cache_shape.c print_size("L3 ", (uint32_t)p->a_un.a_val); uint32_t 106 tools/testing/selftests/powerpc/cache_shape/cache_shape.c print_geo("L3 ", (uint32_t)p->a_un.a_val); uint32_t 22 tools/testing/selftests/powerpc/include/utils.h typedef uint32_t u32; uint32_t 252 tools/testing/selftests/powerpc/pmu/ebb/ebb.c int count_pmc(int pmc, uint32_t sample_period) uint32_t 254 tools/testing/selftests/powerpc/pmu/ebb/ebb.c uint32_t start_value; uint32_t 36 tools/testing/selftests/powerpc/pmu/ebb/ebb.h static inline uint32_t pmc_sample_period(uint32_t value) uint32_t 60 tools/testing/selftests/powerpc/pmu/ebb/ebb.h int count_pmc(int pmc, uint32_t sample_period); uint32_t 33 tools/testing/selftests/prctl/disable-tsc-ctxt-sw-stress-test.c uint32_t lo, hi; uint32_t 35 tools/testing/selftests/prctl/disable-tsc-on-off-stress-test.c uint32_t lo, hi; uint32_t 35 tools/testing/selftests/prctl/disable-tsc-test.c uint32_t lo, hi; uint32_t 82 tools/testing/selftests/proc/proc-pid-vm.c uint32_t e_version; uint32_t 86 tools/testing/selftests/proc/proc-pid-vm.c uint32_t e_flags; uint32_t 96 tools/testing/selftests/proc/proc-pid-vm.c uint32_t p_type; uint32_t 97 tools/testing/selftests/proc/proc-pid-vm.c uint32_t p_flags; uint32_t 12 tools/testing/selftests/rcutorture/formal/srcu-cbmc/src/int_typedefs.h typedef uint32_t u32; uint32_t 21 tools/testing/selftests/rcutorture/formal/srcu-cbmc/src/int_typedefs.h typedef uint32_t __u32; uint32_t 581 tools/testing/selftests/rseq/rseq-arm.h uint32_t rseq_scratch[3]; uint32_t 705 tools/testing/selftests/rseq/rseq-arm.h uint32_t rseq_scratch[3]; uint32_t 1015 tools/testing/selftests/rseq/rseq-x86.h uint32_t rseq_scratch[3]; uint32_t 1127 tools/testing/selftests/rseq/rseq-x86.h uint32_t rseq_scratch[3]; uint32_t 48 tools/testing/selftests/rseq/rseq.c static __thread volatile uint32_t __rseq_refcount; uint32_t 70 tools/testing/selftests/rseq/rseq.c static int sys_rseq(volatile struct rseq *rseq_abi, uint32_t rseq_len, uint32_t 71 tools/testing/selftests/rseq/rseq.c int flags, uint32_t sig) uint32_t 125 tools/testing/selftests/rseq/rseq.h static inline uint32_t rseq_cpu_start(void) uint32_t 130 tools/testing/selftests/rseq/rseq.h static inline uint32_t rseq_current_cpu(void) uint32_t 65 tools/testing/selftests/x86/ldt_gdt.c uint32_t has_limit = 0, has_ar = 0, limit, ar; uint32_t 66 tools/testing/selftests/x86/ldt_gdt.c uint32_t selector = (index << 3) | (ldt << 2) | 3; uint32_t 92 tools/testing/selftests/x86/ldt_gdt.c uint32_t expected_ar, uint32_t expected_limit, uint32_t 95 tools/testing/selftests/x86/ldt_gdt.c uint32_t has_limit = 0, has_ar = 0, limit, ar; uint32_t 96 tools/testing/selftests/x86/ldt_gdt.c uint32_t selector = (index << 3) | (ldt << 2) | 3; uint32_t 139 tools/testing/selftests/x86/ldt_gdt.c static bool install_valid_mode(const struct user_desc *d, uint32_t ar, uint32_t 169 tools/testing/selftests/x86/ldt_gdt.c uint32_t limit = desc.limit; uint32_t 189 tools/testing/selftests/x86/ldt_gdt.c static bool install_valid(const struct user_desc *desc, uint32_t ar) uint32_t 192 tools/testing/selftests/x86/protection_keys.c #define u32 uint32_t uint32_t 44 tools/testing/selftests/x86/ptrace_syscall.c uint32_t nr, arg0, arg1, arg2, arg3, arg4, arg5; uint32_t 340 tools/testing/selftests/x86/sigreturn.c uint32_t valid = 0, ar; uint32_t 373 tools/testing/selftests/x86/sigreturn.c uint32_t valid = 0, ar; uint32_t 208 tools/usb/usbip/libsrc/usbip_common.c uint32_t busnum, devnum; uint32_t 115 tools/usb/usbip/libsrc/usbip_common.h uint32_t busnum; uint32_t 116 tools/usb/usbip/libsrc/usbip_common.h uint32_t devnum; uint32_t 117 tools/usb/usbip/libsrc/usbip_common.h uint32_t speed; uint32_t 335 tools/usb/usbip/libsrc/vhci_driver.c int usbip_vhci_get_free_port(uint32_t speed) uint32_t 357 tools/usb/usbip/libsrc/vhci_driver.c int usbip_vhci_attach_device2(uint8_t port, int sockfd, uint32_t devid, uint32_t 358 tools/usb/usbip/libsrc/vhci_driver.c uint32_t speed) { uint32_t 392 tools/usb/usbip/libsrc/vhci_driver.c uint8_t devnum, uint32_t speed) uint32_t 25 tools/usb/usbip/libsrc/vhci_driver.h uint32_t status; uint32_t 27 tools/usb/usbip/libsrc/vhci_driver.h uint32_t devid; uint32_t 55 tools/usb/usbip/libsrc/vhci_driver.h int usbip_vhci_get_free_port(uint32_t speed); uint32_t 56 tools/usb/usbip/libsrc/vhci_driver.h int usbip_vhci_attach_device2(uint8_t port, int sockfd, uint32_t devid, uint32_t 57 tools/usb/usbip/libsrc/vhci_driver.h uint32_t speed); uint32_t 61 tools/usb/usbip/libsrc/vhci_driver.h uint8_t devnum, uint32_t speed); uint32_t 85 tools/usb/usbip/src/usbip_attach.c uint32_t speed = udev->speed; uint32_t 53 tools/usb/usbip/src/usbip_network.c uint32_t usbip_net_pack_uint32_t(int pack, uint32_t num) uint32_t 55 tools/usb/usbip/src/usbip_network.c uint32_t i; uint32_t 140 tools/usb/usbip/src/usbip_network.c int usbip_net_send_op_common(int sockfd, uint32_t code, uint32_t status) uint32_t 31 tools/usb/usbip/src/usbip_network.h uint32_t status; /* op_code status (for reply) */ uint32_t 129 tools/usb/usbip/src/usbip_network.h uint32_t key[4]; uint32_t 133 tools/usb/usbip/src/usbip_network.h uint32_t __reserved; uint32_t 147 tools/usb/usbip/src/usbip_network.h uint32_t ndev; uint32_t 163 tools/usb/usbip/src/usbip_network.h uint32_t usbip_net_pack_uint32_t(int pack, uint32_t num); uint32_t 170 tools/usb/usbip/src/usbip_network.h int usbip_net_send_op_common(int sockfd, uint32_t code, uint32_t status); uint32_t 700 virt/kvm/arm/vgic/vgic-mmio-v3.c static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index, uint32_t 701 virt/kvm/arm/vgic/vgic-mmio-v3.c gpa_t base, uint32_t count) uint32_t 275 virt/kvm/eventfd.c uint32_t guest_irq, bool set)