tlb_op            328 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
tlb_op            329 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
tlb_op            330 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
tlb_op            342 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_FULL, "c8, c7, 0", zero);
tlb_op            359 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);
tlb_op            375 arch/arm/include/asm/tlbflush.h 			tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
tlb_op            376 arch/arm/include/asm/tlbflush.h 			tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
tlb_op            377 arch/arm/include/asm/tlbflush.h 			tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
tlb_op            381 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
tlb_op            382 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
tlb_op            383 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
tlb_op            395 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_ASID, "c8, c7, 2", asid);
tlb_op            410 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", 0);
tlb_op            412 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", ASID(mm));
tlb_op            429 arch/arm/include/asm/tlbflush.h 		tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
tlb_op            430 arch/arm/include/asm/tlbflush.h 		tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
tlb_op            431 arch/arm/include/asm/tlbflush.h 		tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
tlb_op            436 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
tlb_op            437 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
tlb_op            438 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
tlb_op            452 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", uaddr);
tlb_op            470 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
tlb_op            472 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr);
tlb_op            484 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
tlb_op            485 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
tlb_op            486 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
tlb_op            490 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
tlb_op            491 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
tlb_op            492 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
tlb_op            505 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", kaddr);
tlb_op            523 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);
tlb_op            581 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
tlb_op            592 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);