timing 314 arch/arm/mach-davinci/board-da830-evm.c .timing = &da830_evm_nandflash_timing, timing 245 arch/arm/mach-davinci/board-da850-evm.c .timing = &da850_evm_nandflash_timing, timing 166 arch/arm/mach-davinci/board-dm644x-evm.c .timing = &davinci_evm_nandflash_timing, timing 847 arch/arm/mach-davinci/board-dm646x-evm.c davinci_nand_data.timing = &dm6467tevm_nandflash_timing; timing 213 arch/arm/mach-davinci/board-omapl138-hawk.c .timing = &omapl138_hawk_nandflash_timing, timing 57 arch/mips/include/asm/mach-rc32434/rb.h u32 timing; timing 756 drivers/ata/ahci.c const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); timing 782 drivers/ata/ahci.c rc = sata_link_hardreset(link, timing, deadline, &online, timing 86 drivers/ata/ahci_qoriq.c const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); timing 124 drivers/ata/ahci_qoriq.c rc = sata_link_hardreset(link, timing, deadline, &online, timing 353 drivers/ata/ahci_xgene.c const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); timing 370 drivers/ata/ahci_xgene.c rc = sata_link_hardreset(link, timing, deadline, online, timing 1535 drivers/ata/libahci.c const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); timing 1552 drivers/ata/libahci.c rc = sata_link_hardreset(link, timing, deadline, online, timing 4006 drivers/ata/libata-core.c const unsigned long *timing = sata_ehc_deb_timing(ehc); timing 4015 drivers/ata/libata-core.c rc = sata_link_resume(link, timing, deadline); timing 4054 drivers/ata/libata-core.c int sata_link_hardreset(struct ata_link *link, const unsigned long *timing, timing 4098 drivers/ata/libata-core.c rc = sata_link_resume(link, timing, deadline); timing 4159 drivers/ata/libata-core.c const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); timing 4164 drivers/ata/libata-core.c rc = sata_link_hardreset(link, timing, deadline, &online, NULL); timing 2034 drivers/ata/libata-sff.c const unsigned long *timing = sata_ehc_deb_timing(ehc); timing 2038 drivers/ata/libata-sff.c rc = sata_link_hardreset(link, timing, deadline, &online, timing 103 drivers/ata/pata_artop.c const u16 timing[2][5] = { timing 109 drivers/ata/pata_artop.c pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); timing 157 drivers/ata/pata_artop.c const u8 timing[2][5] = { timing 163 drivers/ata/pata_artop.c pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]); timing 54 drivers/ata/pata_cmd640.c struct cmd640_reg *timing = ap->private_data; timing 116 drivers/ata/pata_cmd640.c timing->reg58[adev->devno] = (t.active << 4) | t.recover; timing 134 drivers/ata/pata_cmd640.c struct cmd640_reg *timing = ap->private_data; timing 136 drivers/ata/pata_cmd640.c if (ap->port_no != 0 && adev->devno != timing->last) { timing 137 drivers/ata/pata_cmd640.c pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); timing 138 drivers/ata/pata_cmd640.c timing->last = adev->devno; timing 154 drivers/ata/pata_cmd640.c struct cmd640_reg *timing; timing 156 drivers/ata/pata_cmd640.c timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL); timing 157 drivers/ata/pata_cmd640.c if (timing == NULL) timing 159 drivers/ata/pata_cmd640.c timing->last = -1; /* Force a load */ timing 160 drivers/ata/pata_cmd640.c ap->private_data = timing; timing 76 drivers/ata/pata_cs5530.c u32 tuning, timing = 0; timing 84 drivers/ata/pata_cs5530.c timing = 0x00921250;break; timing 86 drivers/ata/pata_cs5530.c timing = 0x00911140;break; timing 88 drivers/ata/pata_cs5530.c timing = 0x00911030;break; timing 90 drivers/ata/pata_cs5530.c timing = 0x00077771;break; timing 92 drivers/ata/pata_cs5530.c timing = 0x00012121;break; timing 94 drivers/ata/pata_cs5530.c timing = 0x00002020;break; timing 99 drivers/ata/pata_cs5530.c timing |= (tuning & 0x80000000UL); timing 101 drivers/ata/pata_cs5530.c iowrite32(timing, base + 0x04); timing 103 drivers/ata/pata_cs5530.c if (timing & 0x00100000) timing 108 drivers/ata/pata_cs5530.c iowrite32(timing, base + 0x0C); timing 33 drivers/ata/pata_hpt366.c u32 timing; timing 129 drivers/ata/pata_hpt366.c return clocks->timing; timing 33 drivers/ata/pata_hpt37x.c u32 timing; timing 217 drivers/ata/pata_hpt37x.c return clocks->timing; timing 413 drivers/ata/pata_hpt37x.c u32 reg, timing, mask; timing 433 drivers/ata/pata_hpt37x.c timing = hpt37x_find_mode(ap, mode); timing 436 drivers/ata/pata_hpt37x.c reg = (reg & ~mask) | (timing & mask); timing 507 drivers/ata/pata_hpt37x.c u32 reg, timing, mask; timing 526 drivers/ata/pata_hpt37x.c timing = hpt37x_find_mode(ap, mode); timing 529 drivers/ata/pata_hpt37x.c reg = (reg & ~mask) | (timing & mask); timing 40 drivers/ata/pata_hpt3x2n.c u32 timing; timing 110 drivers/ata/pata_hpt3x2n.c return clocks->timing; timing 187 drivers/ata/pata_hpt3x2n.c u32 reg, timing, mask; timing 206 drivers/ata/pata_hpt3x2n.c timing = hpt3x2n_find_mode(ap, mode); timing 209 drivers/ata/pata_hpt3x2n.c reg = (reg & ~mask) | (timing & mask); timing 58 drivers/ata/pata_imx.c struct ata_timing timing; timing 69 drivers/ata/pata_imx.c ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0); timing 75 drivers/ata/pata_imx.c writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1); timing 76 drivers/ata/pata_imx.c writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W); timing 77 drivers/ata/pata_imx.c writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R); timing 126 drivers/ata/pata_it821x.c static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing) timing 135 drivers/ata/pata_it821x.c conf = timing >> 8; timing 137 drivers/ata/pata_it821x.c conf = timing & 0xFF; timing 154 drivers/ata/pata_it821x.c static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing) timing 164 drivers/ata/pata_it821x.c conf = timing >> 8; timing 166 drivers/ata/pata_it821x.c conf = timing & 0xFF; timing 85 drivers/ata/pata_legacy.c unsigned long timing; timing 643 drivers/ata/pata_legacy.c u8 timing; timing 655 drivers/ata/pata_legacy.c timing = (recovery << 4) | active | 0x08; timing 656 drivers/ata/pata_legacy.c ld_qdi->clock[adev->devno] = timing; timing 659 drivers/ata/pata_legacy.c outb(timing, ld_qdi->timing + 2 * adev->devno); timing 661 drivers/ata/pata_legacy.c outb(timing, ld_qdi->timing + 2 * ap->port_no); timing 665 drivers/ata/pata_legacy.c outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); timing 685 drivers/ata/pata_legacy.c outb(ld_qdi->clock[adev->devno], ld_qdi->timing + timing 727 drivers/ata/pata_legacy.c ld->timing = lp->private; timing 781 drivers/ata/pata_legacy.c int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); timing 783 drivers/ata/pata_legacy.c reg = winbond_readcfg(ld_winbond->timing, 0x81); timing 793 drivers/ata/pata_legacy.c timing = (active << 4) | recovery; timing 794 drivers/ata/pata_legacy.c winbond_writecfg(ld_winbond->timing, timing, reg); timing 804 drivers/ata/pata_legacy.c winbond_writecfg(ld_winbond->timing, timing + 1, reg); timing 812 drivers/ata/pata_legacy.c ld->timing = lp->private; timing 271 drivers/ata/pata_mpc52xx.c struct mpc52xx_ata_timings *timing = &priv->timings[dev]; timing 286 drivers/ata/pata_mpc52xx.c timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i); timing 287 drivers/ata/pata_mpc52xx.c timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8); timing 333 drivers/ata/pata_mpc52xx.c struct mpc52xx_ata_timings *timing = &priv->timings[device]; timing 335 drivers/ata/pata_mpc52xx.c out_be32(®s->pio1, timing->pio1); timing 336 drivers/ata/pata_mpc52xx.c out_be32(®s->pio2, timing->pio2); timing 337 drivers/ata/pata_mpc52xx.c out_be32(®s->mdma1, timing->mdma1); timing 338 drivers/ata/pata_mpc52xx.c out_be32(®s->mdma2, timing->mdma2); timing 339 drivers/ata/pata_mpc52xx.c out_be32(®s->udma1, timing->udma1); timing 340 drivers/ata/pata_mpc52xx.c out_be32(®s->udma2, timing->udma2); timing 341 drivers/ata/pata_mpc52xx.c out_be32(®s->udma3, timing->udma3); timing 342 drivers/ata/pata_mpc52xx.c out_be32(®s->udma4, timing->udma4); timing 343 drivers/ata/pata_mpc52xx.c out_be32(®s->udma5, timing->udma5); timing 57 drivers/ata/pata_ns87415.c int timing = 0x44 + 2 * unit; timing 73 drivers/ata/pata_ns87415.c pci_write_config_word(dev, timing, clocking); timing 134 drivers/ata/pata_octeon_cf.c struct ata_timing timing; timing 153 drivers/ata/pata_octeon_cf.c BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T)); timing 155 drivers/ata/pata_octeon_cf.c t2 = timing.active; timing 163 drivers/ata/pata_octeon_cf.c pause = (int)timing.cycle - (int)timing.active - timing 164 drivers/ata/pata_octeon_cf.c (int)timing.setup - trh; timing 228 drivers/ata/pata_octeon_cf.c const struct ata_timing *timing; timing 230 drivers/ata/pata_octeon_cf.c timing = ata_timing_find_mode(dev->dma_mode); timing 231 drivers/ata/pata_octeon_cf.c T0 = timing->cycle; timing 232 drivers/ata/pata_octeon_cf.c Td = timing->active; timing 233 drivers/ata/pata_octeon_cf.c Tkr = timing->recover; timing 234 drivers/ata/pata_octeon_cf.c dma_ackh = timing->dmack_hold; timing 106 drivers/ata/pata_samsung_cf.c struct ata_timing timing; timing 119 drivers/ata/pata_samsung_cf.c ata_timing_compute(adev, adev->pio_mode, &timing, timing 122 drivers/ata/pata_samsung_cf.c piotime = pata_s3c_setup_timing(info, &timing); timing 342 drivers/ata/pata_sis.c u16 timing; timing 347 drivers/ata/pata_sis.c pci_read_config_word(pdev, drive_pci, &timing); timing 352 drivers/ata/pata_sis.c timing &= ~0x870F; timing 353 drivers/ata/pata_sis.c timing |= mwdma_bits[speed]; timing 357 drivers/ata/pata_sis.c timing &= ~0x6000; timing 358 drivers/ata/pata_sis.c timing |= udma_bits[speed]; timing 360 drivers/ata/pata_sis.c pci_write_config_word(pdev, drive_pci, timing); timing 381 drivers/ata/pata_sis.c u16 timing; timing 387 drivers/ata/pata_sis.c pci_read_config_word(pdev, drive_pci, &timing); timing 392 drivers/ata/pata_sis.c timing &= ~0x870F; timing 393 drivers/ata/pata_sis.c timing |= mwdma_bits[speed]; timing 397 drivers/ata/pata_sis.c timing &= ~0xF000; timing 398 drivers/ata/pata_sis.c timing |= udma_bits[speed]; timing 400 drivers/ata/pata_sis.c pci_write_config_word(pdev, drive_pci, timing); timing 420 drivers/ata/pata_sis.c u8 timing; timing 424 drivers/ata/pata_sis.c pci_read_config_byte(pdev, drive_pci + 1, &timing); timing 431 drivers/ata/pata_sis.c timing &= ~0x8F; timing 432 drivers/ata/pata_sis.c timing |= udma_bits[speed]; timing 434 drivers/ata/pata_sis.c pci_write_config_byte(pdev, drive_pci + 1, timing); timing 454 drivers/ata/pata_sis.c u8 timing; timing 458 drivers/ata/pata_sis.c pci_read_config_byte(pdev, drive_pci + 1, &timing); timing 465 drivers/ata/pata_sis.c timing &= ~0x8F; timing 466 drivers/ata/pata_sis.c timing |= udma_bits[speed]; timing 468 drivers/ata/pata_sis.c pci_write_config_byte(pdev, drive_pci + 1, timing); timing 85 drivers/ata/pata_sl82c105.c int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); timing 87 drivers/ata/pata_sl82c105.c pci_write_config_word(pdev, timing, pio_timing[pio]); timing 89 drivers/ata/pata_sl82c105.c pci_read_config_word(pdev, timing, &dummy); timing 122 drivers/ata/pata_sl82c105.c int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); timing 125 drivers/ata/pata_sl82c105.c pci_write_config_word(pdev, timing, dma_timing[dma]); timing 127 drivers/ata/pata_sl82c105.c pci_read_config_word(pdev, timing, &dummy); timing 76 drivers/ata/pata_triflex.c u32 timing = 0; timing 88 drivers/ata/pata_triflex.c timing = 0x0103;break; timing 90 drivers/ata/pata_triflex.c timing = 0x0203;break; timing 92 drivers/ata/pata_triflex.c timing = 0x0808;break; timing 96 drivers/ata/pata_triflex.c timing = 0x0F0F;break; timing 98 drivers/ata/pata_triflex.c timing = 0x0202;break; timing 100 drivers/ata/pata_triflex.c timing = 0x0204;break; timing 102 drivers/ata/pata_triflex.c timing = 0x0404;break; timing 104 drivers/ata/pata_triflex.c timing = 0x0508;break; timing 106 drivers/ata/pata_triflex.c timing = 0x0808;break; timing 111 drivers/ata/pata_triflex.c triflex_timing |= (timing << (16 * is_slave)); timing 514 drivers/ata/pata_via.c u32 timing; timing 521 drivers/ata/pata_via.c pci_read_config_dword(pdev, 0x50, &timing); timing 522 drivers/ata/pata_via.c timing |= 0x80008; timing 523 drivers/ata/pata_via.c pci_write_config_dword(pdev, 0x50, timing); timing 527 drivers/ata/pata_via.c pci_read_config_dword(pdev, 0x50, &timing); timing 528 drivers/ata/pata_via.c timing &= ~0x80008; timing 529 drivers/ata/pata_via.c pci_write_config_dword(pdev, 0x50, timing); timing 388 drivers/ata/sata_highbank.c static const unsigned long timing[] = { 5, 100, 500}; timing 408 drivers/ata/sata_highbank.c rc = sata_link_hardreset(link, timing, deadline, &online, NULL); timing 624 drivers/ata/sata_inic162x.c const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); timing 635 drivers/ata/sata_inic162x.c rc = sata_link_resume(link, timing, deadline); timing 3635 drivers/ata/sata_mv.c const unsigned long *timing = timing 3638 drivers/ata/sata_mv.c rc = sata_link_hardreset(link, timing, deadline + extra, timing 1539 drivers/ata/sata_nv.c const unsigned long *timing = sata_ehc_deb_timing(ehc); timing 1547 drivers/ata/sata_nv.c rc = sata_link_resume(link, timing, deadline); timing 116 drivers/clk/tegra/clk-emc.c struct emc_timing *timing = NULL; timing 132 drivers/clk/tegra/clk-emc.c timing = tegra->timings + i; timing 134 drivers/clk/tegra/clk-emc.c if (timing->rate < req->rate && i != t - 1) timing 137 drivers/clk/tegra/clk-emc.c if (timing->rate > req->max_rate) { timing 143 drivers/clk/tegra/clk-emc.c if (timing->rate < req->min_rate) timing 146 drivers/clk/tegra/clk-emc.c req->rate = timing->rate; timing 150 drivers/clk/tegra/clk-emc.c if (timing) { timing 151 drivers/clk/tegra/clk-emc.c req->rate = timing->rate; timing 202 drivers/clk/tegra/clk-emc.c struct emc_timing *timing) timing 213 drivers/clk/tegra/clk-emc.c pr_debug("going to rate %ld prate %ld p %s\n", timing->rate, timing 214 drivers/clk/tegra/clk-emc.c timing->parent_rate, __clk_get_name(timing->parent)); timing 216 drivers/clk/tegra/clk-emc.c if (emc_get_parent(&tegra->hw) == timing->parent_index && timing 217 drivers/clk/tegra/clk-emc.c clk_get_rate(timing->parent) != timing->parent_rate) { timing 219 drivers/clk/tegra/clk-emc.c __clk_get_name(timing->parent), timing 220 drivers/clk/tegra/clk-emc.c clk_get_rate(timing->parent), timing 221 drivers/clk/tegra/clk-emc.c timing->parent_rate); timing 227 drivers/clk/tegra/clk-emc.c err = clk_set_rate(timing->parent, timing->parent_rate); timing 230 drivers/clk/tegra/clk-emc.c __clk_get_name(timing->parent), timing->parent_rate, timing 236 drivers/clk/tegra/clk-emc.c err = clk_prepare_enable(timing->parent); timing 242 drivers/clk/tegra/clk-emc.c div = timing->parent_rate / (timing->rate / 2) - 2; timing 244 drivers/clk/tegra/clk-emc.c err = tegra_emc_prepare_timing_change(emc, timing->rate); timing 253 drivers/clk/tegra/clk-emc.c car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index); timing 262 drivers/clk/tegra/clk-emc.c tegra_emc_complete_timing_change(emc, timing->rate); timing 264 drivers/clk/tegra/clk-emc.c clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); timing 267 drivers/clk/tegra/clk-emc.c tegra->prev_parent = timing->parent; timing 284 drivers/clk/tegra/clk-emc.c struct emc_timing *timing; timing 287 drivers/clk/tegra/clk-emc.c timing = tegra->timings + i; timing 288 drivers/clk/tegra/clk-emc.c if (timing->ram_code != ram_code) timing 291 drivers/clk/tegra/clk-emc.c if (emc_parent_clk_sources[timing->parent_index] != timing 294 drivers/clk/tegra/clk-emc.c return timing; timing 298 drivers/clk/tegra/clk-emc.c timing = tegra->timings + i; timing 299 drivers/clk/tegra/clk-emc.c if (timing->ram_code != ram_code) timing 302 drivers/clk/tegra/clk-emc.c if (emc_parent_clk_sources[timing->parent_index] != timing 305 drivers/clk/tegra/clk-emc.c return timing; timing 315 drivers/clk/tegra/clk-emc.c struct emc_timing *timing = NULL; timing 335 drivers/clk/tegra/clk-emc.c timing = tegra->timings + i; timing 340 drivers/clk/tegra/clk-emc.c if (!timing) { timing 346 drivers/clk/tegra/clk-emc.c emc_parent_clk_sources[timing->parent_index] && timing 347 drivers/clk/tegra/clk-emc.c clk_get_rate(timing->parent) != timing->parent_rate) { timing 371 drivers/clk/tegra/clk-emc.c return emc_set_timing(tegra, timing); timing 377 drivers/clk/tegra/clk-emc.c struct emc_timing *timing, timing 389 drivers/clk/tegra/clk-emc.c timing->rate = tmp; timing 397 drivers/clk/tegra/clk-emc.c timing->parent_rate = tmp; timing 399 drivers/clk/tegra/clk-emc.c timing->parent = of_clk_get_by_name(node, "emc-parent"); timing 400 drivers/clk/tegra/clk-emc.c if (IS_ERR(timing->parent)) { timing 402 drivers/clk/tegra/clk-emc.c return PTR_ERR(timing->parent); timing 405 drivers/clk/tegra/clk-emc.c timing->parent_index = 0xff; timing 408 drivers/clk/tegra/clk-emc.c __clk_get_name(timing->parent))) { timing 409 drivers/clk/tegra/clk-emc.c timing->parent_index = i; timing 413 drivers/clk/tegra/clk-emc.c if (timing->parent_index == 0xff) { timing 415 drivers/clk/tegra/clk-emc.c node, __clk_get_name(timing->parent)); timing 416 drivers/clk/tegra/clk-emc.c clk_put(timing->parent); timing 456 drivers/clk/tegra/clk-emc.c struct emc_timing *timing = timings_ptr + (i++); timing 458 drivers/clk/tegra/clk-emc.c err = load_one_timing_from_dt(tegra, timing, child); timing 464 drivers/clk/tegra/clk-emc.c timing->ram_code = ram_code; timing 65 drivers/devfreq/rk3399_dmc.c struct dram_timing timing; timing 239 drivers/devfreq/rk3399_dmc.c static int of_get_ddr_timings(struct dram_timing *timing, timing 245 drivers/devfreq/rk3399_dmc.c &timing->ddr3_speed_bin); timing 247 drivers/devfreq/rk3399_dmc.c &timing->pd_idle); timing 249 drivers/devfreq/rk3399_dmc.c &timing->sr_idle); timing 251 drivers/devfreq/rk3399_dmc.c &timing->sr_mc_gate_idle); timing 253 drivers/devfreq/rk3399_dmc.c &timing->srpd_lite_idle); timing 255 drivers/devfreq/rk3399_dmc.c &timing->standby_idle); timing 257 drivers/devfreq/rk3399_dmc.c &timing->auto_pd_dis_freq); timing 259 drivers/devfreq/rk3399_dmc.c &timing->dram_dll_dis_freq); timing 261 drivers/devfreq/rk3399_dmc.c &timing->phy_dll_dis_freq); timing 263 drivers/devfreq/rk3399_dmc.c &timing->ddr3_odt_dis_freq); timing 265 drivers/devfreq/rk3399_dmc.c &timing->ddr3_drv); timing 267 drivers/devfreq/rk3399_dmc.c &timing->ddr3_odt); timing 269 drivers/devfreq/rk3399_dmc.c &timing->phy_ddr3_ca_drv); timing 271 drivers/devfreq/rk3399_dmc.c &timing->phy_ddr3_dq_drv); timing 273 drivers/devfreq/rk3399_dmc.c &timing->phy_ddr3_odt); timing 275 drivers/devfreq/rk3399_dmc.c &timing->lpddr3_odt_dis_freq); timing 277 drivers/devfreq/rk3399_dmc.c &timing->lpddr3_drv); timing 279 drivers/devfreq/rk3399_dmc.c &timing->lpddr3_odt); timing 281 drivers/devfreq/rk3399_dmc.c &timing->phy_lpddr3_ca_drv); timing 283 drivers/devfreq/rk3399_dmc.c &timing->phy_lpddr3_dq_drv); timing 285 drivers/devfreq/rk3399_dmc.c &timing->phy_lpddr3_odt); timing 287 drivers/devfreq/rk3399_dmc.c &timing->lpddr4_odt_dis_freq); timing 289 drivers/devfreq/rk3399_dmc.c &timing->lpddr4_drv); timing 291 drivers/devfreq/rk3399_dmc.c &timing->lpddr4_dq_odt); timing 293 drivers/devfreq/rk3399_dmc.c &timing->lpddr4_ca_odt); timing 295 drivers/devfreq/rk3399_dmc.c &timing->phy_lpddr4_ca_drv); timing 297 drivers/devfreq/rk3399_dmc.c &timing->phy_lpddr4_ck_cs_drv); timing 299 drivers/devfreq/rk3399_dmc.c &timing->phy_lpddr4_dq_drv); timing 301 drivers/devfreq/rk3399_dmc.c &timing->phy_lpddr4_odt); timing 313 drivers/devfreq/rk3399_dmc.c uint32_t *timing; timing 357 drivers/devfreq/rk3399_dmc.c if (!of_get_ddr_timings(&data->timing, np)) { timing 358 drivers/devfreq/rk3399_dmc.c timing = &data->timing.ddr3_speed_bin; timing 361 drivers/devfreq/rk3399_dmc.c arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index, timing 385 drivers/devfreq/rk3399_dmc.c data->odt_dis_freq = data->timing.ddr3_odt_dis_freq; timing 388 drivers/devfreq/rk3399_dmc.c data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq; timing 391 drivers/devfreq/rk3399_dmc.c data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq; timing 416 drivers/devfreq/rk3399_dmc.c data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) | timing 417 drivers/devfreq/rk3399_dmc.c ((data->timing.sr_mc_gate_idle & 0xff) << 8) | timing 418 drivers/devfreq/rk3399_dmc.c ((data->timing.standby_idle & 0xffff) << 16); timing 419 drivers/devfreq/rk3399_dmc.c data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) | timing 420 drivers/devfreq/rk3399_dmc.c ((data->timing.srpd_lite_idle & 0xfff) << 16); timing 3144 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dst.width = stream->timing.h_addressable; timing 3145 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dst.height = stream->timing.v_addressable; timing 3164 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dst.x = (stream->timing.h_addressable - dst.width) / 2; timing 3165 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dst.y = (stream->timing.v_addressable - dst.height) / 2; timing 3328 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct dc_crtc_timing *timing_out = &stream->timing; timing 3354 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c timing_out->vic = old_stream->timing.vic; timing 3355 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; timing 3356 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; timing 3511 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ timing 3512 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); timing 3636 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c stream->timing.flags.DSC = 0; timing 3649 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &stream->timing, timing 3650 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &stream->timing.dsc_cfg)) timing 3651 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c stream->timing.flags.DSC = 1; timing 5517 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (!new_stream->timing.h_total || !new_stream->timing.v_total) timing 5593 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (!new_stream->timing.h_total || !new_stream->timing.v_total) timing 7528 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct detailed_timing *timing; timing 7578 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c timing = &edid->detailed_timings[i]; timing 7579 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c data = &timing->data.other_data; timing 708 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c switch (dm_crtc_state->stream->timing.display_color_depth) { timing 207 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c clock = stream->timing.pix_clk_100hz / 10; timing 209 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c switch (stream->timing.display_color_depth) { timing 2796 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); timing 2797 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); timing 2798 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_100hz, 10000); timing 2894 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); timing 2895 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); timing 2896 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c pixel_clock_100hz = pipe[i].stream->timing.pix_clk_100hz; timing 2897 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (pipe[i].stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) timing 2962 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable); timing 2964 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable); timing 411 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top timing 412 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c + pipe->stream->timing.v_border_bottom; timing 420 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.htotal = pipe->stream->timing.h_total; timing 421 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch; timing 423 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->stream->timing.h_addressable timing 424 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->stream->timing.h_border_left timing 425 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->stream->timing.h_border_right; timing 427 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.vtotal = pipe->stream->timing.v_total; timing 428 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch; timing 430 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->stream->timing.v_addressable timing 431 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->stream->timing.v_border_bottom timing 432 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->stream->timing.v_border_top; timing 433 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0; timing 705 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz); timing 877 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->htotal[input_idx] = pipe->stream->timing.h_total; timing 878 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->vtotal[input_idx] = pipe->stream->timing.v_total; timing 879 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->vactive[input_idx] = pipe->stream->timing.v_addressable + timing 880 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom; timing 881 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total timing 883 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->stream->timing.v_front_porch; timing 884 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0; timing 885 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) timing 892 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; timing 893 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->viewport_height[input_idx] = pipe->stream->timing.v_addressable; timing 1002 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->output_format[input_idx] = pipe->stream->timing.pixel_encoding == timing 1008 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c switch (pipe->stream->timing.display_color_depth) { timing 1186 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; timing 1187 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; timing 1188 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c vesa_sync_start = pipe->stream->timing.v_addressable + timing 1189 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->stream->timing.v_border_bottom + timing 1190 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->stream->timing.v_front_porch; timing 1192 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c asic_blank_end = (pipe->stream->timing.v_total - timing 1194 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->stream->timing.v_border_top) timing 1195 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); timing 1198 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c (pipe->stream->timing.v_border_top + timing 1199 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->stream->timing.v_addressable + timing 1200 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->stream->timing.v_border_bottom) timing 1201 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); timing 1216 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c (pipe->stream->timing.timing_3d_format == timing 1218 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->stream->timing.timing_3d_format == timing 1227 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; timing 1228 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; timing 101 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c uint32_t vertical_total_min = stream->timing.v_total; timing 106 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c vertical_blank_in_pixels = stream->timing.h_total * timing 108 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c - stream->timing.v_addressable); timing 110 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c * 10000 / stream->timing.pix_clk_100hz; timing 163 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c cfg->v_refresh = stream->timing.pix_clk_100hz * 100; timing 164 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c cfg->v_refresh /= stream->timing.h_total; timing 165 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) timing 166 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c / stream->timing.v_total; timing 236 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c const struct dc_crtc_timing *timing = timing 237 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c &context->streams[0]->timing; timing 241 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; timing 362 drivers/gpu/drm/amd/display/dc/core/dc.c param.windowa_x_end = pipe->stream->timing.h_addressable; timing 363 drivers/gpu/drm/amd/display/dc/core/dc.c param.windowa_y_end = pipe->stream->timing.v_addressable; timing 366 drivers/gpu/drm/amd/display/dc/core/dc.c param.windowb_x_end = pipe->stream->timing.h_addressable; timing 367 drivers/gpu/drm/amd/display/dc/core/dc.c param.windowb_y_end = pipe->stream->timing.v_addressable; timing 1136 drivers/gpu/drm/amd/display/dc/core/dc.c context->streams[i]->timing.h_addressable, timing 1137 drivers/gpu/drm/amd/display/dc/core/dc.c context->streams[i]->timing.v_addressable, timing 1138 drivers/gpu/drm/amd/display/dc/core/dc.c context->streams[i]->timing.h_total, timing 1139 drivers/gpu/drm/amd/display/dc/core/dc.c context->streams[i]->timing.v_total, timing 1140 drivers/gpu/drm/amd/display/dc/core/dc.c context->streams[i]->timing.pix_clk_100hz / 10); timing 1877 drivers/gpu/drm/amd/display/dc/core/dc.c struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; timing 1878 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t old_dsc_enabled = stream->timing.flags.DSC; timing 1882 drivers/gpu/drm/amd/display/dc/core/dc.c stream->timing.dsc_cfg = *update->dsc_config; timing 1883 drivers/gpu/drm/amd/display/dc/core/dc.c stream->timing.flags.DSC = enable_dsc; timing 1886 drivers/gpu/drm/amd/display/dc/core/dc.c stream->timing.dsc_cfg = old_dsc_cfg; timing 1887 drivers/gpu/drm/amd/display/dc/core/dc.c stream->timing.flags.DSC = old_dsc_enabled; timing 340 drivers/gpu/drm/amd/display/dc/core/dc_debug.c pipe_ctx->stream->timing.h_total, timing 341 drivers/gpu/drm/amd/display/dc/core/dc_debug.c pipe_ctx->stream->timing.v_total, timing 2035 drivers/gpu/drm/amd/display/dc/core/dc_link.c bool is_vga_mode = (stream->timing.h_addressable == 640) timing 2036 drivers/gpu/drm/amd/display/dc/core/dc_link.c && (stream->timing.v_addressable == 480); timing 2039 drivers/gpu/drm/amd/display/dc/core/dc_link.c stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; timing 2067 drivers/gpu/drm/amd/display/dc/core/dc_link.c stream->timing.flags.LTE_340MCSC_SCRAMBLE); timing 2072 drivers/gpu/drm/amd/display/dc/core/dc_link.c display_color_depth = stream->timing.display_color_depth; timing 2073 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) timing 2093 drivers/gpu/drm/amd/display/dc/core/dc_link.c stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; timing 2185 drivers/gpu/drm/amd/display/dc/core/dc_link.c static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing) timing 2188 drivers/gpu/drm/amd/display/dc/core/dc_link.c uint32_t pxl_clk = timing->pix_clk_100hz; timing 2190 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) timing 2192 drivers/gpu/drm/amd/display/dc/core/dc_link.c else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) timing 2195 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (timing->display_color_depth == COLOR_DEPTH_101010) timing 2197 drivers/gpu/drm/amd/display/dc/core/dc_link.c else if (timing->display_color_depth == COLOR_DEPTH_121212) timing 2204 drivers/gpu/drm/amd/display/dc/core/dc_link.c const struct dc_crtc_timing *timing, timing 2213 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (timing->pixel_encoding == PIXEL_ENCODING_RGB) timing 2226 drivers/gpu/drm/amd/display/dc/core/dc_link.c switch (timing->pixel_encoding) { timing 2243 drivers/gpu/drm/amd/display/dc/core/dc_link.c switch (timing->display_color_depth) { timing 2263 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10)) timing 2272 drivers/gpu/drm/amd/display/dc/core/dc_link.c const struct dc_crtc_timing *timing) timing 2284 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk) timing 2288 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (!dp_active_dongle_validate_timing(timing, dpcd_caps)) timing 2296 drivers/gpu/drm/amd/display/dc/core/dc_link.c timing)) timing 2441 drivers/gpu/drm/amd/display/dc/core/dc_link.c kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing); timing 2688 drivers/gpu/drm/amd/display/dc/core/dc_link.c stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); timing 2694 drivers/gpu/drm/amd/display/dc/core/dc_link.c &stream->timing, timing 2701 drivers/gpu/drm/amd/display/dc/core/dc_link.c &stream->timing, timing 2710 drivers/gpu/drm/amd/display/dc/core/dc_link.c &stream->timing, timing 2717 drivers/gpu/drm/amd/display/dc/core/dc_link.c &stream->timing); timing 2772 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->timing.flags.DSC) { timing 2782 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->timing.flags.DSC) { timing 2847 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (pipe_ctx->stream->timing.flags.DSC) { timing 2914 drivers/gpu/drm/amd/display/dc/core/dc_link.c const struct dc_crtc_timing *timing) timing 2920 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (timing->flags.DSC) { timing 2921 drivers/gpu/drm/amd/display/dc/core/dc_link.c kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); timing 2927 drivers/gpu/drm/amd/display/dc/core/dc_link.c switch (timing->display_color_depth) { timing 2952 drivers/gpu/drm/amd/display/dc/core/dc_link.c kbps = timing->pix_clk_100hz / 10; timing 2955 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (timing->flags.Y_ONLY != 1) { timing 2958 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) timing 2960 drivers/gpu/drm/amd/display/dc/core/dc_link.c else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) timing 1866 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c const struct dc_crtc_timing *timing) timing 1874 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 && timing 1875 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c timing->h_addressable == (uint32_t) 640 && timing 1876 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c timing->v_addressable == (uint32_t) 480) timing 1887 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c req_bw = dc_bandwidth_in_kbps_from_timing(timing); timing 2007 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing); timing 3055 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c stream->timing.display_color_depth; timing 3059 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c int width = pipe_ctx->stream->timing.h_addressable + timing 3060 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->timing.h_border_left + timing 3061 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->timing.h_border_right; timing 3062 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c int height = pipe_ctx->stream->timing.v_addressable + timing 3063 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->timing.v_border_bottom + timing 3064 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c pipe_ctx->stream->timing.v_border_top; timing 91 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipes[i].stream->timing.pix_clk_100hz; timing 399 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; timing 400 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; timing 401 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; timing 402 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.color_depth = stream->timing.display_color_depth; timing 403 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; timing 467 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (!pipe_ctx->stream->timing.flags.DSC) timing 492 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (!pipe_ctx->stream->timing.flags.DSC || !dsc) timing 500 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; timing 501 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; timing 502 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; timing 503 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.color_depth = stream->timing.display_color_depth; timing 504 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; timing 531 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (!pipe_ctx->stream->timing.flags.DSC) timing 378 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (stream1->timing.h_total != stream2->timing.h_total) timing 381 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (stream1->timing.v_total != stream2->timing.v_total) timing 384 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (stream1->timing.h_addressable timing 385 drivers/gpu/drm/amd/display/dc/core/dc_resource.c != stream2->timing.h_addressable) timing 388 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (stream1->timing.v_addressable timing 389 drivers/gpu/drm/amd/display/dc/core/dc_resource.c != stream2->timing.v_addressable) timing 392 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (stream1->timing.pix_clk_100hz timing 393 drivers/gpu/drm/amd/display/dc/core/dc_resource.c != stream2->timing.pix_clk_100hz) timing 965 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; timing 990 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left; timing 991 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top; timing 993 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; timing 994 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; timing 1502 drivers/gpu/drm/amd/display/dc/core/dc_resource.c &cur_stream->timing, timing 1503 drivers/gpu/drm/amd/display/dc/core/dc_resource.c &new_stream->timing, timing 1807 drivers/gpu/drm/amd/display/dc/core/dc_resource.c static int get_norm_pix_clk(const struct dc_crtc_timing *timing) timing 1809 drivers/gpu/drm/amd/display/dc/core/dc_resource.c uint32_t pix_clk = timing->pix_clk_100hz; timing 1812 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) timing 1814 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { timing 1815 drivers/gpu/drm/amd/display/dc/core/dc_resource.c switch (timing->display_color_depth) { timing 1842 drivers/gpu/drm/amd/display/dc/core/dc_resource.c &stream->timing) / 10; timing 1845 drivers/gpu/drm/amd/display/dc/core/dc_resource.c stream->timing.pix_clk_100hz / 10; timing 1847 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) timing 1933 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing)) timing 2134 drivers/gpu/drm/amd/display/dc/core/dc_resource.c unsigned int vic = pipe_ctx->stream->timing.vic; timing 2141 drivers/gpu/drm/amd/display/dc/core/dc_resource.c color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? timing 2156 drivers/gpu/drm/amd/display/dc/core/dc_resource.c switch (stream->timing.pixel_encoding) { timing 2211 drivers/gpu/drm/amd/display/dc/core/dc_resource.c aspect = stream->timing.aspect_ratio; timing 2296 drivers/gpu/drm/amd/display/dc/core/dc_resource.c format = stream->timing.timing_3d_format; timing 2300 drivers/gpu/drm/amd/display/dc/core/dc_resource.c switch (pipe_ctx->stream->timing.hdmi_vic) { timing 2340 drivers/gpu/drm/amd/display/dc/core/dc_resource.c hdmi_info.bits.bar_top = stream->timing.v_border_top; timing 2341 drivers/gpu/drm/amd/display/dc/core/dc_resource.c hdmi_info.bits.bar_bottom = (stream->timing.v_total timing 2342 drivers/gpu/drm/amd/display/dc/core/dc_resource.c - stream->timing.v_border_bottom + 1); timing 2343 drivers/gpu/drm/amd/display/dc/core/dc_resource.c hdmi_info.bits.bar_left = stream->timing.h_border_left; timing 2344 drivers/gpu/drm/amd/display/dc/core/dc_resource.c hdmi_info.bits.bar_right = (stream->timing.h_total timing 2345 drivers/gpu/drm/amd/display/dc/core/dc_resource.c - stream->timing.h_border_right + 1); timing 2624 drivers/gpu/drm/amd/display/dc/core/dc_resource.c stream->timing.pixel_encoding; timing 2629 drivers/gpu/drm/amd/display/dc/core/dc_resource.c switch (stream->timing.display_color_depth) { timing 2754 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (!tg->funcs->validate_timing(tg, &stream->timing)) timing 2768 drivers/gpu/drm/amd/display/dc/core/dc_resource.c &stream->timing); timing 53 drivers/gpu/drm/amd/display/dc/core/dc_stream.c (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && timing 109 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; timing 112 drivers/gpu/drm/amd/display/dc/core/dc_stream.c memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); timing 113 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.num_slices_h = 0; timing 114 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.num_slices_v = 0; timing 115 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.bits_per_pixel = 128; timing 116 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.block_pred_enable = 1; timing 117 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.linebuf_depth = 9; timing 118 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.version_minor = 2; timing 119 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.ycbcr422_simple = 0; timing 256 drivers/gpu/drm/amd/display/dc/core/dc_stream.c us_per_line = stream->timing.h_total * 10000 / stream->timing.pix_clk_100hz; timing 651 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.pix_clk_100hz / 10, timing 652 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.h_total, timing 653 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.v_total, timing 654 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.pixel_encoding, timing 655 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.display_color_depth); timing 52 drivers/gpu/drm/amd/display/dc/dc_dsc.h const struct dc_crtc_timing *timing, timing 59 drivers/gpu/drm/amd/display/dc/dc_dsc.h const struct dc_crtc_timing *timing, timing 295 drivers/gpu/drm/amd/display/dc/dc_link.h const struct dc_crtc_timing *timing); timing 125 drivers/gpu/drm/amd/display/dc/dc_stream.h struct dc_crtc_timing timing; timing 535 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c cfg->v_refresh = stream->timing.pix_clk_100hz * 100; timing 536 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c cfg->v_refresh /= stream->timing.h_total; timing 537 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) timing 538 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c / stream->timing.v_total; timing 554 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c vertical_blank_in_pixels = stream->timing.h_total * timing 555 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c (stream->timing.v_total timing 556 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c - stream->timing.v_addressable); timing 559 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c * 10000 / stream->timing.pix_clk_100hz; timing 656 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c const struct dc_crtc_timing *timing = timing 657 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c &context->streams[0]->timing; timing 661 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; timing 796 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c &stream->timing); timing 801 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c &stream->timing, timing 807 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110, &stream->timing); timing 812 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c (stream->timing. timing 984 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c m_vid_l *= param->timing.pix_clk_100hz / 10; timing 655 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; timing 674 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c timing->h_addressable timing 675 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c + timing->h_border_left timing 676 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c + timing->h_border_right; timing 1060 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c params.timing = pipe_ctx->stream->timing; timing 1125 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c stream->timing.h_total; timing 1132 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c stream->timing.h_addressable timing 1133 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c + stream->timing.h_border_left timing 1134 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c + stream->timing.h_border_right; timing 1137 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c stream->timing.v_addressable timing 1138 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c + stream->timing.v_border_top timing 1139 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c + stream->timing.v_border_bottom; timing 1144 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c stream->timing.flags.INTERLACE; timing 1147 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (stream->timing.pix_clk_100hz*100)/ timing 1148 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (stream->timing.h_total*stream->timing.v_total); timing 1151 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c stream->timing.display_color_depth; timing 1162 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (stream->timing.pix_clk_100hz)) { timing 1257 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) timing 1304 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &stream->timing, timing 1393 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c stream->timing.display_color_depth, timing 1405 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c stream->timing.display_color_depth, timing 1639 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (stream->timing.h_total * 10) / timing 1640 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c stream->timing.pix_clk_100hz + timing 1866 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c params.source_view_width = pipe_ctx->stream->timing.h_addressable; timing 1867 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c params.source_view_height = pipe_ctx->stream->timing.v_addressable; timing 2125 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->timing.display_color_depth; timing 2610 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->timing.h_total, timing 2611 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->timing.v_total, timing 2612 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->timing.pix_clk_100hz / 10, timing 2689 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, timing 819 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; timing 828 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c stream->timing.display_color_depth; timing 830 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == timing 832 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; timing 833 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { timing 836 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { timing 839 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) timing 853 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; timing 913 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c context->streams[0]->timing.h_addressable, timing 914 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c context->streams[0]->timing.v_addressable, timing 915 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c context->streams[0]->timing.pix_clk_100hz / 10); timing 1007 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (context->streams[i]->timing.pixel_encoding timing 1085 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c &stream->timing, timing 1096 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c &stream->timing); timing 1099 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c stream->timing.h_total, timing 1100 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c stream->timing.v_total, timing 1101 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c stream->timing.pix_clk_100hz / 10, timing 67 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dc_crtc_timing *timing) timing 69 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->flags.INTERLACE == 1) { timing 70 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->v_front_porch < 2) timing 71 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->v_front_porch = 2; timing 73 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->v_front_porch < 1) timing 74 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->v_front_porch = 1; timing 257 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c const struct dc_crtc_timing *timing) timing 268 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->flags.HORZ_COUNT_BY_TWO) timing 598 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c const struct dc_crtc_timing *timing) timing 600 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t vsync_offset = timing->v_border_bottom + timing 601 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->v_front_porch; timing 602 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t v_sync_start =timing->v_addressable + vsync_offset; timing 604 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t hsync_offset = timing->h_border_right + timing 605 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->h_front_porch; timing 606 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t h_sync_start = timing->h_addressable + hsync_offset; timing 618 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->h_total - 1, timing 627 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->v_total - 1, timing 639 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->v_total - 1, timing 648 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->v_total - 1, timing 656 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tmp = timing->h_total - timing 657 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c (h_sync_start + timing->h_border_left); timing 665 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tmp = tmp + timing->h_addressable + timing 666 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->h_border_left + timing->h_border_right; timing 679 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tmp = timing->v_total - (v_sync_start + timing->v_border_top); timing 687 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tmp = tmp + timing->v_addressable + timing->v_border_top + timing 688 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->v_border_bottom; timing 1111 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c const struct dc_crtc_timing *timing, timing 1119 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c ASSERT(timing != NULL); timing 1121 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (!timing) timing 1124 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c hsync_offset = timing->h_border_right + timing->h_front_porch; timing 1125 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c h_sync_start = timing->h_addressable + hsync_offset; timing 1128 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) timing 1132 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->flags.INTERLACE == 1) timing 1140 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->h_total > tg110->max_h_total || timing 1141 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->v_total > tg110->max_v_total) timing 1144 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c h_blank = (timing->h_total - timing->h_addressable - timing 1145 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->h_border_right - timing 1146 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->h_border_left); timing 1151 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->h_front_porch < tg110->min_h_front_porch) timing 1155 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->h_addressable - timing 1156 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->h_border_right - timing 1157 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->h_sync_width); timing 1412 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c const struct dc_crtc_timing *timing) timing 1432 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if ((timing->v_sync_width + timing->v_front_porch) <= 3) { timing 1954 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c const struct dc_crtc_timing *timing, timing 1963 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c dce110_timing_generator_program_timing_generator(tg, timing); timing 1965 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c dce110_timing_generator_program_blanking(tg, timing); timing 2014 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c const struct dc_crtc_timing *timing) timing 2016 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c return dce110_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); timing 129 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h const struct dc_crtc_timing *timing, timing 203 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h const struct dc_crtc_timing *timing); timing 246 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h const struct dc_crtc_timing *timing); timing 258 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h const struct dc_crtc_timing *timing, timing 272 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h const struct dc_crtc_timing *timing); timing 244 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c const struct dc_crtc_timing *timing) timing 246 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t vsync_offset = timing->v_border_bottom + timing 247 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c timing->v_front_porch; timing 248 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t v_sync_start = timing->v_addressable + vsync_offset; timing 250 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t hsync_offset = timing->h_border_right + timing 251 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c timing->h_front_porch; timing 252 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t h_sync_start = timing->h_addressable + hsync_offset; timing 263 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c timing->h_total - 1, timing 272 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c timing->v_total - 1, timing 280 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tmp = timing->h_total - timing 281 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c (h_sync_start + timing->h_border_left); timing 289 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tmp = tmp + timing->h_addressable + timing 290 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c timing->h_border_left + timing->h_border_right; timing 303 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tmp = timing->v_total - (v_sync_start + timing->v_border_top); timing 311 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tmp = tmp + timing->v_addressable + timing->v_border_top + timing 312 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c timing->v_border_bottom; timing 326 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c timing->h_sync_width, timing 333 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c if (timing->flags.HSYNC_POSITIVE_POLARITY) { timing 352 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c timing->v_sync_width, timing 359 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c if (timing->flags.VSYNC_POSITIVE_POLARITY) { timing 378 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c timing->flags.INTERLACE, timing 387 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c const struct dc_crtc_timing *timing) timing 393 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c if ((timing->v_sync_width + timing->v_front_porch) <= 3) { timing 437 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c const struct dc_crtc_timing *timing, timing 446 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c dce110_timing_generator_program_timing_generator(tg, timing); timing 448 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c dce110_timing_generator_v_program_blanking(tg, timing); timing 103 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c const struct dc_crtc_timing *timing, timing 106 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; timing 108 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c (timing->v_total - timing->v_addressable - timing 109 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_border_top - timing->v_border_bottom) * timing 115 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing, timing 121 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->h_sync_width < tg110->min_h_sync_width || timing 122 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_sync_width < tg110->min_v_sync_width) timing 129 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c const struct dc_crtc_timing *timing) timing 131 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); timing 430 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c const struct dc_crtc_timing *timing) timing 434 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t vsync_offset = timing->v_border_bottom + timing 435 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_front_porch; timing 436 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t v_sync_start = timing->v_addressable + vsync_offset; timing 438 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t hsync_offset = timing->h_border_right + timing 439 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->h_front_porch; timing 440 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t h_sync_start = timing->h_addressable + hsync_offset; timing 446 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->h_total - 1); timing 451 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_total - 1); timing 459 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_total - 1); timing 464 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_total - 1); timing 466 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tmp1 = timing->h_total - timing 467 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c (h_sync_start + timing->h_border_left); timing 468 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tmp2 = tmp1 + timing->h_addressable + timing 469 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->h_border_left + timing->h_border_right; timing 476 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tmp1 = timing->v_total - (v_sync_start + timing->v_border_top); timing 477 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tmp2 = tmp1 + timing->v_addressable + timing->v_border_top + timing 478 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_border_bottom; timing 667 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c const struct dc_crtc_timing *timing) timing 671 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_total - timing->v_addressable - timing 672 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_border_bottom - timing->v_front_porch; timing 738 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c const struct dc_crtc_timing *timing, timing 747 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dce110_timing_generator_program_timing_generator(tg, timing); timing 749 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dce120_timing_generator_program_blanking(tg, timing); timing 790 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c const struct dc_crtc_timing *timing); timing 109 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c const struct dc_crtc_timing *timing, timing 118 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c program_pix_dur(tg, timing->pix_clk_100hz); timing 120 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); timing 126 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c const struct dc_crtc_timing *timing) timing 146 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c if ((timing->v_sync_width + timing->v_front_porch) <= 3) { timing 764 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &stream->timing, timing 1343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c (pipe_ctx->stream->timing.timing_3d_format == timing 1345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream->timing.timing_3d_format == timing 2428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) timing 2513 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); timing 2674 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (context->streams[i]->timing.timing_3d_format timing 2812 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c stream->timing.timing_3d_format; timing 2836 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c stream->timing.flags.RIGHT_EYE_3D_POLARITY; timing 2851 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) { timing 2861 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &stream->timing); timing 2865 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &stream->timing, timing 2960 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, timing 3064 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_crtc_timing *timing) timing 3066 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (timing->flags.INTERLACE == 1) { timing 3067 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (timing->v_front_porch < 2) timing 3068 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c timing->v_front_porch = 2; timing 3070 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (timing->v_front_porch < 1) timing 3071 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c timing->v_front_porch = 1; timing 3077 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing; timing 3136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing; timing 3232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c params.timing = pipe_ctx->stream->timing; timing 3237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) timing 3238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c params.timing.pix_clk_100hz /= 2; timing 792 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c &stream->timing); timing 797 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c &stream->timing, timing 803 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10, &stream->timing); timing 806 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; timing 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c const struct dc_crtc_timing *timing) timing 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; timing 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t space1_size = timing->v_total - timing->v_addressable; timing 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t space2_size = timing->v_total - timing->v_addressable; timing 329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE) timing 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h const struct dc_crtc_timing *timing); timing 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c static void apply_front_porch_workaround(struct dc_crtc_timing *timing) timing 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (timing->flags.INTERLACE == 1) { timing 52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (timing->v_front_porch < 2) timing 53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->v_front_porch = 2; timing 55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (timing->v_front_porch < 1) timing 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->v_front_porch = 1; timing 506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c const struct dc_crtc_timing *timing) timing 513 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c ASSERT(timing != NULL); timing 515 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c v_blank = (timing->v_total - timing->v_addressable - timing 516 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->v_border_top - timing->v_border_bottom); timing 518 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c h_blank = (timing->h_total - timing->h_addressable - timing 519 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->h_border_right - timing 520 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->h_border_left); timing 522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && timing 523 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && timing 524 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && timing 525 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && timing 526 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && timing 527 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) timing 531 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (timing->flags.INTERLACE == 1) timing 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (timing->h_total > optc1->max_h_total || timing 540 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->v_total > optc1->max_v_total) timing 547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (timing->h_sync_width < optc1->min_h_sync_width || timing 548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->v_sync_width < optc1->min_v_sync_width) timing 551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; timing 1176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) timing 1208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) timing 1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1_enable_stereo(optc, timing, flags); timing 1548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) timing 1550 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; timing 1553 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 timing 1554 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c && !timing->dsc_cfg.ycbcr422_simple); timing 556 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h const struct dc_crtc_timing *timing); timing 640 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); timing 669 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing); timing 990 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; timing 999 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c stream->timing.display_color_depth; timing 1001 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; timing 1003 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) timing 1006 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) timing 1008 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) timing 1016 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c stream->clamping.c_depth = stream->timing.display_color_depth; timing 1017 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c stream->clamping.pixel_encoding = stream->timing.pixel_encoding; timing 1030 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; timing 941 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { timing 949 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c m_vid_l *= param->timing.pix_clk_100hz / 10; timing 553 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->stream->timing); timing 570 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &stream->timing, timing 841 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->stream->timing); timing 844 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); timing 860 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; timing 861 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; timing 884 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c stream->timing.display_color_depth, timing 894 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c stream->timing.display_color_depth, timing 1047 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); timing 1339 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); timing 1534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c (pipe_ctx->stream->timing.timing_3d_format == timing 1536 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream->timing.timing_3d_format == timing 1595 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c params.timing = pipe_ctx->stream->timing; timing 1600 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) timing 1601 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c params.timing.pix_clk_100hz /= 2; timing 1674 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); timing 1926 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; timing 1948 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c timing->h_addressable timing 1949 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c + timing->h_border_left timing 1950 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c + timing->h_border_right; timing 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct dc_crtc_timing *timing) timing 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) timing 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) timing 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) timing 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h struct dc_crtc_timing *timing); timing 1445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; timing 1454 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c stream->timing.display_color_depth; timing 1456 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; timing 1458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) timing 1463 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) timing 1466 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) timing 1474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c stream->clamping.c_depth = stream->timing.display_color_depth; timing 1475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c stream->clamping.pixel_encoding = stream->timing.pixel_encoding; timing 1488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; timing 1639 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (result == DC_OK && dc_stream->timing.flags.DSC) timing 1789 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (next_odm_pipe->stream->timing.flags.DSC == 1) { timing 1895 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; timing 1906 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; timing 1908 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; timing 1914 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c (timing->v_total - timing->v_addressable timing 1915 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c - timing->v_border_top - timing->v_border_bottom) / 2; timing 1923 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; timing 1925 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c - timing->h_addressable timing 1926 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c - timing->h_border_left timing 1927 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c - timing->h_border_right; timing 1928 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch; timing 1930 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c - timing->v_addressable timing 1931 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c - timing->v_border_top timing 1932 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c - timing->v_border_bottom; timing 1933 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; timing 1934 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; timing 1935 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; timing 1936 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable; timing 1937 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; timing 1938 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; timing 1939 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) timing 1978 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { timing 2010 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { timing 2048 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; timing 2051 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; timing 2068 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total; timing 2069 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total; timing 2269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) timing 2272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left timing 2273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c + stream->timing.h_border_right) / opp_cnt; timing 2274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top timing 2275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c + stream->timing.v_border_bottom; timing 2276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; timing 2277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.color_depth = stream->timing.display_color_depth; timing 2278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; timing 2565 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c (pipe->stream->timing.timing_3d_format == timing 2567 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe->stream->timing.timing_3d_format == timing 439 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) timing 441 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; timing 444 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 timing 445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c && !timing->dsc_cfg.ycbcr422_simple); timing 463 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { timing 471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c m_vid_l *= param->timing.pix_clk_100hz / 10; timing 289 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c const struct dc_crtc_timing *timing, timing 293 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing); timing 296 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c range->max_kbps = dsc_div_by_10_round_up(max_bpp * timing->pix_clk_100hz); timing 301 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c range->max_target_bpp_x16 = calc_dsc_bpp_x16(range->stream_kbps, timing->pix_clk_100hz, dsc_caps->bpp_increment_div); timing 305 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c range->min_kbps = dsc_div_by_10_round_up(min_bpp * timing->pix_clk_100hz); timing 326 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c const struct dc_crtc_timing *timing, timing 335 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_common_caps, timing, &range); timing 346 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c *target_bpp_x16 = calc_dsc_bpp_x16(target_bandwidth_kbps, timing->pix_clk_100hz, dsc_common_caps->bpp_increment_div); timing 514 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c const struct dc_crtc_timing *timing, timing 532 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; timing 533 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; timing 542 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps); timing 547 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c is_dsc_possible = decide_dsc_target_bpp_x16(&dsc_policy, &dsc_common_caps, target_bandwidth_kbps, timing, &target_bpp); timing 559 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c switch (timing->pixel_encoding) { timing 590 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c if (branch_max_throughput_mps && dsc_div_by_10_round_up(timing->pix_clk_100hz) > branch_max_throughput_mps * 1000) timing 597 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c switch (timing->display_color_depth) { timing 635 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c int pix_clk_per_slice_khz = dsc_div_by_10_round_up(timing->pix_clk_100hz) / min_slices_h; timing 686 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0))) timing 689 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) // For the case when pic_height < dsc_policy.min_sice_height timing 809 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c const struct dc_crtc_timing *timing, timing 817 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c get_dsc_enc_caps(dc, &dsc_enc_caps, timing->pix_clk_100hz); timing 820 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c timing->pixel_encoding, &dsc_common_caps); timing 826 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c timing, &config); timing 829 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range); timing 838 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c const struct dc_crtc_timing *timing, timing 844 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c get_dsc_enc_caps(dc, &dsc_enc_caps, timing->pix_clk_100hz); timing 848 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c timing, dsc_cfg); timing 72 drivers/gpu/drm/amd/display/dc/inc/core_types.h const struct dc_crtc_timing *timing); timing 48 drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h const struct dc_crtc_timing *timing); timing 301 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h const struct dc_crtc_timing *timing); timing 92 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h struct dc_crtc_timing timing; timing 138 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h const struct dc_crtc_timing *timing); timing 140 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h const struct dc_crtc_timing *timing, timing 210 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h bool enable, const struct dc_crtc_timing *timing); timing 228 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); timing 277 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h struct dc_crtc_timing *timing); timing 115 drivers/gpu/drm/amd/display/modules/freesync/freesync.c * 10000) * stream->timing.h_total, timing 116 drivers/gpu/drm/amd/display/modules/freesync/freesync.c stream->timing.pix_clk_100hz)); timing 125 drivers/gpu/drm/amd/display/modules/freesync/freesync.c unsigned int v_total = stream->timing.v_total; timing 133 drivers/gpu/drm/amd/display/modules/freesync/freesync.c frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), timing 134 drivers/gpu/drm/amd/display/modules/freesync/freesync.c stream->timing.h_total), 1000000); timing 137 drivers/gpu/drm/amd/display/modules/freesync/freesync.c if (v_total < stream->timing.v_total) { timing 138 drivers/gpu/drm/amd/display/modules/freesync/freesync.c ASSERT(v_total < stream->timing.v_total); timing 139 drivers/gpu/drm/amd/display/modules/freesync/freesync.c v_total = stream->timing.v_total; timing 159 drivers/gpu/drm/amd/display/modules/freesync/freesync.c duration_in_us) * (stream->timing.pix_clk_100hz / 10)), timing 160 drivers/gpu/drm/amd/display/modules/freesync/freesync.c stream->timing.h_total), 1000); timing 163 drivers/gpu/drm/amd/display/modules/freesync/freesync.c if (v_total < stream->timing.v_total) { timing 164 drivers/gpu/drm/amd/display/modules/freesync/freesync.c ASSERT(v_total < stream->timing.v_total); timing 165 drivers/gpu/drm/amd/display/modules/freesync/freesync.c v_total = stream->timing.v_total; timing 234 drivers/gpu/drm/amd/display/modules/freesync/freesync.c current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)), timing 235 drivers/gpu/drm/amd/display/modules/freesync/freesync.c stream->timing.h_total), 1000); timing 776 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_min = stream->timing.v_total; timing 777 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_max = stream->timing.v_total; timing 816 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_min = stream->timing.v_total; timing 817 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_max = stream->timing.v_total; timing 819 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_min = stream->timing.v_total; timing 820 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_max = stream->timing.v_total; timing 822 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_min = stream->timing.v_total; timing 823 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_max = stream->timing.v_total; timing 852 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_min = stream->timing.v_total; timing 853 drivers/gpu/drm/amd/display/modules/freesync/freesync.c in_out_vrr->adjust.v_total_max = stream->timing.v_total; timing 1005 drivers/gpu/drm/amd/display/modules/freesync/freesync.c unsigned int total = stream->timing.h_total * stream->timing.v_total; timing 1008 drivers/gpu/drm/amd/display/modules/freesync/freesync.c nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz / 10; timing 126 drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) { timing 206 drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c switch (stream->timing.timing_3d_format) { timing 299 drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c switch (stream->timing.pixel_encoding) { timing 318 drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c switch (stream->timing.pixel_encoding) { timing 354 drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c switch (stream->timing.display_color_depth) { timing 1960 drivers/gpu/drm/drm_edid.c typedef void detailed_cb(struct detailed_timing *timing, void *closure); timing 2286 drivers/gpu/drm/drm_edid.c struct detailed_timing *timing, timing 2290 drivers/gpu/drm/drm_edid.c struct detailed_pixel_timing *pt = &timing->data.pixel_data; timing 2332 drivers/gpu/drm/drm_edid.c timing->pixel_clock = cpu_to_le16(1088); timing 2334 drivers/gpu/drm/drm_edid.c mode->clock = le16_to_cpu(timing->pixel_clock) * 10; timing 2435 drivers/gpu/drm/drm_edid.c struct detailed_timing *timing) timing 2438 drivers/gpu/drm/drm_edid.c u8 *t = (u8 *)timing; timing 2481 drivers/gpu/drm/drm_edid.c struct detailed_timing *timing) timing 2488 drivers/gpu/drm/drm_edid.c if (mode_in_range(drm_dmt_modes + i, edid, timing) && timing 2516 drivers/gpu/drm/drm_edid.c struct detailed_timing *timing) timing 2529 drivers/gpu/drm/drm_edid.c if (!mode_in_range(newmode, edid, timing) || timing 2544 drivers/gpu/drm/drm_edid.c struct detailed_timing *timing) timing 2558 drivers/gpu/drm/drm_edid.c if (!mode_in_range(newmode, edid, timing) || timing 2572 drivers/gpu/drm/drm_edid.c do_inferred_modes(struct detailed_timing *timing, void *c) timing 2575 drivers/gpu/drm/drm_edid.c struct detailed_non_pixel *data = &timing->data.other_data; timing 2583 drivers/gpu/drm/drm_edid.c timing); timing 2593 drivers/gpu/drm/drm_edid.c timing); timing 2601 drivers/gpu/drm/drm_edid.c timing); timing 2625 drivers/gpu/drm/drm_edid.c drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) timing 2629 drivers/gpu/drm/drm_edid.c u8 *est = ((u8 *)timing) + 6; timing 2654 drivers/gpu/drm/drm_edid.c do_established_modes(struct detailed_timing *timing, void *c) timing 2657 drivers/gpu/drm/drm_edid.c struct detailed_non_pixel *data = &timing->data.other_data; timing 2660 drivers/gpu/drm/drm_edid.c closure->modes += drm_est3_modes(closure->connector, timing); timing 2703 drivers/gpu/drm/drm_edid.c do_standard_modes(struct detailed_timing *timing, void *c) timing 2706 drivers/gpu/drm/drm_edid.c struct detailed_non_pixel *data = &timing->data.other_data; timing 2764 drivers/gpu/drm/drm_edid.c struct detailed_timing *timing) timing 2775 drivers/gpu/drm/drm_edid.c cvt = &(timing->data.other_data.data.cvt[i]); timing 2813 drivers/gpu/drm/drm_edid.c do_cvt_mode(struct detailed_timing *timing, void *c) timing 2816 drivers/gpu/drm/drm_edid.c struct detailed_non_pixel *data = &timing->data.other_data; timing 2819 drivers/gpu/drm/drm_edid.c closure->modes += drm_cvt_modes(closure->connector, timing); timing 2841 drivers/gpu/drm/drm_edid.c do_detailed_mode(struct detailed_timing *timing, void *c) timing 2846 drivers/gpu/drm/drm_edid.c if (timing->pixel_clock) { timing 2848 drivers/gpu/drm/drm_edid.c closure->edid, timing, timing 41 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct intf_timing_params *timing) timing 43 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c memset(timing, 0, sizeof(*timing)); timing 70 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->width = mode->hdisplay; /* active width */ timing 71 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->height = mode->vdisplay; /* active height */ timing 72 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->xres = timing->width; timing 73 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->yres = timing->height; timing 74 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->h_back_porch = mode->htotal - mode->hsync_end; timing 75 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->h_front_porch = mode->hsync_start - mode->hdisplay; timing 76 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->v_back_porch = mode->vtotal - mode->vsync_end; timing 77 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->v_front_porch = mode->vsync_start - mode->vdisplay; timing 78 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start; timing 79 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start; timing 80 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0; timing 81 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; timing 82 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->border_clr = 0; timing 83 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->underflow_clr = 0xff; timing 84 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->hsync_skew = mode->hskew; timing 88 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->hsync_polarity = 0; timing 89 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->vsync_polarity = 0; timing 105 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c static u32 get_horizontal_total(const struct intf_timing_params *timing) timing 107 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c u32 active = timing->xres; timing 109 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->h_back_porch + timing->h_front_porch + timing 110 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->hsync_pulse_width; timing 114 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c static u32 get_vertical_total(const struct intf_timing_params *timing) timing 116 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c u32 active = timing->yres; timing 118 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->v_back_porch + timing->v_front_porch + timing 119 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->vsync_pulse_width; timing 139 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c const struct intf_timing_params *timing) timing 144 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->v_back_porch + timing->vsync_pulse_width; timing 153 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c } else if (timing->v_front_porch < needed_vfp_lines) { timing 159 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c actual_vfp_lines = timing->v_front_porch; timing 167 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->v_front_porch, timing->v_back_porch, timing 168 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c timing->vsync_pulse_width); timing 187 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c const struct intf_timing_params *timing) timing 199 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing); timing 201 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c vert_total = get_vertical_total(timing); timing 202 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c horiz_total = get_horizontal_total(timing); timing 26 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, timing 33 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; timing 44 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; timing 45 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_zero = clk_z + 8 - temp; timing 48 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, timing 70 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); timing 74 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_rqst = temp; timing 76 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_rqst = max_t(s32, 0, temp - 2); timing 79 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); timing 84 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); timing 90 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true); timing 93 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui; timing 96 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true); timing 102 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true); timing 106 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true); timing 109 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = ((timing->hs_exit >> 1) + 1) * 2 * ui; timing 112 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0, timing 115 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui; timing 116 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp += ((timing->clk_zero >> 1) + 1) * 2 * ui; timing 121 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = temp >> 1; timing 122 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = true; timing 124 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = timing 126 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = false; timing 129 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->ta_go = 3; timing 130 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->ta_sure = 0; timing 131 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->ta_get = 4; timing 134 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre, timing->shared_timings.clk_post, timing 135 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, timing 136 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_trail, timing->clk_prepare, timing->hs_exit, timing 137 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing 138 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_rqst); timing 143 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, timing 164 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_halfbyte_en = 0; timing 166 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_halfbyte_en_ckln = 0; timing 168 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3; timing 169 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c pd_ckln = timing->hs_prep_dly_ckln; timing 170 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1; timing 171 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c pd = timing->hs_prep_dly; timing 184 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); timing 186 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui; timing 189 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); timing 194 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); timing 200 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); timing 202 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui; timing 205 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); timing 210 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); timing 213 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); timing 217 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); timing 220 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8); timing 225 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_post = timing 228 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui; timing 229 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui; timing 230 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) : timing 231 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c (((timing->hs_rqst_ckln << 3) + 8) * ui); timing 236 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = temp >> 1; timing 237 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = 1; timing 239 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = timing 241 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = 0; timing 244 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->ta_go = 3; timing 245 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->ta_sure = 0; timing 246 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->ta_get = 4; timing 249 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre, timing->shared_timings.clk_post, timing 250 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, timing 251 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_trail, timing->clk_prepare, timing->hs_exit, timing 252 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing 253 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, timing 254 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_halfbyte_en_ckln, timing->hs_prep_dly, timing 255 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_prep_dly_ckln); timing 260 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, timing 280 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_halfbyte_en = 0; timing 282 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_halfbyte_en_ckln = 0; timing 293 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); timing 295 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = 300 * coeff - (timing->clk_prepare << 3) * ui; timing 298 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); timing 303 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); timing 309 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); timing 311 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui; timing 314 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); timing 319 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); timing 322 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); timing 326 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); timing 329 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8); timing 334 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_post = timing 337 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp = 8 * ui + (timing->clk_prepare << 3) * ui; timing 338 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp += (((timing->clk_zero + 3) << 3) + 11) * ui; timing 339 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) : timing 340 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c (((timing->hs_rqst_ckln << 3) + 8) * ui); timing 345 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = temp >> 1; timing 346 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = 1; timing 348 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = timing 350 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = 0; timing 353 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->ta_go = 3; timing 354 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->ta_sure = 0; timing 355 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->ta_get = 4; timing 358 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre, timing->shared_timings.clk_post, timing 359 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, timing 360 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->clk_trail, timing->clk_prepare, timing->hs_exit, timing 361 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing 362 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, timing 363 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_halfbyte_en_ckln, timing->hs_prep_dly, timing 364 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->hs_prep_dly_ckln); timing 736 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c memcpy(shared_timings, &phy->timing.shared_timings, timing 85 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h struct msm_dsi_dphy_timing timing; timing 97 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, timing 99 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, timing 101 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, timing 94 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c struct msm_dsi_dphy_timing *timing = &phy->timing; timing 100 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c if (msm_dsi_dphy_timing_calc_v3(timing, clk_req)) { timing 140 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->hs_halfbyte_en); timing 142 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->clk_zero); timing 144 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->clk_prepare); timing 146 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->clk_trail); timing 148 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->hs_exit); timing 150 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->hs_zero); timing 152 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->hs_prepare); timing 154 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->hs_trail); timing 156 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->hs_rqst); timing 158 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->ta_go | (timing->ta_sure << 3)); timing 160 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c timing->ta_get); timing 14 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c struct msm_dsi_dphy_timing *timing, timing 19 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; timing 20 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; timing 21 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; timing 22 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; timing 23 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; timing 24 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : timing 25 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c timing->hs_halfbyte_en; timing 28 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); timing 42 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) | timing 43 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); timing 45 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get)); timing 53 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c struct msm_dsi_dphy_timing *timing = &phy->timing; timing 60 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) { timing 92 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_14nm_dphy_set_timing(phy, timing, i); timing 10 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c struct msm_dsi_dphy_timing *timing) timing 15 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); timing 17 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); timing 19 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); timing 20 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c if (timing->clk_zero & BIT(8)) timing 24 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); timing 26 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); timing 28 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); timing 30 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); timing 32 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); timing 34 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | timing 35 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); timing 37 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); timing 69 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c struct msm_dsi_dphy_timing *timing = &phy->timing; timing 76 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c if (msm_dsi_dphy_timing_calc(timing, clk_req)) { timing 108 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_20nm_dphy_set_timing(phy, timing); timing 10 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c struct msm_dsi_dphy_timing *timing) timing 15 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); timing 17 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); timing 19 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); timing 20 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c if (timing->clk_zero & BIT(8)) timing 24 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); timing 26 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); timing 28 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); timing 30 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); timing 32 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); timing 34 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | timing 35 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); timing 37 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); timing 64 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c struct msm_dsi_dphy_timing *timing = &phy->timing; timing 70 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c if (msm_dsi_dphy_timing_calc(timing, clk_req)) { timing 82 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_28nm_dphy_set_timing(phy, timing); timing 12 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c struct msm_dsi_dphy_timing *timing) timing 17 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); timing 19 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); timing 21 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); timing 24 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); timing 26 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); timing 28 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); timing 30 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); timing 32 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); timing 34 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | timing 35 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); timing 37 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); timing 123 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c struct msm_dsi_dphy_timing *timing = &phy->timing; timing 128 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c if (msm_dsi_dphy_timing_calc(timing, clk_req)) { timing 160 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_28nm_dphy_set_timing(phy, timing); timing 115 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h unsigned timing[11]; timing 33 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c u32 timing = 0; timing 37 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c timing = nvbios_rd32(bios, bit_P.offset + 4); timing 40 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c timing = nvbios_rd32(bios, bit_P.offset + 8); timing 42 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c if (timing) { timing 43 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c *ver = nvbios_rd08(bios, timing + 0); timing 46 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c *hdr = nvbios_rd08(bios, timing + 1); timing 47 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c *cnt = nvbios_rd08(bios, timing + 2); timing 48 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c *len = nvbios_rd08(bios, timing + 3); timing 51 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c return timing; timing 53 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c *hdr = nvbios_rd08(bios, timing + 1); timing 54 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c *cnt = nvbios_rd08(bios, timing + 5); timing 55 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c *len = nvbios_rd08(bios, timing + 2); timing 56 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c *snr = nvbios_rd08(bios, timing + 4); timing 57 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c *ssz = nvbios_rd08(bios, timing + 3); timing 58 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c return timing; timing 73 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); timing 74 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c if (timing && idx < *cnt) { timing 75 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c timing += *hdr + idx * (*len + (snr * ssz)); timing 79 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c return timing; timing 140 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[0] = nvbios_rd32(bios, data + 0x00); timing 141 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[1] = nvbios_rd32(bios, data + 0x04); timing 142 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[2] = nvbios_rd32(bios, data + 0x08); timing 143 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[3] = nvbios_rd32(bios, data + 0x0c); timing 144 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[4] = nvbios_rd32(bios, data + 0x10); timing 145 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[5] = nvbios_rd32(bios, data + 0x14); timing 146 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[6] = nvbios_rd32(bios, data + 0x18); timing 147 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[7] = nvbios_rd32(bios, data + 0x1c); timing 148 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[8] = nvbios_rd32(bios, data + 0x20); timing 149 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[9] = nvbios_rd32(bios, data + 0x24); timing 150 drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c p->timing[10] = nvbios_rd32(bios, data + 0x28); timing 85 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; timing 86 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; timing 87 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; timing 58 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; timing 59 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c CL = (ram->next->bios.timing[1] & 0x0000001f); timing 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; timing 140 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c } rammap, ramcfg, timing; timing 170 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, timing 172 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c if (!timing.data || ver != 0x10 || timing.size < 0x19) { timing 177 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c timing.data = 0; timing 461 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); timing 462 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); timing 463 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); timing 464 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); timing 465 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); timing 466 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); timing 467 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); timing 468 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); timing 469 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); timing 470 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); timing 471 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); timing 566 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c data = (next->bios.timing[10] & 0x7f000000) >> 24; timing 855 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); timing 856 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); timing 857 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); timing 858 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); timing 859 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); timing 860 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); timing 861 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); timing 862 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); timing 863 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); timing 864 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); timing 865 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); timing 896 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c data = (next->bios.timing[10] & 0x7f000000) >> 24; timing 348 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing) timing 374 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); timing 375 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[1] = (T(WR) + 1 + T(CWL)) << 24 | timing 379 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[2] = (T(CWL) - 1) << 24 | timing 383 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[3] = (cur3 & 0x00ff0000) | timing 387 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[4] = T(20) << 24 | timing 391 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[5] = T(RFC) << 24 | timing 395 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[6] = (0x5a + T(CL)) << 16 | timing 398 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[7] = (cur7 & 0xff000000) | timing 401 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[8] = cur8 & 0xffffff00; timing 408 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[8] |= T(CL); timing 415 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[0], timing[1], timing[2], timing[3]); timing 417 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[4], timing[5], timing[6], timing[7]); timing 418 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c nvkm_debug(subdev, " 240: %08x\n", timing[8]); timing 508 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c u32 timing[9]; timing 557 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c gt215_ram_timing_calc(ram, timing); timing 755 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x100220[3], timing[3]); timing 756 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x100220[1], timing[1]); timing 757 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x100220[6], timing[6]); timing 758 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x100220[7], timing[7]); timing 759 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x100220[2], timing[2]); timing 760 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x100220[4], timing[4]); timing 761 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x100220[5], timing[5]); timing 762 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x100220[0], timing[0]); timing 763 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x100220[8], timing[8]); timing 73 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) timing 98 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[6] = (0x2d + T(CL) - T(CWL) + timing 104 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | timing 109 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); timing 110 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[1] = (T(WR) + 1 + T(CWL)) << 24 | timing 114 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[2] = (T(CWL) - 1) << 24 | timing 118 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[3] = (unkt3b - 2 + T(CL)) << 24 | timing 122 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[4] = (cur4 & 0xffff0000) | timing 125 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[5] = T(RFC) << 24 | timing 129 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; timing 130 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[8] = (cur8 & 0xffffff00); timing 134 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[5] |= (T(CL) + 3) << 8; timing 135 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[8] |= (T(CL) - 4); timing 138 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[5] |= (T(CL) + 2) << 8; timing 139 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[8] |= (T(CL) - 2); timing 143 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[0], timing[1], timing[2], timing[3]); timing 145 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[4], timing[5], timing[6], timing[7]); timing 146 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nvkm_debug(subdev, " 240: %08x\n", timing[8]); timing 151 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) timing 159 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[i] = nvkm_rd32(device, 0x100220 + (i * 4)); timing 163 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c T(CL) = (timing[3] & 0xff) + 1; timing 170 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1; timing 177 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); timing 233 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c u32 timing[9]; timing 277 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nv50_ram_timing_calc(ram, timing); timing 279 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nv50_ram_timing_read(ram, timing); timing 390 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, timing[3], 0xffffffff, timing[3]); timing 391 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, timing[1], 0xffffffff, timing[1]); timing 392 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, timing[6], 0xffffffff, timing[6]); timing 393 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, timing[7], 0xffffffff, timing[7]); timing 394 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, timing[8], 0xffffffff, timing[8]); timing 395 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, timing[0], 0xffffffff, timing[0]); timing 396 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, timing[2], 0xffffffff, timing[2]); timing 397 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, timing[4], 0xffffffff, timing[4]); timing 398 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, timing[5], 0xffffffff, timing[5]); timing 73 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c CL = (ram->next->bios.timing[1] & 0x0000001f); timing 74 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; timing 88 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; timing 89 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; timing 90 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; timing 1168 drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c struct display_timing timing; timing 1186 drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c err = of_get_display_timing(node, "panel-timing", &timing); timing 1188 drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c videomode_from_timing(&timing, &ddata->vm); timing 145 drivers/gpu/drm/panel/panel-lvds.c struct display_timing timing; timing 149 drivers/gpu/drm/panel/panel-lvds.c ret = of_get_display_timing(np, "panel-timing", &timing); timing 156 drivers/gpu/drm/panel/panel-lvds.c videomode_from_timing(&timing, &lvds->video_mode); timing 122 drivers/gpu/drm/sti/sti_awg_utils.c struct awg_timing *timing) timing 127 drivers/gpu/drm/sti/sti_awg_utils.c if (timing->trailing_pixels > 0) { timing 129 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; timing 132 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->trailing_pixels - 1 + AWG_DELAY; timing 137 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; timing 138 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, timing 141 drivers/gpu/drm/sti/sti_awg_utils.c if (timing->blanking_pixels > 0) { timing 143 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->active_pixels - 1; timing 147 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; timing 156 drivers/gpu/drm/sti/sti_awg_utils.c struct awg_timing *timing) timing 161 drivers/gpu/drm/sti/sti_awg_utils.c if (timing->trailing_lines > 0) { timing 163 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; timing 166 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->trailing_lines - 1; timing 170 drivers/gpu/drm/sti/sti_awg_utils.c tmp_val = timing->active_lines - 1; timing 174 drivers/gpu/drm/sti/sti_awg_utils.c ret |= awg_generate_line_signal(fwparams, timing); timing 182 drivers/gpu/drm/sti/sti_awg_utils.c if (timing->blanking_lines > 0) { timing 184 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_level; timing 187 drivers/gpu/drm/sti/sti_awg_utils.c val = timing->blanking_lines - 1; timing 33 drivers/gpu/drm/sti/sti_awg_utils.h struct awg_timing *timing); timing 57 drivers/gpu/drm/sti/sti_dvo.c struct awg_timing *timing); timing 116 drivers/gpu/drm/sti/sti_dvo.c struct awg_timing timing; timing 121 drivers/gpu/drm/sti/sti_dvo.c timing.total_lines = mode->vtotal; timing 122 drivers/gpu/drm/sti/sti_dvo.c timing.active_lines = mode->vdisplay; timing 123 drivers/gpu/drm/sti/sti_dvo.c timing.blanking_lines = mode->vsync_start - mode->vdisplay; timing 124 drivers/gpu/drm/sti/sti_dvo.c timing.trailing_lines = mode->vtotal - mode->vsync_start; timing 125 drivers/gpu/drm/sti/sti_dvo.c timing.total_pixels = mode->htotal; timing 126 drivers/gpu/drm/sti/sti_dvo.c timing.active_pixels = mode->hdisplay; timing 127 drivers/gpu/drm/sti/sti_dvo.c timing.blanking_pixels = mode->hsync_start - mode->hdisplay; timing 128 drivers/gpu/drm/sti/sti_dvo.c timing.trailing_pixels = mode->htotal - mode->hsync_start; timing 129 drivers/gpu/drm/sti/sti_dvo.c timing.blanking_level = BLANKING_LEVEL; timing 131 drivers/gpu/drm/sti/sti_dvo.c if (config->awg_fwgen_fct(&fw_gen_params, &timing)) { timing 35 drivers/gpu/drm/tegra/dsi.c struct mipi_dphy_timing timing; timing 367 drivers/gpu/drm/tegra/dsi.c const struct mipi_dphy_timing *timing) timing 371 drivers/gpu/drm/tegra/dsi.c value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | timing 372 drivers/gpu/drm/tegra/dsi.c DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | timing 373 drivers/gpu/drm/tegra/dsi.c DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | timing 374 drivers/gpu/drm/tegra/dsi.c DSI_TIMING_FIELD(timing->hsprepare, period, 1); timing 377 drivers/gpu/drm/tegra/dsi.c value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | timing 378 drivers/gpu/drm/tegra/dsi.c DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | timing 379 drivers/gpu/drm/tegra/dsi.c DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | timing 380 drivers/gpu/drm/tegra/dsi.c DSI_TIMING_FIELD(timing->lpx, period, 1); timing 383 drivers/gpu/drm/tegra/dsi.c value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | timing 384 drivers/gpu/drm/tegra/dsi.c DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | timing 388 drivers/gpu/drm/tegra/dsi.c value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | timing 389 drivers/gpu/drm/tegra/dsi.c DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | timing 390 drivers/gpu/drm/tegra/dsi.c DSI_TIMING_FIELD(timing->tago, period, 1); timing 394 drivers/gpu/drm/tegra/dsi.c tegra_dsi_set_phy_timing(dsi->slave, period, timing); timing 923 drivers/gpu/drm/tegra/dsi.c tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); timing 986 drivers/gpu/drm/tegra/dsi.c err = mipi_dphy_timing_get_default(&state->timing, state->period); timing 990 drivers/gpu/drm/tegra/dsi.c err = mipi_dphy_timing_validate(&state->timing, state->period); timing 16 drivers/gpu/drm/tegra/mipi-phy.c int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, timing 19 drivers/gpu/drm/tegra/mipi-phy.c timing->clkmiss = 0; timing 20 drivers/gpu/drm/tegra/mipi-phy.c timing->clkpost = 70 + 52 * period; timing 21 drivers/gpu/drm/tegra/mipi-phy.c timing->clkpre = 8; timing 22 drivers/gpu/drm/tegra/mipi-phy.c timing->clkprepare = 65; timing 23 drivers/gpu/drm/tegra/mipi-phy.c timing->clksettle = 95; timing 24 drivers/gpu/drm/tegra/mipi-phy.c timing->clktermen = 0; timing 25 drivers/gpu/drm/tegra/mipi-phy.c timing->clktrail = 80; timing 26 drivers/gpu/drm/tegra/mipi-phy.c timing->clkzero = 260; timing 27 drivers/gpu/drm/tegra/mipi-phy.c timing->dtermen = 0; timing 28 drivers/gpu/drm/tegra/mipi-phy.c timing->eot = 0; timing 29 drivers/gpu/drm/tegra/mipi-phy.c timing->hsexit = 120; timing 30 drivers/gpu/drm/tegra/mipi-phy.c timing->hsprepare = 65 + 5 * period; timing 31 drivers/gpu/drm/tegra/mipi-phy.c timing->hszero = 145 + 5 * period; timing 32 drivers/gpu/drm/tegra/mipi-phy.c timing->hssettle = 85 + 6 * period; timing 33 drivers/gpu/drm/tegra/mipi-phy.c timing->hsskip = 40; timing 46 drivers/gpu/drm/tegra/mipi-phy.c timing->hstrail = max(4 * 8 * period, 60 + 4 * 4 * period); timing 48 drivers/gpu/drm/tegra/mipi-phy.c timing->init = 100000; timing 49 drivers/gpu/drm/tegra/mipi-phy.c timing->lpx = 60; timing 50 drivers/gpu/drm/tegra/mipi-phy.c timing->taget = 5 * timing->lpx; timing 51 drivers/gpu/drm/tegra/mipi-phy.c timing->tago = 4 * timing->lpx; timing 52 drivers/gpu/drm/tegra/mipi-phy.c timing->tasure = 2 * timing->lpx; timing 53 drivers/gpu/drm/tegra/mipi-phy.c timing->wakeup = 1000000; timing 62 drivers/gpu/drm/tegra/mipi-phy.c int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing, timing 65 drivers/gpu/drm/tegra/mipi-phy.c if (timing->clkmiss > 60) timing 68 drivers/gpu/drm/tegra/mipi-phy.c if (timing->clkpost < (60 + 52 * period)) timing 71 drivers/gpu/drm/tegra/mipi-phy.c if (timing->clkpre < 8) timing 74 drivers/gpu/drm/tegra/mipi-phy.c if (timing->clkprepare < 38 || timing->clkprepare > 95) timing 77 drivers/gpu/drm/tegra/mipi-phy.c if (timing->clksettle < 95 || timing->clksettle > 300) timing 80 drivers/gpu/drm/tegra/mipi-phy.c if (timing->clktermen > 38) timing 83 drivers/gpu/drm/tegra/mipi-phy.c if (timing->clktrail < 60) timing 86 drivers/gpu/drm/tegra/mipi-phy.c if (timing->clkprepare + timing->clkzero < 300) timing 89 drivers/gpu/drm/tegra/mipi-phy.c if (timing->dtermen > 35 + 4 * period) timing 92 drivers/gpu/drm/tegra/mipi-phy.c if (timing->eot > 105 + 12 * period) timing 95 drivers/gpu/drm/tegra/mipi-phy.c if (timing->hsexit < 100) timing 98 drivers/gpu/drm/tegra/mipi-phy.c if (timing->hsprepare < 40 + 4 * period || timing 99 drivers/gpu/drm/tegra/mipi-phy.c timing->hsprepare > 85 + 6 * period) timing 102 drivers/gpu/drm/tegra/mipi-phy.c if (timing->hsprepare + timing->hszero < 145 + 10 * period) timing 105 drivers/gpu/drm/tegra/mipi-phy.c if ((timing->hssettle < 85 + 6 * period) || timing 106 drivers/gpu/drm/tegra/mipi-phy.c (timing->hssettle > 145 + 10 * period)) timing 109 drivers/gpu/drm/tegra/mipi-phy.c if (timing->hsskip < 40 || timing->hsskip > 55 + 4 * period) timing 112 drivers/gpu/drm/tegra/mipi-phy.c if (timing->hstrail < max(8 * period, 60 + 4 * period)) timing 115 drivers/gpu/drm/tegra/mipi-phy.c if (timing->init < 100000) timing 118 drivers/gpu/drm/tegra/mipi-phy.c if (timing->lpx < 50) timing 121 drivers/gpu/drm/tegra/mipi-phy.c if (timing->taget != 5 * timing->lpx) timing 124 drivers/gpu/drm/tegra/mipi-phy.c if (timing->tago != 4 * timing->lpx) timing 127 drivers/gpu/drm/tegra/mipi-phy.c if (timing->tasure < timing->lpx || timing->tasure > 2 * timing->lpx) timing 130 drivers/gpu/drm/tegra/mipi-phy.c if (timing->wakeup < 1000000) timing 43 drivers/gpu/drm/tegra/mipi-phy.h int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, timing 45 drivers/gpu/drm/tegra/mipi-phy.h int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing, timing 172 drivers/gpu/drm/zte/zx_vou.c void __iomem *timing; timing 372 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_active, val); timing 377 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_htiming, val); timing 382 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_vtiming, val); timing 388 drivers/gpu/drm/zte/zx_vou.c val = zx_readl(vou->timing + SEC_V_ACTIVE); timing 391 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + SEC_V_ACTIVE, val); timing 400 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->sec_vtiming, val); timing 409 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask, timing 416 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->timing_shift, val); timing 417 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL); timing 421 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + SCAN_CTRL, scan_mask, timing 425 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, timing 472 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0); timing 505 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_INT_CTRL, int_frame_mask, timing 516 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_INT_CTRL, timing 688 drivers/gpu/drm/zte/zx_vou.c state = zx_readl(vou->timing + TIMING_INT_STATE); timing 689 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + TIMING_INT_STATE, state); timing 744 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + TIMING_INT_STATE, ~0); timing 748 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + TIMING_INT_CTRL, TIMING_INT_ENABLE); timing 784 drivers/gpu/drm/zte/zx_vou.c vou->timing = devm_ioremap_resource(dev, res); timing 785 drivers/gpu/drm/zte/zx_vou.c if (IS_ERR(vou->timing)) { timing 786 drivers/gpu/drm/zte/zx_vou.c ret = PTR_ERR(vou->timing); timing 1157 drivers/i2c/busses/i2c-img-scb.c struct img_i2c_timings timing; timing 1180 drivers/i2c/busses/i2c-img-scb.c timing = timings[0]; timing 1183 drivers/i2c/busses/i2c-img-scb.c timing = timings[i]; timing 1192 drivers/i2c/busses/i2c-img-scb.c timing = timings[ARRAY_SIZE(timings) - 1]; timing 1193 drivers/i2c/busses/i2c-img-scb.c i2c->bitrate = timing.max_bitrate; timing 1252 drivers/i2c/busses/i2c-img-scb.c data = DIV_ROUND_UP(timing.tckl, clk_period); timing 1269 drivers/i2c/busses/i2c-img-scb.c tsdh = DIV_ROUND_UP(timing.tsdh, clk_period); timing 1281 drivers/i2c/busses/i2c-img-scb.c data = timing.tpl / clk_period; timing 1287 drivers/i2c/busses/i2c-img-scb.c data = timing.tph / clk_period; timing 1296 drivers/i2c/busses/i2c-img-scb.c data = timing.tp2s / clk_period; timing 298 drivers/i2c/busses/i2c-stm32f7.c struct stm32f7_i2c_timings timing; timing 588 drivers/i2c/busses/i2c-stm32f7.c &i2c_dev->timing); timing 642 drivers/i2c/busses/i2c-stm32f7.c struct stm32f7_i2c_timings *t = &i2c_dev->timing; timing 643 drivers/i2c/busses/i2c-stm32f7.c u32 timing = 0; timing 646 drivers/i2c/busses/i2c-stm32f7.c timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); timing 647 drivers/i2c/busses/i2c-stm32f7.c timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); timing 648 drivers/i2c/busses/i2c-stm32f7.c timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); timing 649 drivers/i2c/busses/i2c-stm32f7.c timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); timing 650 drivers/i2c/busses/i2c-stm32f7.c timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); timing 651 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); timing 47 drivers/ide/amd74xx.c struct ide_timing *timing) timing 52 drivers/ide/amd74xx.c t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); timing 56 drivers/ide/amd74xx.c ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); timing 59 drivers/ide/amd74xx.c ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); timing 62 drivers/ide/amd74xx.c case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; timing 63 drivers/ide/amd74xx.c case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break; timing 64 drivers/ide/amd74xx.c case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break; timing 65 drivers/ide/amd74xx.c case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break; timing 69 drivers/ide/amd74xx.c if (timing->udma) timing 121 drivers/ide/ht6560b.c u8 select, timing; timing 126 drivers/ide/ht6560b.c timing = HT_TIMING(drive); timing 136 drivers/ide/ht6560b.c if (select != current_select || timing != current_timing) { timing 138 drivers/ide/ht6560b.c current_timing = timing; timing 147 drivers/ide/ht6560b.c outb(timing, hwif->io_ports.device_addr); timing 151 drivers/ide/ht6560b.c drive->name, select, timing); timing 286 drivers/ide/ht6560b.c u8 timing; timing 295 drivers/ide/ht6560b.c timing = ht_pio2timings(drive, pio); timing 300 drivers/ide/ht6560b.c config |= timing; timing 305 drivers/ide/ht6560b.c printk("ht6560b: drive %s tuned to pio mode %#x timing=%#x\n", drive->name, pio, timing); timing 112 drivers/ide/it821x.c static void it821x_program(ide_drive_t *drive, u16 timing) timing 122 drivers/ide/it821x.c conf = timing >> 8; timing 124 drivers/ide/it821x.c conf = timing & 0xFF; timing 138 drivers/ide/it821x.c static void it821x_program_udma(ide_drive_t *drive, u16 timing) timing 148 drivers/ide/it821x.c conf = timing >> 8; timing 150 drivers/ide/it821x.c conf = timing & 0xFF; timing 181 drivers/ide/qd65xx.c static void qd_set_timing (ide_drive_t *drive, u8 timing) timing 186 drivers/ide/qd65xx.c data |= timing; timing 189 drivers/ide/qd65xx.c printk(KERN_DEBUG "%s: %#x\n", drive->name, timing); timing 29 drivers/ide/triflex.c u16 timing = 0; timing 36 drivers/ide/triflex.c timing = 0x0103; timing 39 drivers/ide/triflex.c timing = 0x0203; timing 42 drivers/ide/triflex.c timing = 0x0808; timing 47 drivers/ide/triflex.c timing = 0x0f0f; timing 50 drivers/ide/triflex.c timing = 0x0202; timing 53 drivers/ide/triflex.c timing = 0x0204; timing 56 drivers/ide/triflex.c timing = 0x0404; timing 59 drivers/ide/triflex.c timing = 0x0508; timing 62 drivers/ide/triflex.c timing = 0x0808; timing 67 drivers/ide/triflex.c triflex_timings |= (timing << (16 * unit)); timing 121 drivers/ide/via82cxxx.c static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) timing 130 drivers/ide/via82cxxx.c t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); timing 135 drivers/ide/via82cxxx.c ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); timing 138 drivers/ide/via82cxxx.c ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); timing 141 drivers/ide/via82cxxx.c case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; timing 142 drivers/ide/via82cxxx.c case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; timing 143 drivers/ide/via82cxxx.c case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; timing 144 drivers/ide/via82cxxx.c case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; timing 156 drivers/ide/via82cxxx.c if (timing->udma) { timing 215 drivers/iio/adc/cpcap-adc.c enum cpcap_adc_timing timing; timing 564 drivers/iio/adc/cpcap-adc.c switch (req->timing) { timing 603 drivers/iio/adc/cpcap-adc.c if (req->timing == CPCAP_ADC_TIMING_IMM) { timing 634 drivers/iio/adc/cpcap-adc.c req->timing = CPCAP_ADC_TIMING_IMM; timing 55 drivers/iio/light/tcs3414.c u8 timing; timing 154 drivers/iio/light/tcs3414.c *val2 = tcs3414_times[data->timing & TCS3414_INTEG_MASK] * 1000; timing 185 drivers/iio/light/tcs3414.c data->timing &= ~TCS3414_INTEG_MASK; timing 186 drivers/iio/light/tcs3414.c data->timing |= i; timing 189 drivers/iio/light/tcs3414.c data->timing); timing 315 drivers/iio/light/tcs3414.c data->timing = TCS3414_INTEG_12MS; /* free running */ timing 317 drivers/iio/light/tcs3414.c data->timing); timing 230 drivers/iio/light/tsl2563.c static int tsl2563_adc_shiftbits(u8 timing) timing 234 drivers/iio/light/tsl2563.c switch (timing & TSL2563_TIMING_MASK) { timing 246 drivers/iio/light/tsl2563.c if (!(timing & TSL2563_TIMING_GAIN16)) timing 253 drivers/iio/light/tsl2563.c static u32 tsl2563_normalize_adc(u16 adc, u8 timing) timing 255 drivers/iio/light/tsl2563.c return adc << tsl2563_adc_shiftbits(timing); timing 167 drivers/media/dvb-frontends/stb0899_algo.c s8 timing; timing 174 drivers/media/dvb-frontends/stb0899_algo.c timing = stb0899_read_reg(state, STB0899_RTF); timing 177 drivers/media/dvb-frontends/stb0899_algo.c if ((lock > 48) && (abs(timing) >= 110)) { timing 1183 drivers/media/dvb-frontends/stv0900_sw.c u8 timing; timing 1187 drivers/media/dvb-frontends/stv0900_sw.c timing = stv0900_read_reg(intp, TMGREG2); timing 1191 drivers/media/dvb-frontends/stv0900_sw.c while ((i <= 50) && (timing != 0) && (timing != 0xff)) { timing 1192 drivers/media/dvb-frontends/stv0900_sw.c timing = stv0900_read_reg(intp, TMGREG2); timing 70 drivers/media/i2c/bt819.c static struct timing timing_data[] = { timing 175 drivers/media/i2c/bt819.c struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; timing 178 drivers/media/i2c/bt819.c (((timing->vdelay >> 8) & 0x03) << 6) | timing 179 drivers/media/i2c/bt819.c (((timing->vactive >> 8) & 0x03) << 4) | timing 180 drivers/media/i2c/bt819.c (((timing->hdelay >> 8) & 0x03) << 2) | timing 181 drivers/media/i2c/bt819.c ((timing->hactive >> 8) & 0x03); timing 182 drivers/media/i2c/bt819.c init[0x04 * 2 - 1] = timing->vdelay & 0xff; timing 183 drivers/media/i2c/bt819.c init[0x05 * 2 - 1] = timing->vactive & 0xff; timing 184 drivers/media/i2c/bt819.c init[0x06 * 2 - 1] = timing->hdelay & 0xff; timing 185 drivers/media/i2c/bt819.c init[0x07 * 2 - 1] = timing->hactive & 0xff; timing 186 drivers/media/i2c/bt819.c init[0x08 * 2 - 1] = timing->hscale >> 8; timing 187 drivers/media/i2c/bt819.c init[0x09 * 2 - 1] = timing->hscale & 0xff; timing 238 drivers/media/i2c/bt819.c struct timing *timing = NULL; timing 253 drivers/media/i2c/bt819.c timing = &timing_data[1]; timing 262 drivers/media/i2c/bt819.c timing = &timing_data[0]; timing 269 drivers/media/i2c/bt819.c (((timing->vdelay >> 8) & 0x03) << 6) | timing 270 drivers/media/i2c/bt819.c (((timing->vactive >> 8) & 0x03) << 4) | timing 271 drivers/media/i2c/bt819.c (((timing->hdelay >> 8) & 0x03) << 2) | timing 272 drivers/media/i2c/bt819.c ((timing->hactive >> 8) & 0x03)); timing 273 drivers/media/i2c/bt819.c bt819_write(decoder, 0x04, timing->vdelay & 0xff); timing 274 drivers/media/i2c/bt819.c bt819_write(decoder, 0x05, timing->vactive & 0xff); timing 275 drivers/media/i2c/bt819.c bt819_write(decoder, 0x06, timing->hdelay & 0xff); timing 276 drivers/media/i2c/bt819.c bt819_write(decoder, 0x07, timing->hactive & 0xff); timing 277 drivers/media/i2c/bt819.c bt819_write(decoder, 0x08, (timing->hscale >> 8) & 0xff); timing 278 drivers/media/i2c/bt819.c bt819_write(decoder, 0x09, timing->hscale & 0xff); timing 295 drivers/media/pci/intel/ipu3/ipu3-cio2.c struct cio2_csi2_timing *timing) timing 325 drivers/media/pci/intel/ipu3/ipu3-cio2.c timing->clk_termen = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_A, timing 329 drivers/media/pci/intel/ipu3/ipu3-cio2.c timing->clk_settle = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A, timing 333 drivers/media/pci/intel/ipu3/ipu3-cio2.c timing->dat_termen = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_A, timing 337 drivers/media/pci/intel/ipu3/ipu3-cio2.c timing->dat_settle = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_A, timing 342 drivers/media/pci/intel/ipu3/ipu3-cio2.c dev_dbg(dev, "freq ct value is %d\n", timing->clk_termen); timing 343 drivers/media/pci/intel/ipu3/ipu3-cio2.c dev_dbg(dev, "freq cs value is %d\n", timing->clk_settle); timing 344 drivers/media/pci/intel/ipu3/ipu3-cio2.c dev_dbg(dev, "freq dt value is %d\n", timing->dat_termen); timing 345 drivers/media/pci/intel/ipu3/ipu3-cio2.c dev_dbg(dev, "freq ds value is %d\n", timing->dat_settle); timing 362 drivers/media/pci/intel/ipu3/ipu3-cio2.c struct cio2_csi2_timing timing; timing 371 drivers/media/pci/intel/ipu3/ipu3-cio2.c r = cio2_csi2_calc_timing(cio2, q, &timing); timing 375 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(timing.clk_termen, q->csi_rx_base + timing 377 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(timing.clk_settle, q->csi_rx_base + timing 381 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(timing.dat_termen, q->csi_rx_base + timing 383 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(timing.dat_settle, q->csi_rx_base + timing 361 drivers/media/platform/omap/omap_vout.c struct omap_video_timings *timing; timing 374 drivers/media/platform/omap/omap_vout.c timing = &dssdev->panel.timings; timing 384 drivers/media/platform/omap/omap_vout.c posy = (timing->y_res - win->w.width) - win->w.left; timing 389 drivers/media/platform/omap/omap_vout.c posx = (timing->x_res - win->w.width) - win->w.left; timing 390 drivers/media/platform/omap/omap_vout.c posy = (timing->y_res - win->w.height) - win->w.top; timing 396 drivers/media/platform/omap/omap_vout.c posx = (timing->x_res - win->w.height) - win->w.top; timing 611 drivers/media/platform/omap/omap_vout.c struct omap_video_timings *timing; timing 623 drivers/media/platform/omap/omap_vout.c timing = &dssdev->panel.timings; timing 625 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.height = timing->y_res; timing 626 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.width = timing->x_res; timing 638 drivers/media/platform/omap/omap_vout.c struct omap_video_timings *timing; timing 654 drivers/media/platform/omap/omap_vout.c timing = &dssdev->panel.timings; timing 667 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.height = timing->x_res; timing 668 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.width = timing->y_res; timing 670 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.height = timing->y_res; timing 671 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.width = timing->x_res; timing 821 drivers/media/platform/omap/omap_vout.c struct omap_video_timings *timing; timing 843 drivers/media/platform/omap/omap_vout.c timing = &dssdev->panel.timings; timing 846 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.height = timing->x_res; timing 847 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.width = timing->y_res; timing 849 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.height = timing->y_res; timing 850 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.width = timing->x_res; timing 1194 drivers/media/platform/omap/omap_vout.c struct omap_video_timings *timing; timing 1205 drivers/media/platform/omap/omap_vout.c timing = &dssdev->panel.timings; timing 1207 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.height = timing->y_res; timing 1208 drivers/media/platform/omap/omap_vout.c vout->fbuf.fmt.width = timing->x_res; timing 356 drivers/media/platform/omap3isp/ispcsi2.c struct isp_csi2_timing_cfg *timing) timing 362 drivers/media/platform/omap3isp/ispcsi2.c if (timing->force_rx_mode) timing 363 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); timing 365 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); timing 367 drivers/media/platform/omap3isp/ispcsi2.c if (timing->stop_state_16x) timing 368 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); timing 370 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); timing 372 drivers/media/platform/omap3isp/ispcsi2.c if (timing->stop_state_4x) timing 373 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); timing 375 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); timing 377 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum); timing 378 drivers/media/platform/omap3isp/ispcsi2.c reg |= timing->stop_state_counter << timing 379 drivers/media/platform/omap3isp/ispcsi2.c ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing->ionum); timing 551 drivers/media/platform/omap3isp/ispcsi2.c struct isp_csi2_timing_cfg *timing = &csi2->timing[0]; timing 580 drivers/media/platform/omap3isp/ispcsi2.c timing->ionum = 1; timing 581 drivers/media/platform/omap3isp/ispcsi2.c timing->force_rx_mode = 1; timing 582 drivers/media/platform/omap3isp/ispcsi2.c timing->stop_state_16x = 1; timing 583 drivers/media/platform/omap3isp/ispcsi2.c timing->stop_state_4x = 1; timing 584 drivers/media/platform/omap3isp/ispcsi2.c timing->stop_state_counter = 0x1FF; timing 619 drivers/media/platform/omap3isp/ispcsi2.c csi2_timing_config(isp, csi2, timing); timing 138 drivers/media/platform/omap3isp/ispcsi2.h struct isp_csi2_timing_cfg timing[2]; timing 77 drivers/media/rc/img-ir/img-ir-hw.c static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing, timing 80 drivers/media/rc/img-ir/img-ir-hw.c img_ir_timing_preprocess(&timing->pulse, unit); timing 81 drivers/media/rc/img-ir/img-ir-hw.c img_ir_timing_preprocess(&timing->space, unit); timing 109 drivers/media/rc/img-ir/img-ir-hw.c static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing, timing 112 drivers/media/rc/img-ir/img-ir-hw.c img_ir_timing_defaults(&timing->pulse, &defaults->pulse); timing 113 drivers/media/rc/img-ir/img-ir-hw.c img_ir_timing_defaults(&timing->space, &defaults->space); timing 203 drivers/media/rc/img-ir/img-ir-hw.c static u32 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing, timing 211 drivers/media/rc/img-ir/img-ir-hw.c hw_period.min = timing->pulse.min + timing->space.min; timing 212 drivers/media/rc/img-ir/img-ir-hw.c hw_period.max = timing->pulse.max + timing->space.max; timing 215 drivers/media/rc/img-ir/img-ir-hw.c img_ir_timing_range_convert(&hw_pulse, &timing->pulse, timing 231 drivers/media/rc/img-ir/img-ir-hw.c static u32 img_ir_free_timing(const struct img_ir_free_timing *timing, timing 236 drivers/media/rc/img-ir/img-ir-hw.c if (timing->minlen < 30) timing 237 drivers/media/rc/img-ir/img-ir-hw.c minlen = timing->minlen & -2; timing 241 drivers/media/rc/img-ir/img-ir-hw.c if (timing->maxlen < 48) timing 242 drivers/media/rc/img-ir/img-ir-hw.c maxlen = (timing->maxlen + 1) & -2; timing 246 drivers/media/rc/img-ir/img-ir-hw.c ft_min = (timing->ft_min*clock_hz + 999999) / 1000000; timing 71 drivers/memory/samsung/exynos-srom.c u32 timing[6]; timing 80 drivers/memory/samsung/exynos-srom.c if (of_property_read_u32_array(np, "samsung,srom-timing", timing, timing 81 drivers/memory/samsung/exynos-srom.c ARRAY_SIZE(timing))) timing 94 drivers/memory/samsung/exynos-srom.c writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) | timing 95 drivers/memory/samsung/exynos-srom.c (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) | timing 96 drivers/memory/samsung/exynos-srom.c (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) | timing 97 drivers/memory/samsung/exynos-srom.c (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) | timing 98 drivers/memory/samsung/exynos-srom.c (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) | timing 99 drivers/memory/samsung/exynos-srom.c (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT), timing 313 drivers/memory/tegra/mc.c struct tegra_mc_timing *timing = NULL; timing 317 drivers/memory/tegra/mc.c timing = &mc->timings[i]; timing 322 drivers/memory/tegra/mc.c if (!timing) { timing 329 drivers/memory/tegra/mc.c mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); timing 344 drivers/memory/tegra/mc.c struct tegra_mc_timing *timing, timing 357 drivers/memory/tegra/mc.c timing->rate = tmp; timing 358 drivers/memory/tegra/mc.c timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, timing 360 drivers/memory/tegra/mc.c if (!timing->emem_data) timing 364 drivers/memory/tegra/mc.c timing->emem_data, timing 379 drivers/memory/tegra/mc.c struct tegra_mc_timing *timing; timing 383 drivers/memory/tegra/mc.c mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), timing 391 drivers/memory/tegra/mc.c timing = &mc->timings[i++]; timing 393 drivers/memory/tegra/mc.c err = load_one_timing(mc, timing, child); timing 539 drivers/memory/tegra/tegra124-emc.c struct emc_timing *timing = NULL; timing 544 drivers/memory/tegra/tegra124-emc.c timing = &emc->timings[i]; timing 549 drivers/memory/tegra/tegra124-emc.c if (!timing) { timing 554 drivers/memory/tegra/tegra124-emc.c return timing; timing 560 drivers/memory/tegra/tegra124-emc.c struct emc_timing *timing = tegra_emc_find_timing(emc, rate); timing 568 drivers/memory/tegra/tegra124-emc.c if (!timing) timing 571 drivers/memory/tegra/tegra124-emc.c if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) timing 573 drivers/memory/tegra/tegra124-emc.c else if (timing->emc_mode_1 & 0x1) timing 605 drivers/memory/tegra/tegra124-emc.c if (!(timing->emc_bgbias_ctl0 & timing 625 drivers/memory/tegra/tegra124-emc.c if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && timing 631 drivers/memory/tegra/tegra124-emc.c if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && timing 650 drivers/memory/tegra/tegra124-emc.c if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { timing 652 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_ctt_term_ctrl, timing 658 drivers/memory/tegra/tegra124-emc.c for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) timing 659 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_burst_data[i], timing 662 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); timing 663 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); timing 665 drivers/memory/tegra/tegra124-emc.c tegra_mc_write_emem_configuration(emc->mc, timing->rate); timing 667 drivers/memory/tegra/tegra124-emc.c val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; timing 671 drivers/memory/tegra/tegra124-emc.c if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2) timing 672 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, timing 675 drivers/memory/tegra/tegra124-emc.c if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3) timing 676 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, timing 679 drivers/memory/tegra/tegra124-emc.c if (timing->emc_auto_cal_config != last->emc_auto_cal_config) { timing 680 drivers/memory/tegra/tegra124-emc.c val = timing->emc_auto_cal_config; timing 690 drivers/memory/tegra/tegra124-emc.c if (timing->emc_zcal_interval != 0 && timing 694 drivers/memory/tegra/tegra124-emc.c val = (timing->emc_mrs_wait_cnt timing 700 drivers/memory/tegra/tegra124-emc.c val = timing->emc_mrs_wait_cnt timing 708 drivers/memory/tegra/tegra124-emc.c val = timing->emc_cfg_2; timing 714 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); timing 737 drivers/memory/tegra/tegra124-emc.c if (timing->emc_mode_1 != last->emc_mode_1) timing 738 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); timing 739 drivers/memory/tegra/tegra124-emc.c if (timing->emc_mode_2 != last->emc_mode_2) timing 740 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); timing 742 drivers/memory/tegra/tegra124-emc.c if ((timing->emc_mode_reset != last->emc_mode_reset) || timing 744 drivers/memory/tegra/tegra124-emc.c val = timing->emc_mode_reset; timing 754 drivers/memory/tegra/tegra124-emc.c if (timing->emc_mode_2 != last->emc_mode_2) timing 755 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); timing 756 drivers/memory/tegra/tegra124-emc.c if (timing->emc_mode_1 != last->emc_mode_1) timing 757 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); timing 758 drivers/memory/tegra/tegra124-emc.c if (timing->emc_mode_4 != last->emc_mode_4) timing 759 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); timing 763 drivers/memory/tegra/tegra124-emc.c if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) { timing 773 drivers/memory/tegra/tegra124-emc.c if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) timing 774 drivers/memory/tegra/tegra124-emc.c emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); timing 788 drivers/memory/tegra/tegra124-emc.c struct emc_timing *timing = tegra_emc_find_timing(emc, rate); timing 792 drivers/memory/tegra/tegra124-emc.c if (!timing) timing 799 drivers/memory/tegra/tegra124-emc.c if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) timing 800 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_auto_cal_interval, timing 804 drivers/memory/tegra/tegra124-emc.c if (timing->emc_cfg & EMC_CFG_PWR_MASK) timing 805 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_cfg, emc->regs + EMC_CFG); timing 808 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); timing 812 drivers/memory/tegra/tegra124-emc.c timing->emc_bgbias_ctl0 & timing 814 drivers/memory/tegra/tegra124-emc.c val = timing->emc_bgbias_ctl0; timing 821 drivers/memory/tegra/tegra124-emc.c timing->emc_bgbias_ctl0) { timing 822 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_bgbias_ctl0, timing 826 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_auto_cal_interval, timing 834 drivers/memory/tegra/tegra124-emc.c writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); timing 837 drivers/memory/tegra/tegra124-emc.c emc->last_timing = *timing; timing 843 drivers/memory/tegra/tegra124-emc.c struct emc_timing *timing) timing 848 drivers/memory/tegra/tegra124-emc.c timing->emc_burst_data[i] = timing 851 drivers/memory/tegra/tegra124-emc.c timing->emc_cfg = readl(emc->regs + EMC_CFG); timing 853 drivers/memory/tegra/tegra124-emc.c timing->emc_auto_cal_interval = 0; timing 854 drivers/memory/tegra/tegra124-emc.c timing->emc_zcal_cnt_long = 0; timing 855 drivers/memory/tegra/tegra124-emc.c timing->emc_mode_1 = 0; timing 856 drivers/memory/tegra/tegra124-emc.c timing->emc_mode_2 = 0; timing 857 drivers/memory/tegra/tegra124-emc.c timing->emc_mode_4 = 0; timing 858 drivers/memory/tegra/tegra124-emc.c timing->emc_mode_reset = 0; timing 875 drivers/memory/tegra/tegra124-emc.c struct emc_timing *timing, timing 888 drivers/memory/tegra/tegra124-emc.c timing->rate = value; timing 891 drivers/memory/tegra/tegra124-emc.c timing->emc_burst_data, timing 892 drivers/memory/tegra/tegra124-emc.c ARRAY_SIZE(timing->emc_burst_data)); timing 901 drivers/memory/tegra/tegra124-emc.c err = of_property_read_u32(node, dtprop, &timing->prop); \ timing 950 drivers/memory/tegra/tegra124-emc.c struct emc_timing *timing; timing 954 drivers/memory/tegra/tegra124-emc.c emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), timing 962 drivers/memory/tegra/tegra124-emc.c timing = &emc->timings[i++]; timing 964 drivers/memory/tegra/tegra124-emc.c err = load_one_timing_from_dt(emc, timing, child); timing 971 drivers/memory/tegra/tegra124-emc.c sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, timing 1029 drivers/memory/tegra/tegra124-emc.c struct emc_timing *timing = &emc->timings[i]; timing 1031 drivers/memory/tegra/tegra124-emc.c seq_printf(s, "%s%lu", prefix, timing->rate); timing 178 drivers/memory/tegra/tegra20-emc.c struct emc_timing *timing = NULL; timing 183 drivers/memory/tegra/tegra20-emc.c timing = &emc->timings[i]; timing 188 drivers/memory/tegra/tegra20-emc.c if (!timing) { timing 193 drivers/memory/tegra/tegra20-emc.c return timing; timing 198 drivers/memory/tegra/tegra20-emc.c struct emc_timing *timing = tegra_emc_find_timing(emc, rate); timing 201 drivers/memory/tegra/tegra20-emc.c if (!timing) timing 205 drivers/memory/tegra/tegra20-emc.c __func__, timing->rate, rate); timing 208 drivers/memory/tegra/tegra20-emc.c for (i = 0; i < ARRAY_SIZE(timing->data); i++) timing 209 drivers/memory/tegra/tegra20-emc.c writel_relaxed(timing->data[i], timing 279 drivers/memory/tegra/tegra20-emc.c struct emc_timing *timing, timing 298 drivers/memory/tegra/tegra20-emc.c timing->data, timing 311 drivers/memory/tegra/tegra20-emc.c timing->rate = rate * 2 * 1000; timing 314 drivers/memory/tegra/tegra20-emc.c __func__, node, timing->rate); timing 337 drivers/memory/tegra/tegra20-emc.c struct emc_timing *timing; timing 347 drivers/memory/tegra/tegra20-emc.c emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), timing 353 drivers/memory/tegra/tegra20-emc.c timing = emc->timings; timing 356 drivers/memory/tegra/tegra20-emc.c err = load_one_timing_from_dt(emc, timing++, child); timing 363 drivers/memory/tegra/tegra20-emc.c sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, timing 908 drivers/mmc/core/core.c 1 << ios->bus_width, ios->timing); timing 999 drivers/mmc/core/core.c host->ios.timing = MMC_TIMING_LEGACY; timing 1271 drivers/mmc/core/core.c void mmc_set_timing(struct mmc_host *host, unsigned int timing) timing 1273 drivers/mmc/core/core.c host->ios.timing = timing; timing 51 drivers/mmc/core/core.h void mmc_set_timing(struct mmc_host *host, unsigned int timing); timing 118 drivers/mmc/core/debugfs.c switch (ios->timing) { timing 157 drivers/mmc/core/debugfs.c seq_printf(s, "timing spec:\t%u (%s)\n", ios->timing, str); timing 137 drivers/mmc/core/host.c if (host->ios.timing == MMC_TIMING_MMC_HS400) { timing 62 drivers/mmc/core/host.h return card->host->ios.timing == MMC_TIMING_MMC_HS200; timing 67 drivers/mmc/core/host.h return card->host->ios.timing == MMC_TIMING_MMC_DDR52; timing 72 drivers/mmc/core/host.h return card->host->ios.timing == MMC_TIMING_MMC_HS400; timing 1464 drivers/mmc/core/mmc.c old_timing = host->ios.timing; timing 526 drivers/mmc/core/mmc_ops.c unsigned int timeout_ms, unsigned char timing, timing 533 drivers/mmc/core/mmc_ops.c unsigned char old_timing = host->ios.timing; timing 589 drivers/mmc/core/mmc_ops.c if (timing) timing 590 drivers/mmc/core/mmc_ops.c mmc_set_timing(host, timing); timing 594 drivers/mmc/core/mmc_ops.c if (err && timing) timing 35 drivers/mmc/core/mmc_ops.h unsigned int timeout_ms, unsigned char timing, timing 464 drivers/mmc/core/sd.c unsigned int timing = 0; timing 468 drivers/mmc/core/sd.c timing = MMC_TIMING_UHS_SDR104; timing 472 drivers/mmc/core/sd.c timing = MMC_TIMING_UHS_DDR50; timing 476 drivers/mmc/core/sd.c timing = MMC_TIMING_UHS_SDR50; timing 480 drivers/mmc/core/sd.c timing = MMC_TIMING_UHS_SDR25; timing 484 drivers/mmc/core/sd.c timing = MMC_TIMING_UHS_SDR12; timing 499 drivers/mmc/core/sd.c mmc_set_timing(card->host, timing); timing 643 drivers/mmc/core/sd.c (card->host->ios.timing == MMC_TIMING_UHS_SDR50 || timing 644 drivers/mmc/core/sd.c card->host->ios.timing == MMC_TIMING_UHS_DDR50 || timing 645 drivers/mmc/core/sd.c card->host->ios.timing == MMC_TIMING_UHS_SDR104)) { timing 655 drivers/mmc/core/sd.c if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { timing 440 drivers/mmc/core/sdio.c unsigned int bus_speed, timing; timing 453 drivers/mmc/core/sdio.c timing = MMC_TIMING_UHS_SDR12; timing 457 drivers/mmc/core/sdio.c timing = MMC_TIMING_UHS_SDR104; timing 463 drivers/mmc/core/sdio.c timing = MMC_TIMING_UHS_DDR50; timing 470 drivers/mmc/core/sdio.c timing = MMC_TIMING_UHS_SDR50; timing 477 drivers/mmc/core/sdio.c timing = MMC_TIMING_UHS_SDR25; timing 485 drivers/mmc/core/sdio.c timing = MMC_TIMING_UHS_SDR12; timing 504 drivers/mmc/core/sdio.c mmc_set_timing(card->host, timing); timing 539 drivers/mmc/core/sdio.c ((card->host->ios.timing == MMC_TIMING_UHS_SDR50) || timing 540 drivers/mmc/core/sdio.c (card->host->ios.timing == MMC_TIMING_UHS_SDR104))) timing 696 drivers/mmc/host/alcor.c if (ios->timing == MMC_TIMING_LEGACY) { timing 1451 drivers/mmc/host/atmel-mci.c if (ios->timing == MMC_TIMING_SD_HS) timing 869 drivers/mmc/host/cavium.c if (ios->bus_width && ios->timing == MMC_TIMING_MMC_DDR52) timing 882 drivers/mmc/host/cavium.c (ios->timing == MMC_TIMING_MMC_HS)) | timing 507 drivers/mmc/host/cqhci.c u8 timing; timing 511 drivers/mmc/host/cqhci.c timing = 0x1; timing 515 drivers/mmc/host/cqhci.c timing = 0x0; timing 518 drivers/mmc/host/cqhci.c timing = 0x1; timing 530 drivers/mmc/host/cqhci.c CQHCI_CMD_TIMING(timing) | CQHCI_RESP_TYPE(resp_type)); timing 536 drivers/mmc/host/cqhci.c mmc_hostname(mmc), mrq->cmd->opcode, timing, resp_type); timing 130 drivers/mmc/host/dw_mmc-exynos.c static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) timing 141 drivers/mmc/host/dw_mmc-exynos.c clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; timing 230 drivers/mmc/host/dw_mmc-exynos.c static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) timing 240 drivers/mmc/host/dw_mmc-exynos.c if (timing == MMC_TIMING_MMC_HS400) timing 249 drivers/mmc/host/dw_mmc-exynos.c if (timing == MMC_TIMING_MMC_HS400) { timing 252 drivers/mmc/host/dw_mmc-exynos.c } else if (timing == MMC_TIMING_UHS_SDR104) { timing 298 drivers/mmc/host/dw_mmc-exynos.c u32 timing = ios->timing, clksel; timing 300 drivers/mmc/host/dw_mmc-exynos.c switch (timing) { timing 330 drivers/mmc/host/dw_mmc-exynos.c dw_mci_exynos_config_hs400(host, timing); timing 340 drivers/mmc/host/dw_mmc-exynos.c u32 timing[2]; timing 364 drivers/mmc/host/dw_mmc-exynos.c "samsung,dw-mshc-sdr-timing", timing, 2); timing 368 drivers/mmc/host/dw_mmc-exynos.c priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); timing 371 drivers/mmc/host/dw_mmc-exynos.c "samsung,dw-mshc-ddr-timing", timing, 2); timing 375 drivers/mmc/host/dw_mmc-exynos.c priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); timing 378 drivers/mmc/host/dw_mmc-exynos.c "samsung,dw-mshc-hs400-timing", timing, 2); timing 384 drivers/mmc/host/dw_mmc-exynos.c priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], timing 38 drivers/mmc/host/dw_mmc-hi3798cv200.c if (ios->timing == MMC_TIMING_MMC_DDR52 || timing 39 drivers/mmc/host/dw_mmc-hi3798cv200.c ios->timing == MMC_TIMING_UHS_DDR50) timing 46 drivers/mmc/host/dw_mmc-hi3798cv200.c if (ios->timing == MMC_TIMING_MMC_DDR52) timing 53 drivers/mmc/host/dw_mmc-hi3798cv200.c if (ios->timing == MMC_TIMING_MMC_HS400) timing 59 drivers/mmc/host/dw_mmc-hi3798cv200.c if (ios->timing == MMC_TIMING_MMC_HS || timing 60 drivers/mmc/host/dw_mmc-hi3798cv200.c ios->timing == MMC_TIMING_LEGACY) timing 62 drivers/mmc/host/dw_mmc-hi3798cv200.c else if (ios->timing == MMC_TIMING_MMC_HS200) timing 216 drivers/mmc/host/dw_mmc-k3.c static void dw_mci_hs_set_timing(struct dw_mci *host, int timing, timing 230 drivers/mmc/host/dw_mmc-k3.c drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase; timing 231 drivers/mmc/host/dw_mmc-k3.c smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly; timing 233 drivers/mmc/host/dw_mmc-k3.c smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max + timing 234 drivers/mmc/host/dw_mmc-k3.c hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2; timing 236 drivers/mmc/host/dw_mmc-k3.c switch (timing) { timing 315 drivers/mmc/host/dw_mmc-k3.c dw_mci_hs_set_timing(host, ios->timing, -1); timing 380 drivers/mmc/host/dw_mmc-k3.c dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase); timing 394 drivers/mmc/host/dw_mmc-k3.c dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl); timing 47 drivers/mmc/host/dw_mmc-rockchip.c ios->timing == MMC_TIMING_MMC_DDR52) timing 104 drivers/mmc/host/dw_mmc-rockchip.c switch (ios->timing) { timing 1042 drivers/mmc/host/dw_mmc.c host->timing != MMC_TIMING_MMC_HS400) timing 1050 drivers/mmc/host/dw_mmc.c if (host->timing != MMC_TIMING_MMC_HS200 && timing 1051 drivers/mmc/host/dw_mmc.c host->timing != MMC_TIMING_UHS_SDR104 && timing 1052 drivers/mmc/host/dw_mmc.c host->timing != MMC_TIMING_MMC_HS400) timing 1425 drivers/mmc/host/dw_mmc.c if (ios->timing == MMC_TIMING_MMC_DDR52 || timing 1426 drivers/mmc/host/dw_mmc.c ios->timing == MMC_TIMING_UHS_DDR50 || timing 1427 drivers/mmc/host/dw_mmc.c ios->timing == MMC_TIMING_MMC_HS400) timing 1433 drivers/mmc/host/dw_mmc.c slot->host->timing = ios->timing; timing 171 drivers/mmc/host/dw_mmc.h unsigned char timing; timing 552 drivers/mmc/host/meson-gx-mmc.c switch (ios->timing) { timing 569 drivers/mmc/host/meson-gx-mmc.c switch (ios->timing) { timing 415 drivers/mmc/host/mmci.c if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || timing 416 drivers/mmc/host/mmci.c host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) timing 1037 drivers/mmc/host/mmci.c if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || timing 1038 drivers/mmc/host/mmci.c host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) timing 174 drivers/mmc/host/mmci_stm32_sdmmc.c if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 || timing 175 drivers/mmc/host/mmci_stm32_sdmmc.c host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) timing 221 drivers/mmc/host/mmci_stm32_sdmmc.c if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) { timing 223 drivers/mmc/host/mmci_stm32_sdmmc.c if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) { timing 422 drivers/mmc/host/mtk-sd.c unsigned char timing; timing 749 drivers/mmc/host/mtk-sd.c static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) timing 772 drivers/mmc/host/mtk-sd.c if (timing == MMC_TIMING_UHS_DDR50 || timing 773 drivers/mmc/host/mtk-sd.c timing == MMC_TIMING_MMC_DDR52 || timing 774 drivers/mmc/host/mtk-sd.c timing == MMC_TIMING_MMC_HS400) { timing 775 drivers/mmc/host/mtk-sd.c if (timing == MMC_TIMING_MMC_HS400) timing 789 drivers/mmc/host/mtk-sd.c if (timing == MMC_TIMING_MMC_HS400 && timing 841 drivers/mmc/host/mtk-sd.c host->timing = timing; timing 876 drivers/mmc/host/mtk-sd.c if (timing == MMC_TIMING_MMC_HS400 && timing 882 drivers/mmc/host/mtk-sd.c timing); timing 1697 drivers/mmc/host/mtk-sd.c if (host->mclk != ios->clock || host->timing != ios->timing) timing 1698 drivers/mmc/host/mtk-sd.c msdc_set_mclk(host, ios->timing, ios->clock); timing 1792 drivers/mmc/host/mtk-sd.c if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || timing 1793 drivers/mmc/host/mtk-sd.c mmc->ios.timing == MMC_TIMING_UHS_SDR104) timing 1887 drivers/mmc/host/mtk-sd.c if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || timing 1888 drivers/mmc/host/mtk-sd.c mmc->ios.timing == MMC_TIMING_UHS_SDR104) timing 645 drivers/mmc/host/mvsdio.c if (ios->timing == MMC_TIMING_MMC_HS || timing 646 drivers/mmc/host/mvsdio.c ios->timing == MMC_TIMING_SD_HS) timing 568 drivers/mmc/host/omap_hsmmc.c (ios->timing != MMC_TIMING_MMC_DDR52) && timing 569 drivers/mmc/host/omap_hsmmc.c (ios->timing != MMC_TIMING_UHS_DDR50) && timing 589 drivers/mmc/host/omap_hsmmc.c if (ios->timing == MMC_TIMING_MMC_DDR52 || timing 590 drivers/mmc/host/omap_hsmmc.c ios->timing == MMC_TIMING_UHS_DDR50) timing 182 drivers/mmc/host/renesas_sdhi_core.c if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) timing 502 drivers/mmc/host/renesas_sdhi_core.c if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && timing 503 drivers/mmc/host/renesas_sdhi_core.c !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && timing 504 drivers/mmc/host/renesas_sdhi_core.c !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) timing 965 drivers/mmc/host/rtsx_pci_sdmmc.c static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) timing 972 drivers/mmc/host/rtsx_pci_sdmmc.c switch (timing) { timing 1054 drivers/mmc/host/rtsx_pci_sdmmc.c sd_set_timing(host, ios->timing); timing 1059 drivers/mmc/host/rtsx_pci_sdmmc.c switch (ios->timing) { timing 1278 drivers/mmc/host/rtsx_pci_sdmmc.c switch (mmc->ios.timing) { timing 1299 drivers/mmc/host/rtsx_pci_sdmmc.c if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || timing 1300 drivers/mmc/host/rtsx_pci_sdmmc.c (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) timing 1302 drivers/mmc/host/rtsx_pci_sdmmc.c else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) timing 1048 drivers/mmc/host/rtsx_usb_sdmmc.c unsigned char timing, bool *ddr_mode) timing 1057 drivers/mmc/host/rtsx_usb_sdmmc.c switch (timing) { timing 1121 drivers/mmc/host/rtsx_usb_sdmmc.c sd_set_timing(host, ios->timing, &host->ddr_mode); timing 1126 drivers/mmc/host/rtsx_usb_sdmmc.c switch (ios->timing) { timing 561 drivers/mmc/host/sdhci-acpi.c unsigned int old_timing = host->timing; timing 565 drivers/mmc/host/sdhci-acpi.c ios->timing == MMC_TIMING_MMC_HS) timing 568 drivers/mmc/host/sdhci-acpi.c ios->timing == MMC_TIMING_MMC_HS400) { timing 198 drivers/mmc/host/sdhci-cadence.c unsigned int timing) timing 203 drivers/mmc/host/sdhci-cadence.c switch (timing) { timing 228 drivers/mmc/host/sdhci-cadence.c sdhci_set_uhs_signaling(host, timing); timing 293 drivers/mmc/host/sdhci-cadence.c if (host->timing != MMC_TIMING_MMC_HS200) timing 862 drivers/mmc/host/sdhci-esdhc-imx.c if (host->timing == MMC_TIMING_UHS_DDR50) timing 1042 drivers/mmc/host/sdhci-esdhc-imx.c static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) timing 1054 drivers/mmc/host/sdhci-esdhc-imx.c switch (timing) { timing 1092 drivers/mmc/host/sdhci-esdhc-imx.c esdhc_change_pinstate(host, timing); timing 312 drivers/mmc/host/sdhci-msm.c if (ios.timing == MMC_TIMING_UHS_DDR50 || timing 313 drivers/mmc/host/sdhci-msm.c ios.timing == MMC_TIMING_MMC_DDR52 || timing 314 drivers/mmc/host/sdhci-msm.c ios.timing == MMC_TIMING_MMC_HS400 || timing 334 drivers/mmc/host/sdhci-msm.c curr_ios.timing); timing 340 drivers/mmc/host/sdhci-msm.c curr_ios.timing); timing 816 drivers/mmc/host/sdhci-msm.c if (ios.timing == MMC_TIMING_MMC_HS400 || timing 1042 drivers/mmc/host/sdhci-msm.c !(ios->timing == MMC_TIMING_MMC_HS400 || timing 1043 drivers/mmc/host/sdhci-msm.c ios->timing == MMC_TIMING_MMC_HS200 || timing 1044 drivers/mmc/host/sdhci-msm.c ios->timing == MMC_TIMING_UHS_SDR104) || timing 1283 drivers/mmc/host/sdhci-msm.c if (mmc->ios.timing == MMC_TIMING_MMC_HS400) timing 110 drivers/mmc/host/sdhci-of-at91.c unsigned int timing) timing 112 drivers/mmc/host/sdhci-of-at91.c if (timing == MMC_TIMING_MMC_DDR52) timing 114 drivers/mmc/host/sdhci-of-at91.c sdhci_set_uhs_signaling(host, timing); timing 617 drivers/mmc/host/sdhci-of-esdhc.c esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) timing 620 drivers/mmc/host/sdhci-of-esdhc.c fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; timing 638 drivers/mmc/host/sdhci-of-esdhc.c (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || timing 669 drivers/mmc/host/sdhci-of-esdhc.c if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && timing 1075 drivers/mmc/host/sdhci-of-esdhc.c unsigned int timing) timing 1077 drivers/mmc/host/sdhci-of-esdhc.c if (timing == MMC_TIMING_MMC_HS400) timing 1080 drivers/mmc/host/sdhci-of-esdhc.c sdhci_set_uhs_signaling(host, timing); timing 103 drivers/mmc/host/sdhci-omap.c u8 timing; timing 302 drivers/mmc/host/sdhci-omap.c if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50)) timing 559 drivers/mmc/host/sdhci-omap.c static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing) timing 568 drivers/mmc/host/sdhci-omap.c if (omap_host->timing == timing) timing 573 drivers/mmc/host/sdhci-omap.c pinctrl_state = omap_host->pinctrl_state[timing]; timing 581 drivers/mmc/host/sdhci-omap.c omap_host->timing = timing; timing 620 drivers/mmc/host/sdhci-omap.c sdhci_omap_set_timing(omap_host, ios->timing); timing 758 drivers/mmc/host/sdhci-omap.c unsigned int timing) timing 767 drivers/mmc/host/sdhci-omap.c if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) timing 773 drivers/mmc/host/sdhci-omap.c sdhci_set_uhs_signaling(host, timing); timing 1065 drivers/mmc/host/sdhci-omap.c omap_host->timing = MMC_TIMING_LEGACY; timing 267 drivers/mmc/host/sdhci-pci-arasan.c switch (host->mmc->ios.timing) { timing 1561 drivers/mmc/host/sdhci-pci-core.c if (host->timing == MMC_TIMING_MMC_HS200) timing 308 drivers/mmc/host/sdhci-pci-o2micro.c if (host->timing != MMC_TIMING_MMC_HS200) timing 86 drivers/mmc/host/sdhci-sprd.c u8 timing; timing 302 drivers/mmc/host/sdhci-sprd.c unsigned int timing) timing 309 drivers/mmc/host/sdhci-sprd.c if (timing == host->timing) timing 315 drivers/mmc/host/sdhci-sprd.c switch (timing) { timing 347 drivers/mmc/host/sdhci-sprd.c sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); timing 505 drivers/mmc/host/sdhci-sprd.c index = sdhci_sprd_phy_cfgs[i].timing; timing 524 drivers/mmc/host/sdhci-tegra.c switch (ios->timing) { timing 953 drivers/mmc/host/sdhci-tegra.c unsigned timing) timing 964 drivers/mmc/host/sdhci-tegra.c switch (timing) { timing 999 drivers/mmc/host/sdhci-tegra.c sdhci_set_uhs_signaling(host, timing); timing 443 drivers/mmc/host/sdhci-xenon-phy.c if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400)) timing 490 drivers/mmc/host/sdhci-xenon-phy.c unsigned char timing) timing 506 drivers/mmc/host/sdhci-xenon-phy.c switch (timing) { timing 545 drivers/mmc/host/sdhci-xenon-phy.c unsigned char timing) timing 576 drivers/mmc/host/sdhci-xenon-phy.c if (timing == MMC_TIMING_LEGACY) { timing 577 drivers/mmc/host/sdhci-xenon-phy.c xenon_emmc_phy_slow_mode(host, timing); timing 592 drivers/mmc/host/sdhci-xenon-phy.c if (xenon_emmc_phy_slow_mode(host, timing)) timing 614 drivers/mmc/host/sdhci-xenon-phy.c switch (timing) { timing 637 drivers/mmc/host/sdhci-xenon-phy.c if (timing == MMC_TIMING_MMC_HS400) timing 742 drivers/mmc/host/sdhci-xenon-phy.c switch (host->timing) { timing 794 drivers/mmc/host/sdhci-xenon-phy.c (ios->timing == priv->timing)) timing 797 drivers/mmc/host/sdhci-xenon-phy.c xenon_emmc_phy_set(host, ios->timing); timing 802 drivers/mmc/host/sdhci-xenon-phy.c priv->timing = ios->timing; timing 806 drivers/mmc/host/sdhci-xenon-phy.c if (ios->timing == MMC_TIMING_LEGACY) timing 191 drivers/mmc/host/sdhci-xenon.c unsigned int timing) timing 198 drivers/mmc/host/sdhci-xenon.c if (timing == MMC_TIMING_MMC_HS200) timing 200 drivers/mmc/host/sdhci-xenon.c else if (timing == MMC_TIMING_UHS_SDR104) timing 202 drivers/mmc/host/sdhci-xenon.c else if (timing == MMC_TIMING_UHS_SDR12) timing 204 drivers/mmc/host/sdhci-xenon.c else if (timing == MMC_TIMING_UHS_SDR25) timing 206 drivers/mmc/host/sdhci-xenon.c else if (timing == MMC_TIMING_UHS_SDR50) timing 208 drivers/mmc/host/sdhci-xenon.c else if ((timing == MMC_TIMING_UHS_DDR50) || timing 209 drivers/mmc/host/sdhci-xenon.c (timing == MMC_TIMING_MMC_DDR52)) timing 211 drivers/mmc/host/sdhci-xenon.c else if (timing == MMC_TIMING_MMC_HS400) timing 284 drivers/mmc/host/sdhci-xenon.c if ((ios->timing == MMC_TIMING_MMC_HS400) || timing 285 drivers/mmc/host/sdhci-xenon.c (ios->timing == MMC_TIMING_MMC_HS200) || timing 286 drivers/mmc/host/sdhci-xenon.c (ios->timing == MMC_TIMING_MMC_HS)) { timing 353 drivers/mmc/host/sdhci-xenon.c if (host->timing == MMC_TIMING_UHS_DDR50 || timing 354 drivers/mmc/host/sdhci-xenon.c host->timing == MMC_TIMING_MMC_DDR52) timing 81 drivers/mmc/host/sdhci-xenon.h unsigned char timing; timing 1511 drivers/mmc/host/sdhci.c switch (host->timing) { timing 1865 drivers/mmc/host/sdhci.c void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) timing 1872 drivers/mmc/host/sdhci.c if ((timing == MMC_TIMING_MMC_HS200) || timing 1873 drivers/mmc/host/sdhci.c (timing == MMC_TIMING_UHS_SDR104)) timing 1875 drivers/mmc/host/sdhci.c else if (timing == MMC_TIMING_UHS_SDR12) timing 1877 drivers/mmc/host/sdhci.c else if (timing == MMC_TIMING_UHS_SDR25) timing 1879 drivers/mmc/host/sdhci.c else if (timing == MMC_TIMING_UHS_SDR50) timing 1881 drivers/mmc/host/sdhci.c else if ((timing == MMC_TIMING_UHS_DDR50) || timing 1882 drivers/mmc/host/sdhci.c (timing == MMC_TIMING_MMC_DDR52)) timing 1884 drivers/mmc/host/sdhci.c else if (timing == MMC_TIMING_MMC_HS400) timing 1949 drivers/mmc/host/sdhci.c if (ios->timing == MMC_TIMING_SD_HS || timing 1950 drivers/mmc/host/sdhci.c ios->timing == MMC_TIMING_MMC_HS || timing 1951 drivers/mmc/host/sdhci.c ios->timing == MMC_TIMING_MMC_HS400 || timing 1952 drivers/mmc/host/sdhci.c ios->timing == MMC_TIMING_MMC_HS200 || timing 1953 drivers/mmc/host/sdhci.c ios->timing == MMC_TIMING_MMC_DDR52 || timing 1954 drivers/mmc/host/sdhci.c ios->timing == MMC_TIMING_UHS_SDR50 || timing 1955 drivers/mmc/host/sdhci.c ios->timing == MMC_TIMING_UHS_SDR104 || timing 1956 drivers/mmc/host/sdhci.c ios->timing == MMC_TIMING_UHS_DDR50 || timing 1957 drivers/mmc/host/sdhci.c ios->timing == MMC_TIMING_UHS_SDR25) timing 2013 drivers/mmc/host/sdhci.c host->ops->set_uhs_signaling(host, ios->timing); timing 2014 drivers/mmc/host/sdhci.c host->timing = ios->timing; timing 2017 drivers/mmc/host/sdhci.c ((ios->timing == MMC_TIMING_UHS_SDR12) || timing 2018 drivers/mmc/host/sdhci.c (ios->timing == MMC_TIMING_UHS_SDR25) || timing 2019 drivers/mmc/host/sdhci.c (ios->timing == MMC_TIMING_UHS_SDR50) || timing 2020 drivers/mmc/host/sdhci.c (ios->timing == MMC_TIMING_UHS_SDR104) || timing 2021 drivers/mmc/host/sdhci.c (ios->timing == MMC_TIMING_UHS_DDR50) || timing 2022 drivers/mmc/host/sdhci.c (ios->timing == MMC_TIMING_MMC_DDR52))) { timing 2456 drivers/mmc/host/sdhci.c switch (host->timing) { timing 576 drivers/mmc/host/sdhci.h unsigned timing; /* Current timing */ timing 769 drivers/mmc/host/sdhci.h void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); timing 120 drivers/mmc/host/sdhci_am654.c if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { timing 220 drivers/mmc/host/sdhci_am654.c unsigned char timing = host->mmc->ios.timing; timing 223 drivers/mmc/host/sdhci_am654.c switch (timing) { timing 226 drivers/mmc/host/sh_mmcif.c unsigned char timing; timing 842 drivers/mmc/host/sh_mmcif.c switch (host->timing) { timing 1066 drivers/mmc/host/sh_mmcif.c host->timing = ios->timing; timing 736 drivers/mmc/host/sunxi-mmc.c if (ios->timing != MMC_TIMING_UHS_DDR50 && timing 737 drivers/mmc/host/sunxi-mmc.c ios->timing != MMC_TIMING_MMC_DDR52) { timing 782 drivers/mmc/host/sunxi-mmc.c if (ios->timing == MMC_TIMING_MMC_DDR52 && timing 886 drivers/mmc/host/sunxi-mmc.c if (ios->timing == MMC_TIMING_UHS_DDR50 || timing 887 drivers/mmc/host/sunxi-mmc.c ios->timing == MMC_TIMING_MMC_DDR52) timing 745 drivers/mmc/host/usdhi6rol0.c if (ios->timing != MMC_TIMING_UHS_DDR50) { timing 820 drivers/mmc/host/usdhi6rol0.c ios->clock, ios->vdd, ios->power_mode, ios->bus_width, ios->timing); timing 848 drivers/mmc/host/usdhi6rol0.c if (ios->timing == MMC_TIMING_UHS_DDR50) timing 855 drivers/mmc/host/usdhi6rol0.c mode = ios->timing == MMC_TIMING_UHS_DDR50; timing 377 drivers/mmc/host/ushc.c ushc_set_bus_freq(ushc, ios->clock, ios->timing == MMC_TIMING_SD_HS); timing 740 drivers/mmc/host/via-sdmmc.c if (ios->timing == MMC_TIMING_SD_HS) timing 92 drivers/mtd/nand/raw/cafe_nand.c static int timing[3]; timing 93 drivers/mtd/nand/raw/cafe_nand.c module_param_array(timing, int, &numtimings, 0644); timing 732 drivers/mtd/nand/raw/cafe_nand.c timing[0], timing[1], timing[2]); timing 734 drivers/mtd/nand/raw/cafe_nand.c timing[0] = cafe_readl(cafe, NAND_TIMING1); timing 735 drivers/mtd/nand/raw/cafe_nand.c timing[1] = cafe_readl(cafe, NAND_TIMING2); timing 736 drivers/mtd/nand/raw/cafe_nand.c timing[2] = cafe_readl(cafe, NAND_TIMING3); timing 738 drivers/mtd/nand/raw/cafe_nand.c if (timing[0] | timing[1] | timing[2]) { timing 740 drivers/mtd/nand/raw/cafe_nand.c timing[0], timing[1], timing[2]); timing 743 drivers/mtd/nand/raw/cafe_nand.c timing[0] = timing[1] = timing[2] = 0xffffffff; timing 751 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, timing[0], NAND_TIMING1); timing 752 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, timing[1], NAND_TIMING2); timing 753 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, timing[2], NAND_TIMING3); timing 849 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, timing[0], NAND_TIMING1); timing 850 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, timing[1], NAND_TIMING2); timing 851 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, timing[2], NAND_TIMING3); timing 58 drivers/mtd/nand/raw/davinci_nand.c struct davinci_aemif_timing *timing; timing 760 drivers/mtd/nand/raw/davinci_nand.c info->timing = pdata->timing; timing 338 drivers/mtd/nand/raw/fsl_ifc_nand.c int timing = IFC_FIR_OP_RB; timing 340 drivers/mtd/nand/raw/fsl_ifc_nand.c timing = IFC_FIR_OP_RBCD; timing 346 drivers/mtd/nand/raw/fsl_ifc_nand.c (timing << IFC_NAND_FIR0_OP2_SHIFT), timing 167 drivers/mtd/nand/raw/meson_nand.c struct nand_timing timing; timing 233 drivers/mtd/nand/raw/meson_nand.c nfc->timing.twb = meson_chip->twb; timing 234 drivers/mtd/nand/raw/meson_nand.c nfc->timing.tadl = meson_chip->tadl; timing 235 drivers/mtd/nand/raw/meson_nand.c nfc->timing.tbers_max = meson_chip->tbers_max; timing 395 drivers/mtd/nand/raw/meson_nand.c meson_nfc_cmd_idle(nfc, nfc->timing.twb); timing 407 drivers/mtd/nand/raw/meson_nand.c | nfc->param.chip_select | nfc->timing.tbers_max; timing 620 drivers/mtd/nand/raw/meson_nand.c meson_nfc_cmd_idle(nfc, nfc->timing.tadl); timing 1464 drivers/mtd/nand/raw/stm32_fmc2_nand.c unsigned long timing, tar, tclr, thiz, twait; timing 1468 drivers/mtd/nand/raw/stm32_fmc2_nand.c timing = DIV_ROUND_UP(tar, hclkp) - 1; timing 1469 drivers/mtd/nand/raw/stm32_fmc2_nand.c tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); timing 1472 drivers/mtd/nand/raw/stm32_fmc2_nand.c timing = DIV_ROUND_UP(tclr, hclkp) - 1; timing 1473 drivers/mtd/nand/raw/stm32_fmc2_nand.c tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); timing 1486 drivers/mtd/nand/raw/stm32_fmc2_nand.c timing = DIV_ROUND_UP(twait, hclkp); timing 1487 drivers/mtd/nand/raw/stm32_fmc2_nand.c tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); timing 1502 drivers/mtd/nand/raw/stm32_fmc2_nand.c timing = DIV_ROUND_UP(tset_mem, hclkp); timing 1503 drivers/mtd/nand/raw/stm32_fmc2_nand.c tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); timing 1520 drivers/mtd/nand/raw/stm32_fmc2_nand.c timing = DIV_ROUND_UP(thold_mem, hclkp); timing 1521 drivers/mtd/nand/raw/stm32_fmc2_nand.c tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); timing 1543 drivers/mtd/nand/raw/stm32_fmc2_nand.c timing = DIV_ROUND_UP(tset_att, hclkp); timing 1544 drivers/mtd/nand/raw/stm32_fmc2_nand.c tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); timing 1582 drivers/mtd/nand/raw/stm32_fmc2_nand.c timing = DIV_ROUND_UP(thold_att, hclkp); timing 1583 drivers/mtd/nand/raw/stm32_fmc2_nand.c tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); timing 408 drivers/net/can/grcan.c u32 timing = 0; timing 435 drivers/net/can/grcan.c timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR; timing 436 drivers/net/can/grcan.c timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ; timing 437 drivers/net/can/grcan.c timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1; timing 438 drivers/net/can/grcan.c timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2; timing 439 drivers/net/can/grcan.c timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER; timing 440 drivers/net/can/grcan.c netdev_info(dev, "setting timing=0x%x\n", timing); timing 441 drivers/net/can/grcan.c grcan_write_bits(®s->conf, timing, GRCAN_CONF_TIMING); timing 662 drivers/net/wireless/intel/iwlegacy/3945-mac.c le16_to_cpu(il->timing.beacon_interval)); timing 676 drivers/net/wireless/intel/iwlegacy/3945-mac.c le16_to_cpu(il->timing.beacon_interval)); timing 1467 drivers/net/wireless/intel/iwlegacy/4965.c u16 beacon_interval = le16_to_cpu(il->timing.beacon_interval); timing 3644 drivers/net/wireless/intel/iwlegacy/common.c memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd)); timing 3646 drivers/net/wireless/intel/iwlegacy/common.c il->timing.timestamp = cpu_to_le64(il->timestamp); timing 3647 drivers/net/wireless/intel/iwlegacy/common.c il->timing.listen_interval = cpu_to_le16(conf->listen_interval); timing 3655 drivers/net/wireless/intel/iwlegacy/common.c il->timing.atim_win = 0; timing 3661 drivers/net/wireless/intel/iwlegacy/common.c il->timing.beacon_interval = cpu_to_le16(beacon_int); timing 3666 drivers/net/wireless/intel/iwlegacy/common.c il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); timing 3668 drivers/net/wireless/intel/iwlegacy/common.c il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1; timing 3671 drivers/net/wireless/intel/iwlegacy/common.c le16_to_cpu(il->timing.beacon_interval), timing 3672 drivers/net/wireless/intel/iwlegacy/common.c le32_to_cpu(il->timing.beacon_init_val), timing 3673 drivers/net/wireless/intel/iwlegacy/common.c le16_to_cpu(il->timing.atim_win)); timing 3675 drivers/net/wireless/intel/iwlegacy/common.c return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing), timing 3676 drivers/net/wireless/intel/iwlegacy/common.c &il->timing); timing 1230 drivers/net/wireless/intel/iwlegacy/common.h struct il_rxon_time_cmd timing; timing 500 drivers/net/wireless/intel/iwlwifi/dvm/dev.h struct iwl_rxon_time_cmd timing; timing 401 drivers/net/wireless/intel/iwlwifi/dvm/devices.c u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval); timing 562 drivers/net/wireless/intel/iwlwifi/dvm/devices.c u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval); timing 290 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd)); timing 292 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c ctx->timing.timestamp = cpu_to_le64(priv->timestamp); timing 293 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); timing 301 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c ctx->timing.atim_window = 0; timing 308 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c ctx->timing.beacon_interval = timing 309 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; timing 310 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c beacon_int = le16_to_cpu(ctx->timing.beacon_interval); timing 317 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c ctx->timing.beacon_interval = timing 318 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; timing 319 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c beacon_int = le16_to_cpu(ctx->timing.beacon_interval); timing 323 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c ctx->timing.beacon_interval = cpu_to_le16(beacon_int); timing 331 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); timing 333 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1; timing 337 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c le16_to_cpu(ctx->timing.beacon_interval), timing 338 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c le32_to_cpu(ctx->timing.beacon_init_val), timing 339 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c le16_to_cpu(ctx->timing.atim_window)); timing 342 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c 0, sizeof(ctx->timing), &ctx->timing); timing 122 drivers/net/wireless/intel/iwlwifi/fw/api/tdls.h struct iwl_tdls_channel_switch_timing timing; timing 1319 drivers/net/wireless/intel/iwlwifi/mvm/scan.c struct iwl_mvm_scan_timing_params *timing, *hb_timing; timing 1322 drivers/net/wireless/intel/iwlwifi/mvm/scan.c timing = &scan_timing[params->type]; timing 1351 drivers/net/wireless/intel/iwlwifi/mvm/scan.c cpu_to_le32(timing->max_out_time); timing 1353 drivers/net/wireless/intel/iwlwifi/mvm/scan.c cpu_to_le32(timing->suspend_time); timing 1398 drivers/net/wireless/intel/iwlwifi/mvm/scan.c cpu_to_le32(timing->max_out_time); timing 1400 drivers/net/wireless/intel/iwlwifi/mvm/scan.c cpu_to_le32(timing->suspend_time); timing 1405 drivers/net/wireless/intel/iwlwifi/mvm/scan.c cpu_to_le32(timing->max_out_time); timing 1407 drivers/net/wireless/intel/iwlwifi/mvm/scan.c cpu_to_le32(timing->suspend_time); timing 410 drivers/net/wireless/intel/iwlwifi/mvm/tdls.c tail->timing.frame_timestamp = cpu_to_le32(timestamp); timing 411 drivers/net/wireless/intel/iwlwifi/mvm/tdls.c tail->timing.switch_time = cpu_to_le32(switch_time); timing 412 drivers/net/wireless/intel/iwlwifi/mvm/tdls.c tail->timing.switch_timeout = cpu_to_le32(switch_timeout); timing 448 drivers/net/wireless/intel/iwlwifi/mvm/tdls.c tail->timing.max_offchan_duration = timing 196 drivers/net/wireless/rsi/rsi_91x_sdio.c host->ios.timing = MMC_TIMING_LEGACY; timing 303 drivers/net/wireless/rsi/rsi_91x_sdio.c host->ios.timing = MMC_TIMING_SD_HS; timing 2492 drivers/nfc/pn533/pn533.c struct pn533_config_timing timing; timing 2506 drivers/nfc/pn533/pn533.c timing.rfu = PN533_CONFIG_TIMING_102; timing 2507 drivers/nfc/pn533/pn533.c timing.atr_res_timeout = PN533_CONFIG_TIMING_102; timing 2508 drivers/nfc/pn533/pn533.c timing.dep_timeout = PN533_CONFIG_TIMING_204; timing 2528 drivers/nfc/pn533/pn533.c (u8 *)&timing, sizeof(timing)); timing 174 drivers/nvmem/imx-ocotp.c u32 timing = 0; timing 214 drivers/nvmem/imx-ocotp.c timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000; timing 215 drivers/nvmem/imx-ocotp.c timing |= strobe_prog & 0x00000FFF; timing 216 drivers/nvmem/imx-ocotp.c timing |= (relax << 12) & 0x0000F000; timing 217 drivers/nvmem/imx-ocotp.c timing |= (strobe_read << 16) & 0x003F0000; timing 219 drivers/nvmem/imx-ocotp.c writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); timing 226 drivers/nvmem/imx-ocotp.c u32 timing = 0; timing 237 drivers/nvmem/imx-ocotp.c timing = strobe_prog & 0x00000FFF; timing 238 drivers/nvmem/imx-ocotp.c timing |= (fsource << 12) & 0x000FF000; timing 240 drivers/nvmem/imx-ocotp.c writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); timing 94 drivers/nvmem/vf610-ocotp.c int timing; timing 118 drivers/nvmem/vf610-ocotp.c u32 timing; timing 127 drivers/nvmem/vf610-ocotp.c timing = BF(relax, OCOTP_TIMING_RELAX); timing 128 drivers/nvmem/vf610-ocotp.c timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ); timing 129 drivers/nvmem/vf610-ocotp.c timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG); timing 131 drivers/nvmem/vf610-ocotp.c return timing; timing 158 drivers/nvmem/vf610-ocotp.c writel(ocotp->timing, base + OCOTP_TIMING); timing 234 drivers/nvmem/vf610-ocotp.c ocotp_dev->timing = vf610_ocotp_calculate_timing(ocotp_dev); timing 942 drivers/pcmcia/cistpl.c static u_char *parse_timing(u_char *p, u_char *q, cistpl_timing_t *timing) timing 952 drivers/pcmcia/cistpl.c timing->wait = SPEED_CVT(*p); timing 953 drivers/pcmcia/cistpl.c timing->waitscale = exponent[scale & 3]; timing 955 drivers/pcmcia/cistpl.c timing->wait = 0; timing 960 drivers/pcmcia/cistpl.c timing->ready = SPEED_CVT(*p); timing 961 drivers/pcmcia/cistpl.c timing->rdyscale = exponent[scale & 7]; timing 963 drivers/pcmcia/cistpl.c timing->ready = 0; timing 968 drivers/pcmcia/cistpl.c timing->reserved = SPEED_CVT(*p); timing 969 drivers/pcmcia/cistpl.c timing->rsvscale = exponent[scale]; timing 971 drivers/pcmcia/cistpl.c timing->reserved = 0; timing 1130 drivers/pcmcia/cistpl.c p = parse_timing(p, q, &entry->timing); timing 1134 drivers/pcmcia/cistpl.c entry->timing.wait = 0; timing 1135 drivers/pcmcia/cistpl.c entry->timing.ready = 0; timing 1136 drivers/pcmcia/cistpl.c entry->timing.reserved = 0; timing 166 drivers/pcmcia/pxa2xx_base.c struct soc_pcmcia_timing timing; timing 169 drivers/pcmcia/pxa2xx_base.c soc_common_pcmcia_get_timing(skt, &timing); timing 171 drivers/pcmcia/pxa2xx_base.c pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk); timing 172 drivers/pcmcia/pxa2xx_base.c pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk); timing 173 drivers/pcmcia/pxa2xx_base.c pxa2xx_pcmcia_set_mcio(sock, timing.io, clk); timing 81 drivers/pcmcia/sa11xx_base.c struct soc_pcmcia_timing timing; timing 86 drivers/pcmcia/sa11xx_base.c soc_common_pcmcia_get_timing(skt, &timing); timing 88 drivers/pcmcia/sa11xx_base.c bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io); timing 89 drivers/pcmcia/sa11xx_base.c bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem); timing 90 drivers/pcmcia/sa11xx_base.c bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr); timing 146 drivers/pcmcia/sa11xx_base.c struct soc_pcmcia_timing timing; timing 151 drivers/pcmcia/sa11xx_base.c soc_common_pcmcia_get_timing(skt, &timing); timing 153 drivers/pcmcia/sa11xx_base.c p+=sprintf(p, "I/O : %uns (%uns)\n", timing.io, timing 156 drivers/pcmcia/sa11xx_base.c p+=sprintf(p, "attribute: %uns (%uns)\n", timing.attr, timing 159 drivers/pcmcia/sa11xx_base.c p+=sprintf(p, "common : %uns (%uns)\n", timing.mem, timing 135 drivers/pcmcia/soc_common.c struct soc_pcmcia_timing *timing) timing 137 drivers/pcmcia/soc_common.c timing->io = timing 139 drivers/pcmcia/soc_common.c timing->mem = timing 141 drivers/pcmcia/soc_common.c timing->attr = timing 593 drivers/staging/greybus/sdio.c u8 timing; timing 640 drivers/staging/greybus/sdio.c switch (ios->timing) { timing 643 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_LEGACY; timing 646 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_MMC_HS; timing 649 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_SD_HS; timing 652 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_UHS_SDR12; timing 655 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_UHS_SDR25; timing 658 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_UHS_SDR50; timing 661 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_UHS_SDR104; timing 664 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_UHS_DDR50; timing 667 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_MMC_DDR52; timing 670 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_MMC_HS200; timing 673 drivers/staging/greybus/sdio.c timing = GB_SDIO_TIMING_MMC_HS400; timing 676 drivers/staging/greybus/sdio.c request.timing = timing; timing 363 drivers/staging/media/omap4iss/iss_csi2.c struct iss_csi2_timing_cfg *timing) timing 369 drivers/staging/media/omap4iss/iss_csi2.c if (timing->force_rx_mode) timing 374 drivers/staging/media/omap4iss/iss_csi2.c if (timing->stop_state_16x) timing 379 drivers/staging/media/omap4iss/iss_csi2.c if (timing->stop_state_4x) timing 385 drivers/staging/media/omap4iss/iss_csi2.c reg |= timing->stop_state_counter << timing 528 drivers/staging/media/omap4iss/iss_csi2.c struct iss_csi2_timing_cfg *timing = &csi2->timing[0]; timing 552 drivers/staging/media/omap4iss/iss_csi2.c timing->force_rx_mode = 1; timing 553 drivers/staging/media/omap4iss/iss_csi2.c timing->stop_state_16x = 1; timing 554 drivers/staging/media/omap4iss/iss_csi2.c timing->stop_state_4x = 1; timing 555 drivers/staging/media/omap4iss/iss_csi2.c timing->stop_state_counter = 0x1ff; timing 590 drivers/staging/media/omap4iss/iss_csi2.c csi2_timing_config(csi2, timing); timing 140 drivers/staging/media/omap4iss/iss_csi2.h struct iss_csi2_timing_cfg timing[2]; timing 666 drivers/usb/dwc3/ep0.c } __packed timing; timing 670 drivers/usb/dwc3/ep0.c memcpy(&timing, req->buf, sizeof(timing)); timing 672 drivers/usb/dwc3/ep0.c dwc->u1sel = timing.u1sel; timing 673 drivers/usb/dwc3/ep0.c dwc->u1pel = timing.u1pel; timing 674 drivers/usb/dwc3/ep0.c dwc->u2sel = le16_to_cpu(timing.u2sel); timing 675 drivers/usb/dwc3/ep0.c dwc->u2pel = le16_to_cpu(timing.u2pel); timing 560 drivers/video/fbdev/amba-clcd.c struct display_timing timing; timing 563 drivers/video/fbdev/amba-clcd.c err = of_get_display_timing(node, "panel-timing", &timing); timing 569 drivers/video/fbdev/amba-clcd.c videomode_from_timing(&timing, &video); timing 576 drivers/video/fbdev/amba-clcd.c if (timing.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) timing 578 drivers/video/fbdev/amba-clcd.c else if (!(timing.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)) timing 587 drivers/video/fbdev/amba-clcd.c if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW) timing 590 drivers/video/fbdev/amba-clcd.c if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW) timing 593 drivers/video/fbdev/amba-clcd.c if (timing.flags & DISPLAY_FLAGS_DE_LOW) timing 37 drivers/video/fbdev/gbefb.c struct gbe_timing_info timing; timing 412 drivers/video/fbdev/gbefb.c static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) timing 418 drivers/video/fbdev/gbefb.c (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); timing 420 drivers/video/fbdev/gbefb.c (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); timing 428 drivers/video/fbdev/gbefb.c timing->pll_m = 4; timing 429 drivers/video/fbdev/gbefb.c timing->pll_n = 1; timing 430 drivers/video/fbdev/gbefb.c timing->pll_p = 0; timing 457 drivers/video/fbdev/gbefb.c struct gbe_timing_info *timing) timing 505 drivers/video/fbdev/gbefb.c if (timing) { timing 506 drivers/video/fbdev/gbefb.c timing->width = var->xres; timing 507 drivers/video/fbdev/gbefb.c timing->height = var->yres; timing 508 drivers/video/fbdev/gbefb.c timing->pll_m = best_m; timing 509 drivers/video/fbdev/gbefb.c timing->pll_n = best_n; timing 510 drivers/video/fbdev/gbefb.c timing->pll_p = best_p; timing 511 drivers/video/fbdev/gbefb.c timing->cfreq = gbe_pll->clock_rate * 1000 * timing->pll_m / timing 512 drivers/video/fbdev/gbefb.c (timing->pll_n << timing->pll_p); timing 513 drivers/video/fbdev/gbefb.c timing->htotal = var->left_margin + var->xres + timing 515 drivers/video/fbdev/gbefb.c timing->vtotal = var->upper_margin + var->yres + timing 517 drivers/video/fbdev/gbefb.c timing->fields_sec = 1000 * timing->cfreq / timing->htotal * timing 518 drivers/video/fbdev/gbefb.c 1000 / timing->vtotal; timing 519 drivers/video/fbdev/gbefb.c timing->hblank_start = var->xres; timing 520 drivers/video/fbdev/gbefb.c timing->vblank_start = var->yres; timing 521 drivers/video/fbdev/gbefb.c timing->hblank_end = timing->htotal; timing 522 drivers/video/fbdev/gbefb.c timing->hsync_start = var->xres + var->right_margin + 1; timing 523 drivers/video/fbdev/gbefb.c timing->hsync_end = timing->hsync_start + var->hsync_len; timing 524 drivers/video/fbdev/gbefb.c timing->vblank_end = timing->vtotal; timing 525 drivers/video/fbdev/gbefb.c timing->vsync_start = var->yres + var->lower_margin + 1; timing 526 drivers/video/fbdev/gbefb.c timing->vsync_end = timing->vsync_start + var->vsync_len; timing 532 drivers/video/fbdev/gbefb.c static void gbe_set_timing_info(struct gbe_timing_info *timing) timing 539 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DOTCLK, M, val, timing->pll_m - 1); timing 540 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DOTCLK, N, val, timing->pll_n - 1); timing 541 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(DOTCLK, P, val, timing->pll_p); timing 548 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_XYMAX, MAXX, val, timing->htotal); timing 549 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_XYMAX, MAXY, val, timing->vtotal); timing 554 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VSYNC, VSYNC_ON, val, timing->vsync_start); timing 555 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VSYNC, VSYNC_OFF, val, timing->vsync_end); timing 558 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HSYNC, HSYNC_ON, val, timing->hsync_start); timing 559 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HSYNC, HSYNC_OFF, val, timing->hsync_end); timing 562 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VBLANK, VBLANK_ON, val, timing->vblank_start); timing 563 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VBLANK, VBLANK_OFF, val, timing->vblank_end); timing 567 drivers/video/fbdev/gbefb.c timing->hblank_start - 5); timing 569 drivers/video/fbdev/gbefb.c timing->hblank_end - 3); timing 574 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VCMAP, VCMAP_ON, val, timing->vblank_start); timing 575 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VCMAP, VCMAP_OFF, val, timing->vblank_end); timing 578 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HCMAP, HCMAP_ON, val, timing->hblank_start); timing 579 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_HCMAP, HCMAP_OFF, val, timing->hblank_end); timing 583 drivers/video/fbdev/gbefb.c temp = timing->vblank_start - timing->vblank_end - 1; timing 588 drivers/video/fbdev/gbefb.c gbefb_setup_flatpanel(timing); timing 591 drivers/video/fbdev/gbefb.c if (timing->hblank_end >= 20) timing 593 drivers/video/fbdev/gbefb.c timing->hblank_end - 20); timing 596 drivers/video/fbdev/gbefb.c timing->htotal - (20 - timing->hblank_end)); timing 601 drivers/video/fbdev/gbefb.c if (timing->hblank_end >= GBE_CRS_MAGIC) timing 603 drivers/video/fbdev/gbefb.c timing->hblank_end - GBE_CRS_MAGIC); timing 606 drivers/video/fbdev/gbefb.c timing->htotal - (GBE_CRS_MAGIC - timing 607 drivers/video/fbdev/gbefb.c timing->hblank_end)); timing 612 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VC_START_XY, VC_STARTX, val, timing->hblank_end - 4); timing 616 drivers/video/fbdev/gbefb.c temp = timing->hblank_end - GBE_PIXEN_MAGIC_ON; timing 618 drivers/video/fbdev/gbefb.c temp += timing->htotal; /* allow blank to wrap around */ timing 622 drivers/video/fbdev/gbefb.c ((temp + timing->width - timing 623 drivers/video/fbdev/gbefb.c GBE_PIXEN_MAGIC_OFF) % timing->htotal)); timing 627 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VPIXEN, VPIXEN_ON, val, timing->vblank_end); timing 628 drivers/video/fbdev/gbefb.c SET_GBE_FIELD(VT_VPIXEN, VPIXEN_OFF, val, timing->vblank_start); timing 651 drivers/video/fbdev/gbefb.c compute_gbe_timing(&info->var, &par->timing); timing 655 drivers/video/fbdev/gbefb.c xpmax = par->timing.width; timing 656 drivers/video/fbdev/gbefb.c ypmax = par->timing.height; timing 662 drivers/video/fbdev/gbefb.c gbe_set_timing_info(&par->timing); timing 904 drivers/video/fbdev/gbefb.c struct gbe_timing_info timing; timing 924 drivers/video/fbdev/gbefb.c ret = compute_gbe_timing(var, &timing); timing 986 drivers/video/fbdev/gbefb.c var->left_margin = timing.htotal - timing.hsync_end; timing 987 drivers/video/fbdev/gbefb.c var->right_margin = timing.hsync_start - timing.width; timing 988 drivers/video/fbdev/gbefb.c var->upper_margin = timing.vtotal - timing.vsync_end; timing 989 drivers/video/fbdev/gbefb.c var->lower_margin = timing.vsync_start - timing.height; timing 990 drivers/video/fbdev/gbefb.c var->hsync_len = timing.hsync_end - timing.hsync_start; timing 991 drivers/video/fbdev/gbefb.c var->vsync_len = timing.vsync_end - timing.vsync_start; timing 203 drivers/video/fbdev/omap2/omapfb/displays/panel-dpi.c struct display_timing timing; timing 215 drivers/video/fbdev/omap2/omapfb/displays/panel-dpi.c r = of_get_display_timing(node, "panel-timing", &timing); timing 221 drivers/video/fbdev/omap2/omapfb/displays/panel-dpi.c videomode_from_timing(&timing, &vm); timing 231 drivers/video/fbdev/pm2fb.c static u32 to3264(u32 timing, int bpp, int is64) timing 235 drivers/video/fbdev/pm2fb.c timing *= 3; timing 238 drivers/video/fbdev/pm2fb.c timing >>= 1; timing 241 drivers/video/fbdev/pm2fb.c timing >>= 1; timing 246 drivers/video/fbdev/pm2fb.c timing >>= 1; timing 247 drivers/video/fbdev/pm2fb.c return timing; timing 1458 drivers/video/fbdev/via/hw.c struct via_display_timing timing; timing 1461 drivers/video/fbdev/via/hw.c timing.hor_addr = cxres; timing 1462 drivers/video/fbdev/via/hw.c timing.hor_sync_start = timing.hor_addr + var->right_margin + dx; timing 1463 drivers/video/fbdev/via/hw.c timing.hor_sync_end = timing.hor_sync_start + var->hsync_len; timing 1464 drivers/video/fbdev/via/hw.c timing.hor_total = timing.hor_sync_end + var->left_margin + dx; timing 1465 drivers/video/fbdev/via/hw.c timing.hor_blank_start = timing.hor_addr + dx; timing 1466 drivers/video/fbdev/via/hw.c timing.hor_blank_end = timing.hor_total - dx; timing 1467 drivers/video/fbdev/via/hw.c timing.ver_addr = cyres; timing 1468 drivers/video/fbdev/via/hw.c timing.ver_sync_start = timing.ver_addr + var->lower_margin + dy; timing 1469 drivers/video/fbdev/via/hw.c timing.ver_sync_end = timing.ver_sync_start + var->vsync_len; timing 1470 drivers/video/fbdev/via/hw.c timing.ver_total = timing.ver_sync_end + var->upper_margin + dy; timing 1471 drivers/video/fbdev/via/hw.c timing.ver_blank_start = timing.ver_addr + dy; timing 1472 drivers/video/fbdev/via/hw.c timing.ver_blank_end = timing.ver_total - dy; timing 1473 drivers/video/fbdev/via/hw.c return timing; timing 538 drivers/video/fbdev/via/lcd.c struct via_display_timing timing; timing 556 drivers/video/fbdev/via/lcd.c timing = var_to_timing(&panel_var, panel_hres, panel_vres); timing 559 drivers/video/fbdev/via/lcd.c timing = var_to_timing(&panel_var, set_hres, set_vres); timing 567 drivers/video/fbdev/via/lcd.c via_set_primary_timing(&timing); timing 569 drivers/video/fbdev/via/lcd.c via_set_secondary_timing(&timing); timing 18 drivers/video/fbdev/via/via_modesetting.c void via_set_primary_timing(const struct via_display_timing *timing) timing 22 drivers/video/fbdev/via/via_modesetting.c raw.hor_total = timing->hor_total / 8 - 5; timing 23 drivers/video/fbdev/via/via_modesetting.c raw.hor_addr = timing->hor_addr / 8 - 1; timing 24 drivers/video/fbdev/via/via_modesetting.c raw.hor_blank_start = timing->hor_blank_start / 8 - 1; timing 25 drivers/video/fbdev/via/via_modesetting.c raw.hor_blank_end = timing->hor_blank_end / 8 - 1; timing 26 drivers/video/fbdev/via/via_modesetting.c raw.hor_sync_start = timing->hor_sync_start / 8; timing 27 drivers/video/fbdev/via/via_modesetting.c raw.hor_sync_end = timing->hor_sync_end / 8; timing 28 drivers/video/fbdev/via/via_modesetting.c raw.ver_total = timing->ver_total - 2; timing 29 drivers/video/fbdev/via/via_modesetting.c raw.ver_addr = timing->ver_addr - 1; timing 30 drivers/video/fbdev/via/via_modesetting.c raw.ver_blank_start = timing->ver_blank_start - 1; timing 31 drivers/video/fbdev/via/via_modesetting.c raw.ver_blank_end = timing->ver_blank_end - 1; timing 32 drivers/video/fbdev/via/via_modesetting.c raw.ver_sync_start = timing->ver_sync_start - 1; timing 33 drivers/video/fbdev/via/via_modesetting.c raw.ver_sync_end = timing->ver_sync_end - 1; timing 76 drivers/video/fbdev/via/via_modesetting.c void via_set_secondary_timing(const struct via_display_timing *timing) timing 80 drivers/video/fbdev/via/via_modesetting.c raw.hor_total = timing->hor_total - 1; timing 81 drivers/video/fbdev/via/via_modesetting.c raw.hor_addr = timing->hor_addr - 1; timing 82 drivers/video/fbdev/via/via_modesetting.c raw.hor_blank_start = timing->hor_blank_start - 1; timing 83 drivers/video/fbdev/via/via_modesetting.c raw.hor_blank_end = timing->hor_blank_end - 1; timing 84 drivers/video/fbdev/via/via_modesetting.c raw.hor_sync_start = timing->hor_sync_start - 1; timing 85 drivers/video/fbdev/via/via_modesetting.c raw.hor_sync_end = timing->hor_sync_end - 1; timing 86 drivers/video/fbdev/via/via_modesetting.c raw.ver_total = timing->ver_total - 1; timing 87 drivers/video/fbdev/via/via_modesetting.c raw.ver_addr = timing->ver_addr - 1; timing 88 drivers/video/fbdev/via/via_modesetting.c raw.ver_blank_start = timing->ver_blank_start - 1; timing 89 drivers/video/fbdev/via/via_modesetting.c raw.ver_blank_end = timing->ver_blank_end - 1; timing 90 drivers/video/fbdev/via/via_modesetting.c raw.ver_sync_start = timing->ver_sync_start - 1; timing 91 drivers/video/fbdev/via/via_modesetting.c raw.ver_sync_end = timing->ver_sync_end - 1; timing 37 drivers/video/fbdev/via/via_modesetting.h void via_set_primary_timing(const struct via_display_timing *timing); timing 38 drivers/video/fbdev/via/via_modesetting.h void via_set_secondary_timing(const struct via_display_timing *timing); timing 1473 include/linux/greybus/greybus_protocols.h __u8 timing; timing 1088 include/linux/libata.h const unsigned long *timing, unsigned long deadline, timing 50 include/linux/mmc/host.h unsigned char timing; /* timing specification used */ timing 559 include/linux/mmc/host.h return card->host->ios.timing == MMC_TIMING_SD_HS || timing 560 include/linux/mmc/host.h card->host->ios.timing == MMC_TIMING_MMC_HS; timing 566 include/linux/mmc/host.h return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && timing 567 include/linux/mmc/host.h card->host->ios.timing <= MMC_TIMING_UHS_DDR50; timing 84 include/linux/platform_data/mtd-davinci.h struct davinci_aemif_timing *timing; timing 460 include/pcmcia/cistpl.h cistpl_timing_t timing; timing 83 sound/pci/sis7019.c struct voice *timing; timing 332 sound/pci/sis7019.c if (!voice->timing) timing 394 sound/pci/sis7019.c if (voice->timing) { timing 396 sound/pci/sis7019.c voice->timing->flags &= ~(VOICE_IN_USE | VOICE_SSO_TIMING | timing 398 sound/pci/sis7019.c voice->timing = NULL; timing 454 sound/pci/sis7019.c if (needed && !voice->timing) { timing 456 sound/pci/sis7019.c voice->timing = __sis_alloc_playback_voice(sis); timing 457 sound/pci/sis7019.c if (voice->timing) timing 460 sound/pci/sis7019.c if (!voice->timing) timing 462 sound/pci/sis7019.c voice->timing->substream = substream; timing 463 sound/pci/sis7019.c } else if (!needed && voice->timing) { timing 465 sound/pci/sis7019.c voice->timing = NULL; timing 619 sound/pci/sis7019.c voice = voice->timing; timing 720 sound/pci/sis7019.c struct voice *timing = voice->timing; timing 721 sound/pci/sis7019.c void __iomem *play_base = timing->ctrl_base; timing 722 sound/pci/sis7019.c void __iomem *wave_base = timing->wave_base; timing 773 sound/pci/sis7019.c timing->flags |= VOICE_SYNC_TIMING; timing 774 sound/pci/sis7019.c timing->sync_base = voice->ctrl_base; timing 775 sound/pci/sis7019.c timing->sync_cso = runtime->period_size; timing 776 sound/pci/sis7019.c timing->sync_period_size = runtime->period_size; timing 777 sound/pci/sis7019.c timing->sync_buffer_size = runtime->buffer_size; timing 778 sound/pci/sis7019.c timing->period_size = period_size; timing 779 sound/pci/sis7019.c timing->buffer_size = buffer_size; timing 780 sound/pci/sis7019.c timing->sso = sso; timing 781 sound/pci/sis7019.c timing->vperiod = vperiod; timing 793 sound/pci/sis7019.c control = timing->buffer_size - 1; timing 795 sound/pci/sis7019.c sso_eso = timing->buffer_size - 1; timing 796 sound/pci/sis7019.c sso_eso |= timing->sso << 16; timing 845 sound/pci/sis7019.c if (voice->timing) { timing 543 sound/soc/sh/rcar/core.c int shift, int add, int timing) timing 548 sound/soc/sh/rcar/core.c int func_call = (val == timing); timing 55 tools/testing/selftests/seccomp/seccomp_benchmark.c if (timing(CLOCK_REALTIME, samples) / 1000000000ULL > 5) timing 80 tools/testing/selftests/seccomp/seccomp_benchmark.c native = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; timing 89 tools/testing/selftests/seccomp/seccomp_benchmark.c filtered = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples;