timer_of_base 127 drivers/clocksource/timer-atcpit100.c val = readl(timer_of_base(to) + CH_EN); timer_of_base 128 drivers/clocksource/timer-atcpit100.c writel(val & ~CH0TMR0EN, timer_of_base(to) + CH_EN); timer_of_base 129 drivers/clocksource/timer-atcpit100.c writel(evt, timer_of_base(to) + CH0_REL); timer_of_base 130 drivers/clocksource/timer-atcpit100.c writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); timer_of_base 139 drivers/clocksource/timer-atcpit100.c atcpit100_clkevt_time_setup(timer_of_base(to), timer_of_period(to)); timer_of_base 140 drivers/clocksource/timer-atcpit100.c atcpit100_clkevt_time_start(timer_of_base(to)); timer_of_base 148 drivers/clocksource/timer-atcpit100.c atcpit100_clkevt_time_stop(timer_of_base(to)); timer_of_base 157 drivers/clocksource/timer-atcpit100.c writel(~0x0, timer_of_base(to) + CH0_REL); timer_of_base 158 drivers/clocksource/timer-atcpit100.c val = readl(timer_of_base(to) + CH_EN); timer_of_base 159 drivers/clocksource/timer-atcpit100.c writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); timer_of_base 169 drivers/clocksource/timer-atcpit100.c atcpit100_timer_clear_interrupt(timer_of_base(to)); timer_of_base 207 drivers/clocksource/timer-atcpit100.c return ~readl(timer_of_base(&to) + CH1_CNT); timer_of_base 231 drivers/clocksource/timer-atcpit100.c base = timer_of_base(&to); timer_of_base 28 drivers/clocksource/timer-gx6605s.c void __iomem *base = timer_of_base(to_timer_of(ce)); timer_of_base 39 drivers/clocksource/timer-gx6605s.c void __iomem *base = timer_of_base(to_timer_of(ce)); timer_of_base 54 drivers/clocksource/timer-gx6605s.c void __iomem *base = timer_of_base(to_timer_of(ce)); timer_of_base 68 drivers/clocksource/timer-gx6605s.c void __iomem *base = timer_of_base(to_timer_of(ce)); timer_of_base 97 drivers/clocksource/timer-gx6605s.c base = timer_of_base(&to) + CLKSRC_OFFSET; timer_of_base 150 drivers/clocksource/timer-gx6605s.c gx6605s_clkevt_init(timer_of_base(&to)); timer_of_base 152 drivers/clocksource/timer-gx6605s.c return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET); timer_of_base 142 drivers/clocksource/timer-imx-sysctr.c sys_ctr_base = timer_of_base(&to_sysctr); timer_of_base 195 drivers/clocksource/timer-imx-tpm.c timer_base = timer_of_base(&to_tpm); timer_of_base 56 drivers/clocksource/timer-mediatek.c #define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON) timer_of_base 57 drivers/clocksource/timer-mediatek.c #define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL) timer_of_base 139 drivers/clocksource/timer-mediatek.c val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); timer_of_base 140 drivers/clocksource/timer-mediatek.c writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) + timer_of_base 147 drivers/clocksource/timer-mediatek.c writel(delay, timer_of_base(to) + GPT_CMP_REG(timer)); timer_of_base 156 drivers/clocksource/timer-mediatek.c writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG); timer_of_base 158 drivers/clocksource/timer-mediatek.c val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); timer_of_base 169 drivers/clocksource/timer-mediatek.c timer_of_base(to) + GPT_CTRL_REG(timer)); timer_of_base 208 drivers/clocksource/timer-mediatek.c writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG); timer_of_base 218 drivers/clocksource/timer-mediatek.c timer_of_base(to) + GPT_CTRL_REG(timer)); timer_of_base 221 drivers/clocksource/timer-mediatek.c timer_of_base(to) + GPT_CLK_REG(timer)); timer_of_base 223 drivers/clocksource/timer-mediatek.c writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer)); timer_of_base 226 drivers/clocksource/timer-mediatek.c timer_of_base(to) + GPT_CTRL_REG(timer)); timer_of_base 234 drivers/clocksource/timer-mediatek.c writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG); timer_of_base 237 drivers/clocksource/timer-mediatek.c writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG); timer_of_base 239 drivers/clocksource/timer-mediatek.c val = readl(timer_of_base(to) + GPT_IRQ_EN_REG); timer_of_base 241 drivers/clocksource/timer-mediatek.c timer_of_base(to) + GPT_IRQ_EN_REG); timer_of_base 297 drivers/clocksource/timer-mediatek.c clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC), timer_of_base 300 drivers/clocksource/timer-mediatek.c gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC); timer_of_base 55 drivers/clocksource/timer-milbeaut.c val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); timer_of_base 57 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); timer_of_base 71 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); timer_of_base 76 drivers/clocksource/timer-milbeaut.c u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); timer_of_base 79 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); timer_of_base 84 drivers/clocksource/timer-milbeaut.c writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS); timer_of_base 129 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); timer_of_base 130 drivers/clocksource/timer-milbeaut.c writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS); timer_of_base 131 drivers/clocksource/timer-milbeaut.c writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS); timer_of_base 133 drivers/clocksource/timer-milbeaut.c writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); timer_of_base 139 drivers/clocksource/timer-milbeaut.c writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); timer_of_base 165 drivers/clocksource/timer-milbeaut.c return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS); timer_of_base 179 drivers/clocksource/timer-milbeaut.c clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS, timer_of_base 61 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 63 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 73 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 75 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 85 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 88 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 98 drivers/clocksource/timer-npcm7xx.c writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0); timer_of_base 100 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 103 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 114 drivers/clocksource/timer-npcm7xx.c writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0); timer_of_base 115 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 117 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); timer_of_base 127 drivers/clocksource/timer-npcm7xx.c writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR); timer_of_base 158 drivers/clocksource/timer-npcm7xx.c timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0); timer_of_base 161 drivers/clocksource/timer-npcm7xx.c timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR); timer_of_base 174 drivers/clocksource/timer-npcm7xx.c timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1); timer_of_base 176 drivers/clocksource/timer-npcm7xx.c timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TICR1); timer_of_base 178 drivers/clocksource/timer-npcm7xx.c val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1); timer_of_base 180 drivers/clocksource/timer-npcm7xx.c writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1); timer_of_base 182 drivers/clocksource/timer-npcm7xx.c clocksource_mmio_init(timer_of_base(&npcm7xx_to) + timer_of_base 206 drivers/clocksource/timer-npcm7xx.c timer_of_base(&npcm7xx_to), timer_of_irq(&npcm7xx_to)); timer_of_base 71 drivers/clocksource/timer-rda.c rda_ostimer_stop(timer_of_base(to)); timer_of_base 80 drivers/clocksource/timer-rda.c rda_ostimer_stop(timer_of_base(to)); timer_of_base 90 drivers/clocksource/timer-rda.c rda_ostimer_stop(timer_of_base(to)); timer_of_base 94 drivers/clocksource/timer-rda.c rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy); timer_of_base 109 drivers/clocksource/timer-rda.c rda_ostimer_start(timer_of_base(to), false, evt); timer_of_base 121 drivers/clocksource/timer-rda.c timer_of_base(to) + RDA_TIMER_IRQ_CLR); timer_of_base 158 drivers/clocksource/timer-rda.c void __iomem *base = timer_of_base(&rda_ostimer_of); timer_of_base 84 drivers/clocksource/timer-sprd.c sprd_timer_disable(timer_of_base(to)); timer_of_base 85 drivers/clocksource/timer-sprd.c sprd_timer_update_counter(timer_of_base(to), cycles); timer_of_base 86 drivers/clocksource/timer-sprd.c sprd_timer_enable(timer_of_base(to), 0); timer_of_base 95 drivers/clocksource/timer-sprd.c sprd_timer_disable(timer_of_base(to)); timer_of_base 96 drivers/clocksource/timer-sprd.c sprd_timer_update_counter(timer_of_base(to), timer_of_period(to)); timer_of_base 97 drivers/clocksource/timer-sprd.c sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE); timer_of_base 106 drivers/clocksource/timer-sprd.c sprd_timer_disable(timer_of_base(to)); timer_of_base 115 drivers/clocksource/timer-sprd.c sprd_timer_clear_interrupt(timer_of_base(to)); timer_of_base 118 drivers/clocksource/timer-sprd.c sprd_timer_disable(timer_of_base(to)); timer_of_base 152 drivers/clocksource/timer-sprd.c sprd_timer_enable_interrupt(timer_of_base(&to)); timer_of_base 165 drivers/clocksource/timer-sprd.c return ~(u64)readl_relaxed(timer_of_base(&suspend_to) + timer_of_base 171 drivers/clocksource/timer-sprd.c sprd_timer_update_counter(timer_of_base(&suspend_to), timer_of_base 173 drivers/clocksource/timer-sprd.c sprd_timer_enable(timer_of_base(&suspend_to), TIMER_CTL_PERIOD_MODE); timer_of_base 180 drivers/clocksource/timer-sprd.c sprd_timer_disable(timer_of_base(&suspend_to)); timer_of_base 101 drivers/clocksource/timer-stm32.c writel_relaxed(0, timer_of_base(to) + TIM_DIER); timer_of_base 114 drivers/clocksource/timer-stm32.c writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); timer_of_base 132 drivers/clocksource/timer-stm32.c next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; timer_of_base 133 drivers/clocksource/timer-stm32.c writel_relaxed(next, timer_of_base(to) + TIM_CCR1); timer_of_base 134 drivers/clocksource/timer-stm32.c now = readl_relaxed(timer_of_base(to) + TIM_CNT); timer_of_base 139 drivers/clocksource/timer-stm32.c writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); timer_of_base 167 drivers/clocksource/timer-stm32.c writel_relaxed(0, timer_of_base(to) + TIM_SR); timer_of_base 192 drivers/clocksource/timer-stm32.c writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); timer_of_base 194 drivers/clocksource/timer-stm32.c width = readl_relaxed(timer_of_base(to) + TIM_ARR); timer_of_base 222 drivers/clocksource/timer-stm32.c writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); timer_of_base 223 drivers/clocksource/timer-stm32.c writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); timer_of_base 224 drivers/clocksource/timer-stm32.c writel_relaxed(0, timer_of_base(to) + TIM_SR); timer_of_base 253 drivers/clocksource/timer-stm32.c stm32_timer_cnt = timer_of_base(to) + TIM_CNT; timer_of_base 263 drivers/clocksource/timer-stm32.c return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name, timer_of_base 89 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_stop(timer_of_base(to), 0); timer_of_base 98 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_stop(timer_of_base(to), 0); timer_of_base 99 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_start(timer_of_base(to), 0, false); timer_of_base 108 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_stop(timer_of_base(to), 0); timer_of_base 109 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to)); timer_of_base 110 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_start(timer_of_base(to), 0, true); timer_of_base 120 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_stop(timer_of_base(to), 0); timer_of_base 121 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS); timer_of_base 122 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_start(timer_of_base(to), 0, false); timer_of_base 137 drivers/clocksource/timer-sun4i.c sun4i_timer_clear_interrupt(timer_of_base(to)); timer_of_base 166 drivers/clocksource/timer-sun4i.c return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1)); timer_of_base 178 drivers/clocksource/timer-sun4i.c writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1)); timer_of_base 181 drivers/clocksource/timer-sun4i.c timer_of_base(&to) + TIMER_CTL_REG(1)); timer_of_base 194 drivers/clocksource/timer-sun4i.c ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1), timer_of_base 203 drivers/clocksource/timer-sun4i.c timer_of_base(&to) + TIMER_CTL_REG(0)); timer_of_base 206 drivers/clocksource/timer-sun4i.c sun4i_clkevt_time_stop(timer_of_base(&to), 0); timer_of_base 209 drivers/clocksource/timer-sun4i.c sun4i_timer_clear_interrupt(timer_of_base(&to)); timer_of_base 215 drivers/clocksource/timer-sun4i.c val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG); timer_of_base 216 drivers/clocksource/timer-sun4i.c writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG); timer_of_base 57 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); timer_of_base 75 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); timer_of_base 84 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); timer_of_base 96 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); timer_of_base 106 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); timer_of_base 136 drivers/clocksource/timer-tegra.c writel_relaxed(0, timer_of_base(to) + TIMER_PTV); timer_of_base 137 drivers/clocksource/timer-tegra.c writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); timer_of_base 196 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(&suspend_rtc_to); timer_of_base 262 drivers/clocksource/timer-tegra.c timer_reg_base = timer_of_base(to);