tiling_mode 110 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c enum bw_defines tiling_mode[maximum_number_of_surfaces]; tiling_mode 261 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[0] = bw_def_linear; tiling_mode 262 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[1] = bw_def_linear; tiling_mode 263 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[2] = bw_def_linear; tiling_mode 264 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[3] = bw_def_linear; tiling_mode 267 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[0] = bw_def_landscape; tiling_mode 268 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[1] = bw_def_landscape; tiling_mode 269 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[2] = bw_def_landscape; tiling_mode 270 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[3] = bw_def_landscape; tiling_mode 326 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[i] = bw_def_linear; tiling_mode 329 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[i] = bw_def_tiled; tiling_mode 373 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear; tiling_mode 374 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear; tiling_mode 581 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) { tiling_mode 680 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (tiling_mode[i] == bw_def_linear) { tiling_mode 865 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if ((dceip->dmif_pipe_en_fbc_chunk_tracker + 3 == i && fbc_enabled == 0 && tiling_mode[i] != bw_def_linear)) { tiling_mode 994 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (tiling_mode[i] == bw_def_linear) { tiling_mode 1098 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] != bw_def_linear) { tiling_mode 1101 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) { tiling_mode 160 drivers/gpu/drm/i915/gem/i915_gem_tiling.c int tiling_mode, unsigned int stride) tiling_mode 168 drivers/gpu/drm/i915/gem/i915_gem_tiling.c size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride); tiling_mode 172 drivers/gpu/drm/i915/gem/i915_gem_tiling.c alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride); tiling_mode 182 drivers/gpu/drm/i915/gem/i915_gem_tiling.c int tiling_mode, unsigned int stride) tiling_mode 187 drivers/gpu/drm/i915/gem/i915_gem_tiling.c if (tiling_mode == I915_TILING_NONE) tiling_mode 191 drivers/gpu/drm/i915/gem/i915_gem_tiling.c if (i915_vma_fence_prepare(vma, tiling_mode, stride)) tiling_mode 333 drivers/gpu/drm/i915/gem/i915_gem_tiling.c if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) { tiling_mode 338 drivers/gpu/drm/i915/gem/i915_gem_tiling.c if (args->tiling_mode == I915_TILING_NONE) { tiling_mode 342 drivers/gpu/drm/i915/gem/i915_gem_tiling.c if (args->tiling_mode == I915_TILING_X) tiling_mode 361 drivers/gpu/drm/i915/gem/i915_gem_tiling.c args->tiling_mode = I915_TILING_NONE; tiling_mode 371 drivers/gpu/drm/i915/gem/i915_gem_tiling.c err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride); tiling_mode 376 drivers/gpu/drm/i915/gem/i915_gem_tiling.c args->tiling_mode = i915_gem_object_get_tiling(obj); tiling_mode 408 drivers/gpu/drm/i915/gem/i915_gem_tiling.c args->tiling_mode = tiling_mode 416 drivers/gpu/drm/i915/gem/i915_gem_tiling.c switch (args->tiling_mode) { tiling_mode 169 drivers/gpu/drm/i915/gvt/dmabuf.c unsigned int tiling_mode = 0; tiling_mode 174 drivers/gpu/drm/i915/gvt/dmabuf.c tiling_mode = I915_TILING_NONE; tiling_mode 177 drivers/gpu/drm/i915/gvt/dmabuf.c tiling_mode = I915_TILING_X; tiling_mode 182 drivers/gpu/drm/i915/gvt/dmabuf.c tiling_mode = I915_TILING_Y; tiling_mode 189 drivers/gpu/drm/i915/gvt/dmabuf.c obj->tiling_and_stride = tiling_mode | stride; tiling_mode 1297 include/uapi/drm/i915_drm.h __u32 tiling_mode; tiling_mode 1320 include/uapi/drm/i915_drm.h __u32 tiling_mode; tiling_mode 1297 tools/include/uapi/drm/i915_drm.h __u32 tiling_mode; tiling_mode 1320 tools/include/uapi/drm/i915_drm.h __u32 tiling_mode;