tile 1030 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t *tile, *macrotile; tile 1032 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile = adev->gfx.config.tile_mode_array; tile 1049 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[reg_offset] = 0; tile 1055 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1059 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1063 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1067 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1071 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1075 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1078 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1082 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[7] = (TILE_SPLIT(split_equal_to_row_size)); tile 1083 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 1085 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1088 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1092 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1096 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[12] = (TILE_SPLIT(split_equal_to_row_size)); tile 1097 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1100 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1104 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | tile 1108 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1112 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[17] = (TILE_SPLIT(split_equal_to_row_size)); tile 1113 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | tile 1117 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | tile 1120 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | tile 1124 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | tile 1128 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | tile 1132 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[23] = (TILE_SPLIT(split_equal_to_row_size)); tile 1133 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | tile 1137 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | tile 1141 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | tile 1145 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1148 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1152 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1156 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[30] = (TILE_SPLIT(split_equal_to_row_size)); tile 1216 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); tile 1222 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1226 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1230 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1234 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1238 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1242 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1246 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1250 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1254 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 1256 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1259 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1263 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1267 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 1271 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1274 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1278 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | tile 1282 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1286 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1290 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | tile 1294 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | tile 1297 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | tile 1301 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | tile 1305 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | tile 1309 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | tile 1313 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | tile 1317 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | tile 1321 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | tile 1325 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1328 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1332 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1336 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1399 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); tile 1408 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1412 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1416 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1420 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1424 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1428 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1431 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1435 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[7] = (TILE_SPLIT(split_equal_to_row_size)); tile 1436 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 1438 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1441 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1445 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1449 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[12] = (TILE_SPLIT(split_equal_to_row_size)); tile 1450 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1453 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1457 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | tile 1461 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1465 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[17] = (TILE_SPLIT(split_equal_to_row_size)); tile 1466 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | tile 1470 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | tile 1473 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | tile 1477 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | tile 1481 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | tile 1485 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[23] = (TILE_SPLIT(split_equal_to_row_size)); tile 1486 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | tile 1490 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | tile 1494 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | tile 1498 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 1501 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 1505 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 1509 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[30] = (TILE_SPLIT(split_equal_to_row_size)); tile 1569 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); tile 1820 drivers/gpu/drm/drm_connector.c char tile[256]; tile 1833 drivers/gpu/drm/drm_connector.c snprintf(tile, 256, "%d:%d:%d:%d:%d:%d:%d:%d", tile 1841 drivers/gpu/drm/drm_connector.c strlen(tile) + 1, tile 1842 drivers/gpu/drm/drm_connector.c tile, tile 5380 drivers/gpu/drm/drm_edid.c struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; tile 5386 drivers/gpu/drm/drm_edid.c w = tile->tile_size[0] | tile->tile_size[1] << 8; tile 5387 drivers/gpu/drm/drm_edid.c h = tile->tile_size[2] | tile->tile_size[3] << 8; tile 5389 drivers/gpu/drm/drm_edid.c num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); tile 5390 drivers/gpu/drm/drm_edid.c num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); tile 5391 drivers/gpu/drm/drm_edid.c tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); tile 5392 drivers/gpu/drm/drm_edid.c tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); tile 5395 drivers/gpu/drm/drm_edid.c if (tile->tile_cap & 0x80) tile 5405 drivers/gpu/drm/drm_edid.c DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); tile 5409 drivers/gpu/drm/drm_edid.c DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); tile 5411 drivers/gpu/drm/drm_edid.c tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); tile 5413 drivers/gpu/drm/drm_edid.c tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); tile 143 drivers/gpu/drm/exynos/exynos_drm_scaler.c u32 src_fmt, u32 tile) tile 147 drivers/gpu/drm/exynos/exynos_drm_scaler.c val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10); tile 29 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c static u64 tiled_offset(const struct tile *tile, u64 v) tile 33 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c if (tile->tiling == I915_TILING_NONE) tile 36 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c y = div64_u64_rem(v, tile->stride, &x); tile 37 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height; tile 39 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c if (tile->tiling == I915_TILING_X) { tile 40 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c v += y * tile->width; tile 41 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c v += div64_u64_rem(x, tile->width, &x) << tile->size; tile 43 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c } else if (tile->width == 128) { tile 59 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c switch (tile->swizzle) { tile 78 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c const struct tile *tile, tile 89 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c __func__, tile->tiling, tile->stride)) tile 92 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); tile 95 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile->tiling, tile->stride, err); tile 99 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); tile 100 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); tile 143 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c offset = tiled_offset(tile, page << PAGE_SHIFT); tile 158 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile->tiling ? tile_row_pages(obj) : 0, tile 159 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride, tile 213 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c struct tile tile; tile 215 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.height = 1; tile 216 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.width = 1; tile 217 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.size = 0; tile 218 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.stride = 0; tile 219 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.swizzle = I915_BIT_6_SWIZZLE_NONE; tile 220 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.tiling = I915_TILING_NONE; tile 222 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c err = check_partial_mapping(obj, &tile, end); tile 231 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c struct tile tile; tile 241 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.tiling = tiling; tile 244 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.swizzle = i915->mm.bit_6_swizzle_x; tile 247 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.swizzle = i915->mm.bit_6_swizzle_y; tile 251 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c GEM_BUG_ON(tile.swizzle == I915_BIT_6_SWIZZLE_UNKNOWN); tile 252 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 || tile 253 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17) tile 257 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.height = 16; tile 258 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.width = 128; tile 259 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.size = 11; tile 260 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c } else if (tile.tiling == I915_TILING_Y && tile 262 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.height = 32; tile 263 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.width = 128; tile 264 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.size = 12; tile 266 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.height = 8; tile 267 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.width = 512; tile 268 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.size = 12; tile 272 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c max_pitch = 8192 / tile.width; tile 274 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c max_pitch = 128 * I965_FENCE_MAX_PITCH_VAL / tile.width; tile 276 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c max_pitch = 128 * GEN7_FENCE_MAX_PITCH_VAL / tile.width; tile 279 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.stride = tile.width * pitch; tile 280 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c err = check_partial_mapping(obj, &tile, end); tile 287 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.stride = tile.width * (pitch - 1); tile 288 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c err = check_partial_mapping(obj, &tile, end); tile 296 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.stride = tile.width * (pitch + 1); tile 297 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c err = check_partial_mapping(obj, &tile, end); tile 307 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c tile.stride = tile.width * pitch; tile 308 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c err = check_partial_mapping(obj, &tile, end); tile 1320 drivers/gpu/drm/i915/gvt/cmd_parser.c u32 stride, tile; tile 1327 drivers/gpu/drm/i915/gvt/cmd_parser.c tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & tile 1332 drivers/gpu/drm/i915/gvt/cmd_parser.c tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; tile 1338 drivers/gpu/drm/i915/gvt/cmd_parser.c if (tile != info->tile_val) tile 25 drivers/gpu/drm/nouveau/include/nvkm/core/engine.h void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); tile 42 drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h } tile; tile 56 drivers/gpu/drm/nouveau/nouveau_bo.c int i = reg - drm->tile.reg; tile 58 drivers/gpu/drm/nouveau/nouveau_bo.c struct nvkm_fb_tile *tile = &fb->tile.region[i]; tile 62 drivers/gpu/drm/nouveau/nouveau_bo.c if (tile->pitch) tile 63 drivers/gpu/drm/nouveau/nouveau_bo.c nvkm_fb_tile_fini(fb, i, tile); tile 66 drivers/gpu/drm/nouveau/nouveau_bo.c nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); tile 68 drivers/gpu/drm/nouveau/nouveau_bo.c nvkm_fb_tile_prog(fb, i, tile); tile 75 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm_tile *tile = &drm->tile.reg[i]; tile 77 drivers/gpu/drm/nouveau/nouveau_bo.c spin_lock(&drm->tile.lock); tile 79 drivers/gpu/drm/nouveau/nouveau_bo.c if (!tile->used && tile 80 drivers/gpu/drm/nouveau/nouveau_bo.c (!tile->fence || nouveau_fence_done(tile->fence))) tile 81 drivers/gpu/drm/nouveau/nouveau_bo.c tile->used = true; tile 83 drivers/gpu/drm/nouveau/nouveau_bo.c tile = NULL; tile 85 drivers/gpu/drm/nouveau/nouveau_bo.c spin_unlock(&drm->tile.lock); tile 86 drivers/gpu/drm/nouveau/nouveau_bo.c return tile; tile 90 drivers/gpu/drm/nouveau/nouveau_bo.c nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, tile 95 drivers/gpu/drm/nouveau/nouveau_bo.c if (tile) { tile 96 drivers/gpu/drm/nouveau/nouveau_bo.c spin_lock(&drm->tile.lock); tile 97 drivers/gpu/drm/nouveau/nouveau_bo.c tile->fence = (struct nouveau_fence *)dma_fence_get(fence); tile 98 drivers/gpu/drm/nouveau/nouveau_bo.c tile->used = false; tile 99 drivers/gpu/drm/nouveau/nouveau_bo.c spin_unlock(&drm->tile.lock); tile 109 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm_tile *tile, *found = NULL; tile 112 drivers/gpu/drm/nouveau/nouveau_bo.c for (i = 0; i < fb->tile.regions; i++) { tile 113 drivers/gpu/drm/nouveau/nouveau_bo.c tile = nv10_bo_get_tile_region(dev, i); tile 116 drivers/gpu/drm/nouveau/nouveau_bo.c found = tile; tile 119 drivers/gpu/drm/nouveau/nouveau_bo.c } else if (tile && fb->tile.region[i].pitch) { tile 121 drivers/gpu/drm/nouveau/nouveau_bo.c nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); tile 124 drivers/gpu/drm/nouveau/nouveau_bo.c nv10_bo_put_tile_region(dev, tile, NULL); tile 140 drivers/gpu/drm/nouveau/nouveau_bo.c nv10_bo_put_tile_region(dev, nvbo->tile, NULL); tile 1422 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); tile 36 drivers/gpu/drm/nouveau/nouveau_bo.h struct nouveau_drm_tile *tile; tile 523 drivers/gpu/drm/nouveau/nouveau_drm.c spin_lock_init(&drm->tile.lock); tile 192 drivers/gpu/drm/nouveau/nouveau_drv.h } tile; tile 73 drivers/gpu/drm/nouveau/nvkm/core/engine.c if (engine->func->tile) tile 74 drivers/gpu/drm/nouveau/nvkm/core/engine.c engine->func->tile(engine, region, &fb->tile.region[region]); tile 139 drivers/gpu/drm/nouveau/nvkm/core/engine.c for (i = 0; fb && i < fb->tile.regions; i++) tile 65 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) tile 68 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->tile) tile 69 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c gr->func->tile(gr, region, tile); tile 170 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c .tile = nvkm_gr_tile, tile 1124 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5); tile 207 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5); tile 125 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5); tile 1928 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->tile[i++] = gpc_map[j]; tile 1980 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c memset(gr->tile, 0xff, sizeof(gr->tile)); tile 2289 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c data |= bank[gr->tile[i + j]] << (j * 4); tile 2290 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c bank[gr->tile[i + j]]++; tile 127 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h u8 tile[TPC_MAX]; tile 134 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c data |= bank[gr->tile[i + j]] << (j * 4); tile 135 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c bank[gr->tile[i + j]]++; tile 112 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total); tile 116 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total); tile 120 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total); tile 1049 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) tile 1059 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit); tile 1060 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch); tile 1061 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr); tile 1192 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c .tile = nv10_gr_tile, tile 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c .tile = nv10_gr_tile, tile 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c .tile = nv10_gr_tile, tile 149 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) tile 159 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); tile 160 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); tile 161 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); tile 164 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit); tile 166 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch); tile 168 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr); tile 171 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); tile 173 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp); tile 350 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c .tile = nv20_gr_tile, tile 109 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c .tile = nv20_gr_tile, tile 100 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c .tile = nv20_gr_tile, tile 171 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c .tile = nv20_gr_tile, tile 108 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c .tile = nv20_gr_tile, tile 108 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c .tile = nv20_gr_tile, tile 173 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) tile 189 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); tile 190 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); tile 191 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); tile 192 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); tile 193 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); tile 194 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); tile 198 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); tile 199 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); tile 204 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); tile 205 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); tile 214 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); tile 215 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); tile 216 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); tile 217 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); tile 218 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); tile 219 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); tile 220 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); tile 221 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); tile 448 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c .tile = nv40_gr_tile, tile 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) tile 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); tile 45 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); tile 46 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); tile 53 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); tile 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); tile 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); tile 56 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); tile 57 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); tile 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); tile 61 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); tile 62 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); tile 63 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); tile 64 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); tile 65 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); tile 66 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); tile 80 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c .tile = nv44_gr_tile, tile 21 drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); tile 114 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile) tile 119 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch); tile 120 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit); tile 121 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr); tile 267 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c .tile = nv31_mpeg_tile, tile 197 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c .tile = nv31_mpeg_tile, tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c fb->func->tile.fini(fb, region, tile); tile 42 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c u32 pitch, u32 flags, struct nvkm_fb_tile *tile) tile 44 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); tile 48 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) tile 51 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c if (fb->func->tile.prog) { tile 52 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c fb->func->tile.prog(fb, region, tile); tile 140 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c for (i = 0; i < fb->tile.regions; i++) tile 141 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c fb->func->tile.prog(fb, i, &fb->tile.region[i]); tile 169 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c for (i = 0; i < fb->tile.regions; i++) tile 170 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c fb->func->tile.fini(fb, i, &fb->tile.region[i]); tile 194 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c fb->tile.regions = fb->func->tile.regions; tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c u32 flags, struct nvkm_fb_tile *tile) tile 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c tile->addr = 0x80000000 | addr; tile 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c tile->limit = max(1u, addr + size) - 1; tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c tile->pitch = pitch; tile 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) tile 41 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c tile->addr = 0; tile 42 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c tile->limit = 0; tile 43 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c tile->pitch = 0; tile 44 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c tile->zcomp = 0; tile 48 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) tile 51 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c nvkm_wr32(device, 0x100244 + (i * 0x10), tile->limit); tile 52 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c nvkm_wr32(device, 0x100248 + (i * 0x10), tile->pitch); tile 53 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c nvkm_wr32(device, 0x100240 + (i * 0x10), tile->addr); tile 59 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c .tile.regions = 8, tile 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c .tile.init = nv10_fb_tile_init, tile 61 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c .tile.fini = nv10_fb_tile_fini, tile 62 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c .tile.prog = nv10_fb_tile_prog, tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c .tile.regions = 8, tile 32 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c .tile.init = nv10_fb_tile_init, tile 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c .tile.fini = nv10_fb_tile_fini, tile 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c .tile.prog = nv10_fb_tile_prog, tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c u32 flags, struct nvkm_fb_tile *tile) tile 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->addr = 0x00000001 | addr; tile 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->limit = max(1u, addr + size) - 1; tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->pitch = pitch; tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c fb->func->tile.comp(fb, i, size, flags, tile); tile 38 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->addr |= 2; tile 44 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c struct nvkm_fb_tile *tile) tile 48 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile 49 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ tile 50 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c else tile->zcomp = 0x04000000; /* Z24S8 */ tile 51 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->zcomp |= tile->tag->offset; tile 52 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->zcomp |= 0x80000000; /* enable */ tile 54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->zcomp |= 0x08000000; tile 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) tile 62 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->addr = 0; tile 63 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->limit = 0; tile 64 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->pitch = 0; tile 65 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c tile->zcomp = 0; tile 66 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c nvkm_mm_free(&fb->tags, &tile->tag); tile 70 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c nv20_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) tile 73 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c nvkm_wr32(device, 0x100244 + (i * 0x10), tile->limit); tile 74 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c nvkm_wr32(device, 0x100248 + (i * 0x10), tile->pitch); tile 75 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c nvkm_wr32(device, 0x100240 + (i * 0x10), tile->addr); tile 77 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c nvkm_wr32(device, 0x100300 + (i * 0x04), tile->zcomp); tile 90 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c .tile.regions = 8, tile 91 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c .tile.init = nv20_fb_tile_init, tile 92 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c .tile.comp = nv20_fb_tile_comp, tile 93 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c .tile.fini = nv20_fb_tile_fini, tile 94 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c .tile.prog = nv20_fb_tile_prog, tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c struct nvkm_fb_tile *tile) tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c else tile->zcomp = 0x00200000; /* Z24S8 */ tile 38 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c tile->zcomp |= tile->tag->offset; tile 40 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c tile->zcomp |= 0x01000000; tile 48 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c .tile.regions = 8, tile 49 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c .tile.init = nv20_fb_tile_init, tile 50 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c .tile.comp = nv25_fb_tile_comp, tile 51 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c .tile.fini = nv20_fb_tile_fini, tile 52 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c .tile.prog = nv20_fb_tile_prog, tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c u32 flags, struct nvkm_fb_tile *tile) tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c tile->addr = (0 << 4); tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c if (fb->func->tile.comp) /* z compression */ tile 38 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c fb->func->tile.comp(fb, i, size, flags, tile); tile 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c tile->addr = (1 << 4); tile 42 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c tile->addr |= 0x00000001; /* enable */ tile 43 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c tile->addr |= addr; tile 44 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c tile->limit = max(1u, addr + size) - 1; tile 45 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c tile->pitch = pitch; tile 50 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c struct nvkm_fb_tile *tile) tile 54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile 55 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ tile 56 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c else tile->zcomp |= 0x02000000; /* Z24S8 */ tile 57 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c tile->zcomp |= ((tile->tag->offset ) >> 6); tile 58 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 12; tile 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c tile->zcomp |= 0x10000000; tile 121 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c .tile.regions = 8, tile 122 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c .tile.init = nv30_fb_tile_init, tile 123 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c .tile.comp = nv30_fb_tile_comp, tile 124 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c .tile.fini = nv20_fb_tile_fini, tile 125 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c .tile.prog = nv20_fb_tile_prog, tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c struct nvkm_fb_tile *tile) tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c else tile->zcomp |= 0x08000000; /* Z24S8 */ tile 38 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c tile->zcomp |= ((tile->tag->offset ) >> 6); tile 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; tile 41 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c tile->zcomp |= 0x40000000; tile 50 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c .tile.regions = 8, tile 51 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c .tile.init = nv30_fb_tile_init, tile 52 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c .tile.comp = nv35_fb_tile_comp, tile 53 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c .tile.fini = nv20_fb_tile_fini, tile 54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c .tile.prog = nv20_fb_tile_prog, tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c struct nvkm_fb_tile *tile) tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c else tile->zcomp |= 0x20000000; /* Z24S8 */ tile 38 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c tile->zcomp |= ((tile->tag->offset ) >> 6); tile 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; tile 41 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c tile->zcomp |= 0x80000000; tile 50 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c .tile.regions = 8, tile 51 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c .tile.init = nv30_fb_tile_init, tile 52 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c .tile.comp = nv36_fb_tile_comp, tile 53 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c .tile.fini = nv20_fb_tile_fini, tile 54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c .tile.prog = nv20_fb_tile_prog, tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c struct nvkm_fb_tile *tile) tile 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c !nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ tile 38 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c tile->zcomp |= ((tile->tag->offset ) >> 8); tile 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; tile 41 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c tile->zcomp |= 0x40000000; tile 56 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c .tile.regions = 8, tile 57 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c .tile.init = nv30_fb_tile_init, tile 58 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c .tile.comp = nv40_fb_tile_comp, tile 59 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c .tile.fini = nv20_fb_tile_fini, tile 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c .tile.prog = nv20_fb_tile_prog, tile 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) tile 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); tile 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); tile 50 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c .tile.regions = 12, tile 51 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c .tile.init = nv30_fb_tile_init, tile 52 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c .tile.comp = nv40_fb_tile_comp, tile 53 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c .tile.fini = nv20_fb_tile_fini, tile 54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c .tile.prog = nv41_fb_tile_prog, tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c u32 flags, struct nvkm_fb_tile *tile) tile 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c tile->addr = 0x00000001; /* mode = vram */ tile 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c tile->addr |= addr; tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c tile->limit = max(1u, addr + size) - 1; tile 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c tile->pitch = pitch; tile 40 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) tile 43 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); tile 44 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); tile 45 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); tile 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c .tile.regions = 12, tile 61 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c .tile.init = nv44_fb_tile_init, tile 62 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c .tile.fini = nv20_fb_tile_fini, tile 63 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c .tile.prog = nv44_fb_tile_prog, tile 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c u32 flags, struct nvkm_fb_tile *tile) tile 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c if (!(flags & 4)) tile->addr = (0 << 3); tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c else tile->addr = (1 << 3); tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c tile->addr |= 0x00000001; /* mode = vram */ tile 38 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c tile->addr |= addr; tile 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c tile->limit = max(1u, addr + size) - 1; tile 40 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c tile->pitch = pitch; tile 46 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c .tile.regions = 15, tile 47 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c .tile.init = nv46_fb_tile_init, tile 48 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c .tile.fini = nv20_fb_tile_fini, tile 49 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c .tile.prog = nv44_fb_tile_prog, tile 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c .tile.regions = 15, tile 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c .tile.init = nv30_fb_tile_init, tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c .tile.comp = nv40_fb_tile_comp, tile 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c .tile.fini = nv20_fb_tile_fini, tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c .tile.prog = nv41_fb_tile_prog, tile 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c .tile.regions = 15, tile 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c .tile.init = nv30_fb_tile_init, tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c .tile.comp = nv40_fb_tile_comp, tile 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c .tile.fini = nv20_fb_tile_fini, tile 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c .tile.prog = nv41_fb_tile_prog, tile 32 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c .tile.regions = 12, tile 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c .tile.init = nv46_fb_tile_init, tile 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c .tile.fini = nv20_fb_tile_fini, tile 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c .tile.prog = nv44_fb_tile_prog, tile 27 drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h } tile; tile 2335 drivers/gpu/drm/radeon/cik.c u32 *tile = rdev->config.cik.tile_mode_array; tile 2364 drivers/gpu/drm/radeon/cik.c tile[reg_offset] = 0; tile 2370 drivers/gpu/drm/radeon/cik.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2374 drivers/gpu/drm/radeon/cik.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2378 drivers/gpu/drm/radeon/cik.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2382 drivers/gpu/drm/radeon/cik.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2386 drivers/gpu/drm/radeon/cik.c tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2390 drivers/gpu/drm/radeon/cik.c tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2393 drivers/gpu/drm/radeon/cik.c tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2397 drivers/gpu/drm/radeon/cik.c tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2401 drivers/gpu/drm/radeon/cik.c tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 2403 drivers/gpu/drm/radeon/cik.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2406 drivers/gpu/drm/radeon/cik.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2410 drivers/gpu/drm/radeon/cik.c tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2414 drivers/gpu/drm/radeon/cik.c tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2418 drivers/gpu/drm/radeon/cik.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2421 drivers/gpu/drm/radeon/cik.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2425 drivers/gpu/drm/radeon/cik.c tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2429 drivers/gpu/drm/radeon/cik.c tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2433 drivers/gpu/drm/radeon/cik.c tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2436 drivers/gpu/drm/radeon/cik.c tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2440 drivers/gpu/drm/radeon/cik.c tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2444 drivers/gpu/drm/radeon/cik.c tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2507 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); tile 2513 drivers/gpu/drm/radeon/cik.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2517 drivers/gpu/drm/radeon/cik.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2521 drivers/gpu/drm/radeon/cik.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2525 drivers/gpu/drm/radeon/cik.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2529 drivers/gpu/drm/radeon/cik.c tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2533 drivers/gpu/drm/radeon/cik.c tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2536 drivers/gpu/drm/radeon/cik.c tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2540 drivers/gpu/drm/radeon/cik.c tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2544 drivers/gpu/drm/radeon/cik.c tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 2546 drivers/gpu/drm/radeon/cik.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2549 drivers/gpu/drm/radeon/cik.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2553 drivers/gpu/drm/radeon/cik.c tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2557 drivers/gpu/drm/radeon/cik.c tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2561 drivers/gpu/drm/radeon/cik.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2564 drivers/gpu/drm/radeon/cik.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2568 drivers/gpu/drm/radeon/cik.c tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2572 drivers/gpu/drm/radeon/cik.c tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2576 drivers/gpu/drm/radeon/cik.c tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2579 drivers/gpu/drm/radeon/cik.c tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2583 drivers/gpu/drm/radeon/cik.c tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2587 drivers/gpu/drm/radeon/cik.c tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2650 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); tile 2657 drivers/gpu/drm/radeon/cik.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2661 drivers/gpu/drm/radeon/cik.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2665 drivers/gpu/drm/radeon/cik.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2669 drivers/gpu/drm/radeon/cik.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2673 drivers/gpu/drm/radeon/cik.c tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2677 drivers/gpu/drm/radeon/cik.c tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2680 drivers/gpu/drm/radeon/cik.c tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2684 drivers/gpu/drm/radeon/cik.c tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2688 drivers/gpu/drm/radeon/cik.c tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 2690 drivers/gpu/drm/radeon/cik.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2693 drivers/gpu/drm/radeon/cik.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2697 drivers/gpu/drm/radeon/cik.c tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2701 drivers/gpu/drm/radeon/cik.c tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2705 drivers/gpu/drm/radeon/cik.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2708 drivers/gpu/drm/radeon/cik.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2712 drivers/gpu/drm/radeon/cik.c tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2716 drivers/gpu/drm/radeon/cik.c tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2720 drivers/gpu/drm/radeon/cik.c tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2723 drivers/gpu/drm/radeon/cik.c tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2727 drivers/gpu/drm/radeon/cik.c tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2731 drivers/gpu/drm/radeon/cik.c tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2737 drivers/gpu/drm/radeon/cik.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2741 drivers/gpu/drm/radeon/cik.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2745 drivers/gpu/drm/radeon/cik.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2749 drivers/gpu/drm/radeon/cik.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2753 drivers/gpu/drm/radeon/cik.c tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2757 drivers/gpu/drm/radeon/cik.c tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2760 drivers/gpu/drm/radeon/cik.c tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2764 drivers/gpu/drm/radeon/cik.c tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2768 drivers/gpu/drm/radeon/cik.c tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 2770 drivers/gpu/drm/radeon/cik.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2773 drivers/gpu/drm/radeon/cik.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2777 drivers/gpu/drm/radeon/cik.c tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2781 drivers/gpu/drm/radeon/cik.c tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2785 drivers/gpu/drm/radeon/cik.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2788 drivers/gpu/drm/radeon/cik.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2792 drivers/gpu/drm/radeon/cik.c tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2796 drivers/gpu/drm/radeon/cik.c tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2800 drivers/gpu/drm/radeon/cik.c tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2803 drivers/gpu/drm/radeon/cik.c tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2807 drivers/gpu/drm/radeon/cik.c tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2811 drivers/gpu/drm/radeon/cik.c tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2875 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); tile 2881 drivers/gpu/drm/radeon/cik.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2885 drivers/gpu/drm/radeon/cik.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2889 drivers/gpu/drm/radeon/cik.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2893 drivers/gpu/drm/radeon/cik.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2897 drivers/gpu/drm/radeon/cik.c tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2901 drivers/gpu/drm/radeon/cik.c tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2904 drivers/gpu/drm/radeon/cik.c tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2908 drivers/gpu/drm/radeon/cik.c tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2912 drivers/gpu/drm/radeon/cik.c tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 2914 drivers/gpu/drm/radeon/cik.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2917 drivers/gpu/drm/radeon/cik.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2921 drivers/gpu/drm/radeon/cik.c tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2925 drivers/gpu/drm/radeon/cik.c tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2929 drivers/gpu/drm/radeon/cik.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2932 drivers/gpu/drm/radeon/cik.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2936 drivers/gpu/drm/radeon/cik.c tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2940 drivers/gpu/drm/radeon/cik.c tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2944 drivers/gpu/drm/radeon/cik.c tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2947 drivers/gpu/drm/radeon/cik.c tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 2951 drivers/gpu/drm/radeon/cik.c tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile 2955 drivers/gpu/drm/radeon/cik.c tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile 3018 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); tile 2495 drivers/gpu/drm/radeon/si.c u32 *tile = rdev->config.si.tile_mode_array; tile 2514 drivers/gpu/drm/radeon/si.c tile[reg_offset] = 0; tile 2520 drivers/gpu/drm/radeon/si.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2529 drivers/gpu/drm/radeon/si.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2538 drivers/gpu/drm/radeon/si.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2547 drivers/gpu/drm/radeon/si.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2556 drivers/gpu/drm/radeon/si.c tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2565 drivers/gpu/drm/radeon/si.c tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2574 drivers/gpu/drm/radeon/si.c tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2583 drivers/gpu/drm/radeon/si.c tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2592 drivers/gpu/drm/radeon/si.c tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 2601 drivers/gpu/drm/radeon/si.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2610 drivers/gpu/drm/radeon/si.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2619 drivers/gpu/drm/radeon/si.c tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2628 drivers/gpu/drm/radeon/si.c tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2637 drivers/gpu/drm/radeon/si.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2646 drivers/gpu/drm/radeon/si.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2655 drivers/gpu/drm/radeon/si.c tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2664 drivers/gpu/drm/radeon/si.c tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2673 drivers/gpu/drm/radeon/si.c tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2682 drivers/gpu/drm/radeon/si.c tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2691 drivers/gpu/drm/radeon/si.c tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2700 drivers/gpu/drm/radeon/si.c tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2709 drivers/gpu/drm/radeon/si.c tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2718 drivers/gpu/drm/radeon/si.c tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2728 drivers/gpu/drm/radeon/si.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); tile 2735 drivers/gpu/drm/radeon/si.c tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2744 drivers/gpu/drm/radeon/si.c tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2753 drivers/gpu/drm/radeon/si.c tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2762 drivers/gpu/drm/radeon/si.c tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2771 drivers/gpu/drm/radeon/si.c tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2780 drivers/gpu/drm/radeon/si.c tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2789 drivers/gpu/drm/radeon/si.c tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2798 drivers/gpu/drm/radeon/si.c tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2807 drivers/gpu/drm/radeon/si.c tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile 2816 drivers/gpu/drm/radeon/si.c tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2825 drivers/gpu/drm/radeon/si.c tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2834 drivers/gpu/drm/radeon/si.c tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2843 drivers/gpu/drm/radeon/si.c tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2852 drivers/gpu/drm/radeon/si.c tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile 2861 drivers/gpu/drm/radeon/si.c tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2870 drivers/gpu/drm/radeon/si.c tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2879 drivers/gpu/drm/radeon/si.c tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2888 drivers/gpu/drm/radeon/si.c tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2897 drivers/gpu/drm/radeon/si.c tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2906 drivers/gpu/drm/radeon/si.c tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2915 drivers/gpu/drm/radeon/si.c tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2924 drivers/gpu/drm/radeon/si.c tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2933 drivers/gpu/drm/radeon/si.c tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile 2943 drivers/gpu/drm/radeon/si.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); tile 726 drivers/gpu/drm/vc4/vc4_plane.c u32 tile_w, tile, x_off, pix_per_tile; tile 753 drivers/gpu/drm/vc4/vc4_plane.c tile = vc4_state->src_x / pix_per_tile; tile 760 drivers/gpu/drm/vc4/vc4_plane.c vc4_state->offsets[i] += param * tile_w * tile; tile 123 drivers/gpu/ipu-v3/ipu-image-convert.c struct ipu_image_tile tile[MAX_TILES]; tile 662 drivers/gpu/ipu-v3/ipu-image-convert.c in_tile = &in->tile[tile_idx]; tile 663 drivers/gpu/ipu-v3/ipu-image-convert.c out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; tile 694 drivers/gpu/ipu-v3/ipu-image-convert.c in_tile = &in->tile[tile_idx]; tile 695 drivers/gpu/ipu-v3/ipu-image-convert.c out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; tile 855 drivers/gpu/ipu-v3/ipu-image-convert.c struct ipu_image_tile *tile; tile 860 drivers/gpu/ipu-v3/ipu-image-convert.c tile = &image->tile[ctx->out_tile_map[i]]; tile 862 drivers/gpu/ipu-v3/ipu-image-convert.c tile = &image->tile[i]; tile 864 drivers/gpu/ipu-v3/ipu-image-convert.c tile->size = ((tile->height * image->fmt->bpp) >> 3) * tile 865 drivers/gpu/ipu-v3/ipu-image-convert.c tile->width; tile 868 drivers/gpu/ipu-v3/ipu-image-convert.c tile->stride = tile->width; tile 869 drivers/gpu/ipu-v3/ipu-image-convert.c tile->rot_stride = tile->height; tile 871 drivers/gpu/ipu-v3/ipu-image-convert.c tile->stride = tile 872 drivers/gpu/ipu-v3/ipu-image-convert.c (image->fmt->bpp * tile->width) >> 3; tile 873 drivers/gpu/ipu-v3/ipu-image-convert.c tile->rot_stride = tile 874 drivers/gpu/ipu-v3/ipu-image-convert.c (image->fmt->bpp * tile->height) >> 3; tile 882 drivers/gpu/ipu-v3/ipu-image-convert.c tile->width, tile->height, tile->left, tile->top); tile 884 drivers/gpu/ipu-v3/ipu-image-convert.c if (!tile->width || tile->width > max_width || tile 885 drivers/gpu/ipu-v3/ipu-image-convert.c !tile->height || tile->height > max_height) { tile 888 drivers/gpu/ipu-v3/ipu-image-convert.c "output", tile->width, tile->height); tile 958 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int row, col, tile = 0; tile 962 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->out_tile_map[tile] = tile 964 drivers/gpu/ipu-v3/ipu-image-convert.c tile++; tile 975 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int row, col, tile = 0; tile 993 drivers/gpu/ipu-v3/ipu-image-convert.c top = image->tile[tile].top; tile 998 drivers/gpu/ipu-v3/ipu-image-convert.c y_col_off = image->tile[tile].left; tile 1014 drivers/gpu/ipu-v3/ipu-image-convert.c image->tile[tile].offset = y_off; tile 1015 drivers/gpu/ipu-v3/ipu-image-convert.c image->tile[tile].u_off = u_off; tile 1016 drivers/gpu/ipu-v3/ipu-image-convert.c image->tile[tile++].v_off = v_off; tile 1040 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int row, col, tile = 0; tile 1049 drivers/gpu/ipu-v3/ipu-image-convert.c row_off = image->tile[tile].top * stride; tile 1052 drivers/gpu/ipu-v3/ipu-image-convert.c col_off = (image->tile[tile].left * bpp) >> 3; tile 1056 drivers/gpu/ipu-v3/ipu-image-convert.c image->tile[tile].offset = offset; tile 1057 drivers/gpu/ipu-v3/ipu-image-convert.c image->tile[tile].u_off = 0; tile 1058 drivers/gpu/ipu-v3/ipu-image-convert.c image->tile[tile++].v_off = 0; tile 1127 drivers/gpu/ipu-v3/ipu-image-convert.c in_tile = &ctx->in.tile[tile_idx]; tile 1128 drivers/gpu/ipu-v3/ipu-image-convert.c out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; tile 1162 drivers/gpu/ipu-v3/ipu-image-convert.c in_tile = &ctx->in.tile[tile_idx]; tile 1163 drivers/gpu/ipu-v3/ipu-image-convert.c out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; tile 1184 drivers/gpu/ipu-v3/ipu-image-convert.c in_tile = &ctx->in.tile[tile_idx]; tile 1185 drivers/gpu/ipu-v3/ipu-image-convert.c out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; tile 1219 drivers/gpu/ipu-v3/ipu-image-convert.c in_tile = &ctx->in.tile[tile_idx]; tile 1220 drivers/gpu/ipu-v3/ipu-image-convert.c out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; tile 1282 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int tile) tile 1292 drivers/gpu/ipu-v3/ipu-image-convert.c tile_idx[0] = ctx->out_tile_map[tile]; tile 1295 drivers/gpu/ipu-v3/ipu-image-convert.c tile_idx[0] = tile; tile 1300 drivers/gpu/ipu-v3/ipu-image-convert.c width = image->tile[tile_idx[0]].height; tile 1301 drivers/gpu/ipu-v3/ipu-image-convert.c height = image->tile[tile_idx[0]].width; tile 1302 drivers/gpu/ipu-v3/ipu-image-convert.c stride = image->tile[tile_idx[0]].rot_stride; tile 1307 drivers/gpu/ipu-v3/ipu-image-convert.c width = image->tile[tile_idx[0]].width; tile 1308 drivers/gpu/ipu-v3/ipu-image-convert.c height = image->tile[tile_idx[0]].height; tile 1311 drivers/gpu/ipu-v3/ipu-image-convert.c image->tile[tile_idx[0]].offset; tile 1314 drivers/gpu/ipu-v3/ipu-image-convert.c image->tile[tile_idx[1]].offset; tile 1327 drivers/gpu/ipu-v3/ipu-image-convert.c tile_image.u_offset = image->tile[tile_idx[0]].u_off; tile 1328 drivers/gpu/ipu-v3/ipu-image-convert.c tile_image.v_offset = image->tile[tile_idx[0]].v_off; tile 1367 drivers/gpu/ipu-v3/ipu-image-convert.c static int convert_start(struct ipu_image_convert_run *run, unsigned int tile) tile 1374 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int dst_tile = ctx->out_tile_map[tile]; tile 1381 drivers/gpu/ipu-v3/ipu-image-convert.c __func__, chan->ic_task, ctx, run, tile, dst_tile); tile 1385 drivers/gpu/ipu-v3/ipu-image-convert.c dest_width = d_image->tile[dst_tile].height; tile 1386 drivers/gpu/ipu-v3/ipu-image-convert.c dest_height = d_image->tile[dst_tile].width; tile 1388 drivers/gpu/ipu-v3/ipu-image-convert.c dest_width = d_image->tile[dst_tile].width; tile 1389 drivers/gpu/ipu-v3/ipu-image-convert.c dest_height = d_image->tile[dst_tile].height; tile 1392 drivers/gpu/ipu-v3/ipu-image-convert.c row = tile / s_image->num_cols; tile 1393 drivers/gpu/ipu-v3/ipu-image-convert.c col = tile % s_image->num_cols; tile 1401 drivers/gpu/ipu-v3/ipu-image-convert.c __func__, s_image->tile[tile].width, tile 1402 drivers/gpu/ipu-v3/ipu-image-convert.c s_image->tile[tile].height, dest_width, dest_height, rsc); tile 1406 drivers/gpu/ipu-v3/ipu-image-convert.c s_image->tile[tile].width, tile 1407 drivers/gpu/ipu-v3/ipu-image-convert.c s_image->tile[tile].height, tile 1418 drivers/gpu/ipu-v3/ipu-image-convert.c IPU_ROTATE_NONE, false, tile); tile 1423 drivers/gpu/ipu-v3/ipu-image-convert.c IPU_ROTATE_NONE, true, tile); tile 1427 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->rot_mode, true, tile); tile 1431 drivers/gpu/ipu-v3/ipu-image-convert.c IPU_ROTATE_NONE, false, tile); tile 1438 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->rot_mode, false, tile); tile 1608 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->in.tile[cur_tile].width != ctx->in.tile[next_tile].width || tile 1609 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->in.tile[cur_tile].height != ctx->in.tile[next_tile].height || tile 1610 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->out.tile[cur_tile].width != ctx->out.tile[next_tile].width || tile 1611 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->out.tile[cur_tile].height != ctx->out.tile[next_tile].height) tile 1664 drivers/gpu/ipu-v3/ipu-image-convert.c src_tile = &s_image->tile[ctx->next_tile]; tile 1666 drivers/gpu/ipu-v3/ipu-image-convert.c dst_tile = &d_image->tile[dst_idx]; tile 1688 drivers/gpu/ipu-v3/ipu-image-convert.c src_tile = &s_image->tile[ctx->next_tile + 1]; tile 1690 drivers/gpu/ipu-v3/ipu-image-convert.c dst_tile = &d_image->tile[dst_idx]; tile 2158 drivers/gpu/ipu-v3/ipu-image-convert.c if (ctx->in.tile[i].width != ctx->in.tile[0].width || tile 2159 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->in.tile[i].height != ctx->in.tile[0].height || tile 2160 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->out.tile[i].width != ctx->out.tile[0].width || tile 2161 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->out.tile[i].height != ctx->out.tile[0].height) { tile 2180 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned long intermediate_size = d_image->tile[0].size; tile 2183 drivers/gpu/ipu-v3/ipu-image-convert.c if (d_image->tile[i].size > intermediate_size) tile 2184 drivers/gpu/ipu-v3/ipu-image-convert.c intermediate_size = d_image->tile[i].size; tile 91 drivers/hid/hid-picolcd_fb.c int chip, int tile) tile 114 drivers/hid/hid-picolcd_fb.c hid_set_field(report1->field[0], 4, 0xb8 | tile); tile 127 drivers/hid/hid-picolcd_fb.c tdata = vbitmap + (tile * 4 + chip) * 64; tile 142 drivers/hid/hid-picolcd_fb.c int chip, int tile) tile 146 drivers/hid/hid-picolcd_fb.c u8 *vdata = vbitmap + (tile * 4 + chip) * 64; tile 150 drivers/hid/hid-picolcd_fb.c const u8 *bdata = bitmap + tile * 256 + chip * 8 + b * 32; tile 158 drivers/hid/hid-picolcd_fb.c const u8 *bdata = bitmap + (tile * 256 + chip * 8 + b * 32) * 8; tile 227 drivers/hid/hid-picolcd_fb.c int chip, tile, n; tile 248 drivers/hid/hid-picolcd_fb.c for (tile = 0; tile < 8; tile++) { tile 251 drivers/hid/hid-picolcd_fb.c fbdata->bpp, chip, tile)) tile 269 drivers/hid/hid-picolcd_fb.c fbdata->vbitmap, chip, tile)) tile 73 drivers/pinctrl/qcom/pinctrl-msm.c return readl(pctrl->regs[g->tile] + g->name##_reg); \ tile 78 drivers/pinctrl/qcom/pinctrl-msm.c writel(val, pctrl->regs[g->tile] + g->name##_reg); \ tile 71 drivers/pinctrl/qcom/pinctrl-msm.h unsigned int tile:2; tile 55 drivers/pinctrl/qcom/pinctrl-qcs404.c .tile = _tile, \ tile 82 drivers/pinctrl/qcom/pinctrl-qcs404.c .tile = SOUTH, \ tile 53 drivers/pinctrl/qcom/pinctrl-sc7180.c .tile = _tile, \ tile 80 drivers/pinctrl/qcom/pinctrl-sc7180.c .tile = SOUTH, \ tile 106 drivers/pinctrl/qcom/pinctrl-sc7180.c .tile = SOUTH, \ tile 59 drivers/pinctrl/qcom/pinctrl-sdm660.c .tile = _tile, \ tile 86 drivers/pinctrl/qcom/pinctrl-sdm660.c .tile = NORTH, \ tile 55 drivers/pinctrl/qcom/pinctrl-sm8150.c .tile = _tile, \ tile 82 drivers/pinctrl/qcom/pinctrl-sm8150.c .tile = NORTH, \ tile 108 drivers/pinctrl/qcom/pinctrl-sm8150.c .tile = SOUTH, \ tile 867 drivers/video/fbdev/cirrusfb.c unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); tile 877 drivers/video/fbdev/cirrusfb.c fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407); tile 1003 drivers/video/fbdev/gbefb.c u16 *tile; tile 1022 drivers/video/fbdev/gbefb.c tile = &gbe_tiles.cpu[offset >> TILE_SHIFT]; tile 1028 drivers/video/fbdev/gbefb.c phys_addr = (((unsigned long) (*tile)) << TILE_SHIFT) + offset; tile 1041 drivers/video/fbdev/gbefb.c tile++;