tilcdc_set        119 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
tilcdc_set        125 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
tilcdc_set        147 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
tilcdc_set        150 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_DMA_CTRL_REG,
tilcdc_set        187 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
tilcdc_set        263 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
tilcdc_set        365 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 			tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
tilcdc_set        403 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
tilcdc_set        408 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
tilcdc_set        413 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
tilcdc_set        418 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
tilcdc_set        423 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
tilcdc_set        428 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
tilcdc_set        477 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
tilcdc_set        938 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 				tilcdc_set(dev, LCDC_RASTER_CTRL_REG,