tilcdc_read       291 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
tilcdc_read       327 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
tilcdc_read       374 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
tilcdc_read       686 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) {
tilcdc_read       934 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 			reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
tilcdc_read       293 drivers/gpu/drm/tilcdc/tilcdc_drv.c 	switch (tilcdc_read(ddev, LCDC_PID_REG)) {
tilcdc_read       304 drivers/gpu/drm/tilcdc/tilcdc_drv.c 			tilcdc_read(ddev, LCDC_PID_REG));
tilcdc_read       467 drivers/gpu/drm/tilcdc/tilcdc_drv.c 					tilcdc_read(dev, registers[i].reg));
tilcdc_read       143 drivers/gpu/drm/tilcdc/tilcdc_regs.h 	tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask));
tilcdc_read       148 drivers/gpu/drm/tilcdc/tilcdc_regs.h 	tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);
tilcdc_read       153 drivers/gpu/drm/tilcdc/tilcdc_regs.h 	tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);
tilcdc_read       165 drivers/gpu/drm/tilcdc/tilcdc_regs.h 	return tilcdc_read(dev, tilcdc_irqstatus_reg(dev));