tilcdc_clear 133 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); tilcdc_clear 135 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA); tilcdc_clear 166 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, tilcdc_clear 169 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_DMA_CTRL_REG, tilcdc_clear 189 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); tilcdc_clear 368 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, tilcdc_clear 405 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); tilcdc_clear 410 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); tilcdc_clear 415 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); tilcdc_clear 420 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); tilcdc_clear 425 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); tilcdc_clear 430 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); tilcdc_clear 464 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); tilcdc_clear 506 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); tilcdc_clear 692 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); tilcdc_clear 922 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, tilcdc_clear 936 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, tilcdc_clear 961 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,