tf_regs 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->tf_regs->reg tf_regs 565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c const struct dcn_dpp_registers *tf_regs, tf_regs 575 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->tf_regs = tf_regs; tf_regs 1347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h const struct dcn_dpp_registers *tf_regs; tf_regs 1510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h const struct dcn_dpp_registers *tf_regs, tf_regs 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->tf_regs->reg tf_regs 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->tf_regs->reg tf_regs 382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn_dpp_registers tf_regs[] = { tf_regs 383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c tf_regs(0), tf_regs 384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c tf_regs(1), tf_regs 385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c tf_regs(2), tf_regs 386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c tf_regs(3), tf_regs 596 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &tf_regs[inst], &tf_shift, &tf_mask); tf_regs 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->tf_regs->reg tf_regs 498 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c const struct dcn2_dpp_registers *tf_regs, tf_regs 508 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->tf_regs = tf_regs; tf_regs 629 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h const struct dcn2_dpp_registers *tf_regs; tf_regs 702 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h const struct dcn2_dpp_registers *tf_regs, tf_regs 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp->tf_regs->reg tf_regs 685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn2_dpp_registers tf_regs[] = { tf_regs 686 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c tf_regs(0), tf_regs 687 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c tf_regs(1), tf_regs 688 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c tf_regs(2), tf_regs 689 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c tf_regs(3), tf_regs 690 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c tf_regs(4), tf_regs 691 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c tf_regs(5), tf_regs 983 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &tf_regs[inst], &tf_shift, &tf_mask)) tf_regs 604 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn2_dpp_registers tf_regs[] = { tf_regs 605 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c tf_regs(0), tf_regs 606 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c tf_regs(1), tf_regs 607 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c tf_regs(2), tf_regs 608 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c tf_regs(3), tf_regs 667 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &tf_regs[inst], &tf_shift, &tf_mask))