D2VGA_CONTROL 206 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D2VGA_CONTROL), \ D2VGA_CONTROL 272 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D2VGA_CONTROL), \ D2VGA_CONTROL 325 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D2VGA_CONTROL), \ D2VGA_CONTROL 418 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t D2VGA_CONTROL; D2VGA_CONTROL 573 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ D2VGA_CONTROL 472 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode); D2VGA_CONTROL 481 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_WRITE(D2VGA_CONTROL, 0); D2VGA_CONTROL 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_WRITE(D2VGA_CONTROL, 0);