D1VGA_CONTROL     669 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
D1VGA_CONTROL     825 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
D1VGA_CONTROL     945 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
D1VGA_CONTROL    1063 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
D1VGA_CONTROL    1149 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
D1VGA_CONTROL     205 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(D1VGA_CONTROL), \
D1VGA_CONTROL     271 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(D1VGA_CONTROL), \
D1VGA_CONTROL     324 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(D1VGA_CONTROL), \
D1VGA_CONTROL     417 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t D1VGA_CONTROL;
D1VGA_CONTROL     572 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
D1VGA_CONTROL    1829 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);
D1VGA_CONTROL    1830 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);
D1VGA_CONTROL    1832 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 			value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);
D1VGA_CONTROL    1833 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);
D1VGA_CONTROL     418 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);
D1VGA_CONTROL     419 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);
D1VGA_CONTROL     421 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 			value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);
D1VGA_CONTROL     422 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);
D1VGA_CONTROL     471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
D1VGA_CONTROL     480 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_WRITE(D1VGA_CONTROL, 0);
D1VGA_CONTROL     173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_WRITE(D1VGA_CONTROL, 0);