tegra_dc_writel    47 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
tegra_dc_writel    49 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
tegra_dc_writel    86 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
tegra_dc_writel   116 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel   117 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_writel   873 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
tegra_dc_writel   877 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
tegra_dc_writel   883 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel   892 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
tegra_dc_writel   896 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
tegra_dc_writel   913 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel  1456 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
tegra_dc_writel  1465 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
tegra_dc_writel  1556 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
tegra_dc_writel  1568 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
tegra_dc_writel  1593 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
tegra_dc_writel  1596 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
tegra_dc_writel  1601 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
tegra_dc_writel  1605 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
tegra_dc_writel  1609 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
tegra_dc_writel  1612 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
tegra_dc_writel  1678 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
tegra_dc_writel  1694 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
tegra_dc_writel  1759 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
tegra_dc_writel  1797 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
tegra_dc_writel  1800 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
tegra_dc_writel  1806 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
tegra_dc_writel  1813 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
tegra_dc_writel  1817 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
tegra_dc_writel  1820 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
tegra_dc_writel  1822 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
tegra_dc_writel  1826 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
tegra_dc_writel  1830 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
tegra_dc_writel  1835 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
tegra_dc_writel  1839 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
tegra_dc_writel  1843 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
tegra_dc_writel  1847 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
tegra_dc_writel  1851 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
tegra_dc_writel  1853 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
tegra_dc_writel  1865 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
tegra_dc_writel  1871 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
tegra_dc_writel  1877 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
tegra_dc_writel  1883 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
tegra_dc_writel  1918 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
tegra_dc_writel  1922 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
tegra_dc_writel  1939 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
tegra_dc_writel   866 drivers/gpu/drm/tegra/dsi.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel   933 drivers/gpu/drm/tegra/dsi.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel  1157 drivers/gpu/drm/tegra/hdmi.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel  1223 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, VSYNC_H_POSITION(1),
tegra_dc_writel  1225 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
tegra_dc_writel  1231 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
tegra_dc_writel  1235 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
tegra_dc_writel  1238 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
tegra_dc_writel  1382 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel    93 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
tegra_dc_writel   172 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
tegra_dc_writel   192 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
tegra_dc_writel   264 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, value, offset);
tegra_dc_writel   667 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);
tegra_dc_writel   671 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
tegra_dc_writel   673 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
tegra_dc_writel   675 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
tegra_dc_writel    84 drivers/gpu/drm/tegra/rgb.c 		tegra_dc_writel(dc, table[i].value, table[i].offset);
tegra_dc_writel   144 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
tegra_dc_writel   150 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
tegra_dc_writel   155 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
tegra_dc_writel   159 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
tegra_dc_writel  1612 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel  1968 drivers/gpu/drm/tegra/sor.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel  2406 drivers/gpu/drm/tegra/sor.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel  2609 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
tegra_dc_writel  2612 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
tegra_dc_writel  2616 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
tegra_dc_writel  2706 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
tegra_dc_writel  2736 drivers/gpu/drm/tegra/sor.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
tegra_dc_writel  2781 drivers/gpu/drm/tegra/sor.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel  2787 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));