tegra_dc_readl     48 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, offset);
tegra_dc_readl     80 drivers/gpu/drm/tegra/dc.c 	return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
tegra_dc_readl    881 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl    885 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
tegra_dc_readl    911 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl   1433 drivers/gpu/drm/tegra/dc.c 			   offset, tegra_dc_readl(dc, offset));
tegra_dc_readl   1462 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
tegra_dc_readl   1554 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
tegra_dc_readl   1566 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
tegra_dc_readl   1692 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
tegra_dc_readl   1756 drivers/gpu/drm/tegra/dc.c 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
tegra_dc_readl   1863 drivers/gpu/drm/tegra/dc.c 		value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
tegra_dc_readl   1868 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
tegra_dc_readl   1874 drivers/gpu/drm/tegra/dc.c 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
tegra_dc_readl   1919 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
tegra_dc_readl   1923 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
tegra_dc_readl   1938 drivers/gpu/drm/tegra/dc.c 	status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
tegra_dc_readl    864 drivers/gpu/drm/tegra/dsi.c 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl    931 drivers/gpu/drm/tegra/dsi.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl   1155 drivers/gpu/drm/tegra/hdmi.c 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl   1380 drivers/gpu/drm/tegra/hdmi.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl     87 drivers/gpu/drm/tegra/hub.c 	return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
tegra_dc_readl    177 drivers/gpu/drm/tegra/hub.c 		value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
tegra_dc_readl    197 drivers/gpu/drm/tegra/hub.c 		value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
tegra_dc_readl    211 drivers/gpu/drm/tegra/hub.c 	return tegra_dc_readl(dc, offset) & OWNER_MASK;
tegra_dc_readl    240 drivers/gpu/drm/tegra/hub.c 	value = tegra_dc_readl(dc, offset);
tegra_dc_readl    665 drivers/gpu/drm/tegra/hub.c 	value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL);
tegra_dc_readl    669 drivers/gpu/drm/tegra/hub.c 	value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
tegra_dc_readl    674 drivers/gpu/drm/tegra/hub.c 	tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
tegra_dc_readl    676 drivers/gpu/drm/tegra/hub.c 	tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
tegra_dc_readl    147 drivers/gpu/drm/tegra/rgb.c 	value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
tegra_dc_readl   1610 drivers/gpu/drm/tegra/sor.c 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl   1966 drivers/gpu/drm/tegra/sor.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl   2399 drivers/gpu/drm/tegra/sor.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl   2614 drivers/gpu/drm/tegra/sor.c 		value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
tegra_dc_readl   2709 drivers/gpu/drm/tegra/sor.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
tegra_dc_readl   2774 drivers/gpu/drm/tegra/sor.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_readl   2784 drivers/gpu/drm/tegra/sor.c 		value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));