td043mtea1_write  108 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 0x11, val);
td043mtea1_write  112 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 0x12, val);
td043mtea1_write  116 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 0x13, val);
td043mtea1_write  120 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 		td043mtea1_write(lcd, 0x14 + i, gamma[i] & 0xff);
td043mtea1_write  130 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	return td043mtea1_write(lcd, 4, reg4);
td043mtea1_write  149 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 2, TPO_R02_MODE(lcd->mode) | TPO_R02_NCLK_RISING);
td043mtea1_write  150 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 3, TPO_R03_VAL_NORMAL);
td043mtea1_write  151 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 0x20, 0xf0);
td043mtea1_write  152 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 0x21, 0xf0);
td043mtea1_write  166 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 3, TPO_R03_VAL_STANDBY | TPO_R03_EN_PWM);
td043mtea1_write  173 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 3, TPO_R03_VAL_STANDBY);
td043mtea1_write  234 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c 	td043mtea1_write(lcd, 2, val);