tcr 114 arch/arm/mach-davinci/time.c u32 tcr; tcr 131 arch/arm/mach-davinci/time.c tcr = __raw_readl(t->base + TCR); tcr 134 arch/arm/mach-davinci/time.c tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); tcr 135 arch/arm/mach-davinci/time.c __raw_writel(tcr, t->base + TCR); tcr 143 arch/arm/mach-davinci/time.c tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; tcr 145 arch/arm/mach-davinci/time.c tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; tcr 147 arch/arm/mach-davinci/time.c __raw_writel(tcr, t->base + TCR); tcr 207 arch/arm/mach-rpc/dma.c int tcr, speed; tcr 218 arch/arm/mach-rpc/dma.c tcr = iomd_readb(IOMD_DMATCR); tcr 223 arch/arm/mach-rpc/dma.c tcr = (tcr & ~0x03) | speed; tcr 227 arch/arm/mach-rpc/dma.c tcr = (tcr & ~0x0c) | (speed << 2); tcr 231 arch/arm/mach-rpc/dma.c tcr = (tcr & ~0x30) | (speed << 4); tcr 235 arch/arm/mach-rpc/dma.c tcr = (tcr & ~0xc0) | (speed << 6); tcr 242 arch/arm/mach-rpc/dma.c iomd_writeb(tcr, IOMD_DMATCR); tcr 356 arch/arm64/include/asm/assembler.h .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1 tcr 600 arch/arm64/include/asm/assembler.h .macro tcr_clear_errata_bits, tcr, tmp1, tmp2 tcr 86 arch/arm64/include/asm/mmu_context.h unsigned long tcr; tcr 91 arch/arm64/include/asm/mmu_context.h tcr = read_sysreg(tcr_el1); tcr 92 arch/arm64/include/asm/mmu_context.h tcr &= ~TCR_T0SZ_MASK; tcr 93 arch/arm64/include/asm/mmu_context.h tcr |= t0sz << TCR_T0SZ_OFFSET; tcr 94 arch/arm64/include/asm/mmu_context.h write_sysreg(tcr, tcr_el1); tcr 1088 arch/arm64/kernel/cpufeature.c u64 tcr = read_sysreg(tcr_el1) | TCR_HD; tcr 1090 arch/arm64/kernel/cpufeature.c write_sysreg(tcr, tcr_el1); tcr 15 arch/arm64/kvm/hyp/tlb.c u64 tcr; tcr 36 arch/arm64/kvm/hyp/tlb.c val = cxt->tcr = read_sysreg_el1(SYS_TCR); tcr 92 arch/arm64/kvm/hyp/tlb.c write_sysreg_el1(cxt->tcr, SYS_TCR); tcr 27 arch/c6x/platforms/timer64.c u32 tcr; tcr 79 arch/c6x/platforms/timer64.c u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK; tcr 81 arch/c6x/platforms/timer64.c soc_writel(tcr, &timer->tcr); tcr 84 arch/c6x/platforms/timer64.c tcr |= timer64_mode; tcr 85 arch/c6x/platforms/timer64.c soc_writel(tcr, &timer->tcr); tcr 96 arch/c6x/platforms/timer64.c soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr); tcr 100 arch/c6x/platforms/timer64.c val = soc_readl(&timer->tcr); tcr 101 arch/c6x/platforms/timer64.c soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr); tcr 112 arch/c6x/platforms/timer64.c soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr); tcr 31 arch/m68k/include/asm/bvme6000hw.h pad_q[3], tcr, tcr 15 arch/mips/include/asm/txx9tmr.h u32 tcr; tcr 63 arch/mips/kernel/cevt-txx9.c __raw_writel(TCR_BASE, &tmrptr->tcr); tcr 68 arch/mips/kernel/cevt-txx9.c __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); tcr 83 arch/mips/kernel/cevt-txx9.c __raw_writel(TCR_BASE, &tmrptr->tcr); tcr 100 arch/mips/kernel/cevt-txx9.c __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); tcr 148 arch/mips/kernel/cevt-txx9.c __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); tcr 216 arch/mips/kernel/cevt-txx9.c __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr); tcr 218 arch/mips/kernel/cevt-txx9.c __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); tcr 405 arch/mips/txx9/generic/setup.c __raw_writel(0, &tmrptr->tcr); tcr 410 arch/mips/txx9/generic/setup.c &tmrptr->tcr); tcr 620 arch/powerpc/include/asm/kvm_host.h u32 tcr; tcr 91 arch/powerpc/include/asm/mpc52xx.h u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */ tcr 562 arch/powerpc/include/asm/reg_booke.h #define TCR_GET_WP(tcr) ((((tcr) & 0xC0000000) >> 30) | \ tcr 563 arch/powerpc/include/asm/reg_booke.h (((tcr) & 0x1E0000) >> 15)) tcr 565 arch/powerpc/include/asm/reg_booke.h #define TCR_GET_WP(tcr) (((tcr) & 0xC0000000) >> 30) tcr 226 arch/powerpc/include/uapi/asm/kvm.h __u32 tcr; tcr 768 arch/powerpc/kernel/time.c unsigned int tcr; tcr 773 arch/powerpc/kernel/time.c tcr = mfspr(SPRN_TCR); tcr 778 arch/powerpc/kernel/time.c tcr &= TCR_WP_MASK; /* Clear all bits except for TCR[WP] */ tcr 779 arch/powerpc/kernel/time.c tcr |= TCR_DIE; /* Enable decrementer */ tcr 780 arch/powerpc/kernel/time.c mtspr(SPRN_TCR, tcr); tcr 554 arch/powerpc/kvm/booke.c u32 period = TCR_GET_WP(vcpu->arch.tcr); tcr 632 arch/powerpc/kvm/booke.c if (final && (vcpu->arch.tcr & TCR_WRC_MASK) && tcr 651 arch/powerpc/kvm/booke.c if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS)) tcr 656 arch/powerpc/kvm/booke.c if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS)) tcr 1504 arch/powerpc/kvm/booke.c sregs->u.e.tcr = vcpu->arch.tcr; tcr 1522 arch/powerpc/kvm/booke.c kvmppc_set_tcr(vcpu, sregs->u.e.tcr); tcr 1690 arch/powerpc/kvm/booke.c *val = get_reg_val(id, vcpu->arch.tcr); tcr 1763 arch/powerpc/kvm/booke.c u32 tcr = set_reg_val(id, *val); tcr 1764 arch/powerpc/kvm/booke.c kvmppc_set_tcr(vcpu, tcr); tcr 1848 arch/powerpc/kvm/booke.c vcpu->arch.tcr = new_tcr; tcr 1877 arch/powerpc/kvm/booke.c if (vcpu->arch.tcr & TCR_ARE) { tcr 269 arch/powerpc/kvm/booke_emulate.c if (vcpu->arch.tcr & TCR_WRC_MASK) { tcr 271 arch/powerpc/kvm/booke_emulate.c spr_val |= vcpu->arch.tcr & TCR_WRC_MASK; tcr 446 arch/powerpc/kvm/booke_emulate.c *spr_val = vcpu->arch.tcr; tcr 28 arch/powerpc/platforms/4xx/gpio.c __be32 tcr; tcr 106 arch/powerpc/platforms/4xx/gpio.c clrbits32(®s->tcr, GPIO_MASK(gpio)); tcr 139 arch/powerpc/platforms/4xx/gpio.c setbits32(®s->tcr, GPIO_MASK(gpio)); tcr 182 arch/powerpc/platforms/52xx/lite5200_pm.c out_be16(&bes->tcr[i], sbes.tcr[i]); tcr 81 arch/powerpc/platforms/52xx/mpc52xx_pci.c u32 tcr; /* PCI + 0x6C */ tcr 318 arch/powerpc/platforms/52xx/mpc52xx_pci.c out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8); tcr 142 arch/powerpc/sysdev/mpic_timer.c u32 tcr; tcr 151 arch/powerpc/sysdev/mpic_timer.c tcr = casc_priv->tcr_value | tcr 153 arch/powerpc/sysdev/mpic_timer.c setbits32(priv->group_tcr, tcr); tcr 336 arch/powerpc/sysdev/mpic_timer.c u32 tcr; tcr 337 arch/powerpc/sysdev/mpic_timer.c tcr = casc_priv->tcr_value | (casc_priv->tcr_value << tcr 339 arch/powerpc/sysdev/mpic_timer.c clrbits32(priv->group_tcr, tcr); tcr 2142 drivers/atm/idt77252.c int tcr, tcra; tcr 2157 drivers/atm/idt77252.c tcr = atm_pcr_goal(&qos->txtp); tcr 2158 drivers/atm/idt77252.c tcra = tcr >= 0 ? tcr : -tcr; tcr 2166 drivers/atm/idt77252.c if (tcr > 0) { tcr 2169 drivers/atm/idt77252.c } else if (tcr == 0) { tcr 2212 drivers/atm/idt77252.c int tcr; tcr 2225 drivers/atm/idt77252.c tcr = atm_pcr_goal(&qos->txtp); tcr 2226 drivers/atm/idt77252.c if (tcr == 0) tcr 2227 drivers/atm/idt77252.c tcr = card->link_pcr; tcr 2229 drivers/atm/idt77252.c vc->estimator = idt77252_init_est(vc, tcr); tcr 2232 drivers/atm/idt77252.c vc->init_er = idt77252_rate_logindex(card, tcr); tcr 2234 drivers/atm/idt77252.c if (tcr < 0) tcr 1233 drivers/atm/nicstar.c int tcr, tcra; /* target cell rate, and absolute value */ tcr 1288 drivers/atm/nicstar.c tcr = atm_pcr_goal(&(vcc->qos.txtp)); tcr 1289 drivers/atm/nicstar.c tcra = tcr >= 0 ? tcr : -tcr; tcr 1300 drivers/atm/nicstar.c if (tcr > 0) { tcr 1303 drivers/atm/nicstar.c } else if (tcr == 0) { tcr 88 drivers/clocksource/timer-davinci.c unsigned int tcr; tcr 90 drivers/clocksource/timer-davinci.c tcr = DAVINCI_TIMER_ENAMODE_DISABLED << tcr 97 drivers/clocksource/timer-davinci.c tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC << tcr 100 drivers/clocksource/timer-davinci.c writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); tcr 105 drivers/clocksource/timer-davinci.c unsigned int tcr; tcr 107 drivers/clocksource/timer-davinci.c tcr = DAVINCI_TIMER_ENAMODE_ONESHOT << tcr 110 drivers/clocksource/timer-davinci.c tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC << tcr 113 drivers/clocksource/timer-davinci.c writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); tcr 199 drivers/clocksource/timer-davinci.c int tcr; tcr 201 drivers/clocksource/timer-davinci.c tcr = DAVINCI_TIMER_ENAMODE_PERIODIC << tcr 203 drivers/clocksource/timer-davinci.c tcr |= DAVINCI_TIMER_ENAMODE_ONESHOT << tcr 208 drivers/clocksource/timer-davinci.c writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); tcr 218 drivers/clocksource/timer-davinci.c unsigned int tcr; tcr 220 drivers/clocksource/timer-davinci.c tcr = DAVINCI_TIMER_ENAMODE_PERIODIC << tcr 225 drivers/clocksource/timer-davinci.c writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); tcr 76 drivers/clocksource/timer-keystone.c u32 tcr; tcr 79 drivers/clocksource/timer-keystone.c tcr = keystone_timer_readl(TCR); tcr 80 drivers/clocksource/timer-keystone.c off = tcr & ~(TCR_ENAMODE_MASK); tcr 83 drivers/clocksource/timer-keystone.c tcr |= mask; tcr 102 drivers/clocksource/timer-keystone.c keystone_timer_writel(tcr, TCR); tcr 108 drivers/clocksource/timer-keystone.c u32 tcr; tcr 110 drivers/clocksource/timer-keystone.c tcr = keystone_timer_readl(TCR); tcr 113 drivers/clocksource/timer-keystone.c tcr &= ~(TCR_ENAMODE_MASK); tcr 114 drivers/clocksource/timer-keystone.c keystone_timer_writel(tcr, TCR); tcr 84 drivers/dma/bestcomm/ata.c offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); tcr 316 drivers/dma/bestcomm/bestcomm.c out_be16(&bcom_eng->regs->tcr[task], 0); tcr 350 drivers/dma/bestcomm/bestcomm.c out_be16(&bcom_eng->regs->tcr[task], 0); tcr 128 drivers/dma/bestcomm/fec.c offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); tcr 229 drivers/dma/bestcomm/fec.c offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); tcr 131 drivers/dma/bestcomm/gen_bd.c offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); tcr 215 drivers/dma/bestcomm/gen_bd.c offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); tcr 51 drivers/dma/sh/rcar-dmac.c u32 tcr; tcr 736 drivers/dma/sh/rcar-dmac.c hwdesc->tcr = chunk->size >> desc->xfer_shift; tcr 47 drivers/dma/sh/shdma.h u32 tcr; /* TCR / transfer count */ tcr 219 drivers/dma/sh/shdmac.c sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); tcr 291 drivers/dma/sh/shdmac.c sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); tcr 389 drivers/dma/sh/shdmac.c sh_desc->hw.tcr = *len; tcr 422 drivers/dma/sh/shdmac.c return sh_desc->hw.tcr - tcr 464 drivers/dma/sh/shdmac.c (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) || tcr 466 drivers/dma/sh/shdmac.c (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf); tcr 296 drivers/iommu/arm-smmu-v3.c #define ARM_SMMU_TCR2CD(tcr, fld) FIELD_PREP(CTXDESC_CD_0_TCR_##fld, \ tcr 297 drivers/iommu/arm-smmu-v3.c FIELD_GET(ARM64_TCR_##fld, tcr)) tcr 557 drivers/iommu/arm-smmu-v3.c u64 tcr; tcr 1447 drivers/iommu/arm-smmu-v3.c static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) tcr 1452 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, T0SZ); tcr 1453 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, TG0); tcr 1454 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, IRGN0); tcr 1455 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, ORGN0); tcr 1456 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, SH0); tcr 1457 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, EPD0); tcr 1458 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, EPD1); tcr 1459 drivers/iommu/arm-smmu-v3.c val |= ARM_SMMU_TCR2CD(tcr, IPS); tcr 1473 drivers/iommu/arm-smmu-v3.c val = arm_smmu_cpu_tcr_to_cd(cfg->cd.tcr) | tcr 2176 drivers/iommu/arm-smmu-v3.c cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; tcr 95 drivers/iommu/arm-smmu.c u32 tcr[2]; tcr 506 drivers/iommu/arm-smmu.c cb->tcr[0] = pgtbl_cfg->arm_v7s_cfg.tcr; tcr 508 drivers/iommu/arm-smmu.c cb->tcr[0] = pgtbl_cfg->arm_lpae_s1_cfg.tcr; tcr 509 drivers/iommu/arm-smmu.c cb->tcr[1] = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; tcr 510 drivers/iommu/arm-smmu.c cb->tcr[1] |= FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM); tcr 512 drivers/iommu/arm-smmu.c cb->tcr[1] |= TCR2_AS; tcr 515 drivers/iommu/arm-smmu.c cb->tcr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; tcr 597 drivers/iommu/arm-smmu.c arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); tcr 598 drivers/iommu/arm-smmu.c arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); tcr 802 drivers/iommu/io-pgtable-arm-v7s.c cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1; tcr 855 drivers/iommu/io-pgtable-arm.c cfg->arm_lpae_s1_cfg.tcr = reg; tcr 995 drivers/iommu/io-pgtable-arm.c cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE; tcr 996 drivers/iommu/io-pgtable-arm.c cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff; tcr 281 drivers/iommu/msm_iommu.c SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); tcr 280 drivers/iommu/qcom_iommu.c (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | tcr 283 drivers/iommu/qcom_iommu.c pgtbl_cfg.arm_lpae_s1_cfg.tcr); tcr 82 drivers/net/can/rcar/rcar_can.c u8 tcr; /* Test Control Register */ tcr 419 drivers/net/ethernet/natsemi/sonic.c u16 tcr = SONIC_READ(SONIC_TCR); tcr 422 drivers/net/ethernet/natsemi/sonic.c __func__, tcr); tcr 424 drivers/net/ethernet/natsemi/sonic.c if (tcr & (SONIC_TCR_EXD | SONIC_TCR_EXC | tcr 630 drivers/net/usb/rtl8150.c u8 cr, tcr, rcr, msr; tcr 637 drivers/net/usb/rtl8150.c tcr = 0xd8; tcr 642 drivers/net/usb/rtl8150.c set_registers(dev, TCR, 1, &tcr); tcr 215 drivers/staging/vt6655/desc.h volatile u8 tcr; tcr 910 drivers/staging/vt6655/device_main.c if (desc->td1.tcr & TCR_STP) { tcr 1169 drivers/staging/vt6655/device_main.c head_td->td1.tcr = 0; tcr 1187 drivers/staging/vt6655/device_main.c head_td->td1.tcr |= (TCR_STP | TCR_EDP | EDMSDU); tcr 812 drivers/tty/serial/dz.c unsigned short csr, tcr, trdy, mask; tcr 818 drivers/tty/serial/dz.c tcr = dz_in(dport, DZ_TCR); tcr 819 drivers/tty/serial/dz.c tcr |= 1 << dport->port.line; tcr 820 drivers/tty/serial/dz.c mask = tcr; tcr 841 drivers/tty/serial/dz.c dz_out(dport, DZ_TCR, tcr); tcr 18 drivers/tty/serial/sunsab.h u8 tcr; /* Termination Character Register */ tcr 49 drivers/tty/serial/sunsab.h u8 tcr; tcr 85 drivers/tty/serial/sunsab.h u8 tcr; tcr 4460 drivers/tty/synclink_gt.c unsigned short tcr; tcr 4465 drivers/tty/synclink_gt.c tcr = rd_reg16(info, TCR); tcr 4468 drivers/tty/synclink_gt.c tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; tcr 4471 drivers/tty/synclink_gt.c } else if (!(tcr & BIT6)) { tcr 4473 drivers/tty/synclink_gt.c tcr &= ~(BIT5 + BIT4); tcr 4475 drivers/tty/synclink_gt.c wr_reg16(info, TCR, tcr); tcr 58 drivers/watchdog/txx9wdt.c &txx9wdt_reg->tcr); tcr 68 drivers/watchdog/txx9wdt.c __raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE, tcr 69 drivers/watchdog/txx9wdt.c &txx9wdt_reg->tcr); tcr 264 include/linux/fsl/bestcomm/bestcomm_priv.h reg = in_be16(&bcom_eng->regs->tcr[task]); tcr 265 include/linux/fsl/bestcomm/bestcomm_priv.h out_be16(&bcom_eng->regs->tcr[task], reg | TASK_ENABLE); tcr 271 include/linux/fsl/bestcomm/bestcomm_priv.h u16 reg = in_be16(&bcom_eng->regs->tcr[task]); tcr 272 include/linux/fsl/bestcomm/bestcomm_priv.h out_be16(&bcom_eng->regs->tcr[task], reg & ~TASK_ENABLE); tcr 337 include/linux/fsl/bestcomm/bestcomm_priv.h u16 __iomem *tcr = &bcom_eng->regs->tcr[task]; tcr 338 include/linux/fsl/bestcomm/bestcomm_priv.h out_be16(tcr, (in_be16(tcr) & ~0xff) | 0x00c0 | next_task); tcr 344 include/linux/fsl/bestcomm/bestcomm_priv.h u16 __iomem *tcr = &bcom_eng->regs->tcr[task]; tcr 345 include/linux/fsl/bestcomm/bestcomm_priv.h out_be16(tcr, (in_be16(tcr) & ~0x1f00) | ((initiator & 0x1f) << 8)); tcr 104 include/linux/io-pgtable.h u64 tcr; tcr 115 include/linux/io-pgtable.h u32 tcr; tcr 226 tools/arch/powerpc/include/uapi/asm/kvm.h __u32 tcr;