tc_port 2780 drivers/gpu/drm/i915/display/intel_ddi.c enum tc_port tc_port = intel_port_to_tc(dev_priv, tc_port 2783 drivers/gpu/drm/i915/display/intel_ddi.c return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); tc_port 3000 drivers/gpu/drm/i915/display/intel_ddi.c enum tc_port tc_port = intel_port_to_tc(dev_priv, port); tc_port 3004 drivers/gpu/drm/i915/display/intel_ddi.c if (tc_port == PORT_TC_NONE) tc_port 3017 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_MISC_SUS0(tc_port)); tc_port 3025 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_MISC_SUS0(tc_port), val); tc_port 3032 drivers/gpu/drm/i915/display/intel_ddi.c enum tc_port tc_port = intel_port_to_tc(dev_priv, port); tc_port 3036 drivers/gpu/drm/i915/display/intel_ddi.c if (tc_port == PORT_TC_NONE) tc_port 3049 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_MISC_SUS0(tc_port)); tc_port 3057 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_MISC_SUS0(tc_port), val); tc_port 6714 drivers/gpu/drm/i915/display/intel_display.c enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) tc_port 454 drivers/gpu/drm/i915/display/intel_display.h enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, tc_port 2613 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id) tc_port 2618 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) tc_port 2620 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return tc_port + DPLL_ID_ICL_MGPLL1; tc_port 3047 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enum tc_port tc_port = icl_pll_id_to_tc_port(id); tc_port 3057 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_PLL_ENABLE(tc_port)); tc_port 3061 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port)); tc_port 3065 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port)); tc_port 3070 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port)); tc_port 3077 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port)); tc_port 3078 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port)); tc_port 3079 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port)); tc_port 3080 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port)); tc_port 3081 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port)); tc_port 3083 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port)); tc_port 3085 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); tc_port 3192 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); tc_port 3201 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_REFCLKIN_CTL(tc_port)); tc_port 3204 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_REFCLKIN_CTL(tc_port), val); tc_port 3206 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port)); tc_port 3209 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_CLKTOP2_CORECLKCTL1(tc_port), val); tc_port 3211 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port)); tc_port 3217 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_CLKTOP2_HSCLKCTL(tc_port), val); tc_port 3219 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); tc_port 3220 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); tc_port 3221 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_LF(tc_port), hw_state->mg_pll_lf); tc_port 3222 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock); tc_port 3223 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); tc_port 3225 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_PLL_BIAS(tc_port)); tc_port 3228 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_BIAS(tc_port), val); tc_port 3230 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); tc_port 3233 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_TDC_COLDST_BIAS(tc_port), val); tc_port 3235 drivers/gpu/drm/i915/display/intel_dpll_mgr.c POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); tc_port 379 drivers/gpu/drm/i915/display/intel_dpll_mgr.h enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); tc_port 36 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port) tc_port 45 drivers/gpu/drm/i915/display/intel_tc.c return tc_port / 2; tc_port 51 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); tc_port 60 drivers/gpu/drm/i915/display/intel_tc.c return (lane_mask & DP_LANE_ASSIGNMENT_MASK(tc_port)) >> tc_port 61 drivers/gpu/drm/i915/display/intel_tc.c DP_LANE_ASSIGNMENT_SHIFT(tc_port); tc_port 98 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); tc_port 107 drivers/gpu/drm/i915/display/intel_tc.c val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port); tc_port 111 drivers/gpu/drm/i915/display/intel_tc.c val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) : tc_port 112 drivers/gpu/drm/i915/display/intel_tc.c DFLEXDPMLE1_DPMLETC_ML0(tc_port); tc_port 115 drivers/gpu/drm/i915/display/intel_tc.c val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) : tc_port 116 drivers/gpu/drm/i915/display/intel_tc.c DFLEXDPMLE1_DPMLETC_ML1_0(tc_port); tc_port 119 drivers/gpu/drm/i915/display/intel_tc.c val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port); tc_port 153 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); tc_port 167 drivers/gpu/drm/i915/display/intel_tc.c if (val & TC_LIVE_STATE_TBT(tc_port)) tc_port 169 drivers/gpu/drm/i915/display/intel_tc.c if (val & TC_LIVE_STATE_TC(tc_port)) tc_port 172 drivers/gpu/drm/i915/display/intel_tc.c if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)) tc_port 185 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); tc_port 197 drivers/gpu/drm/i915/display/intel_tc.c return val & DP_PHY_MODE_STATUS_COMPLETED(tc_port); tc_port 204 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); tc_port 218 drivers/gpu/drm/i915/display/intel_tc.c val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port); tc_port 220 drivers/gpu/drm/i915/display/intel_tc.c val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port); tc_port 235 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); tc_port 247 drivers/gpu/drm/i915/display/intel_tc.c return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)); tc_port 532 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, port); tc_port 534 drivers/gpu/drm/i915/display/intel_tc.c if (WARN_ON(tc_port == PORT_TC_NONE)) tc_port 538 drivers/gpu/drm/i915/display/intel_tc.c "%c/TC#%d", port_name(port), tc_port + 1); tc_port 543 drivers/gpu/drm/i915/display/intel_tc.c dig_port->tc_phy_fia = tc_port_to_fia(i915, tc_port); tc_port 2149 drivers/gpu/drm/i915/i915_reg.h #define MG_MISC_SUS0(tc_port) \ tc_port 2150 drivers/gpu/drm/i915/i915_reg.h _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2)) tc_port 2176 drivers/gpu/drm/i915/i915_reg.h #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port))) tc_port 2177 drivers/gpu/drm/i915/i915_reg.h #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port))) tc_port 2178 drivers/gpu/drm/i915/i915_reg.h #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port))) tc_port 2179 drivers/gpu/drm/i915/i915_reg.h #define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port))) tc_port 2180 drivers/gpu/drm/i915/i915_reg.h #define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port))) tc_port 2181 drivers/gpu/drm/i915/i915_reg.h #define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port))) tc_port 7431 drivers/gpu/drm/i915/i915_reg.h #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16)) tc_port 7444 drivers/gpu/drm/i915/i915_reg.h #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port)) tc_port 7454 drivers/gpu/drm/i915/i915_reg.h #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4) tc_port 7455 drivers/gpu/drm/i915/i915_reg.h #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4) tc_port 7456 drivers/gpu/drm/i915/i915_reg.h #define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) tc_port 7457 drivers/gpu/drm/i915/i915_reg.h #define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4) tc_port 7847 drivers/gpu/drm/i915/i915_reg.h #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24)) tc_port 7948 drivers/gpu/drm/i915/i915_reg.h #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) tc_port 8053 drivers/gpu/drm/i915/i915_reg.h #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) tc_port 8054 drivers/gpu/drm/i915/i915_reg.h #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) tc_port 9745 drivers/gpu/drm/i915/i915_reg.h #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ tc_port 9746 drivers/gpu/drm/i915/i915_reg.h (tc_port) + 12 : \ tc_port 9747 drivers/gpu/drm/i915/i915_reg.h (tc_port) - PORT_TC4 + 21)) tc_port 9768 drivers/gpu/drm/i915/i915_reg.h #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ tc_port 9777 drivers/gpu/drm/i915/i915_reg.h #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \ tc_port 9789 drivers/gpu/drm/i915/i915_reg.h #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \ tc_port 9809 drivers/gpu/drm/i915/i915_reg.h #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \ tc_port 9823 drivers/gpu/drm/i915/i915_reg.h #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \ tc_port 9838 drivers/gpu/drm/i915/i915_reg.h #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \ tc_port 9851 drivers/gpu/drm/i915/i915_reg.h #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \ tc_port 9864 drivers/gpu/drm/i915/i915_reg.h #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \ tc_port 9878 drivers/gpu/drm/i915/i915_reg.h #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \ tc_port 9898 drivers/gpu/drm/i915/i915_reg.h #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \ tc_port 9910 drivers/gpu/drm/i915/i915_reg.h #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \ tc_port 11546 drivers/gpu/drm/i915/i915_reg.h #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6)) tc_port 11547 drivers/gpu/drm/i915/i915_reg.h #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5)) tc_port 11548 drivers/gpu/drm/i915/i915_reg.h #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8) tc_port 11549 drivers/gpu/drm/i915/i915_reg.h #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8)) tc_port 11550 drivers/gpu/drm/i915/i915_reg.h #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8)) tc_port 11553 drivers/gpu/drm/i915/i915_reg.h #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port)) tc_port 11556 drivers/gpu/drm/i915/i915_reg.h #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))