t5 449 arch/arm64/include/asm/assembler.h .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req t5 45 arch/riscv/include/asm/ptrace.h unsigned long t5; t5 50 arch/riscv/include/uapi/asm/ptrace.h unsigned long t5; t5 104 arch/riscv/kernel/asm-offsets.c OFFSET(PT_T5, pt_regs, t5); t5 59 arch/riscv/kernel/process.c regs->t5, regs->t6); t5 952 crypto/ecc.c u64 t5[ECC_MAX_DIGITS]; t5 960 crypto/ecc.c vli_mod_mult_fast(t5, x1, t4, curve_prime, ndigits); t5 994 crypto/ecc.c vli_mod_sub(z1, z1, t5, curve_prime, ndigits); t5 996 crypto/ecc.c vli_mod_sub(z1, z1, t5, curve_prime, ndigits); t5 998 crypto/ecc.c vli_mod_sub(t5, t5, z1, curve_prime, ndigits); t5 1000 crypto/ecc.c vli_mod_mult_fast(x1, x1, t5, curve_prime, ndigits); t5 1052 crypto/ecc.c u64 t5[ECC_MAX_DIGITS]; t5 1055 crypto/ecc.c vli_mod_sub(t5, x2, x1, curve_prime, ndigits); t5 1057 crypto/ecc.c vli_mod_square_fast(t5, t5, curve_prime, ndigits); t5 1059 crypto/ecc.c vli_mod_mult_fast(x1, x1, t5, curve_prime, ndigits); t5 1061 crypto/ecc.c vli_mod_mult_fast(x2, x2, t5, curve_prime, ndigits); t5 1065 crypto/ecc.c vli_mod_square_fast(t5, y2, curve_prime, ndigits); t5 1068 crypto/ecc.c vli_mod_sub(t5, t5, x1, curve_prime, ndigits); t5 1070 crypto/ecc.c vli_mod_sub(t5, t5, x2, curve_prime, ndigits); t5 1076 crypto/ecc.c vli_mod_sub(x2, x1, t5, curve_prime, ndigits); t5 1082 crypto/ecc.c vli_set(x2, t5, ndigits); t5 1093 crypto/ecc.c u64 t5[ECC_MAX_DIGITS]; t5 1098 crypto/ecc.c vli_mod_sub(t5, x2, x1, curve_prime, ndigits); t5 1100 crypto/ecc.c vli_mod_square_fast(t5, t5, curve_prime, ndigits); t5 1102 crypto/ecc.c vli_mod_mult_fast(x1, x1, t5, curve_prime, ndigits); t5 1104 crypto/ecc.c vli_mod_mult_fast(x2, x2, t5, curve_prime, ndigits); t5 1106 crypto/ecc.c vli_mod_add(t5, y2, y1, curve_prime, ndigits); t5 1129 crypto/ecc.c vli_mod_square_fast(t7, t5, curve_prime, ndigits); t5 1135 crypto/ecc.c vli_mod_mult_fast(t6, t6, t5, curve_prime, ndigits); t5 56 drivers/gpu/drm/i915/display/intel_lvds.c int t5; t5 164 drivers/gpu/drm/i915/display/intel_lvds.c pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); t5 184 drivers/gpu/drm/i915/display/intel_lvds.c pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { t5 189 drivers/gpu/drm/i915/display/intel_lvds.c pps->t5 = 200 * 10; t5 197 drivers/gpu/drm/i915/display/intel_lvds.c pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, t5 215 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); t5 65 lib/crc32.c t5[(q >> 16) & 255] ^ t4[(q >> 24) & 255]) t5 70 lib/crc32.c # define DO_CRC8 (t4[(q) & 255] ^ t5[(q >> 8) & 255] ^ \ t5 80 lib/crc32.c const u32 *t4 = tab[4], *t5 = tab[5], *t6 = tab[6], *t7 = tab[7];