t10              2094 drivers/gpu/drm/gma500/cdv_intel_dp.c                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
t10              2101 drivers/gpu/drm/gma500/cdv_intel_dp.c                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
t10              2107 drivers/gpu/drm/gma500/cdv_intel_dp.c                 intel_dp->panel_power_down_delay = cur.t10 / 10;
t10                84 drivers/gpu/drm/gma500/intel_bios.c 				dev_priv->edp.pps.t9, dev_priv->edp.pps.t10,
t10               448 drivers/gpu/drm/gma500/intel_bios.h 	u16 t10;
t10                52 drivers/gpu/drm/i915/display/intel_bios.h 	u16 t10;
t10              6399 drivers/gpu/drm/i915/display/intel_dp.c 	seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
t10              6417 drivers/gpu/drm/i915/display/intel_dp.c 		      seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
t10              6429 drivers/gpu/drm/i915/display/intel_dp.c 	    hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
t10              6475 drivers/gpu/drm/i915/display/intel_dp.c 	spec.t10 = 500 * 10;
t10              6492 drivers/gpu/drm/i915/display/intel_dp.c 	assign_final(t10);
t10              6500 drivers/gpu/drm/i915/display/intel_dp.c 	intel_dp->panel_power_down_delay = get_delay(t10);
t10              6571 drivers/gpu/drm/i915/display/intel_dp.c 		REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
t10               643 drivers/gpu/drm/qxl/qxl_dev.h 	uint32_t	t10;