sst_dsp_shim_update_bits 218 sound/soc/intel/common/sst-dsp.c EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits); sst_dsp_shim_update_bits 220 sound/soc/intel/common/sst-dsp.h int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset, sst_dsp_shim_update_bits 377 sound/soc/intel/haswell/sst-haswell-dsp.c sst_dsp_shim_update_bits(sst, SST_HMDC, sst_dsp_shim_update_bits 382 sound/soc/intel/haswell/sst-haswell-dsp.c sst_dsp_shim_update_bits(sst, SST_IMRX, (SST_IMRX_BUSY | SST_IMRX_DONE), sst_dsp_shim_update_bits 384 sound/soc/intel/haswell/sst-haswell-dsp.c sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY | sst_dsp_shim_update_bits 399 sound/soc/intel/haswell/sst-haswell-dsp.c sst_dsp_shim_update_bits(sst, SST_HMDC, sst_dsp_shim_update_bits 409 sound/soc/intel/haswell/sst-haswell-dsp.c sst_dsp_shim_update_bits(sst, SST_CSR, sst_dsp_shim_update_bits 419 sound/soc/intel/haswell/sst-haswell-dsp.c sst_dsp_shim_update_bits(sst, SST_CSR, sst_dsp_shim_update_bits 504 sound/soc/intel/haswell/sst-haswell-ipc.c sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD, sst_dsp_shim_update_bits 508 sound/soc/intel/haswell/sst-haswell-ipc.c sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0); sst_dsp_shim_update_bits 1515 sound/soc/intel/haswell/sst-haswell-ipc.c sst_dsp_shim_update_bits(sst, SST_HMDC, sst_dsp_shim_update_bits 222 sound/soc/intel/skylake/cnl-sst-dsp.c sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_ADSPIC, sst_dsp_shim_update_bits 235 sound/soc/intel/skylake/cnl-sst-dsp.c sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 240 sound/soc/intel/skylake/cnl-sst-dsp.c sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 248 sound/soc/intel/skylake/cnl-sst-dsp.c sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 252 sound/soc/intel/skylake/cnl-sst-dsp.c sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 311 sound/soc/intel/skylake/cnl-sst.c sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 321 sound/soc/intel/skylake/cnl-sst.c sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 59 sound/soc/intel/skylake/skl-sst-cldma.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, sst_dsp_shim_update_bits 61 sound/soc/intel/skylake/skl-sst-cldma.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, sst_dsp_shim_update_bits 63 sound/soc/intel/skylake/skl-sst-cldma.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, sst_dsp_shim_update_bits 65 sound/soc/intel/skylake/skl-sst-cldma.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, sst_dsp_shim_update_bits 118 sound/soc/intel/skylake/skl-sst-cldma.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, sst_dsp_shim_update_bits 120 sound/soc/intel/skylake/skl-sst-cldma.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, sst_dsp_shim_update_bits 122 sound/soc/intel/skylake/skl-sst-cldma.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, sst_dsp_shim_update_bits 124 sound/soc/intel/skylake/skl-sst-cldma.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, sst_dsp_shim_update_bits 511 sound/soc/intel/skylake/skl-sst-ipc.c sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 521 sound/soc/intel/skylake/skl-sst-ipc.c sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 560 sound/soc/intel/skylake/skl-sst-ipc.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_ADSPIC, sst_dsp_shim_update_bits 573 sound/soc/intel/skylake/skl-sst-ipc.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 577 sound/soc/intel/skylake/skl-sst-ipc.c sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 625 sound/soc/intel/skylake/skl-sst-ipc.c sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL, sst_dsp_shim_update_bits 629 sound/soc/intel/skylake/skl-sst-ipc.c sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,