spu_mfc_sr1_set   586 arch/powerpc/platforms/cell/spu_base.c 	spu_mfc_sr1_set(spu, 0x33);
spu_mfc_sr1_set   708 arch/powerpc/platforms/cell/spu_base.c 		spu_mfc_sr1_set(spu, tmp);
spu_mfc_sr1_set   232 arch/powerpc/platforms/cell/spufs/hw_ops.c 	spu_mfc_sr1_set(spu, sr1);
spu_mfc_sr1_set   243 arch/powerpc/platforms/cell/spufs/hw_ops.c 	spu_mfc_sr1_set(spu, sr1);
spu_mfc_sr1_set   127 arch/powerpc/platforms/cell/spufs/run.c 	spu_mfc_sr1_set(ctx->spu, sr1);
spu_mfc_sr1_set   170 arch/powerpc/platforms/cell/spufs/run.c 	spu_mfc_sr1_set(ctx->spu, sr1);
spu_mfc_sr1_set   496 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
spu_mfc_sr1_set  1042 arch/powerpc/platforms/cell/spufs/switch.c 			spu_mfc_sr1_set(spu,
spu_mfc_sr1_set  1054 arch/powerpc/platforms/cell/spufs/switch.c 			spu_mfc_sr1_set(spu,
spu_mfc_sr1_set  1694 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
spu_mfc_sr1_set  1884 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
spu_mfc_sr1_set  3988 arch/powerpc/xmon/xmon.c 			spu_mfc_sr1_set(spu, tmp);
spu_mfc_sr1_set  4026 arch/powerpc/xmon/xmon.c 			spu_mfc_sr1_set(spu, spu_info[i].saved_mfc_sr1_RW);