spu_mfc_sr1_get    72 arch/powerpc/platforms/cell/spu_base.c 	if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)
spu_mfc_sr1_get   704 arch/powerpc/platforms/cell/spu_base.c 		tmp = spu_mfc_sr1_get(spu);
spu_mfc_sr1_get   231 arch/powerpc/platforms/cell/spufs/hw_ops.c 	sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
spu_mfc_sr1_get   242 arch/powerpc/platforms/cell/spufs/hw_ops.c 	sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
spu_mfc_sr1_get   125 arch/powerpc/platforms/cell/spufs/run.c 	sr1 = spu_mfc_sr1_get(ctx->spu);
spu_mfc_sr1_get   217 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
spu_mfc_sr1_get  3984 arch/powerpc/xmon/xmon.c 			tmp = spu_mfc_sr1_get(spu);