spu_int_stat_clear  297 arch/powerpc/platforms/cell/spu_base.c 	spu_int_stat_clear(spu, 0, stat);
spu_int_stat_clear  319 arch/powerpc/platforms/cell/spu_base.c 	spu_int_stat_clear(spu, 1, stat);
spu_int_stat_clear  364 arch/powerpc/platforms/cell/spu_base.c 	spu_int_stat_clear(spu, 2, stat);
spu_int_stat_clear   64 arch/powerpc/platforms/cell/spufs/hw_ops.c 			spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);
spu_int_stat_clear   72 arch/powerpc/platforms/cell/spufs/hw_ops.c 			spu_int_stat_clear(spu, 2,
spu_int_stat_clear  755 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
spu_int_stat_clear  756 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
spu_int_stat_clear  757 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
spu_int_stat_clear  914 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
spu_int_stat_clear  915 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
spu_int_stat_clear  933 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
spu_int_stat_clear  934 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
spu_int_stat_clear 1410 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
spu_int_stat_clear 1411 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
spu_int_stat_clear 1412 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
spu_int_stat_clear 1684 arch/powerpc/platforms/cell/spufs/switch.c 		spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);