spll 70 drivers/clk/imx/clk-imx31.c clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); spll 733 drivers/clk/microchip/clk-core.c struct pic32_sys_pll *spll; spll 736 drivers/clk/microchip/clk-core.c spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL); spll 737 drivers/clk/microchip/clk-core.c if (!spll) spll 740 drivers/clk/microchip/clk-core.c spll->core = core; spll 741 drivers/clk/microchip/clk-core.c spll->hw.init = &data->init_data; spll 742 drivers/clk/microchip/clk-core.c spll->ctrl_reg = data->ctrl_reg + core->iobase; spll 743 drivers/clk/microchip/clk-core.c spll->status_reg = data->status_reg + core->iobase; spll 744 drivers/clk/microchip/clk-core.c spll->lock_mask = data->lock_mask; spll 747 drivers/clk/microchip/clk-core.c spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK; spll 748 drivers/clk/microchip/clk-core.c spll->idiv += 1; spll 750 drivers/clk/microchip/clk-core.c clk = devm_clk_register(core->dev, &spll->hw); spll 1456 drivers/clk/samsung/clk-exynos5420.c [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, spll 316 drivers/gpu/drm/amd/amdgpu/amdgpu.h struct amdgpu_pll spll; spll 570 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c struct amdgpu_pll *spll = &adev->clock.spll; spll 616 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->reference_freq = spll 618 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->reference_div = 0; spll 620 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->pll_out_min = spll 622 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->pll_out_max = spll 626 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if (spll->pll_out_min == 0) spll 627 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->pll_out_min = 64800; spll 629 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->pll_in_min = spll 631 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->pll_in_max = spll 634 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->min_post_div = 1; spll 635 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->max_post_div = 1; spll 636 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->min_ref_div = 2; spll 637 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->max_ref_div = 0xff; spll 638 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->min_feedback_div = 4; spll 639 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->max_feedback_div = 0xff; spll 640 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c spll->best_vco = 0; spll 346 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c struct amdgpu_pll *spll = &adev->clock.spll; spll 384 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); spll 386 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c spll->reference_div = 0; spll 387 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c spll->min_post_div = 1; spll 388 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c spll->max_post_div = 1; spll 389 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c spll->min_ref_div = 2; spll 390 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c spll->max_ref_div = 0xff; spll 391 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c spll->min_feedback_div = 4; spll 392 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c spll->max_feedback_div = 0xff; spll 393 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c spll->best_vco = 0; spll 843 drivers/gpu/drm/amd/amdgpu/cik.c u32 reference_clock = adev->clock.spll.reference_freq; spll 127 drivers/gpu/drm/amd/amdgpu/nv.c return adev->clock.spll.reference_freq; spll 1216 drivers/gpu/drm/amd/amdgpu/si.c u32 reference_clock = adev->clock.spll.reference_freq; spll 5258 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 reference_clock = adev->clock.spll.reference_freq; spll 277 drivers/gpu/drm/amd/amdgpu/soc15.c u32 reference_clock = adev->clock.spll.reference_freq; spll 329 drivers/gpu/drm/amd/amdgpu/vi.c u32 reference_clock = adev->clock.spll.reference_freq; spll 12800 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.spll); spll 514 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); spll 589 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->spll = val; spll 890 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.spll = spll 915 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->wrpll, hw_state->spll); spll 177 drivers/gpu/drm/i915/display/intel_dpll_mgr.h u32 spll; spll 36 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c u32 spll; spll 175 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; spll 178 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c clk->spll = 0x00000000; spll 193 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); spll 474 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); spll 481 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, spll[0], 0xc03f0100, spll 483 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); spll 1990 drivers/gpu/drm/radeon/ci_dpm.c u32 ref_clock = rdev->clock.spll.reference_freq; spll 3010 drivers/gpu/drm/radeon/ci_dpm.c table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; spll 3169 drivers/gpu/drm/radeon/ci_dpm.c u32 reference_clock = rdev->clock.spll.reference_freq; spll 1720 drivers/gpu/drm/radeon/cik.c u32 reference_clock = rdev->clock.spll.reference_freq; spll 2012 drivers/gpu/drm/radeon/ni_dpm.c u32 reference_clock = rdev->clock.spll.reference_freq; spll 200 drivers/gpu/drm/radeon/r600.c return rdev->clock.spll.reference_freq; spll 227 drivers/gpu/drm/radeon/r600.c if (rdev->clock.spll.reference_freq == 10000) spll 267 drivers/gpu/drm/radeon/radeon.h struct radeon_pll spll; spll 1148 drivers/gpu/drm/radeon/radeon_atombios.c struct radeon_pll *spll = &rdev->clock.spll; spll 1201 drivers/gpu/drm/radeon/radeon_atombios.c spll->reference_freq = spll 1204 drivers/gpu/drm/radeon/radeon_atombios.c spll->reference_freq = spll 1206 drivers/gpu/drm/radeon/radeon_atombios.c spll->reference_div = 0; spll 1208 drivers/gpu/drm/radeon/radeon_atombios.c spll->pll_out_min = spll 1210 drivers/gpu/drm/radeon/radeon_atombios.c spll->pll_out_max = spll 1214 drivers/gpu/drm/radeon/radeon_atombios.c if (spll->pll_out_min == 0) { spll 1216 drivers/gpu/drm/radeon/radeon_atombios.c spll->pll_out_min = 64800; spll 1218 drivers/gpu/drm/radeon/radeon_atombios.c spll->pll_out_min = 20000; spll 1221 drivers/gpu/drm/radeon/radeon_atombios.c spll->pll_in_min = spll 1223 drivers/gpu/drm/radeon/radeon_atombios.c spll->pll_in_max = spll 41 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *spll = &rdev->clock.spll; spll 47 drivers/gpu/drm/radeon/radeon_clocks.c fb_div *= spll->reference_freq; spll 110 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *spll = &rdev->clock.spll; spll 149 drivers/gpu/drm/radeon/radeon_clocks.c spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; spll 150 drivers/gpu/drm/radeon/radeon_clocks.c spll->reference_div = mpll->reference_div = spll 185 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *spll = &rdev->clock.spll; spll 213 drivers/gpu/drm/radeon/radeon_clocks.c if (spll->reference_div < 2) spll 214 drivers/gpu/drm/radeon/radeon_clocks.c spll->reference_div = spll 219 drivers/gpu/drm/radeon/radeon_clocks.c mpll->reference_div = spll->reference_div; spll 232 drivers/gpu/drm/radeon/radeon_clocks.c spll->reference_freq = 1432; spll 237 drivers/gpu/drm/radeon/radeon_clocks.c spll->reference_freq = 2700; spll 266 drivers/gpu/drm/radeon/radeon_clocks.c spll->reference_div = spll 269 drivers/gpu/drm/radeon/radeon_clocks.c mpll->reference_div = spll->reference_div; spll 322 drivers/gpu/drm/radeon/radeon_clocks.c spll->min_post_div = 1; spll 323 drivers/gpu/drm/radeon/radeon_clocks.c spll->max_post_div = 1; spll 324 drivers/gpu/drm/radeon/radeon_clocks.c spll->min_ref_div = 2; spll 325 drivers/gpu/drm/radeon/radeon_clocks.c spll->max_ref_div = 0xff; spll 326 drivers/gpu/drm/radeon/radeon_clocks.c spll->min_feedback_div = 4; spll 327 drivers/gpu/drm/radeon/radeon_clocks.c spll->max_feedback_div = 0xff; spll 328 drivers/gpu/drm/radeon/radeon_clocks.c spll->best_vco = 0; spll 354 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *spll = &rdev->clock.spll; spll 355 drivers/gpu/drm/radeon/radeon_clocks.c int ref_div = spll->reference_div; spll 375 drivers/gpu/drm/radeon/radeon_clocks.c req_clock += spll->reference_freq; spll 376 drivers/gpu/drm/radeon/radeon_clocks.c req_clock /= (2 * spll->reference_freq); spll 381 drivers/gpu/drm/radeon/radeon_clocks.c req_clock *= spll->reference_freq; spll 738 drivers/gpu/drm/radeon/radeon_combios.c struct radeon_pll *spll = &rdev->clock.spll; spll 765 drivers/gpu/drm/radeon/radeon_combios.c spll->reference_freq = RBIOS16(pll_info + 0x1a); spll 766 drivers/gpu/drm/radeon/radeon_combios.c spll->reference_div = RBIOS16(pll_info + 0x1c); spll 767 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_out_min = RBIOS32(pll_info + 0x1e); spll 768 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_out_max = RBIOS32(pll_info + 0x22); spll 771 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_in_min = RBIOS32(pll_info + 0x48); spll 772 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_in_max = RBIOS32(pll_info + 0x4c); spll 775 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_in_min = 40; spll 776 drivers/gpu/drm/radeon/radeon_combios.c spll->pll_in_max = 500; spll 340 drivers/gpu/drm/radeon/radeon_kms.c *value = rdev->clock.spll.reference_freq * 10; spll 969 drivers/gpu/drm/radeon/radeon_uvd.c unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; spll 993 drivers/gpu/drm/radeon/rs780_dpm.c u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / spll 1015 drivers/gpu/drm/radeon/rs780_dpm.c u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / spll 163 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 ref_clk = rdev->clock.spll.reference_freq; spll 428 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 ref_clk = rdev->clock.spll.reference_freq; spll 551 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 ref_clk = rdev->clock.spll.reference_freq; spll 840 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 ref_clk = rdev->clock.spll.reference_freq; spll 51 drivers/gpu/drm/radeon/rv730_dpm.c u32 reference_clock = rdev->clock.spll.reference_freq; spll 131 drivers/gpu/drm/radeon/rv740_dpm.c u32 reference_clock = rdev->clock.spll.reference_freq; spll 796 drivers/gpu/drm/radeon/rv770.c u32 reference_clock = rdev->clock.spll.reference_freq; spll 500 drivers/gpu/drm/radeon/rv770_dpm.c u32 reference_clock = rdev->clock.spll.reference_freq; spll 1345 drivers/gpu/drm/radeon/si.c u32 reference_clock = rdev->clock.spll.reference_freq; spll 4796 drivers/gpu/drm/radeon/si_dpm.c u32 reference_clock = rdev->clock.spll.reference_freq;