soc_readl         109 arch/c6x/platforms/cache.c #define imcr_get(reg) soc_readl(cache_base + (reg))
soc_readl         113 arch/c6x/platforms/cache.c 	soc_readl(cache_base + (reg));				\
soc_readl         227 arch/c6x/platforms/dscr.c 	val = soc_readl(dscr.base + ctl->reg);
soc_readl         246 arch/c6x/platforms/dscr.c 		val = soc_readl(dscr.base + stat->reg);
soc_readl         271 arch/c6x/platforms/dscr.c 	val = soc_readl(dscr.base + r->reg);
soc_readl         289 arch/c6x/platforms/dscr.c 		c6x_devstat = soc_readl(base + val);
soc_readl         301 arch/c6x/platforms/dscr.c 		c6x_silicon_rev = soc_readl(base + vals[0]);
soc_readl         336 arch/c6x/platforms/dscr.c 		fuse = soc_readl(base + vals[f * 5]);
soc_readl          72 arch/c6x/platforms/megamod-pic.c 	soc_writel(soc_readl(evtmask) | (1 << (src & 31)), evtmask);
soc_readl          83 arch/c6x/platforms/megamod-pic.c 	soc_writel(soc_readl(evtmask) & ~(1 << (src & 31)), evtmask);
soc_readl         106 arch/c6x/platforms/megamod-pic.c 	while ((events = soc_readl(&pic->regs->mevtflag[idx])) != 0) {
soc_readl         156 arch/c6x/platforms/megamod-pic.c 	val = soc_readl(&pic->regs->intmux[index]);
soc_readl         314 arch/c6x/platforms/megamod-pic.c 		mask = soc_readl(&mm_pic->regs->mexpflag[i]);
soc_readl         202 arch/c6x/platforms/pll.c 	return soc_readl(pll->base + reg);
soc_readl          66 arch/c6x/platforms/timer64.c 	((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
soc_readl          79 arch/c6x/platforms/timer64.c 	u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK;
soc_readl          96 arch/c6x/platforms/timer64.c 	soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
soc_readl         100 arch/c6x/platforms/timer64.c 	val = soc_readl(&timer->tcr);
soc_readl         104 arch/c6x/platforms/timer64.c 	val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
soc_readl         112 arch/c6x/platforms/timer64.c 	soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);