soc_info 594 arch/arm/mach-davinci/board-da830-evm.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 617 arch/arm/mach-davinci/board-da830-evm.c soc_info->emac_pdata->rmii_en = 1; soc_info 618 arch/arm/mach-davinci/board-da830-evm.c soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID; soc_info 365 arch/arm/mach-davinci/board-da850-evm.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 367 arch/arm/mach-davinci/board-da850-evm.c soc_info->emac_pdata->rmii_en = 1; soc_info 1103 arch/arm/mach-davinci/board-da850-evm.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 1104 arch/arm/mach-davinci/board-da850-evm.c u8 rmii_en = soc_info->emac_pdata->rmii_en; soc_info 1140 arch/arm/mach-davinci/board-da850-evm.c soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID; soc_info 738 arch/arm/mach-davinci/board-dm365-evm.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 746 arch/arm/mach-davinci/board-dm365-evm.c soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID; soc_info 830 arch/arm/mach-davinci/board-dm644x-evm.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 881 arch/arm/mach-davinci/board-dm644x-evm.c soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID; soc_info 828 arch/arm/mach-davinci/board-dm646x-evm.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 857 arch/arm/mach-davinci/board-dm646x-evm.c soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID; soc_info 525 arch/arm/mach-davinci/board-mityomapl138.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 527 arch/arm/mach-davinci/board-mityomapl138.c soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */ soc_info 532 arch/arm/mach-davinci/board-mityomapl138.c if (soc_info->emac_pdata->rmii_en) { soc_info 550 arch/arm/mach-davinci/board-mityomapl138.c soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID; soc_info 176 arch/arm/mach-davinci/board-neuros-osd2.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 210 arch/arm/mach-davinci/board-neuros-osd2.c soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; soc_info 53 arch/arm/mach-davinci/board-omapl138-hawk.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 67 arch/arm/mach-davinci/board-omapl138-hawk.c soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID; soc_info 121 arch/arm/mach-davinci/board-sffsdr.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 131 arch/arm/mach-davinci/board-sffsdr.c soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; soc_info 26 arch/arm/mach-davinci/common.c static int __init davinci_init_id(struct davinci_soc_info *soc_info) soc_info 34 arch/arm/mach-davinci/common.c base = ioremap(soc_info->jtag_id_reg, SZ_4K); soc_info 40 arch/arm/mach-davinci/common.c soc_info->jtag_id = __raw_readl(base); soc_info 43 arch/arm/mach-davinci/common.c variant = (soc_info->jtag_id & 0xf0000000) >> 28; soc_info 44 arch/arm/mach-davinci/common.c part_no = (soc_info->jtag_id & 0x0ffff000) >> 12; soc_info 46 arch/arm/mach-davinci/common.c for (i = 0, dip = soc_info->ids; i < soc_info->ids_num; soc_info 50 arch/arm/mach-davinci/common.c soc_info->cpu_id = dip->cpu_id; soc_info 56 arch/arm/mach-davinci/common.c pr_err("Unknown DaVinci JTAG ID 0x%x\n", soc_info->jtag_id); soc_info 60 arch/arm/mach-davinci/common.c void __init davinci_common_init(const struct davinci_soc_info *soc_info) soc_info 64 arch/arm/mach-davinci/common.c if (!soc_info) { soc_info 69 arch/arm/mach-davinci/common.c memcpy(&davinci_soc_info, soc_info, sizeof(struct davinci_soc_info)); soc_info 76 arch/arm/mach-davinci/include/mach/common.h extern void davinci_common_init(const struct davinci_soc_info *soc_info); soc_info 36 arch/arm/mach-davinci/mux.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 42 arch/arm/mach-davinci/mux.c if (WARN_ON(!soc_info->pinmux_pins)) soc_info 46 arch/arm/mach-davinci/mux.c pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K); soc_info 51 arch/arm/mach-davinci/mux.c if (index >= soc_info->pinmux_pins_num) { soc_info 53 arch/arm/mach-davinci/mux.c index, soc_info->pinmux_pins_num); soc_info 58 arch/arm/mach-davinci/mux.c cfg = &soc_info->pinmux_pins[index]; soc_info 115 arch/arm/mach-davinci/time.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 119 arch/arm/mach-davinci/time.c soc_info->timer_info->timers; soc_info 193 arch/arm/mach-davinci/time.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 194 arch/arm/mach-davinci/time.c struct davinci_timer_instance *dtip = soc_info->timer_info->timers; soc_info 338 arch/arm/mach-davinci/time.c struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info 343 arch/arm/mach-davinci/time.c clockevent_id = soc_info->timer_info->clockevent_id; soc_info 344 arch/arm/mach-davinci/time.c clocksource_id = soc_info->timer_info->clocksource_id; soc_info 356 arch/arm/mach-davinci/time.c soc_info->timer_info->timers; soc_info 35 arch/mips/lantiq/prom.c static struct ltq_soc_info soc_info; soc_info 39 arch/mips/lantiq/prom.c return soc_info.sys_type; soc_info 44 arch/mips/lantiq/prom.c return soc_info.type; soc_info 102 arch/mips/lantiq/prom.c ltq_soc_detect(&soc_info); soc_info 103 arch/mips/lantiq/prom.c snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", soc_info 104 arch/mips/lantiq/prom.c soc_info.name, soc_info.rev_type); soc_info 105 arch/mips/lantiq/prom.c soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; soc_info 106 arch/mips/lantiq/prom.c pr_info("SoC: %s\n", soc_info.sys_type); soc_info 21 arch/mips/ralink/common.h extern struct ralink_soc_info soc_info; soc_info 30 arch/mips/ralink/common.h extern void prom_soc_init(struct ralink_soc_info *soc_info); soc_info 597 arch/mips/ralink/mt7620.c mt7620_dram_init(struct ralink_soc_info *soc_info) soc_info 602 arch/mips/ralink/mt7620.c soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; soc_info 603 arch/mips/ralink/mt7620.c soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; soc_info 608 arch/mips/ralink/mt7620.c soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; soc_info 609 arch/mips/ralink/mt7620.c soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; soc_info 614 arch/mips/ralink/mt7620.c soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; soc_info 615 arch/mips/ralink/mt7620.c soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; soc_info 623 arch/mips/ralink/mt7620.c mt7628_dram_init(struct ralink_soc_info *soc_info) soc_info 628 arch/mips/ralink/mt7620.c soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; soc_info 629 arch/mips/ralink/mt7620.c soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; soc_info 634 arch/mips/ralink/mt7620.c soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; soc_info 635 arch/mips/ralink/mt7620.c soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; soc_info 642 arch/mips/ralink/mt7620.c void prom_soc_init(struct ralink_soc_info *soc_info) soc_info 663 arch/mips/ralink/mt7620.c soc_info->compatible = "ralink,mt7620a-soc"; soc_info 667 arch/mips/ralink/mt7620.c soc_info->compatible = "ralink,mt7620n-soc"; soc_info 679 arch/mips/ralink/mt7620.c soc_info->compatible = "ralink,mt7628an-soc"; soc_info 684 arch/mips/ralink/mt7620.c snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, soc_info 700 arch/mips/ralink/mt7620.c soc_info->mem_base = MT7620_DRAM_BASE; soc_info 702 arch/mips/ralink/mt7620.c mt7628_dram_init(soc_info); soc_info 704 arch/mips/ralink/mt7620.c mt7620_dram_init(soc_info); soc_info 163 arch/mips/ralink/mt7621.c void prom_soc_init(struct ralink_soc_info *soc_info) soc_info 198 arch/mips/ralink/mt7621.c soc_info->compatible = "mtk,mt7621-soc"; soc_info 205 arch/mips/ralink/mt7621.c snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, soc_info 211 arch/mips/ralink/mt7621.c soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN; soc_info 212 arch/mips/ralink/mt7621.c soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX; soc_info 213 arch/mips/ralink/mt7621.c soc_info->mem_base = MT7621_DRAM_BASE; soc_info 86 arch/mips/ralink/of.c else if (soc_info.mem_size) soc_info 87 arch/mips/ralink/of.c add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M, soc_info 90 arch/mips/ralink/of.c detect_memory_region(soc_info.mem_base, soc_info 91 arch/mips/ralink/of.c soc_info.mem_size_min * SZ_1M, soc_info 92 arch/mips/ralink/of.c soc_info.mem_size_max * SZ_1M); soc_info 97 arch/mips/ralink/of.c __dt_register_buses(soc_info.compatible, "palmbus"); soc_info 20 arch/mips/ralink/prom.c struct ralink_soc_info soc_info; soc_info 28 arch/mips/ralink/prom.c return soc_info.sys_type; soc_info 63 arch/mips/ralink/prom.c prom_soc_init(&soc_info); soc_info 80 arch/mips/ralink/rt288x.c void prom_soc_init(struct ralink_soc_info *soc_info) soc_info 93 arch/mips/ralink/rt288x.c soc_info->compatible = "ralink,r2880-soc"; soc_info 99 arch/mips/ralink/rt288x.c snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, soc_info 105 arch/mips/ralink/rt288x.c soc_info->mem_base = RT2880_SDRAM_BASE; soc_info 106 arch/mips/ralink/rt288x.c soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; soc_info 107 arch/mips/ralink/rt288x.c soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; soc_info 217 arch/mips/ralink/rt305x.c void prom_soc_init(struct ralink_soc_info *soc_info) soc_info 235 arch/mips/ralink/rt305x.c soc_info->compatible = "ralink,rt3050-soc"; soc_info 239 arch/mips/ralink/rt305x.c soc_info->compatible = "ralink,rt3052-soc"; soc_info 244 arch/mips/ralink/rt305x.c soc_info->compatible = "ralink,rt3350-soc"; soc_info 248 arch/mips/ralink/rt305x.c soc_info->compatible = "ralink,rt3352-soc"; soc_info 252 arch/mips/ralink/rt305x.c soc_info->compatible = "ralink,rt5350-soc"; soc_info 259 arch/mips/ralink/rt305x.c snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, soc_info 265 arch/mips/ralink/rt305x.c soc_info->mem_base = RT305X_SDRAM_BASE; soc_info 267 arch/mips/ralink/rt305x.c soc_info->mem_size = rt5350_get_mem_size(); soc_info 270 arch/mips/ralink/rt305x.c soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; soc_info 271 arch/mips/ralink/rt305x.c soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; soc_info 274 arch/mips/ralink/rt305x.c soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; soc_info 275 arch/mips/ralink/rt305x.c soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; soc_info 116 arch/mips/ralink/rt3883.c void prom_soc_init(struct ralink_soc_info *soc_info) soc_info 129 arch/mips/ralink/rt3883.c soc_info->compatible = "ralink,rt3883-soc"; soc_info 135 arch/mips/ralink/rt3883.c snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, soc_info 141 arch/mips/ralink/rt3883.c soc_info->mem_base = RT3883_SDRAM_BASE; soc_info 142 arch/mips/ralink/rt3883.c soc_info->mem_size_min = RT3883_MEM_SIZE_MIN; soc_info 143 arch/mips/ralink/rt3883.c soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; soc_info 50 drivers/clk/ingenic/tcu.c const struct ingenic_soc_info *soc_info; soc_info 344 drivers/clk/ingenic/tcu.c tcu->soc_info = id->data; soc_info 346 drivers/clk/ingenic/tcu.c if (tcu->soc_info->has_tcu_clk) { soc_info 371 drivers/clk/ingenic/tcu.c for (i = 0; i < tcu->soc_info->num_channels; i++) { soc_info 396 drivers/clk/ingenic/tcu.c if (tcu->soc_info->has_ost) { soc_info 418 drivers/clk/ingenic/tcu.c if (tcu->soc_info->has_ost) soc_info 428 drivers/clk/ingenic/tcu.c if (tcu->soc_info->has_tcu_clk) soc_info 431 drivers/clk/ingenic/tcu.c if (tcu->soc_info->has_tcu_clk) soc_info 239 drivers/clocksource/ingenic-timer.c const struct ingenic_soc_info *soc_info = id->data; soc_info 256 drivers/clocksource/ingenic-timer.c tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, 2); soc_info 261 drivers/clocksource/ingenic-timer.c if (hweight8(tcu->pwm_channels_mask) > soc_info->num_channels - 2) { soc_info 272 drivers/clocksource/ingenic-timer.c soc_info->num_channels); soc_info 274 drivers/clocksource/ingenic-timer.c soc_info->num_channels, soc_info 602 drivers/gpu/drm/ingenic/ingenic-drm.c const struct jz_soc_info *soc_info; soc_info 613 drivers/gpu/drm/ingenic/ingenic-drm.c soc_info = of_device_get_match_data(dev); soc_info 614 drivers/gpu/drm/ingenic/ingenic-drm.c if (!soc_info) { soc_info 661 drivers/gpu/drm/ingenic/ingenic-drm.c if (soc_info->needs_dev_clk) { soc_info 398 drivers/iio/adc/at91-sama5d2_adc.c struct at91_adc_soc_info soc_info; soc_info 1165 drivers/iio/adc/at91-sama5d2_adc.c startup = at91_adc_startup_time(st->soc_info.startup_time, soc_info 1434 drivers/iio/adc/at91-sama5d2_adc.c if (val < st->soc_info.min_sample_rate || soc_info 1435 drivers/iio/adc/at91-sama5d2_adc.c val > st->soc_info.max_sample_rate) soc_info 1587 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate); soc_info 1682 drivers/iio/adc/at91-sama5d2_adc.c &st->soc_info.min_sample_rate); soc_info 1691 drivers/iio/adc/at91-sama5d2_adc.c &st->soc_info.max_sample_rate); soc_info 1699 drivers/iio/adc/at91-sama5d2_adc.c &st->soc_info.startup_time); soc_info 51 drivers/memory/jz4780-nemc.c const struct jz_soc_info *soc_info; soc_info 207 drivers/memory/jz4780-nemc.c if (cycles > nemc->soc_info->tas_tah_cycles_max) { soc_info 219 drivers/memory/jz4780-nemc.c if (cycles > nemc->soc_info->tas_tah_cycles_max) { soc_info 283 drivers/memory/jz4780-nemc.c nemc->soc_info = device_get_match_data(dev); soc_info 284 drivers/memory/jz4780-nemc.c if (!nemc->soc_info) soc_info 48 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c const struct jz_soc_info *soc_info; soc_info 178 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c writeb(cmd, cs->base + nfc->soc_info->addr_offset); soc_info 180 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c writeb(cmd, cs->base + nfc->soc_info->cmd_offset); soc_info 296 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c mtd_set_ooblayout(mtd, nfc->soc_info->oob_layout); soc_info 362 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c chip->legacy.IO_ADDR_R = cs->base + nfc->soc_info->data_offset; soc_info 363 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c chip->legacy.IO_ADDR_W = cs->base + nfc->soc_info->data_offset; soc_info 446 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c nfc->soc_info = device_get_match_data(dev); soc_info 447 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c if (!nfc->soc_info) soc_info 552 drivers/net/wireless/ath/ath10k/qmi.c qmi->soc_info.soc_id = resp->soc_info.soc_id; soc_info 567 drivers/net/wireless/ath/ath10k/qmi.c qmi->board_info.board_id, qmi->soc_info.soc_id); soc_info 101 drivers/net/wireless/ath/ath10k/qmi.h struct ath10k_qmi_soc_info soc_info; soc_info 891 drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c soc_info), soc_info 312 drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h struct wlfw_soc_info_s_v01 soc_info; soc_info 1226 drivers/tty/serial/ucc_uart.c soc = soc_info(&rev_h, &rev_l);