snd_opl3sa2_write 246 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_MISC, tmp ^ 7); snd_opl3sa2_write 253 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_MIC, 0x8a); snd_opl3sa2_write 258 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_MIC, 0x9f); snd_opl3sa2_write 261 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D0); snd_opl3sa2_write 264 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_SYS_CTRL, (chip->ymode << 4)); snd_opl3sa2_write 267 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_SYS_CTRL, 0x00); snd_opl3sa2_write 269 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_IRQ_CONFIG, 0x0d); /* Interrupt Channel Configuration - IRQ A = OPL3 + MPU + WSS */ snd_opl3sa2_write 271 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_DMA_CONFIG, 0x03); /* DMA Configuration - DMA A = WSS-R + WSS-P */ snd_opl3sa2_write 273 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_DMA_CONFIG, 0x21); /* DMA Configuration - DMA B = WSS-R, DMA A = WSS-P */ snd_opl3sa2_write 275 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_MISC, 0x80 | (tmp & 7)); /* Miscellaneous - default */ snd_opl3sa2_write 277 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA3_DGTL_DOWN, 0x00); /* Digital Block Partial Power Down - default */ snd_opl3sa2_write 278 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA3_ANLG_DOWN, 0x00); /* Analog Block Partial Power Down - default */ snd_opl3sa2_write 547 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D3); snd_opl3sa2_write 563 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D0); snd_opl3sa2_write 568 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, i, chip->ctlregs[i]); snd_opl3sa2_write 572 sound/isa/opl3sa2.c snd_opl3sa2_write(chip, i, chip->ctlregs[i]);