snd_miro_write_mask 1006 sound/isa/opti9xx/miro.c 	snd_miro_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);
snd_miro_write_mask 1007 sound/isa/opti9xx/miro.c 	snd_miro_write_mask(chip, OPTi9XX_MC_REG(2), 0x20, 0x20); /* OPL4 */
snd_miro_write_mask 1008 sound/isa/opti9xx/miro.c 	snd_miro_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);
snd_miro_write_mask 1012 sound/isa/opti9xx/miro.c 		snd_miro_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x02);
snd_miro_write_mask 1013 sound/isa/opti9xx/miro.c 		snd_miro_write_mask(chip, OPTi9XX_MC_REG(3), 0xf0, 0xff);
snd_miro_write_mask 1017 sound/isa/opti9xx/miro.c 		snd_miro_write_mask(chip, OPTi9XX_MC_REG(4), 0x00, 0x0c);
snd_miro_write_mask 1046 sound/isa/opti9xx/miro.c 	snd_miro_write_mask(chip, OPTi9XX_MC_REG(1), wss_base_bits << 4, 0x30);
snd_miro_write_mask 1147 sound/isa/opti9xx/miro.c 		snd_miro_write_mask(chip, OPTi9XX_MC_REG(6),