CVMX_WAIT_FOR_FIELD64 352 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7, CVMX_WAIT_FOR_FIELD64 354 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf, CVMX_WAIT_FOR_FIELD64 155 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 182 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface), CVMX_WAIT_FOR_FIELD64 217 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 220 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), CVMX_WAIT_FOR_FIELD64 167 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 172 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 177 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 188 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 193 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 217 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 221 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 225 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c if (CVMX_WAIT_FOR_FIELD64 CVMX_WAIT_FOR_FIELD64 836 arch/mips/pci/pcie-octeon.c if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port), CVMX_WAIT_FOR_FIELD64 1293 arch/mips/pci/pcie-octeon.c if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {