CVMX_SRXX_COM_CTL  213 arch/mips/cavium-octeon/executive/cvmx-spi.c 	cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0);
CVMX_SRXX_COM_CTL  325 arch/mips/cavium-octeon/executive/cvmx-spi.c 		cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
CVMX_SRXX_COM_CTL  586 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
CVMX_SRXX_COM_CTL  589 arch/mips/cavium-octeon/executive/cvmx-spi.c 		cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
CVMX_SRXX_COM_CTL  641 arch/mips/cavium-octeon/executive/cvmx-spi.c 		srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
CVMX_SRXX_COM_CTL  643 arch/mips/cavium-octeon/executive/cvmx-spi.c 		cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);