smu_clk_type 151 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c static enum smu_clk_type dc_to_smu_clock_type( smu_clk_type 154 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum smu_clk_type smu_clk_type = SMU_CLK_COUNT; smu_clk_type 158 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c smu_clk_type = SMU_DISPCLK; smu_clk_type 161 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c smu_clk_type = SMU_GFXCLK; smu_clk_type 164 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c smu_clk_type = SMU_MCLK; smu_clk_type 167 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c smu_clk_type = SMU_DCEFCLK; smu_clk_type 170 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c smu_clk_type = SMU_SOCCLK; smu_clk_type 178 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c return smu_clk_type; smu_clk_type 159 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 195 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 231 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 274 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 308 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 314 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) smu_clk_type 587 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c enum smu_clk_type type, char *buf) smu_clk_type 752 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c enum smu_clk_type type, uint32_t mask) smu_clk_type 1095 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c enum smu_clk_type clk_type, smu_clk_type 408 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); smu_clk_type 409 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); smu_clk_type 411 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type); smu_clk_type 413 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_clk_type clk_type, smu_clk_type 419 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_clk_type clk_type, smu_clk_type 454 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_clk_type clk_type, smu_clk_type 500 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value); smu_clk_type 542 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); smu_clk_type 818 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 820 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 822 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 824 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 826 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 831 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type); smu_clk_type 651 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, smu_clk_type 670 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) smu_clk_type 684 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, char *buf) smu_clk_type 748 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, uint32_t mask) smu_clk_type 811 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, smu_clk_type 894 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type; smu_clk_type 896 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clks[] = { smu_clk_type 921 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type; smu_clk_type 923 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clks[] = { smu_clk_type 181 drivers/gpu/drm/amd/powerplay/renoir_ppt.c enum smu_clk_type clk_type, char *buf) smu_clk_type 943 drivers/gpu/drm/amd/powerplay/smu_v11_0.c enum smu_clk_type clock_select) smu_clk_type 1099 drivers/gpu/drm/amd/powerplay/smu_v11_0.c enum smu_clk_type clk_id, smu_clk_type 1287 drivers/gpu/drm/amd/powerplay/smu_v11_0.c enum smu_clk_type clk_select = 0; smu_clk_type 1725 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 322 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, smu_clk_type 941 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type type, char *buf) smu_clk_type 1272 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type, uint32_t mask) smu_clk_type 1444 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type, smu_clk_type 1750 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type) smu_clk_type 2540 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type,