smmu_pmu          118 drivers/perf/arm_smmuv3_pmu.c #define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu))
smmu_pmu          134 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
smmu_pmu          137 drivers/perf/arm_smmuv3_pmu.c 	       smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
smmu_pmu          138 drivers/perf/arm_smmuv3_pmu.c 	writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
smmu_pmu          143 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
smmu_pmu          145 drivers/perf/arm_smmuv3_pmu.c 	writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
smmu_pmu          146 drivers/perf/arm_smmuv3_pmu.c 	writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
smmu_pmu          149 drivers/perf/arm_smmuv3_pmu.c static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu,
smmu_pmu          152 drivers/perf/arm_smmuv3_pmu.c 	if (smmu_pmu->counter_mask & BIT(32))
smmu_pmu          153 drivers/perf/arm_smmuv3_pmu.c 		writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
smmu_pmu          155 drivers/perf/arm_smmuv3_pmu.c 		writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
smmu_pmu          158 drivers/perf/arm_smmuv3_pmu.c static inline u64 smmu_pmu_counter_get_value(struct smmu_pmu *smmu_pmu, u32 idx)
smmu_pmu          162 drivers/perf/arm_smmuv3_pmu.c 	if (smmu_pmu->counter_mask & BIT(32))
smmu_pmu          163 drivers/perf/arm_smmuv3_pmu.c 		value = readq(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
smmu_pmu          165 drivers/perf/arm_smmuv3_pmu.c 		value = readl(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
smmu_pmu          170 drivers/perf/arm_smmuv3_pmu.c static inline void smmu_pmu_counter_enable(struct smmu_pmu *smmu_pmu, u32 idx)
smmu_pmu          172 drivers/perf/arm_smmuv3_pmu.c 	writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);
smmu_pmu          175 drivers/perf/arm_smmuv3_pmu.c static inline void smmu_pmu_counter_disable(struct smmu_pmu *smmu_pmu, u32 idx)
smmu_pmu          177 drivers/perf/arm_smmuv3_pmu.c 	writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
smmu_pmu          180 drivers/perf/arm_smmuv3_pmu.c static inline void smmu_pmu_interrupt_enable(struct smmu_pmu *smmu_pmu, u32 idx)
smmu_pmu          182 drivers/perf/arm_smmuv3_pmu.c 	writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);
smmu_pmu          185 drivers/perf/arm_smmuv3_pmu.c static inline void smmu_pmu_interrupt_disable(struct smmu_pmu *smmu_pmu,
smmu_pmu          188 drivers/perf/arm_smmuv3_pmu.c 	writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
smmu_pmu          191 drivers/perf/arm_smmuv3_pmu.c static inline void smmu_pmu_set_evtyper(struct smmu_pmu *smmu_pmu, u32 idx,
smmu_pmu          194 drivers/perf/arm_smmuv3_pmu.c 	writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
smmu_pmu          197 drivers/perf/arm_smmuv3_pmu.c static inline void smmu_pmu_set_smr(struct smmu_pmu *smmu_pmu, u32 idx, u32 val)
smmu_pmu          199 drivers/perf/arm_smmuv3_pmu.c 	writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
smmu_pmu          205 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
smmu_pmu          211 drivers/perf/arm_smmuv3_pmu.c 		now = smmu_pmu_counter_get_value(smmu_pmu, idx);
smmu_pmu          216 drivers/perf/arm_smmuv3_pmu.c 	delta &= smmu_pmu->counter_mask;
smmu_pmu          221 drivers/perf/arm_smmuv3_pmu.c static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu,
smmu_pmu          227 drivers/perf/arm_smmuv3_pmu.c 	if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) {
smmu_pmu          235 drivers/perf/arm_smmuv3_pmu.c 		new = smmu_pmu_counter_get_value(smmu_pmu, idx);
smmu_pmu          243 drivers/perf/arm_smmuv3_pmu.c 		new = smmu_pmu->counter_mask >> 1;
smmu_pmu          244 drivers/perf/arm_smmuv3_pmu.c 		smmu_pmu_counter_set_value(smmu_pmu, idx, new);
smmu_pmu          253 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
smmu_pmu          257 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_set_evtyper(smmu_pmu, idx, evtyper);
smmu_pmu          258 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_set_smr(smmu_pmu, idx, sid);
smmu_pmu          274 drivers/perf/arm_smmuv3_pmu.c static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
smmu_pmu          278 drivers/perf/arm_smmuv3_pmu.c 	unsigned int num_ctrs = smmu_pmu->num_counters;
smmu_pmu          287 drivers/perf/arm_smmuv3_pmu.c 	if (!smmu_pmu->global_filter) {
smmu_pmu          293 drivers/perf/arm_smmuv3_pmu.c 	idx = find_first_bit(smmu_pmu->used_counters, num_ctrs);
smmu_pmu          295 drivers/perf/arm_smmuv3_pmu.c 	    smmu_pmu_check_global_filter(smmu_pmu->events[idx], event)) {
smmu_pmu          303 drivers/perf/arm_smmuv3_pmu.c static int smmu_pmu_get_event_idx(struct smmu_pmu *smmu_pmu,
smmu_pmu          307 drivers/perf/arm_smmuv3_pmu.c 	unsigned int num_ctrs = smmu_pmu->num_counters;
smmu_pmu          309 drivers/perf/arm_smmuv3_pmu.c 	idx = find_first_zero_bit(smmu_pmu->used_counters, num_ctrs);
smmu_pmu          314 drivers/perf/arm_smmuv3_pmu.c 	err = smmu_pmu_apply_event_filter(smmu_pmu, event, idx);
smmu_pmu          318 drivers/perf/arm_smmuv3_pmu.c 	set_bit(idx, smmu_pmu->used_counters);
smmu_pmu          344 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
smmu_pmu          345 drivers/perf/arm_smmuv3_pmu.c 	struct device *dev = smmu_pmu->dev;
smmu_pmu          366 drivers/perf/arm_smmuv3_pmu.c 	    (!test_bit(event_id, smmu_pmu->supported_events))) {
smmu_pmu          376 drivers/perf/arm_smmuv3_pmu.c 		if (++group_num_events > smmu_pmu->num_counters)
smmu_pmu          387 drivers/perf/arm_smmuv3_pmu.c 		if (++group_num_events > smmu_pmu->num_counters)
smmu_pmu          397 drivers/perf/arm_smmuv3_pmu.c 	event->cpu = smmu_pmu->on_cpu;
smmu_pmu          404 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
smmu_pmu          410 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_set_period(smmu_pmu, hwc);
smmu_pmu          412 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_counter_enable(smmu_pmu, idx);
smmu_pmu          417 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
smmu_pmu          424 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_counter_disable(smmu_pmu, idx);
smmu_pmu          434 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
smmu_pmu          436 drivers/perf/arm_smmuv3_pmu.c 	idx = smmu_pmu_get_event_idx(smmu_pmu, event);
smmu_pmu          442 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->events[idx] = event;
smmu_pmu          445 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_interrupt_enable(smmu_pmu, idx);
smmu_pmu          459 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
smmu_pmu          463 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_interrupt_disable(smmu_pmu, idx);
smmu_pmu          464 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->events[idx] = NULL;
smmu_pmu          465 drivers/perf/arm_smmuv3_pmu.c 	clear_bit(idx, smmu_pmu->used_counters);
smmu_pmu          481 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
smmu_pmu          483 drivers/perf/arm_smmuv3_pmu.c 	return cpumap_print_to_pagebuf(true, buf, cpumask_of(smmu_pmu->on_cpu));
smmu_pmu          538 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
smmu_pmu          543 drivers/perf/arm_smmuv3_pmu.c 	if (test_bit(pmu_attr->id, smmu_pmu->supported_events))
smmu_pmu          587 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu;
smmu_pmu          590 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu = hlist_entry_safe(node, struct smmu_pmu, node);
smmu_pmu          591 drivers/perf/arm_smmuv3_pmu.c 	if (cpu != smmu_pmu->on_cpu)
smmu_pmu          598 drivers/perf/arm_smmuv3_pmu.c 	perf_pmu_migrate_context(&smmu_pmu->pmu, cpu, target);
smmu_pmu          599 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->on_cpu = target;
smmu_pmu          600 drivers/perf/arm_smmuv3_pmu.c 	WARN_ON(irq_set_affinity_hint(smmu_pmu->irq, cpumask_of(target)));
smmu_pmu          607 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = data;
smmu_pmu          611 drivers/perf/arm_smmuv3_pmu.c 	ovsr = readq(smmu_pmu->reloc_base + SMMU_PMCG_OVSSET0);
smmu_pmu          615 drivers/perf/arm_smmuv3_pmu.c 	writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
smmu_pmu          617 drivers/perf/arm_smmuv3_pmu.c 	for_each_set_bit(idx, (unsigned long *)&ovsr, smmu_pmu->num_counters) {
smmu_pmu          618 drivers/perf/arm_smmuv3_pmu.c 		struct perf_event *event = smmu_pmu->events[idx];
smmu_pmu          627 drivers/perf/arm_smmuv3_pmu.c 		smmu_pmu_set_period(smmu_pmu, hwc);
smmu_pmu          644 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *pmu = dev_get_drvdata(dev);
smmu_pmu          655 drivers/perf/arm_smmuv3_pmu.c static void smmu_pmu_setup_msi(struct smmu_pmu *pmu)
smmu_pmu          682 drivers/perf/arm_smmuv3_pmu.c static int smmu_pmu_setup_irq(struct smmu_pmu *pmu)
smmu_pmu          696 drivers/perf/arm_smmuv3_pmu.c static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu)
smmu_pmu          698 drivers/perf/arm_smmuv3_pmu.c 	u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0);
smmu_pmu          700 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_disable(&smmu_pmu->pmu);
smmu_pmu          704 drivers/perf/arm_smmuv3_pmu.c 		       smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
smmu_pmu          706 drivers/perf/arm_smmuv3_pmu.c 		       smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
smmu_pmu          708 drivers/perf/arm_smmuv3_pmu.c 		       smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
smmu_pmu          711 drivers/perf/arm_smmuv3_pmu.c static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
smmu_pmu          715 drivers/perf/arm_smmuv3_pmu.c 	model = *(u32 *)dev_get_platdata(smmu_pmu->dev);
smmu_pmu          720 drivers/perf/arm_smmuv3_pmu.c 		smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
smmu_pmu          724 drivers/perf/arm_smmuv3_pmu.c 	dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
smmu_pmu          729 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu;
smmu_pmu          737 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu = devm_kzalloc(dev, sizeof(*smmu_pmu), GFP_KERNEL);
smmu_pmu          738 drivers/perf/arm_smmuv3_pmu.c 	if (!smmu_pmu)
smmu_pmu          741 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->dev = dev;
smmu_pmu          742 drivers/perf/arm_smmuv3_pmu.c 	platform_set_drvdata(pdev, smmu_pmu);
smmu_pmu          744 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->pmu = (struct pmu) {
smmu_pmu          759 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->reg_base = devm_ioremap_resource(dev, res_0);
smmu_pmu          760 drivers/perf/arm_smmuv3_pmu.c 	if (IS_ERR(smmu_pmu->reg_base))
smmu_pmu          761 drivers/perf/arm_smmuv3_pmu.c 		return PTR_ERR(smmu_pmu->reg_base);
smmu_pmu          763 drivers/perf/arm_smmuv3_pmu.c 	cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
smmu_pmu          768 drivers/perf/arm_smmuv3_pmu.c 		smmu_pmu->reloc_base = devm_ioremap_resource(dev, res_1);
smmu_pmu          769 drivers/perf/arm_smmuv3_pmu.c 		if (IS_ERR(smmu_pmu->reloc_base))
smmu_pmu          770 drivers/perf/arm_smmuv3_pmu.c 			return PTR_ERR(smmu_pmu->reloc_base);
smmu_pmu          772 drivers/perf/arm_smmuv3_pmu.c 		smmu_pmu->reloc_base = smmu_pmu->reg_base;
smmu_pmu          777 drivers/perf/arm_smmuv3_pmu.c 		smmu_pmu->irq = irq;
smmu_pmu          779 drivers/perf/arm_smmuv3_pmu.c 	ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
smmu_pmu          780 drivers/perf/arm_smmuv3_pmu.c 	ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
smmu_pmu          781 drivers/perf/arm_smmuv3_pmu.c 	bitmap_from_arr32(smmu_pmu->supported_events, (u32 *)ceid_64,
smmu_pmu          784 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1;
smmu_pmu          786 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE);
smmu_pmu          789 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0);
smmu_pmu          791 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_reset(smmu_pmu);
smmu_pmu          793 drivers/perf/arm_smmuv3_pmu.c 	err = smmu_pmu_setup_irq(smmu_pmu);
smmu_pmu          806 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_get_acpi_options(smmu_pmu);
smmu_pmu          809 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu->on_cpu = raw_smp_processor_id();
smmu_pmu          810 drivers/perf/arm_smmuv3_pmu.c 	WARN_ON(irq_set_affinity_hint(smmu_pmu->irq,
smmu_pmu          811 drivers/perf/arm_smmuv3_pmu.c 				      cpumask_of(smmu_pmu->on_cpu)));
smmu_pmu          814 drivers/perf/arm_smmuv3_pmu.c 					       &smmu_pmu->node);
smmu_pmu          821 drivers/perf/arm_smmuv3_pmu.c 	err = perf_pmu_register(&smmu_pmu->pmu, name, -1);
smmu_pmu          829 drivers/perf/arm_smmuv3_pmu.c 		 &res_0->start, smmu_pmu->num_counters,
smmu_pmu          830 drivers/perf/arm_smmuv3_pmu.c 		 smmu_pmu->global_filter ? "Global(Counter0)" :
smmu_pmu          836 drivers/perf/arm_smmuv3_pmu.c 	cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
smmu_pmu          842 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
smmu_pmu          844 drivers/perf/arm_smmuv3_pmu.c 	perf_pmu_unregister(&smmu_pmu->pmu);
smmu_pmu          845 drivers/perf/arm_smmuv3_pmu.c 	cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
smmu_pmu          852 drivers/perf/arm_smmuv3_pmu.c 	struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
smmu_pmu          854 drivers/perf/arm_smmuv3_pmu.c 	smmu_pmu_disable(&smmu_pmu->pmu);