smc_state 2387 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 2410 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (smc_state->levelCount != state->performance_level_count) smc_state 2415 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[0].dpm2.MaxPS = 0; smc_state 2416 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[0].dpm2.NearTDPDec = 0; smc_state 2417 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[0].dpm2.AboveSafeInc = 0; smc_state 2418 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[0].dpm2.BelowSafeInc = 0; smc_state 2419 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; smc_state 2468 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); smc_state 2469 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; smc_state 2470 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; smc_state 2471 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; smc_state 2472 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); smc_state 2480 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 2491 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (smc_state->levelCount != state->performance_level_count) smc_state 2528 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); smc_state 2529 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); smc_state 5426 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 5433 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); smc_state 5435 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[ps->performance_level_count - 1].bSP = smc_state 5550 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 5564 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[0].aT = cpu_to_be32(a_t); smc_state 5568 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[0].aT = cpu_to_be32(0); smc_state 5584 drivers/gpu/drm/amd/amdgpu/si_dpm.c a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; smc_state 5586 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].aT = cpu_to_be32(a_t); smc_state 5591 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i + 1].aT = cpu_to_be32(a_t); smc_state 5653 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 5671 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; smc_state 5677 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; smc_state 5679 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levelCount = 0; smc_state 5684 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; smc_state 5686 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; smc_state 5691 drivers/gpu/drm/amd/amdgpu/si_dpm.c &smc_state->levels[i]); smc_state 5692 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].arbRefreshState = smc_state 5699 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].displayWatermark = smc_state 5703 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].displayWatermark = (i < 2) ? smc_state 5707 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; smc_state 5709 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levels[i].ACIndex = 0; smc_state 5711 drivers/gpu/drm/amd/amdgpu/si_dpm.c smc_state->levelCount++; smc_state 5718 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_populate_smc_sp(adev, amdgpu_state, smc_state); smc_state 5720 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state); smc_state 5724 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state); smc_state 5728 drivers/gpu/drm/amd/amdgpu/si_dpm.c return si_populate_smc_t(adev, amdgpu_state, smc_state); smc_state 5742 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; smc_state 5744 drivers/gpu/drm/amd/amdgpu/si_dpm.c memset(smc_state, 0, state_size); smc_state 5746 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state); smc_state 5750 drivers/gpu/drm/amd/amdgpu/si_dpm.c return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, smc_state 5763 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; smc_state 5766 drivers/gpu/drm/amd/amdgpu/si_dpm.c memset(smc_state, 0, state_size); smc_state 5768 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_ulv_state(adev, smc_state); smc_state 5770 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, smc_state 765 drivers/gpu/drm/radeon/cypress_dpm.c RV770_SMC_SWSTATE *smc_state) smc_state 772 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; smc_state 776 drivers/gpu/drm/radeon/cypress_dpm.c &smc_state->levels[0], smc_state 783 drivers/gpu/drm/radeon/cypress_dpm.c &smc_state->levels[1], smc_state 790 drivers/gpu/drm/radeon/cypress_dpm.c &smc_state->levels[2], smc_state 795 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; smc_state 796 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; smc_state 797 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; smc_state 800 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->levels[0].ACIndex = 2; smc_state 801 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->levels[1].ACIndex = 3; smc_state 802 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->levels[2].ACIndex = 4; smc_state 804 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->levels[0].ACIndex = 0; smc_state 805 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->levels[1].ACIndex = 0; smc_state 806 drivers/gpu/drm/radeon/cypress_dpm.c smc_state->levels[2].ACIndex = 0; smc_state 809 drivers/gpu/drm/radeon/cypress_dpm.c rv770_populate_smc_sp(rdev, radeon_state, smc_state); smc_state 811 drivers/gpu/drm/radeon/cypress_dpm.c return rv770_populate_smc_t(rdev, radeon_state, smc_state); smc_state 2296 drivers/gpu/drm/radeon/ni_dpm.c NISLANDS_SMC_SWSTATE *smc_state) smc_state 2303 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); smc_state 2305 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[ps->performance_level_count - 1].bSP = smc_state 2392 drivers/gpu/drm/radeon/ni_dpm.c NISLANDS_SMC_SWSTATE *smc_state) smc_state 2407 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[0].aT = cpu_to_be32(a_t); smc_state 2411 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[0].aT = cpu_to_be32(0); smc_state 2436 drivers/gpu/drm/radeon/ni_dpm.c a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; smc_state 2438 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].aT = cpu_to_be32(a_t); smc_state 2444 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i + 1].aT = cpu_to_be32(a_t); smc_state 2452 drivers/gpu/drm/radeon/ni_dpm.c NISLANDS_SMC_SWSTATE *smc_state) smc_state 2473 drivers/gpu/drm/radeon/ni_dpm.c if (smc_state->levelCount != state->performance_level_count) smc_state 2495 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[0].dpm2.MaxPS = 0; smc_state 2496 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[0].dpm2.NearTDPDec = 0; smc_state 2497 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[0].dpm2.AboveSafeInc = 0; smc_state 2498 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[0].dpm2.BelowSafeInc = 0; smc_state 2499 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0; smc_state 2523 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].dpm2.MaxPS = smc_state 2525 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC; smc_state 2526 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC; smc_state 2527 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC; smc_state 2528 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].stateFlags |= smc_state 2538 drivers/gpu/drm/radeon/ni_dpm.c NISLANDS_SMC_SWSTATE *smc_state) smc_state 2550 drivers/gpu/drm/radeon/ni_dpm.c if (smc_state->levelCount != state->performance_level_count) smc_state 2587 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); smc_state 2588 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); smc_state 2626 drivers/gpu/drm/radeon/ni_dpm.c NISLANDS_SMC_SWSTATE *smc_state) smc_state 2635 drivers/gpu/drm/radeon/ni_dpm.c smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; smc_state 2637 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levelCount = 0; smc_state 2644 drivers/gpu/drm/radeon/ni_dpm.c &smc_state->levels[i]); smc_state 2645 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].arbRefreshState = smc_state 2652 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].displayWatermark = smc_state 2656 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].displayWatermark = (i < 2) ? smc_state 2660 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; smc_state 2662 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levels[i].ACIndex = 0; smc_state 2664 drivers/gpu/drm/radeon/ni_dpm.c smc_state->levelCount++; smc_state 2670 drivers/gpu/drm/radeon/ni_dpm.c ni_populate_smc_sp(rdev, radeon_state, smc_state); smc_state 2672 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state); smc_state 2676 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state); smc_state 2680 drivers/gpu/drm/radeon/ni_dpm.c return ni_populate_smc_t(rdev, radeon_state, smc_state); smc_state 2692 drivers/gpu/drm/radeon/ni_dpm.c NISLANDS_SMC_SWSTATE *smc_state = kzalloc(state_size, GFP_KERNEL); smc_state 2694 drivers/gpu/drm/radeon/ni_dpm.c if (smc_state == NULL) smc_state 2697 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); smc_state 2701 drivers/gpu/drm/radeon/ni_dpm.c ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end); smc_state 2704 drivers/gpu/drm/radeon/ni_dpm.c kfree(smc_state); smc_state 257 drivers/gpu/drm/radeon/rv770_dpm.c RV770_SMC_SWSTATE *smc_state) smc_state 289 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[i].aT = cpu_to_be32(a_t); smc_state 295 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT = smc_state 303 drivers/gpu/drm/radeon/rv770_dpm.c RV770_SMC_SWSTATE *smc_state) smc_state 309 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); smc_state 311 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP = smc_state 675 drivers/gpu/drm/radeon/rv770_dpm.c RV770_SMC_SWSTATE *smc_state) smc_state 681 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; smc_state 685 drivers/gpu/drm/radeon/rv770_dpm.c &smc_state->levels[0], smc_state 692 drivers/gpu/drm/radeon/rv770_dpm.c &smc_state->levels[1], smc_state 699 drivers/gpu/drm/radeon/rv770_dpm.c &smc_state->levels[2], smc_state 704 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; smc_state 705 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; smc_state 706 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; smc_state 708 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[0].seqValue = rv770_get_seq_value(rdev, smc_state 710 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[1].seqValue = rv770_get_seq_value(rdev, smc_state 712 drivers/gpu/drm/radeon/rv770_dpm.c smc_state->levels[2].seqValue = rv770_get_seq_value(rdev, smc_state 715 drivers/gpu/drm/radeon/rv770_dpm.c rv770_populate_smc_sp(rdev, radeon_state, smc_state); smc_state 717 drivers/gpu/drm/radeon/rv770_dpm.c return rv770_populate_smc_t(rdev, radeon_state, smc_state); smc_state 231 drivers/gpu/drm/radeon/rv770_dpm.h RV770_SMC_SWSTATE *smc_state); smc_state 234 drivers/gpu/drm/radeon/rv770_dpm.h RV770_SMC_SWSTATE *smc_state); smc_state 2290 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 2313 drivers/gpu/drm/radeon/si_dpm.c if (smc_state->levelCount != state->performance_level_count) smc_state 2318 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[0].dpm2.MaxPS = 0; smc_state 2319 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[0].dpm2.NearTDPDec = 0; smc_state 2320 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[0].dpm2.AboveSafeInc = 0; smc_state 2321 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[0].dpm2.BelowSafeInc = 0; smc_state 2322 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; smc_state 2372 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); smc_state 2373 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; smc_state 2374 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; smc_state 2375 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; smc_state 2376 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); smc_state 2384 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 2395 drivers/gpu/drm/radeon/si_dpm.c if (smc_state->levelCount != state->performance_level_count) smc_state 2432 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); smc_state 2433 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); smc_state 4964 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 4971 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); smc_state 4973 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[ps->performance_level_count - 1].bSP = smc_state 5088 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 5102 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[0].aT = cpu_to_be32(a_t); smc_state 5106 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[0].aT = cpu_to_be32(0); smc_state 5122 drivers/gpu/drm/radeon/si_dpm.c a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; smc_state 5124 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].aT = cpu_to_be32(a_t); smc_state 5129 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i + 1].aT = cpu_to_be32(a_t); smc_state 5191 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state) smc_state 5209 drivers/gpu/drm/radeon/si_dpm.c smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; smc_state 5215 drivers/gpu/drm/radeon/si_dpm.c smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; smc_state 5217 drivers/gpu/drm/radeon/si_dpm.c smc_state->levelCount = 0; smc_state 5222 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; smc_state 5224 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; smc_state 5229 drivers/gpu/drm/radeon/si_dpm.c &smc_state->levels[i]); smc_state 5230 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].arbRefreshState = smc_state 5237 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].displayWatermark = smc_state 5241 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].displayWatermark = (i < 2) ? smc_state 5245 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; smc_state 5247 drivers/gpu/drm/radeon/si_dpm.c smc_state->levels[i].ACIndex = 0; smc_state 5249 drivers/gpu/drm/radeon/si_dpm.c smc_state->levelCount++; smc_state 5256 drivers/gpu/drm/radeon/si_dpm.c si_populate_smc_sp(rdev, radeon_state, smc_state); smc_state 5258 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); smc_state 5262 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); smc_state 5266 drivers/gpu/drm/radeon/si_dpm.c return si_populate_smc_t(rdev, radeon_state, smc_state); smc_state 5280 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; smc_state 5282 drivers/gpu/drm/radeon/si_dpm.c memset(smc_state, 0, state_size); smc_state 5284 drivers/gpu/drm/radeon/si_dpm.c ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); smc_state 5288 drivers/gpu/drm/radeon/si_dpm.c ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, smc_state 5303 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; smc_state 5306 drivers/gpu/drm/radeon/si_dpm.c memset(smc_state, 0, state_size); smc_state 5308 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_ulv_state(rdev, smc_state); smc_state 5310 drivers/gpu/drm/radeon/si_dpm.c ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,