slice_mask        709 arch/powerpc/include/asm/book3s/64/mmu-hash.h 	struct slice_mask mask_64k;
slice_mask        711 arch/powerpc/include/asm/book3s/64/mmu-hash.h 	struct slice_mask mask_4k;
slice_mask        713 arch/powerpc/include/asm/book3s/64/mmu-hash.h 	struct slice_mask mask_16m;
slice_mask        714 arch/powerpc/include/asm/book3s/64/mmu-hash.h 	struct slice_mask mask_16g;
slice_mask        172 arch/powerpc/include/asm/book3s/64/mmu.h static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
slice_mask        218 arch/powerpc/include/asm/nohash/32/mmu-8xx.h 	struct slice_mask mask_base_psize; /* 4k or 16k */
slice_mask        219 arch/powerpc/include/asm/nohash/32/mmu-8xx.h 	struct slice_mask mask_512k;
slice_mask        220 arch/powerpc/include/asm/nohash/32/mmu-8xx.h 	struct slice_mask mask_8m;
slice_mask        256 arch/powerpc/include/asm/nohash/32/mmu-8xx.h static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
slice_mask         34 arch/powerpc/mm/slice.c static void slice_print_mask(const char *label, const struct slice_mask *mask)
slice_mask         48 arch/powerpc/mm/slice.c static void slice_print_mask(const char *label, const struct slice_mask *mask) {}
slice_mask         61 arch/powerpc/mm/slice.c 				struct slice_mask *ret)
slice_mask        117 arch/powerpc/mm/slice.c static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret,
slice_mask        139 arch/powerpc/mm/slice.c 			   const struct slice_mask *available,
slice_mask        188 arch/powerpc/mm/slice.c 				const struct slice_mask *mask, int psize)
slice_mask        193 arch/powerpc/mm/slice.c 	struct slice_mask *psize_mask, *old_mask;
slice_mask        262 arch/powerpc/mm/slice.c 				 const struct slice_mask *available,
slice_mask        280 arch/powerpc/mm/slice.c 					      const struct slice_mask *available,
slice_mask        326 arch/powerpc/mm/slice.c 					     const struct slice_mask *available,
slice_mask        385 arch/powerpc/mm/slice.c 				     const struct slice_mask *mask, int psize,
slice_mask        394 arch/powerpc/mm/slice.c static inline void slice_copy_mask(struct slice_mask *dst,
slice_mask        395 arch/powerpc/mm/slice.c 					const struct slice_mask *src)
slice_mask        403 arch/powerpc/mm/slice.c static inline void slice_or_mask(struct slice_mask *dst,
slice_mask        404 arch/powerpc/mm/slice.c 					const struct slice_mask *src1,
slice_mask        405 arch/powerpc/mm/slice.c 					const struct slice_mask *src2)
slice_mask        413 arch/powerpc/mm/slice.c static inline void slice_andnot_mask(struct slice_mask *dst,
slice_mask        414 arch/powerpc/mm/slice.c 					const struct slice_mask *src1,
slice_mask        415 arch/powerpc/mm/slice.c 					const struct slice_mask *src2)
slice_mask        433 arch/powerpc/mm/slice.c 	struct slice_mask good_mask;
slice_mask        434 arch/powerpc/mm/slice.c 	struct slice_mask potential_mask;
slice_mask        435 arch/powerpc/mm/slice.c 	const struct slice_mask *maskp;
slice_mask        436 arch/powerpc/mm/slice.c 	const struct slice_mask *compat_maskp = NULL;
slice_mask        684 arch/powerpc/mm/slice.c 	struct slice_mask *mask;
slice_mask        732 arch/powerpc/mm/slice.c 	struct slice_mask mask;
slice_mask        763 arch/powerpc/mm/slice.c 	const struct slice_mask *maskp;
slice_mask        772 arch/powerpc/mm/slice.c 		const struct slice_mask *compat_maskp;
slice_mask        773 arch/powerpc/mm/slice.c 		struct slice_mask available;
slice_mask         62 drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h 	unsigned int slice_mask;
slice_mask        321 drivers/crypto/qat/qat_common/qat_hal.c 	ae_reset_csr |= handle->hal_handle->slice_mask << RST_CSR_QAT_LSB;
slice_mask        493 drivers/crypto/qat/qat_common/qat_hal.c 	ae_reset_csr &= ~(handle->hal_handle->slice_mask << RST_CSR_QAT_LSB);
slice_mask        500 drivers/crypto/qat/qat_common/qat_hal.c 		 (handle->hal_handle->slice_mask << RST_CSR_QAT_LSB)) & csr);
slice_mask        504 drivers/crypto/qat/qat_common/qat_hal.c 	clk_csr |= handle->hal_handle->slice_mask << 20;
slice_mask        731 drivers/crypto/qat/qat_common/qat_hal.c 	handle->hal_handle->slice_mask = hw_data->accel_mask;
slice_mask       1212 drivers/gpu/drm/i915/gem/i915_gem_context.c 	if (!user->slice_mask || !user->subslice_mask ||
slice_mask       1224 drivers/gpu/drm/i915/gem/i915_gem_context.c 	if (overflows_type(user->slice_mask, context->slice_mask) ||
slice_mask       1233 drivers/gpu/drm/i915/gem/i915_gem_context.c 	if (user->slice_mask & ~device->slice_mask)
slice_mask       1242 drivers/gpu/drm/i915/gem/i915_gem_context.c 	context->slice_mask = user->slice_mask;
slice_mask       1249 drivers/gpu/drm/i915/gem/i915_gem_context.c 		unsigned int hw_s = hweight8(device->slice_mask);
slice_mask       1251 drivers/gpu/drm/i915/gem/i915_gem_context.c 		unsigned int req_s = hweight8(context->slice_mask);
slice_mask       2195 drivers/gpu/drm/i915/gem/i915_gem_context.c 	user_sseu.slice_mask = ce->sseu.slice_mask;
slice_mask        839 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	unsigned int slices = hweight32(ce->engine->sseu.slice_mask);
slice_mask        895 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			    hweight32(sseu.slice_mask), spin);
slice_mask        925 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	if (hweight32(engine->sseu.slice_mask) < 2)
slice_mask        933 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	pg_sseu.slice_mask = 1;
slice_mask        938 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		name, flags, hweight32(engine->sseu.slice_mask),
slice_mask        939 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		hweight32(pg_sseu.slice_mask));
slice_mask        589 drivers/gpu/drm/i915/gt/intel_engine_types.h 	 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
slice_mask         65 drivers/gpu/drm/i915/gt/intel_sseu.c 			ctx_sseu.slice_mask = 0x1;
slice_mask         69 drivers/gpu/drm/i915/gt/intel_sseu.c 	slices = hweight8(ctx_sseu.slice_mask);
slice_mask         20 drivers/gpu/drm/i915/gt/intel_sseu.h 	u8 slice_mask;
slice_mask         47 drivers/gpu/drm/i915/gt/intel_sseu.h 	u8 slice_mask;
slice_mask         57 drivers/gpu/drm/i915/gt/intel_sseu.h 		.slice_mask = sseu->slice_mask,
slice_mask        787 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
slice_mask        798 drivers/gpu/drm/i915/gt/intel_workarounds.c 	slice = fls(sseu->slice_mask) - 1;
slice_mask        101 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 	blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
slice_mask       3748 drivers/gpu/drm/i915/i915_debugfs.c 		sseu->slice_mask = BIT(0);
slice_mask       3796 drivers/gpu/drm/i915/i915_debugfs.c 		sseu->slice_mask |= BIT(s);
slice_mask       3845 drivers/gpu/drm/i915/i915_debugfs.c 		sseu->slice_mask |= BIT(s);
slice_mask       3879 drivers/gpu/drm/i915/i915_debugfs.c 	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
slice_mask       3881 drivers/gpu/drm/i915/i915_debugfs.c 	if (sseu->slice_mask) {
slice_mask       3884 drivers/gpu/drm/i915/i915_debugfs.c 		for (s = 0; s < fls(sseu->slice_mask); s++) {
slice_mask       3892 drivers/gpu/drm/i915/i915_debugfs.c 		for (s = 0; s < fls(sseu->slice_mask); s++) {
slice_mask       3909 drivers/gpu/drm/i915/i915_debugfs.c 		   sseu->slice_mask);
slice_mask       3911 drivers/gpu/drm/i915/i915_debugfs.c 		   hweight8(sseu->slice_mask));
slice_mask       3914 drivers/gpu/drm/i915/i915_debugfs.c 	for (s = 0; s < fls(sseu->slice_mask); s++) {
slice_mask        144 drivers/gpu/drm/i915/i915_getparam.c 		value = sseu->slice_mask;
slice_mask         50 drivers/gpu/drm/i915/i915_query.c 	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_mask         52 drivers/gpu/drm/i915/i915_query.c 	slice_length = sizeof(sseu->slice_mask);
slice_mask         81 drivers/gpu/drm/i915/i915_query.c 			   &sseu->slice_mask, slice_length))
slice_mask         93 drivers/gpu/drm/i915/intel_device_info.c 		   hweight8(sseu->slice_mask), sseu->slice_mask);
slice_mask        214 drivers/gpu/drm/i915/intel_device_info.c 			sseu->slice_mask |= BIT(s);
slice_mask        239 drivers/gpu/drm/i915/intel_device_info.c 	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
slice_mask        316 drivers/gpu/drm/i915/intel_device_info.c 	sseu->slice_mask = BIT(0);
slice_mask        372 drivers/gpu/drm/i915/intel_device_info.c 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
slice_mask        392 drivers/gpu/drm/i915/intel_device_info.c 		if (!(sseu->slice_mask & BIT(s)))
slice_mask        446 drivers/gpu/drm/i915/intel_device_info.c 		!IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
slice_mask        475 drivers/gpu/drm/i915/intel_device_info.c 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
slice_mask        501 drivers/gpu/drm/i915/intel_device_info.c 		if (!(sseu->slice_mask & BIT(s)))
slice_mask        546 drivers/gpu/drm/i915/intel_device_info.c 	sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
slice_mask        566 drivers/gpu/drm/i915/intel_device_info.c 		sseu->slice_mask = BIT(0);
slice_mask        570 drivers/gpu/drm/i915/intel_device_info.c 		sseu->slice_mask = BIT(0);
slice_mask        574 drivers/gpu/drm/i915/intel_device_info.c 		sseu->slice_mask = BIT(0) | BIT(1);
slice_mask        580 drivers/gpu/drm/i915/intel_device_info.c 	sseu->max_slices = hweight8(sseu->slice_mask);
slice_mask       1610 include/uapi/drm/i915_drm.h 	__u64 slice_mask;
slice_mask       1610 tools/include/uapi/drm/i915_drm.h 	__u64 slice_mask;