CVMX_CACHE_LINE_SIZE 309 arch/mips/cavium-octeon/executive/cvmx-l2c.c len -= CVMX_CACHE_LINE_SIZE; CVMX_CACHE_LINE_SIZE 310 arch/mips/cavium-octeon/executive/cvmx-l2c.c ptr += CVMX_CACHE_LINE_SIZE; CVMX_CACHE_LINE_SIZE 394 arch/mips/cavium-octeon/executive/cvmx-l2c.c fault_in(addr, CVMX_CACHE_LINE_SIZE); CVMX_CACHE_LINE_SIZE 425 arch/mips/cavium-octeon/executive/cvmx-l2c.c start += CVMX_CACHE_LINE_SIZE; CVMX_CACHE_LINE_SIZE 426 arch/mips/cavium-octeon/executive/cvmx-l2c.c len -= CVMX_CACHE_LINE_SIZE; CVMX_CACHE_LINE_SIZE 515 arch/mips/cavium-octeon/executive/cvmx-l2c.c start += CVMX_CACHE_LINE_SIZE; CVMX_CACHE_LINE_SIZE 516 arch/mips/cavium-octeon/executive/cvmx-l2c.c len -= CVMX_CACHE_LINE_SIZE; CVMX_CACHE_LINE_SIZE 764 arch/mips/cavium-octeon/executive/cvmx-l2c.c CVMX_CACHE_LINE_SIZE; CVMX_CACHE_LINE_SIZE 912 arch/mips/cavium-octeon/executive/cvmx-l2c.c index * CVMX_CACHE_LINE_SIZE), CVMX_CACHE_LINE_SIZE 24 arch/mips/include/asm/octeon/cvmx-config.h #define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE) CVMX_CACHE_LINE_SIZE 25 arch/mips/include/asm/octeon/cvmx-config.h #define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE) CVMX_CACHE_LINE_SIZE 26 arch/mips/include/asm/octeon/cvmx-config.h #define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE) CVMX_CACHE_LINE_SIZE 27 arch/mips/include/asm/octeon/cvmx-config.h #define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE) CVMX_CACHE_LINE_SIZE 28 arch/mips/include/asm/octeon/cvmx-config.h #define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE) CVMX_CACHE_LINE_SIZE 29 arch/mips/include/asm/octeon/cvmx-config.h #define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE) CVMX_CACHE_LINE_SIZE 30 arch/mips/include/asm/octeon/cvmx-config.h #define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE) CVMX_CACHE_LINE_SIZE 31 arch/mips/include/asm/octeon/cvmx-config.h #define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE) CVMX_CACHE_LINE_SIZE 88 arch/mips/include/asm/octeon/cvmx.h #define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ CVMX_CACHE_LINE_SIZE 89 arch/mips/include/asm/octeon/cvmx.h #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE))) CVMX_CACHE_LINE_SIZE 63 drivers/mmc/host/cavium-octeon.c end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE); CVMX_CACHE_LINE_SIZE 64 drivers/mmc/host/cavium-octeon.c start = ALIGN(start, CVMX_CACHE_LINE_SIZE); CVMX_CACHE_LINE_SIZE 68 drivers/mmc/host/cavium-octeon.c start += CVMX_CACHE_LINE_SIZE; CVMX_CACHE_LINE_SIZE 79 drivers/mmc/host/cavium-octeon.c end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE); CVMX_CACHE_LINE_SIZE 80 drivers/mmc/host/cavium-octeon.c start = ALIGN(start, CVMX_CACHE_LINE_SIZE); CVMX_CACHE_LINE_SIZE 84 drivers/mmc/host/cavium-octeon.c start += CVMX_CACHE_LINE_SIZE;