CVAL 877 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); CVAL 878 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); CVAL 879 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); CVAL 880 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); CVAL 881 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); CVAL 895 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr)); CVAL 896 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb)); CVAL 897 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg)); CVAL 898 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr)); CVAL 899 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb)); CVAL 694 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); CVAL 695 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); CVAL 696 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); CVAL 697 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); CVAL 698 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); CVAL 38 fs/cifs/smbencrypt.c #define SSVALX(buf,pos,val) (CVAL(buf,pos)=(val)&0xFF,CVAL(buf,pos+1)=(val)>>8)