sif_write_mask    103 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,
sif_write_mask    119 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
sif_write_mask    120 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
sif_write_mask    144 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 		sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,
sif_write_mask    191 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
sif_write_mask    192 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);
sif_write_mask    193 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
sif_write_mask    230 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c 	sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,