shadow_regs        35 arch/powerpc/platforms/cell/pmu.c 		struct cbe_pmd_shadow_regs *shadow_regs;	\
shadow_regs        37 arch/powerpc/platforms/cell/pmu.c 		shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);	\
shadow_regs        39 arch/powerpc/platforms/cell/pmu.c 		shadow_regs->reg = _x;				\
shadow_regs        44 arch/powerpc/platforms/cell/pmu.c 		struct cbe_pmd_shadow_regs *shadow_regs;	\
shadow_regs        45 arch/powerpc/platforms/cell/pmu.c 		shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);	\
shadow_regs        46 arch/powerpc/platforms/cell/pmu.c 		(val) = shadow_regs->reg;			\
shadow_regs        82 arch/powerpc/platforms/cell/pmu.c 	struct cbe_pmd_shadow_regs *shadow_regs;
shadow_regs       100 arch/powerpc/platforms/cell/pmu.c 			shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
shadow_regs       101 arch/powerpc/platforms/cell/pmu.c 			shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
shadow_regs       298 arch/powerpc/platforms/cell/pmu.c 	struct cbe_pmd_shadow_regs *shadow_regs;
shadow_regs       301 arch/powerpc/platforms/cell/pmu.c 	shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
shadow_regs       302 arch/powerpc/platforms/cell/pmu.c 	shadow_regs->counter_value_in_latch = 0;
shadow_regs        70 drivers/regulator/max8660.c 	u8 shadow_regs[MAX8660_N_REGS];		/* as chip is write only */
shadow_regs        80 drivers/regulator/max8660.c 	u8 reg_val = (max8660->shadow_regs[reg] & mask) | val;
shadow_regs        88 drivers/regulator/max8660.c 		max8660->shadow_regs[reg] = reg_val;
shadow_regs       101 drivers/regulator/max8660.c 	u8 val = max8660->shadow_regs[MAX8660_OVER1];
shadow_regs       127 drivers/regulator/max8660.c 	u8 selector = max8660->shadow_regs[reg];
shadow_regs       166 drivers/regulator/max8660.c 	u8 selector = max8660->shadow_regs[MAX8660_MDTV2];
shadow_regs       199 drivers/regulator/max8660.c 	u8 val = max8660->shadow_regs[MAX8660_OVER2];
shadow_regs       225 drivers/regulator/max8660.c 	u8 selector = (max8660->shadow_regs[MAX8660_L12VCR] >> shift) & 0xf;
shadow_regs       412 drivers/regulator/max8660.c 		max8660->shadow_regs[MAX8660_OVER1] = 5;
shadow_regs       424 drivers/regulator/max8660.c 	max8660->shadow_regs[MAX8660_ADTV1] =
shadow_regs       425 drivers/regulator/max8660.c 		max8660->shadow_regs[MAX8660_ADTV2] =
shadow_regs       426 drivers/regulator/max8660.c 		max8660->shadow_regs[MAX8660_SDTV1] =
shadow_regs       427 drivers/regulator/max8660.c 		max8660->shadow_regs[MAX8660_SDTV2] = 0x1b;
shadow_regs       428 drivers/regulator/max8660.c 	max8660->shadow_regs[MAX8660_MDTV1] =
shadow_regs       429 drivers/regulator/max8660.c 		max8660->shadow_regs[MAX8660_MDTV2] = 0x04;
shadow_regs       441 drivers/regulator/max8660.c 				max8660->shadow_regs[MAX8660_OVER1] |= 1;
shadow_regs       446 drivers/regulator/max8660.c 				max8660->shadow_regs[MAX8660_OVER1] |= 4;
shadow_regs       454 drivers/regulator/max8660.c 				max8660->shadow_regs[MAX8660_OVER2] |= 2;
shadow_regs       464 drivers/regulator/max8660.c 				max8660->shadow_regs[MAX8660_OVER2] |= 4;
shadow_regs       694 drivers/scsi/qla4xxx/ql4_def.h 	struct shadow_regs *shadow_regs;
shadow_regs       125 drivers/scsi/qla4xxx/ql4_init.c 		ha->shadow_regs->req_q_out = __constant_cpu_to_le32(0);
shadow_regs       126 drivers/scsi/qla4xxx/ql4_init.c 		ha->shadow_regs->rsp_q_in = __constant_cpu_to_le32(0);
shadow_regs      4158 drivers/scsi/qla4xxx/ql4_os.c 	ha->shadow_regs = NULL;
shadow_regs      4208 drivers/scsi/qla4xxx/ql4_os.c 			  sizeof(struct shadow_regs) +
shadow_regs      4240 drivers/scsi/qla4xxx/ql4_os.c 	ha->shadow_regs = (struct shadow_regs *) (ha->queues + align +
shadow_regs      5691 drivers/scsi/qla4xxx/ql4_os.c 	return (uint16_t)le32_to_cpu(ha->shadow_regs->req_q_out);
shadow_regs      5701 drivers/scsi/qla4xxx/ql4_os.c 	return (uint16_t)le32_to_cpu(ha->shadow_regs->rsp_q_in);