CTX_REG          3210 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
CTX_REG          3218 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
CTX_REG          3219 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
CTX_REG          3220 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
CTX_REG          3221 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
CTX_REG          3223 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
CTX_REG          3224 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
CTX_REG          3225 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
CTX_REG          3226 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
CTX_REG          3227 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
CTX_REG          3228 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
CTX_REG          3232 drivers/gpu/drm/i915/gt/intel_lrc.c 		CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
CTX_REG          3233 drivers/gpu/drm/i915/gt/intel_lrc.c 		CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
CTX_REG          3246 drivers/gpu/drm/i915/gt/intel_lrc.c 		CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
CTX_REG          3257 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
CTX_REG          3259 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
CTX_REG          3260 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
CTX_REG          3261 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0);
CTX_REG          3262 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0);
CTX_REG          3263 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0);
CTX_REG          3264 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0);
CTX_REG          3265 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0);
CTX_REG          3266 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0);
CTX_REG          3283 drivers/gpu/drm/i915/gt/intel_lrc.c 		CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
CTX_REG          1695 drivers/gpu/drm/i915/i915_perf.c 	CTX_REG(reg_state, ctx_oactxctrl, GEN8_OACTXCONTROL,
CTX_REG          1701 drivers/gpu/drm/i915/i915_perf.c 		CTX_REG(reg_state, ctx_flexeu0 + i * 2, flex_regs[i],
CTX_REG          1705 drivers/gpu/drm/i915/i915_perf.c 	CTX_REG(reg_state,