setbits32 101 arch/powerpc/platforms/44x/canyonlands.c setbits32((vaddr + GPIO0_OSRH), 0x42000000); setbits32 102 arch/powerpc/platforms/44x/canyonlands.c setbits32((vaddr + GPIO0_TSRH), 0x42000000); setbits32 73 arch/powerpc/platforms/4xx/gpio.c setbits32(®s->or, GPIO_MASK(gpio)); setbits32 139 arch/powerpc/platforms/4xx/gpio.c setbits32(®s->tcr, GPIO_MASK(gpio)); setbits32 36 arch/powerpc/platforms/512x/pdm360ng.c setbits32(pdm360ng_gpio_base + 0xc, 0x40); setbits32 67 arch/powerpc/platforms/512x/pdm360ng.c setbits32(pdm360ng_gpio_base + 0x18, 0x2000); setbits32 68 arch/powerpc/platforms/512x/pdm360ng.c setbits32(pdm360ng_gpio_base + 0x10, 0x40); setbits32 317 arch/powerpc/platforms/52xx/mpc52xx_common.c setbits32(&simple_gpio->simple_gpioe, sync | out); setbits32 320 arch/powerpc/platforms/52xx/mpc52xx_common.c setbits32(&simple_gpio->simple_ddr, sync | out); setbits32 141 arch/powerpc/platforms/52xx/mpc52xx_gpt.c setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); setbits32 156 arch/powerpc/platforms/82xx/km82xx.c setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10)); setbits32 164 arch/powerpc/platforms/82xx/mpc8272_ads.c setbits32(&bcsr[1], BCSR1_FETH_RST); setbits32 167 arch/powerpc/platforms/82xx/mpc8272_ads.c setbits32(&bcsr[3], BCSR3_FETH2_RST); setbits32 24 arch/powerpc/platforms/82xx/pq2.c setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); setbits32 47 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c setbits32(&priv->regs->mask, 1 << irq); setbits32 141 arch/powerpc/platforms/82xx/pq2fads.c setbits32(&bcsr[1], BCSR1_FETH_RST); setbits32 144 arch/powerpc/platforms/82xx/pq2fads.c setbits32(&bcsr[3], BCSR3_FETH2_RST); setbits32 100 arch/powerpc/platforms/83xx/km83xx.c setbits32((base + 0xa8), 0x00003000); setbits32 106 arch/powerpc/platforms/83xx/km83xx.c setbits32((base + 0xa8), 0x0c000000); setbits32 112 arch/powerpc/platforms/83xx/km83xx.c setbits32((base + 0xac), 0x0000c000); setbits32 117 arch/powerpc/platforms/83xx/mpc836x_mds.c setbits32(immap, 0x0c003000); setbits32 261 arch/powerpc/platforms/85xx/mpc85xx_mds.c setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | setbits32 59 arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c setbits32(&guts->devdisr, mask); setbits32 114 arch/powerpc/platforms/85xx/mpc85xx_rdb.c setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | setbits32 412 arch/powerpc/platforms/85xx/p1022_ds.c setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); setbits32 82 arch/powerpc/platforms/85xx/p1022_rdk.c setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); setbits32 117 arch/powerpc/platforms/85xx/t1042rdb_diu.c setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16)); setbits32 94 arch/powerpc/platforms/85xx/twr_p102x.c setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | setbits32 264 arch/powerpc/platforms/86xx/mpc8610_hpcd.c setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); setbits32 70 arch/powerpc/platforms/8xx/cpm1.c setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); setbits32 193 arch/powerpc/platforms/8xx/cpm1.c setbits32(&cpic_reg->cpic_cicr, CICR_IEN); setbits32 322 arch/powerpc/platforms/8xx/cpm1.c setbits32(&iop->dir, pin); setbits32 327 arch/powerpc/platforms/8xx/cpm1.c setbits32(&iop->par, pin); setbits32 340 arch/powerpc/platforms/8xx/cpm1.c setbits32(&iop->sor, pin); setbits32 345 arch/powerpc/platforms/8xx/cpm1.c setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); setbits32 737 arch/powerpc/platforms/8xx/cpm1.c setbits32(&iop->dir, pin_mask); setbits32 106 arch/powerpc/platforms/8xx/m8xx_setup.c setbits32(&clk_r2->car_sccr, 0x02000000); setbits32 207 arch/powerpc/platforms/8xx/m8xx_setup.c setbits32(&clk_r->car_plprcr, 0x00000080); setbits32 153 arch/powerpc/platforms/8xx/mpc885ads_setup.c setbits32(&bcsr[1], BCSR1_RS232EN_2); setbits32 159 arch/powerpc/platforms/8xx/mpc885ads_setup.c setbits32(bcsr5, BCSR5_MII1_RST); setbits32 165 arch/powerpc/platforms/8xx/mpc885ads_setup.c setbits32(bcsr5, BCSR5_MII2_RST); setbits32 169 arch/powerpc/platforms/8xx/mpc885ads_setup.c setbits32(bcsr5, BCSR5_MII2_EN); setbits32 175 arch/powerpc/platforms/8xx/mpc885ads_setup.c setbits32(&bcsr[4], BCSR4_ETH10_RST); setbits32 177 arch/powerpc/platforms/8xx/mpc885ads_setup.c setbits32(&bcsr[1], BCSR1_ETHEN); setbits32 78 arch/powerpc/platforms/embedded6xx/flipper-pic.c setbits32(io_base + FLIPPER_IMR, 1 << irq); setbits32 73 arch/powerpc/platforms/embedded6xx/hlwd-pic.c setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); setbits32 136 arch/powerpc/platforms/embedded6xx/wii.c setbits32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN); setbits32 139 arch/powerpc/platforms/embedded6xx/wii.c setbits32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN); setbits32 338 arch/powerpc/sysdev/cpm2.c setbits32(&iop[port].dir, pin); setbits32 343 arch/powerpc/sysdev/cpm2.c setbits32(&iop[port].par, pin); setbits32 348 arch/powerpc/sysdev/cpm2.c setbits32(&iop[port].sor, pin); setbits32 353 arch/powerpc/sysdev/cpm2.c setbits32(&iop[port].odr, pin); setbits32 165 arch/powerpc/sysdev/cpm_common.c setbits32(&iop->dir, pin_mask); setbits32 114 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c setbits32(&l2ctlr->ctl, setbits32 119 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c setbits32(&l2ctlr->ctl, setbits32 124 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c setbits32(&l2ctlr->ctl, setbits32 130 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c setbits32(&l2ctlr->ctl, setbits32 191 arch/powerpc/sysdev/fsl_lbc.c setbits32(&lbc->ltesr, LTESR_CLEAR); setbits32 1200 arch/powerpc/sysdev/fsl_pci.c setbits32(&pci->pex_pme_mes_ier, setbits32 1218 arch/powerpc/sysdev/fsl_pci.c setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); setbits32 1254 arch/powerpc/sysdev/fsl_pci.c setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); setbits32 36 arch/powerpc/sysdev/fsl_pmc.c setbits32(&pmc_regs->pmcsr, PMCSR_SLP); setbits32 32 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cpmimr, mask); setbits32 33 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cpmcimr, mask); setbits32 34 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cpmmcmr, mask); setbits32 35 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cpmnmimr, mask); setbits32 43 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tpmimr0, mask); setbits32 44 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tpmcimr0, mask); setbits32 45 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tpmmcmr0, mask); setbits32 46 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tpmnmimr0, mask); setbits32 74 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->ippdexpcr, mask); setbits32 82 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->ippdexpcr[0], mask); setbits32 94 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cdozcr, mask); setbits32 97 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cnapcr, mask); setbits32 113 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu); setbits32 116 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph15setr, mask); setbits32 119 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph20setr, mask); setbits32 122 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph30setr, mask); setbits32 195 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu); setbits32 198 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph15clrr, mask); setbits32 201 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph20clrr, mask); setbits32 204 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph30clrr, mask); setbits32 225 arch/powerpc/sysdev/fsl_rcpm.c setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP); setbits32 252 arch/powerpc/sysdev/fsl_rcpm.c setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST); setbits32 254 arch/powerpc/sysdev/fsl_rcpm.c setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ); setbits32 292 arch/powerpc/sysdev/fsl_rcpm.c setbits32(tben_reg, mask); setbits32 667 arch/powerpc/sysdev/fsl_rio.c setbits32(priv->regs_win setbits32 670 arch/powerpc/sysdev/fsl_rio.c setbits32(priv->regs_win setbits32 354 arch/powerpc/sysdev/fsl_rmu.c setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); setbits32 907 arch/powerpc/sysdev/fsl_rmu.c setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); setbits32 910 arch/powerpc/sysdev/fsl_rmu.c setbits32(&rmu->msg_regs->imr, 0x1); setbits32 1013 arch/powerpc/sysdev/fsl_rmu.c setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); setbits32 153 arch/powerpc/sysdev/mpic_timer.c setbits32(priv->group_tcr, tcr); setbits32 268 arch/powerpc/sysdev/mpic_timer.c setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP); setbits32 507 arch/powerpc/sysdev/mpic_timer.c setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); setbits32 530 arch/powerpc/sysdev/mpic_timer.c setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); setbits32 145 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, setbits32 152 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR, setbits32 166 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE | setbits32 170 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, setbits32 175 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, setbits32 188 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_MCR, mcr); setbits32 196 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_MCR, mcr); setbits32 242 drivers/crypto/talitos.c setbits32(priv->reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE); setbits32 244 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT); setbits32 245 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT); setbits32 250 drivers/crypto/talitos.c setbits32(priv->reg_mdeu + TALITOS_EUICR_LO, setbits32 450 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ setbits32 451 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT); \ setbits32 644 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR, setbits32 646 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0); setbits32 697 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ setbits32 788 drivers/crypto/talitos.c setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR); setbits32 799 drivers/crypto/talitos.c setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0); setbits32 283 drivers/i2c/busses/i2c-mpc.c setbits32(ctrl, 1 << (24 + idx * 2)); setbits32 815 drivers/mtd/nand/raw/fsl_elbc_nand.c setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); setbits32 162 drivers/net/ethernet/freescale/fs_enet/mii-fec.c setbits32(&fec->fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); setbits32 163 drivers/net/ethernet/freescale/fs_enet/mii-fec.c setbits32(&fec->fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | setbits32 1124 drivers/net/ethernet/freescale/ucc_geth.c setbits32(upsmr_register, automatic_flow_control_mode); setbits32 1145 drivers/net/ethernet/freescale/ucc_geth.c setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); setbits32 1181 drivers/net/ethernet/freescale/ucc_geth.c setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); setbits32 2009 drivers/net/ethernet/freescale/ucc_geth.c setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); setbits32 2451 drivers/net/ethernet/freescale/ucc_geth.c setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); setbits32 3301 drivers/net/ethernet/freescale/ucc_geth.c setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS); setbits32 3577 drivers/net/ethernet/freescale/ucc_geth.c setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); setbits32 3578 drivers/net/ethernet/freescale/ucc_geth.c setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); setbits32 112 drivers/soc/fsl/qe/ucc.c setbits32(cmxucr, mask << shift); setbits32 184 drivers/spi/spi-mpc512x-psc.c setbits32(&fifo->txcmd, setbits32 432 drivers/tty/serial/cpm_uart/cpm_uart_core.c setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); setbits32 851 drivers/tty/serial/cpm_uart/cpm_uart_core.c setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); setbits32 1364 drivers/video/fbdev/fsl-diu-fb.c setbits32(&data->diu_reg->gamma, 0); /* Force table reload */