set_drr           293 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.set_drr(&pipe,
set_drr          1374 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->stream_res.tg->funcs->set_drr)
set_drr          1375 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->stream_res.tg->funcs->set_drr(
set_drr          1738 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx[i]->stream_res.tg->funcs->set_drr(
set_drr          2759 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	.set_drr = set_drr,
set_drr          2233 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 		.set_drr =
set_drr          1230 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		.set_drr = dce120_timing_generator_set_drr,
set_drr           211 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c 		.set_drr = dce110_timing_generator_set_drr,
set_drr           858 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (pipe_ctx->stream_res.tg->funcs->set_drr)
set_drr           859 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->stream_res.tg->funcs->set_drr(
set_drr          2768 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx[i]->stream_res.tg->funcs->set_drr(
set_drr          3343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	.set_drr = dcn10_set_drr,
set_drr          1503 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		.set_drr = optc1_set_drr,
set_drr           601 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe_ctx->stream_res.tg->funcs->set_drr)
set_drr           602 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->stream_res.tg->funcs->set_drr(
set_drr          1676 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if (pipe_ctx->stream_res.tg->funcs->set_drr)
set_drr          1677 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->stream_res.tg->funcs->set_drr(
set_drr           447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		.set_drr = optc1_set_drr,
set_drr           211 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 	void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
set_drr           240 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,