seen_reg          571 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_RA, ctx)) {
seen_reg          577 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S1, ctx)) {
seen_reg          581 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S2, ctx)) {
seen_reg          585 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S3, ctx)) {
seen_reg          589 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S4, ctx)) {
seen_reg          593 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S5, ctx)) {
seen_reg          597 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S6, ctx)) {
seen_reg         1439 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_RA, ctx))
seen_reg         1442 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S1, ctx))
seen_reg         1444 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S2, ctx))
seen_reg         1446 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S3, ctx))
seen_reg         1448 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S4, ctx))
seen_reg         1450 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S5, ctx))
seen_reg         1452 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S6, ctx))
seen_reg         1467 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_RA, ctx)) {
seen_reg         1473 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S1, ctx)) {
seen_reg         1477 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S2, ctx)) {
seen_reg         1481 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S3, ctx)) {
seen_reg         1485 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S4, ctx)) {
seen_reg         1489 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S5, ctx)) {
seen_reg         1493 arch/riscv/net/bpf_jit_comp.c 	if (seen_reg(RV_REG_S6, ctx)) {
seen_reg           36 arch/s390/net/bpf_jit_comp.c 	u32 seen_reg[16];	/* Array to remember which registers are used */
seen_reg          117 arch/s390/net/bpf_jit_comp.c 	if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
seen_reg          118 arch/s390/net/bpf_jit_comp.c 		jit->seen_reg[r1] = 1;
seen_reg          126 arch/s390/net/bpf_jit_comp.c #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
seen_reg          359 arch/s390/net/bpf_jit_comp.c 		if (jit->seen_reg[i])
seen_reg          373 arch/s390/net/bpf_jit_comp.c 		if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
seen_reg          376 arch/s390/net/bpf_jit_comp.c 	return jit->seen_reg[15] ? 15 : 14;