sdma_v5_0_get_reg_offset  302 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
sdma_v5_0_get_reg_offset  303 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
sdma_v5_0_get_reg_offset  349 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
sdma_v5_0_get_reg_offset  351 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
sdma_v5_0_get_reg_offset  510 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
sdma_v5_0_get_reg_offset  512 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
sdma_v5_0_get_reg_offset  513 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
sdma_v5_0_get_reg_offset  515 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
sdma_v5_0_get_reg_offset  572 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
sdma_v5_0_get_reg_offset  576 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
sdma_v5_0_get_reg_offset  578 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
sdma_v5_0_get_reg_offset  580 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
sdma_v5_0_get_reg_offset  583 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
sdma_v5_0_get_reg_offset  607 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sdma_v5_0_get_reg_offset  609 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
sdma_v5_0_get_reg_offset  638 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
sdma_v5_0_get_reg_offset  642 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
sdma_v5_0_get_reg_offset  649 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
sdma_v5_0_get_reg_offset  652 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
sdma_v5_0_get_reg_offset  653 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
sdma_v5_0_get_reg_offset  654 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
sdma_v5_0_get_reg_offset  655 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
sdma_v5_0_get_reg_offset  659 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
sdma_v5_0_get_reg_offset  661 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
sdma_v5_0_get_reg_offset  663 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
sdma_v5_0_get_reg_offset  668 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
sdma_v5_0_get_reg_offset  672 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
sdma_v5_0_get_reg_offset  674 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
sdma_v5_0_get_reg_offset  679 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
sdma_v5_0_get_reg_offset  680 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
sdma_v5_0_get_reg_offset  685 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
sdma_v5_0_get_reg_offset  688 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
sdma_v5_0_get_reg_offset  689 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
sdma_v5_0_get_reg_offset  692 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
sdma_v5_0_get_reg_offset  693 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
sdma_v5_0_get_reg_offset  702 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
sdma_v5_0_get_reg_offset  703 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
sdma_v5_0_get_reg_offset  712 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
sdma_v5_0_get_reg_offset  715 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
sdma_v5_0_get_reg_offset  720 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
sdma_v5_0_get_reg_offset  723 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
sdma_v5_0_get_reg_offset  726 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
sdma_v5_0_get_reg_offset  729 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
sdma_v5_0_get_reg_offset  733 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
sdma_v5_0_get_reg_offset  737 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sdma_v5_0_get_reg_offset  739 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
sdma_v5_0_get_reg_offset  744 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
sdma_v5_0_get_reg_offset  746 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
sdma_v5_0_get_reg_offset  752 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
sdma_v5_0_get_reg_offset  817 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
sdma_v5_0_get_reg_offset  822 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
sdma_v5_0_get_reg_offset  825 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
sdma_v5_0_get_reg_offset 1327 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
sdma_v5_0_get_reg_offset 1343 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
sdma_v5_0_get_reg_offset 1344 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
sdma_v5_0_get_reg_offset 1415 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
sdma_v5_0_get_reg_offset 1416 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
sdma_v5_0_get_reg_offset 1484 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
sdma_v5_0_get_reg_offset 1494 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 				WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
sdma_v5_0_get_reg_offset 1497 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
sdma_v5_0_get_reg_offset 1507 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 				WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
sdma_v5_0_get_reg_offset 1521 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
sdma_v5_0_get_reg_offset 1524 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 				WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
sdma_v5_0_get_reg_offset 1528 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
sdma_v5_0_get_reg_offset 1531 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 				WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
sdma_v5_0_get_reg_offset 1576 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
sdma_v5_0_get_reg_offset 1581 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));