scu_base 32 arch/arm/include/asm/smp_scu.h int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu); scu_base 34 arch/arm/include/asm/smp_scu.h static inline unsigned int scu_get_core_count(void __iomem *scu_base) scu_base 38 arch/arm/include/asm/smp_scu.h static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode) scu_base 42 arch/arm/include/asm/smp_scu.h static inline int scu_cpu_power_enable(void __iomem *scu_base, scu_base 47 arch/arm/include/asm/smp_scu.h static inline int scu_get_cpu_power_mode(void __iomem *scu_base, scu_base 55 arch/arm/include/asm/smp_scu.h void scu_enable(void __iomem *scu_base); scu_base 57 arch/arm/include/asm/smp_scu.h static inline void scu_enable(void __iomem *scu_base) {} scu_base 29 arch/arm/kernel/smp_scu.c unsigned int __init scu_get_core_count(void __iomem *scu_base) scu_base 31 arch/arm/kernel/smp_scu.c unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG); scu_base 38 arch/arm/kernel/smp_scu.c void scu_enable(void __iomem *scu_base) scu_base 45 arch/arm/kernel/smp_scu.c scu_ctrl = readl_relaxed(scu_base + 0x30); scu_base 47 arch/arm/kernel/smp_scu.c writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30); scu_base 51 arch/arm/kernel/smp_scu.c scu_ctrl = readl_relaxed(scu_base + SCU_CTRL); scu_base 63 arch/arm/kernel/smp_scu.c writel_relaxed(scu_ctrl, scu_base + SCU_CTRL); scu_base 73 arch/arm/kernel/smp_scu.c static int scu_set_power_mode_internal(void __iomem *scu_base, scu_base 83 arch/arm/kernel/smp_scu.c val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu); scu_base 86 arch/arm/kernel/smp_scu.c writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu); scu_base 99 arch/arm/kernel/smp_scu.c int scu_power_mode(void __iomem *scu_base, unsigned int mode) scu_base 101 arch/arm/kernel/smp_scu.c return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode); scu_base 107 arch/arm/kernel/smp_scu.c int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu) scu_base 109 arch/arm/kernel/smp_scu.c return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL); scu_base 112 arch/arm/kernel/smp_scu.c int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu) scu_base 120 arch/arm/kernel/smp_scu.c val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu); scu_base 38 arch/arm/mach-bcm/bcm63xx_smp.c void __iomem *scu_base; scu_base 53 arch/arm/mach-bcm/bcm63xx_smp.c scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); scu_base 54 arch/arm/mach-bcm/bcm63xx_smp.c if (!scu_base) { scu_base 60 arch/arm/mach-bcm/bcm63xx_smp.c scu_enable(scu_base); scu_base 62 arch/arm/mach-bcm/bcm63xx_smp.c ncores = scu_base ? scu_get_core_count(scu_base) : 1; scu_base 94 arch/arm/mach-bcm/bcm63xx_smp.c iounmap(scu_base); /* That's the last we'll need of this */ scu_base 48 arch/arm/mach-bcm/platsmp.c void __iomem *scu_base; scu_base 62 arch/arm/mach-bcm/platsmp.c scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); scu_base 63 arch/arm/mach-bcm/platsmp.c if (!scu_base) { scu_base 69 arch/arm/mach-bcm/platsmp.c scu_enable(scu_base); scu_base 71 arch/arm/mach-bcm/platsmp.c iounmap(scu_base); /* That's the last we'll need of this */ scu_base 61 arch/arm/mach-berlin/platsmp.c void __iomem *scu_base; scu_base 65 arch/arm/mach-berlin/platsmp.c scu_base = of_iomap(np, 0); scu_base 67 arch/arm/mach-berlin/platsmp.c if (!scu_base) scu_base 80 arch/arm/mach-berlin/platsmp.c scu_enable(scu_base); scu_base 96 arch/arm/mach-berlin/platsmp.c iounmap(scu_base); scu_base 175 arch/arm/mach-exynos/platsmp.c static void __iomem *scu_base; scu_base 177 arch/arm/mach-exynos/platsmp.c if (!scu_base) { scu_base 180 arch/arm/mach-exynos/platsmp.c scu_base = of_iomap(np, 0); scu_base 183 arch/arm/mach-exynos/platsmp.c scu_base = ioremap(scu_a9_get_base(), SZ_4K); scu_base 186 arch/arm/mach-exynos/platsmp.c scu_enable(scu_base); scu_base 42 arch/arm/mach-hisi/platsmp.c void __iomem *scu_base = NULL; scu_base 46 arch/arm/mach-hisi/platsmp.c scu_base = ioremap(base, SZ_4K); scu_base 47 arch/arm/mach-hisi/platsmp.c if (!scu_base) { scu_base 51 arch/arm/mach-hisi/platsmp.c scu_enable(scu_base); scu_base 52 arch/arm/mach-hisi/platsmp.c iounmap(scu_base); scu_base 21 arch/arm/mach-imx/platsmp.c static void __iomem *scu_base; scu_base 40 arch/arm/mach-imx/platsmp.c scu_base = IMX_IO_ADDRESS(base); scu_base 58 arch/arm/mach-imx/platsmp.c ncores = scu_get_core_count(scu_base); scu_base 66 arch/arm/mach-imx/platsmp.c scu_enable(scu_base); scu_base 35 arch/arm/mach-meson/platsmp.c static void __iomem *scu_base; scu_base 93 arch/arm/mach-meson/platsmp.c scu_base = of_iomap(node, 0); scu_base 94 arch/arm/mach-meson/platsmp.c if (!scu_base) { scu_base 99 arch/arm/mach-meson/platsmp.c scu_enable(scu_base); scu_base 129 arch/arm/mach-meson/platsmp.c scu_cpu_power_enable(scu_base, cpu); scu_base 299 arch/arm/mach-meson/platsmp.c scu_power_mode(scu_base, SCU_PM_POWEROFF); scu_base 315 arch/arm/mach-meson/platsmp.c power_mode = scu_get_cpu_power_mode(scu_base, cpu); scu_base 357 arch/arm/mach-meson/platsmp.c power_mode = scu_get_cpu_power_mode(scu_base, cpu); scu_base 36 arch/arm/mach-mvebu/board-v7.c static void __iomem *scu_base; scu_base 47 arch/arm/mach-mvebu/board-v7.c scu_base = of_iomap(np, 0); scu_base 48 arch/arm/mach-mvebu/board-v7.c scu_enable(scu_base); scu_base 55 arch/arm/mach-mvebu/board-v7.c return scu_base; scu_base 58 arch/arm/mach-npcm/platsmp.c void __iomem *scu_base; scu_base 65 arch/arm/mach-npcm/platsmp.c scu_base = of_iomap(scu_np, 0); scu_base 66 arch/arm/mach-npcm/platsmp.c if (!scu_base) { scu_base 71 arch/arm/mach-npcm/platsmp.c scu_enable(scu_base); scu_base 73 arch/arm/mach-npcm/platsmp.c iounmap(scu_base); scu_base 47 arch/arm/mach-omap2/omap-smp.c void __iomem *scu_base; scu_base 71 arch/arm/mach-omap2/omap-smp.c return cfg.scu_base; scu_base 270 arch/arm/mach-omap2/omap-smp.c cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); scu_base 271 arch/arm/mach-omap2/omap-smp.c BUG_ON(!cfg.scu_base); scu_base 272 arch/arm/mach-omap2/omap-smp.c ncores = scu_get_core_count(cfg.scu_base); scu_base 390 arch/arm/mach-omap2/omap-smp.c if (cfg.scu_base) scu_base 391 arch/arm/mach-omap2/omap-smp.c scu_enable(cfg.scu_base); scu_base 34 arch/arm/mach-omap2/pm33xx-core.c static void __iomem *scu_base; scu_base 39 arch/arm/mach-omap2/pm33xx-core.c scu_base = ioremap(scu_a9_get_base(), SZ_256); scu_base 41 arch/arm/mach-omap2/pm33xx-core.c if (!scu_base) scu_base 170 arch/arm/mach-omap2/pm33xx-core.c scu_power_mode(scu_base, SCU_PM_POWEROFF); scu_base 172 arch/arm/mach-omap2/pm33xx-core.c scu_power_mode(scu_base, SCU_PM_NORMAL); scu_base 62 arch/arm/mach-oxnas/platsmp.c void __iomem *scu_base; scu_base 65 arch/arm/mach-oxnas/platsmp.c scu_base = of_iomap(np, 0); scu_base 67 arch/arm/mach-oxnas/platsmp.c if (!scu_base) scu_base 83 arch/arm/mach-oxnas/platsmp.c scu_enable(scu_base); scu_base 87 arch/arm/mach-oxnas/platsmp.c iounmap(scu_base); scu_base 38 arch/arm/mach-realview/platsmp-dt.c void __iomem *scu_base; scu_base 48 arch/arm/mach-realview/platsmp-dt.c scu_base = of_iomap(np, 0); scu_base 50 arch/arm/mach-realview/platsmp-dt.c if (!scu_base) { scu_base 55 arch/arm/mach-realview/platsmp-dt.c scu_enable(scu_base); scu_base 56 arch/arm/mach-realview/platsmp-dt.c ncores = scu_get_core_count(scu_base); scu_base 60 arch/arm/mach-realview/platsmp-dt.c iounmap(scu_base); scu_base 39 arch/arm/mach-spear/platsmp.c static void __iomem *scu_base = IOMEM(VA_SCU_BASE); scu_base 100 arch/arm/mach-spear/platsmp.c unsigned int i, ncores = scu_get_core_count(scu_base); scu_base 115 arch/arm/mach-spear/platsmp.c scu_enable(scu_base); scu_base 52 arch/arm/mach-sti/platsmp.c void __iomem *scu_base; scu_base 59 arch/arm/mach-sti/platsmp.c scu_base = of_iomap(np, 0); scu_base 60 arch/arm/mach-sti/platsmp.c scu_enable(scu_base); scu_base 34 arch/arm/mach-ux500/platsmp.c static void __iomem *scu_base; scu_base 55 arch/arm/mach-ux500/platsmp.c scu_base = of_iomap(np, 0); scu_base 57 arch/arm/mach-ux500/platsmp.c if (!scu_base) { scu_base 62 arch/arm/mach-ux500/platsmp.c scu_enable(scu_base); scu_base 63 arch/arm/mach-ux500/platsmp.c ncores = scu_get_core_count(scu_base); scu_base 66 arch/arm/mach-ux500/platsmp.c iounmap(scu_base); scu_base 39 arch/arm/mach-zx/platsmp.c static void __iomem *scu_base; scu_base 49 arch/arm/mach-zx/platsmp.c scu_base = ioremap(base, SZ_256); scu_base 50 arch/arm/mach-zx/platsmp.c if (!scu_base) { scu_base 55 arch/arm/mach-zx/platsmp.c scu_enable(scu_base); scu_base 163 arch/arm/mach-zx/platsmp.c scu_power_mode(scu_base, SCU_PM_POWEROFF); scu_base 173 arch/arm/mach-zx/platsmp.c scu_power_mode(scu_base, SCU_PM_NORMAL); scu_base 43 drivers/clk/clk-aspeed.c static void __iomem *scu_base; scu_base 444 drivers/clk/clk-aspeed.c scu_base + ASPEED_CLK_SELECTION, 15, 0, scu_base 449 drivers/clk/clk-aspeed.c 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, scu_base 458 drivers/clk/clk-aspeed.c scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, scu_base 467 drivers/clk/clk-aspeed.c scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, scu_base 476 drivers/clk/clk-aspeed.c scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, scu_base 492 drivers/clk/clk-aspeed.c scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0, scu_base 499 drivers/clk/clk-aspeed.c scu_base + ASPEED_CLK_SELECTION, 28, scu_base 620 drivers/clk/clk-aspeed.c scu_base + ASPEED_CLK_SELECTION, 23, 3, 0, scu_base 670 drivers/clk/clk-aspeed.c scu_base = of_iomap(np, 0); scu_base 671 drivers/clk/clk-aspeed.c if (!scu_base) scu_base 210 drivers/gpu/drm/gma500/oaktrail_hdmi.c static void scu_busy_loop(void __iomem *scu_base) scu_base 215 drivers/gpu/drm/gma500/oaktrail_hdmi.c status = readl(scu_base + 0x04); scu_base 218 drivers/gpu/drm/gma500/oaktrail_hdmi.c status = readl(scu_base + 0x04); scu_base 1623 drivers/scsi/isci/host.c void __iomem *scu_base, scu_base 1630 drivers/scsi/isci/host.c ihost->scu_registers = scu_base; scu_base 2347 drivers/scsi/isci/host.c status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost));