CS_SF              49 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
CS_SF              50 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
CS_SF              51 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
CS_SF              52 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
CS_SF              55 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
CS_SF              56 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
CS_SF             100 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
CS_SF             101 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
CS_SF             102 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
CS_SF             103 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
CS_SF             124 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
CS_SF             125 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
CS_SF             126 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
CS_SF             127 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)