s0 448 arch/mips/alchemy/devboards/db1000.c int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1; s0 457 arch/mips/alchemy/devboards/db1000.c s0 = AU1500_GPIO1_INT; s0 464 arch/mips/alchemy/devboards/db1000.c s0 = AU1100_GPIO1_INT; s0 500 arch/mips/alchemy/devboards/db1000.c s0 = AU1000_GPIO1_INT; s0 506 arch/mips/alchemy/devboards/db1000.c s0 = AU1500_GPIO202_INT; s0 519 arch/mips/alchemy/devboards/db1000.c s0 = AU1100_GPIO10_INT; s0 536 arch/mips/alchemy/devboards/db1000.c irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); s0 65 arch/mips/include/asm/asmmacro-32.h LONG_S s0, THREAD_REG16(\thread) s0 78 arch/mips/include/asm/asmmacro-32.h LONG_L s0, THREAD_REG16(\thread) s0 18 arch/mips/include/asm/asmmacro-64.h LONG_S s0, THREAD_REG16(\thread) s0 31 arch/mips/include/asm/asmmacro-64.h LONG_L s0, THREAD_REG16(\thread) s0 23 arch/riscv/include/asm/ptrace.h unsigned long s0; s0 91 arch/riscv/include/asm/ptrace.h return regs->s0; s0 96 arch/riscv/include/asm/ptrace.h regs->s0 = val; s0 28 arch/riscv/include/uapi/asm/ptrace.h unsigned long s0; s0 76 arch/riscv/kernel/asm-offsets.c OFFSET(PT_FP, pt_regs, s0); s0 77 arch/riscv/kernel/asm-offsets.c OFFSET(PT_S0, pt_regs, s0); s0 69 arch/riscv/kernel/perf_callchain.c fp = regs->s0; s0 43 arch/riscv/kernel/process.c regs->t1, regs->t2, regs->s0); s0 102 arch/x86/math-emu/fpu_proto.h extern int poly_l2p1(u_char s0, u_char s1, FPU_REG *r0, FPU_REG *r1, s0 95 crypto/sha512_generic.c W[I & 15] += s1(W[(I-2) & 15]) + W[(I-7) & 15] + s0(W[(I-15) & 15]); s0 76 drivers/devfreq/event/exynos-ppmu.c PPMU_EVENT(drex0-s0), s0 78 drivers/devfreq/event/exynos-ppmu.c PPMU_EVENT(drex1-s0), s0 209 drivers/fsi/fsi-sbefifo.c u32 dh, s0, s1; s0 223 drivers/fsi/fsi-sbefifo.c s0 = be32_to_cpu(response[resp_len - dh]); s0 225 drivers/fsi/fsi-sbefifo.c if (((s0 >> 16) != 0xC0DE) || ((s0 & 0xffff) != cmd)) { s0 227 drivers/fsi/fsi-sbefifo.c cmd >> 8, cmd & 0xff, s0, s1); s0 5829 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; s0 5840 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; s0 5854 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; s0 5864 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; s0 5955 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? s0 6047 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_reg_table->address[i].s0 = s0 6048 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); s0 263 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint16_t s0; s0 313 drivers/gpu/drm/amd/amdgpu/si_dpm.h uint16_t s0; s0 305 drivers/gpu/drm/amd/amdgpu/sislands_smc.h uint16_t s0; s0 352 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h uint16_t s0; s0 357 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint16_t s0; s0 412 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint16_t s0; s0 1732 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c mc_reg_table->address[i].s0 = s0 1733 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); s0 2544 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[i].s0 = s0 2596 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; s0 2608 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; s0 2623 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; s0 2636 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; s0 1699 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c mc_reg_table->address[i].s0 = s0 1700 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); s0 2473 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[i].s0 = s0 2525 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; s0 2537 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; s0 2553 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; s0 2566 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; s0 2077 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mc_reg_table->address[i].s0 = s0 2078 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); s0 2934 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[i].s0 = s0 2989 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; s0 3001 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; s0 3016 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; s0 3028 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; s0 1929 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; s0 1942 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; s0 1958 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; s0 1985 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[i].s0 = s0 4350 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; s0 4361 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; s0 4374 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; s0 4387 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; s0 4501 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[i].s0 = s0 4693 drivers/gpu/drm/radeon/ci_dpm.c mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); s0 956 drivers/gpu/drm/radeon/cypress_dpm.c mc_reg_table->address[i].s0 = s0 957 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); s0 972 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; s0 976 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; s0 980 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; s0 984 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; s0 988 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2; s0 992 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2; s0 996 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2; s0 1000 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2; s0 1004 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; s0 1008 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; s0 1012 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; s0 1016 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2; s0 1020 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2; s0 1024 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2; s0 1174 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value); s0 34 drivers/gpu/drm/radeon/evergreen_smc.h uint16_t s0; s0 2723 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; s0 2734 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; s0 2749 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; s0 2840 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[i].s0 = s0 2932 drivers/gpu/drm/radeon/ni_dpm.c mc_reg_table->address[i].s0 = s0 2933 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s0); s0 254 drivers/gpu/drm/radeon/nislands_smc.h uint16_t s0; s0 5370 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; s0 5381 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; s0 5395 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; s0 5407 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; s0 5501 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? s0 5593 drivers/gpu/drm/radeon/si_dpm.c mc_reg_table->address[i].s0 = s0 5594 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); s0 305 drivers/gpu/drm/radeon/sislands_smc.h uint16_t s0; s0 411 drivers/gpu/drm/radeon/smu7_discrete.h uint16_t s0; s0 4995 drivers/infiniband/hw/mlx5/main.c devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); s0 4996 drivers/infiniband/hw/mlx5/main.c if (!devr->s0) { s0 5001 drivers/infiniband/hw/mlx5/main.c devr->s0->device = &dev->ib_dev; s0 5002 drivers/infiniband/hw/mlx5/main.c devr->s0->pd = devr->p0; s0 5003 drivers/infiniband/hw/mlx5/main.c devr->s0->srq_type = IB_SRQT_XRC; s0 5004 drivers/infiniband/hw/mlx5/main.c devr->s0->ext.xrc.xrcd = devr->x0; s0 5005 drivers/infiniband/hw/mlx5/main.c devr->s0->ext.cq = devr->c0; s0 5006 drivers/infiniband/hw/mlx5/main.c ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); s0 5010 drivers/infiniband/hw/mlx5/main.c atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); s0 5011 drivers/infiniband/hw/mlx5/main.c atomic_inc(&devr->s0->ext.cq->usecnt); s0 5013 drivers/infiniband/hw/mlx5/main.c atomic_set(&devr->s0->usecnt, 0); s0 5048 drivers/infiniband/hw/mlx5/main.c mlx5_ib_destroy_srq(devr->s0, NULL); s0 5050 drivers/infiniband/hw/mlx5/main.c kfree(devr->s0); s0 5072 drivers/infiniband/hw/mlx5/main.c mlx5_ib_destroy_srq(devr->s0, NULL); s0 5073 drivers/infiniband/hw/mlx5/main.c kfree(devr->s0); s0 712 drivers/infiniband/hw/mlx5/mlx5_ib.h struct ib_srq *s0; s0 2225 drivers/infiniband/hw/mlx5/qp.c MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); s0 2231 drivers/infiniband/hw/mlx5/qp.c MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); s0 410 drivers/media/dvb-frontends/mt352.c int s0, s1, s3; s0 424 drivers/media/dvb-frontends/mt352.c if ((s0 = mt352_read_register(state, STATUS_0)) < 0) s0 432 drivers/media/dvb-frontends/mt352.c if (s0 & (1 << 4)) s0 434 drivers/media/dvb-frontends/mt352.c if (s0 & (1 << 1)) s0 436 drivers/media/dvb-frontends/mt352.c if (s0 & (1 << 5)) s0 29 drivers/media/usb/dvb-usb/vp7045-fe.c u8 s0 = vp7045_read_reg(state->d,0x00), s0 34 drivers/media/usb/dvb-usb/vp7045-fe.c if (s0 & (1 << 4)) s0 36 drivers/media/usb/dvb-usb/vp7045-fe.c if (s0 & (1 << 1)) s0 38 drivers/media/usb/dvb-usb/vp7045-fe.c if (s0 & (1 << 5)) s0 1954 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c unsigned int s0 = 0; s0 1963 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); s0 1964 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); s0 1967 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); s0 345 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c union cvmx_agl_gmx_txx_stat0 s0; s0 349 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0); s0 352 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) { s0 355 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol; s0 267 drivers/net/wireless/ath/ath9k/ar9003_mac.c u32 s0, s1; s0 268 drivers/net/wireless/ath/ath9k/ar9003_mac.c s0 = REG_READ(ah, AR_ISR_S0); s0 269 drivers/net/wireless/ath/ath9k/ar9003_mac.c REG_WRITE(ah, AR_ISR_S0, s0); s0 2409 drivers/scsi/aha152x.c int s0, s1; s0 2411 drivers/scsi/aha152x.c s0 = GETPORT(SIMODE0); s0 2416 drivers/scsi/aha152x.c (s0 & ENSELDO) ? "ENSELDO " : "", s0 2417 drivers/scsi/aha152x.c (s0 & ENSELDI) ? "ENSELDI " : "", s0 2418 drivers/scsi/aha152x.c (s0 & ENSELINGO) ? "ENSELINGO " : "", s0 2419 drivers/scsi/aha152x.c (s0 & ENSWRAP) ? "ENSWRAP " : "", s0 2420 drivers/scsi/aha152x.c (s0 & ENSDONE) ? "ENSDONE " : "", s0 2421 drivers/scsi/aha152x.c (s0 & ENSPIORDY) ? "ENSPIORDY " : "", s0 2422 drivers/scsi/aha152x.c (s0 & ENDMADONE) ? "ENDMADONE " : "", s0 2215 drivers/staging/rtl8723bs/core/rtw_security.c u32 s0, s1, s2, s3, t0, t1, t2, t3; s0 2223 drivers/staging/rtl8723bs/core/rtw_security.c s0 = GETU32(pt) ^ rk[0]; s0 2250 drivers/staging/rtl8723bs/core/rtw_security.c s0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0]; s0 2251 drivers/staging/rtl8723bs/core/rtw_security.c PUTU32(ct, s0); s0 677 drivers/tty/synclink.c #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1)) s0 3075 include/linux/platform_data/cros_ec_commands.h float s0; s0 3084 include/linux/platform_data/cros_ec_commands.h float s0; s0 27 include/video/newport.h struct { volatile unsigned short s0, s1; } byshort; s0 1257 kernel/rcu/srcutree.c unsigned long s0 = 0, s1 = 0; s0 1286 kernel/rcu/srcutree.c s0 += c0; s0 1289 kernel/rcu/srcutree.c pr_cont(" T(%ld,%ld)\n", s0, s1); s0 43 lib/crypto/sha256.c W[I] = s1(W[I-2]) + W[I-7] + s0(W[I-15]) + W[I-16]; s0 154 net/dccp/ccids/lib/packet_history.c u64 s0 = tfrc_rx_hist_loss_prev(h)->tfrchrx_seqno, s0 157 net/dccp/ccids/lib/packet_history.c if (!dccp_loss_free(s0, s1, n1)) { /* gap between S0 and S1 */ s0 165 net/dccp/ccids/lib/packet_history.c u64 s0 = tfrc_rx_hist_loss_prev(h)->tfrchrx_seqno, s0 177 net/dccp/ccids/lib/packet_history.c if (dccp_loss_free(s0, s2, n2)) { s0 202 net/dccp/ccids/lib/packet_history.c u64 s0 = tfrc_rx_hist_loss_prev(h)->tfrchrx_seqno, s0 227 net/dccp/ccids/lib/packet_history.c if (dccp_loss_free(s0, s3, n3)) { s0 888 sound/pci/lx6464es/lx_core.c u32 s0, s1, s2, s3; s0 896 sound/pci/lx6464es/lx_core.c s0 = peak_map[chip->rmh.stat[0] & 0x0F]; s0 901 sound/pci/lx6464es/lx_core.c s0 = s1 = s2 = s3 = 0; s0 903 sound/pci/lx6464es/lx_core.c r_levels[0] = s0;