rvu 26 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); rvu 28 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, rvu 30 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, rvu 32 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); rvu 34 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, rvu 62 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) rvu 68 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg = rvu->afreg_base + ((block << 28) | offset); rvu 165 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) rvu 170 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_lock(&rvu->rsrc_lock); rvu 174 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_unlock(&rvu->rsrc_lock); rvu 180 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_unlock(&rvu->rsrc_lock); rvu 190 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) rvu 231 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devnum = rvu_get_hwvf(rvu, pcifunc); rvu 240 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); rvu 248 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); rvu 254 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (is_block_implemented(rvu->hw, blkaddr)) rvu 259 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, rvu 268 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(&rvu->pdev->dev, rvu 277 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devnum = rvu_get_hwvf(rvu, pcifunc); rvu 313 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); rvu 321 drivers/net/ethernet/marvell/octeontx2/af/rvu.c void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) rvu 326 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); rvu 331 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) rvu 340 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); rvu 345 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) rvu 349 drivers/net/ethernet/marvell/octeontx2/af/rvu.c return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; rvu 351 drivers/net/ethernet/marvell/octeontx2/af/rvu.c return &rvu->pf[rvu_get_pf(pcifunc)]; rvu 354 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) rvu 360 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (pf >= rvu->hw->total_pfs) rvu 368 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); rvu 387 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_check_block_implemented(struct rvu *rvu) rvu 389 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 397 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); rvu 403 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) rvu 410 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); rvu 411 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), rvu 416 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) rvu 418 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_block *block = &rvu->hw->block[blkaddr]; rvu 423 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); rvu 424 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); rvu 427 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_reset_all_blocks(struct rvu *rvu) rvu 430 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); rvu 431 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); rvu 432 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); rvu 433 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); rvu 434 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); rvu 435 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); rvu 436 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_block_reset(rvu, BLKADDR_NDC0, NDC_AF_BLK_RST); rvu 437 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_block_reset(rvu, BLKADDR_NDC1, NDC_AF_BLK_RST); rvu 438 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_block_reset(rvu, BLKADDR_NDC2, NDC_AF_BLK_RST); rvu 441 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) rvu 448 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, block->addr, rvu 457 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); rvu 458 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_update_rsrc_map(rvu, pfvf, block, rvu 462 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_set_msix_offset(rvu, pfvf, block, lf); rvu 466 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) rvu 474 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_warn(rvu->dev, rvu 488 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_warn(rvu->dev, rvu 493 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_setup_msix_resources(struct rvu *rvu) rvu 495 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 503 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); rvu 508 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); rvu 510 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pfvf = &rvu->pf[pf]; rvu 512 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); rvu 514 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); rvu 522 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, rvu 537 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); rvu 541 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, rvu 546 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pfvf = &rvu->hwvf[hwvf + vf]; rvu 548 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, rvu 551 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); rvu 559 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devm_kcalloc(rvu->dev, pfvf->msix.max, rvu 568 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, rvu 573 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, rvu 583 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); rvu 585 drivers/net/ethernet/marvell/octeontx2/af/rvu.c phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); rvu 586 drivers/net/ethernet/marvell/octeontx2/af/rvu.c iova = dma_map_resource(rvu->dev, phy_addr, rvu 590 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (dma_mapping_error(rvu->dev, iova)) rvu 593 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); rvu 594 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->msix_base_iova = iova; rvu 599 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_free_hw_resources(struct rvu *rvu) rvu 601 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 607 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_npa_freemem(rvu); rvu 608 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_npc_freemem(rvu); rvu 609 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_nix_freemem(rvu); rvu 619 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pfvf = &rvu->pf[id]; rvu 624 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pfvf = &rvu->hwvf[id]; rvu 629 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu->msix_base_iova) rvu 631 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); rvu 633 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dma_unmap_resource(rvu->dev, rvu->msix_base_iova, rvu 637 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_destroy(&rvu->rsrc_lock); rvu 640 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_setup_hw_resources(struct rvu *rvu) rvu 642 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 648 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); rvu 657 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); rvu 678 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST2); rvu 699 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); rvu 742 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); rvu 764 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS0); rvu 783 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, rvu 785 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu->pf) rvu 788 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, rvu 790 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu->hwvf) rvu 793 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_init(&rvu->rsrc_lock); rvu 795 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_setup_msix_resources(rvu); rvu 805 drivers/net/ethernet/marvell/octeontx2/af/rvu.c block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, rvu 813 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_scan_block(rvu, block); rvu 816 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_npc_init(rvu); rvu 820 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_cgx_init(rvu); rvu 824 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_npa_init(rvu); rvu 828 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_nix_init(rvu); rvu 835 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_cgx_exit(rvu); rvu 841 drivers/net/ethernet/marvell/octeontx2/af/rvu.c void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) rvu 846 drivers/net/ethernet/marvell/octeontx2/af/rvu.c qmem_free(rvu->dev, aq->inst); rvu 847 drivers/net/ethernet/marvell/octeontx2/af/rvu.c qmem_free(rvu->dev, aq->res); rvu 848 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devm_kfree(rvu->dev, aq); rvu 851 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, rvu 857 drivers/net/ethernet/marvell/octeontx2/af/rvu.c *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); rvu 863 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); rvu 865 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devm_kfree(rvu->dev, aq); rvu 870 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); rvu 872 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_aq_free(rvu, aq); rvu 880 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, rvu 908 drivers/net/ethernet/marvell/octeontx2/af/rvu.c bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) rvu 912 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!is_pf_func_valid(rvu, pcifunc)) rvu 915 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 924 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, rvu 930 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, block->addr, block->lookup_reg, val); rvu 933 drivers/net/ethernet/marvell/octeontx2/af/rvu.c while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) rvu 936 drivers/net/ethernet/marvell/octeontx2/af/rvu.c val = rvu_read64(rvu, block->addr, block->lookup_reg); rvu 945 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) rvu 947 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 948 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 953 drivers/net/ethernet/marvell/octeontx2/af/rvu.c blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); rvu 964 drivers/net/ethernet/marvell/octeontx2/af/rvu.c lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); rvu 969 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, blkaddr, block->lfcfg_reg | rvu 973 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_update_rsrc_map(rvu, pfvf, block, rvu 980 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_clear_msix_offset(rvu, pfvf, block, lf); rvu 984 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, rvu 987 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 992 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_lock(&rvu->rsrc_lock); rvu 1019 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_detach_block(rvu, pcifunc, block->type); rvu 1022 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_unlock(&rvu->rsrc_lock); rvu 1026 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_mbox_handler_detach_resources(struct rvu *rvu, rvu 1030 drivers/net/ethernet/marvell/octeontx2/af/rvu.c return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); rvu 1033 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_attach_block(struct rvu *rvu, int pcifunc, rvu 1036 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 1037 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 1046 drivers/net/ethernet/marvell/octeontx2/af/rvu.c blkaddr = rvu_get_blkaddr(rvu, blktype, 0); rvu 1061 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, blkaddr, block->lfcfg_reg | rvu 1063 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_update_rsrc_map(rvu, pfvf, block, rvu 1067 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_set_msix_offset(rvu, pfvf, block, lf); rvu 1071 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_check_rsrc_availability(struct rvu *rvu, rvu 1074 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 1075 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 1086 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(&rvu->pdev->dev, rvu 1099 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(&rvu->pdev->dev, rvu 1109 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(&rvu->pdev->dev, rvu 1125 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(&rvu->pdev->dev, rvu 1140 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(&rvu->pdev->dev, rvu 1155 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(&rvu->pdev->dev, rvu 1170 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_info(rvu->dev, "Request for %s failed\n", block->name); rvu 1174 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_mbox_handler_attach_resources(struct rvu *rvu, rvu 1183 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_detach_rsrcs(rvu, NULL, pcifunc); rvu 1185 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_lock(&rvu->rsrc_lock); rvu 1188 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_check_rsrc_availability(rvu, attach, pcifunc); rvu 1194 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1); rvu 1197 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1); rvu 1206 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); rvu 1207 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, attach->sso); rvu 1212 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); rvu 1213 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, attach->ssow); rvu 1218 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); rvu 1219 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, attach->timlfs); rvu 1224 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); rvu 1225 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, attach->cptlfs); rvu 1229 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_unlock(&rvu->rsrc_lock); rvu 1233 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, rvu 1248 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, rvu 1254 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | rvu 1265 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, block->addr, block->msixcfg_reg | rvu 1273 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, rvu 1279 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | rvu 1284 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, block->addr, block->msixcfg_reg | rvu 1287 drivers/net/ethernet/marvell/octeontx2/af/rvu.c offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); rvu 1297 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, rvu 1300 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 1305 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 1310 drivers/net/ethernet/marvell/octeontx2/af/rvu.c lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); rvu 1311 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); rvu 1313 drivers/net/ethernet/marvell/octeontx2/af/rvu.c lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NIX0], pcifunc, 0); rvu 1314 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NIX0, lf); rvu 1318 drivers/net/ethernet/marvell/octeontx2/af/rvu.c lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); rvu 1320 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); rvu 1325 drivers/net/ethernet/marvell/octeontx2/af/rvu.c lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); rvu 1327 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); rvu 1332 drivers/net/ethernet/marvell/octeontx2/af/rvu.c lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); rvu 1334 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); rvu 1339 drivers/net/ethernet/marvell/octeontx2/af/rvu.c lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); rvu 1341 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); rvu 1346 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, rvu 1354 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, rvu 1359 drivers/net/ethernet/marvell/octeontx2/af/rvu.c __rvu_flr_handler(rvu, pcifunc); rvu 1369 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu = pci_get_drvdata(mbox->pdev); rvu 1398 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_mbox_handler_ ## _fn_name(rvu, \ rvu 1418 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu = mwork->rvu; rvu 1428 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mw = &rvu->afpf_wq_info; rvu 1431 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mw = &rvu->afvf_wq_info; rvu 1472 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", rvu 1477 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", rvu 1502 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu = mwork->rvu; rvu 1512 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mw = &rvu->afpf_wq_info; rvu 1515 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mw = &rvu->afvf_wq_info; rvu 1527 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); rvu 1537 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 1543 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 1554 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 1581 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, rvu 1595 drivers/net/ethernet/marvell/octeontx2/af/rvu.c bar4_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PF_BAR4_ADDR); rvu 1598 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg_base = rvu->afreg_base; rvu 1602 drivers/net/ethernet/marvell/octeontx2/af/rvu.c bar4_addr = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); rvu 1605 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg_base = rvu->pfreg_base; rvu 1617 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mw->mbox_wrk = devm_kcalloc(rvu->dev, num, rvu 1624 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, rvu 1637 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, "Unable to map mailbox region\n"); rvu 1642 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = otx2_mbox_init(&mw->mbox, hwbase, rvu->pdev, reg_base, dir, num); rvu 1646 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = otx2_mbox_init(&mw->mbox_up, hwbase, rvu->pdev, rvu 1653 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mwork->rvu = rvu; rvu 1657 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mwork->rvu = rvu; rvu 1713 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu = (struct rvu *)rvu_irq; rvu 1714 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int vfs = rvu->vfs; rvu 1717 drivers/net/ethernet/marvell/octeontx2/af/rvu.c intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); rvu 1719 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); rvu 1724 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); rvu 1728 drivers/net/ethernet/marvell/octeontx2/af/rvu.c intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); rvu 1729 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); rvu 1731 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); rvu 1735 drivers/net/ethernet/marvell/octeontx2/af/rvu.c intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); rvu 1736 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); rvu 1738 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); rvu 1743 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_enable_mbox_intr(struct rvu *rvu) rvu 1745 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_hwinfo *hw = rvu->hw; rvu 1748 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, rvu 1752 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, rvu 1756 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) rvu 1762 drivers/net/ethernet/marvell/octeontx2/af/rvu.c block = &rvu->hw->block[blkaddr]; rvu 1763 drivers/net/ethernet/marvell/octeontx2/af/rvu.c num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), rvu 1768 drivers/net/ethernet/marvell/octeontx2/af/rvu.c lf = rvu_get_lf(rvu, block, pcifunc, slot); rvu 1774 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); rvu 1776 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_npa_lf_teardown(rvu, pcifunc, lf); rvu 1778 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_lf_reset(rvu, block, lf); rvu 1780 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", rvu 1786 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) rvu 1788 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_lock(&rvu->flr_lock); rvu 1794 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); rvu 1795 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); rvu 1796 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); rvu 1797 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); rvu 1798 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); rvu 1799 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); rvu 1800 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_detach_rsrcs(rvu, NULL, pcifunc); rvu 1801 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_unlock(&rvu->flr_lock); rvu 1804 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) rvu 1809 drivers/net/ethernet/marvell/octeontx2/af/rvu.c __rvu_flr_handler(rvu, vf + 1); rvu 1817 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); rvu 1818 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); rvu 1824 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu = flrwork->rvu; rvu 1829 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pf = flrwork - rvu->flr_wrk; rvu 1830 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (pf >= rvu->hw->total_pfs) { rvu 1831 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); rvu 1835 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); rvu 1840 drivers/net/ethernet/marvell/octeontx2/af/rvu.c __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); rvu 1842 drivers/net/ethernet/marvell/octeontx2/af/rvu.c __rvu_flr_handler(rvu, pcifunc); rvu 1845 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); rvu 1848 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); rvu 1851 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) rvu 1859 drivers/net/ethernet/marvell/octeontx2/af/rvu.c intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); rvu 1866 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev = vf + start_vf + rvu->hw->total_pfs; rvu 1867 drivers/net/ethernet/marvell/octeontx2/af/rvu.c queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); rvu 1869 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); rvu 1870 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); rvu 1876 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu = (struct rvu *)rvu_irq; rvu 1880 drivers/net/ethernet/marvell/octeontx2/af/rvu.c intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); rvu 1884 drivers/net/ethernet/marvell/octeontx2/af/rvu.c for (pf = 0; pf < rvu->hw->total_pfs; pf++) { rvu 1887 drivers/net/ethernet/marvell/octeontx2/af/rvu.c queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); rvu 1889 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, rvu 1892 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, rvu 1898 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_afvf_queue_flr_work(rvu, 0, 64); rvu 1899 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (rvu->vfs > 64) rvu 1900 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); rvu 1905 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) rvu 1915 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); rvu 1917 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); rvu 1925 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu = (struct rvu *)rvu_irq; rvu 1929 drivers/net/ethernet/marvell/octeontx2/af/rvu.c intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); rvu 1932 drivers/net/ethernet/marvell/octeontx2/af/rvu.c intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); rvu 1934 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_me_handle_vfset(rvu, vfset, intr); rvu 1943 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu = (struct rvu *)rvu_irq; rvu 1947 drivers/net/ethernet/marvell/octeontx2/af/rvu.c intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); rvu 1952 drivers/net/ethernet/marvell/octeontx2/af/rvu.c for (pf = 0; pf < rvu->hw->total_pfs; pf++) { rvu 1955 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, rvu 1958 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, rvu 1966 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_unregister_interrupts(struct rvu *rvu) rvu 1971 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, rvu 1972 drivers/net/ethernet/marvell/octeontx2/af/rvu.c INTR_MASK(rvu->hw->total_pfs) & ~1ULL); rvu 1975 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, rvu 1976 drivers/net/ethernet/marvell/octeontx2/af/rvu.c INTR_MASK(rvu->hw->total_pfs) & ~1ULL); rvu 1979 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, rvu 1980 drivers/net/ethernet/marvell/octeontx2/af/rvu.c INTR_MASK(rvu->hw->total_pfs) & ~1ULL); rvu 1982 drivers/net/ethernet/marvell/octeontx2/af/rvu.c for (irq = 0; irq < rvu->num_vec; irq++) { rvu 1983 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (rvu->irq_allocated[irq]) rvu 1984 drivers/net/ethernet/marvell/octeontx2/af/rvu.c free_irq(pci_irq_vector(rvu->pdev, irq), rvu); rvu 1987 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pci_free_irq_vectors(rvu->pdev); rvu 1988 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->num_vec = 0; rvu 1991 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) rvu 1993 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu_pfvf *pfvf = &rvu->pf[0]; rvu 1996 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pfvf = &rvu->pf[0]; rvu 1997 drivers/net/ethernet/marvell/octeontx2/af/rvu.c offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; rvu 2007 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_register_interrupts(struct rvu *rvu) rvu 2011 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->num_vec = pci_msix_vec_count(rvu->pdev); rvu 2013 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, rvu 2015 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu->irq_name) rvu 2018 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, rvu 2020 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu->irq_allocated) rvu 2024 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, rvu 2025 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->num_vec, PCI_IRQ_MSIX); rvu 2027 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2029 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->num_vec, ret); rvu 2034 drivers/net/ethernet/marvell/octeontx2/af/rvu.c sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); rvu 2035 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), rvu 2037 drivers/net/ethernet/marvell/octeontx2/af/rvu.c &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); rvu 2039 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2044 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; rvu 2047 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_enable_mbox_intr(rvu); rvu 2050 drivers/net/ethernet/marvell/octeontx2/af/rvu.c sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], rvu 2052 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), rvu 2054 drivers/net/ethernet/marvell/octeontx2/af/rvu.c &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], rvu 2055 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu); rvu 2057 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2061 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; rvu 2064 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, rvu 2065 drivers/net/ethernet/marvell/octeontx2/af/rvu.c RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); rvu 2067 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, rvu 2068 drivers/net/ethernet/marvell/octeontx2/af/rvu.c INTR_MASK(rvu->hw->total_pfs) & ~1ULL); rvu 2071 drivers/net/ethernet/marvell/octeontx2/af/rvu.c sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], rvu 2073 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), rvu 2075 drivers/net/ethernet/marvell/octeontx2/af/rvu.c &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], rvu 2076 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu); rvu 2078 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2081 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; rvu 2084 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, rvu 2085 drivers/net/ethernet/marvell/octeontx2/af/rvu.c RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); rvu 2087 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, rvu 2088 drivers/net/ethernet/marvell/octeontx2/af/rvu.c INTR_MASK(rvu->hw->total_pfs) & ~1ULL); rvu 2090 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu_afvf_msix_vectors_num_ok(rvu)) rvu 2094 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, rvu 2099 drivers/net/ethernet/marvell/octeontx2/af/rvu.c sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); rvu 2100 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = request_irq(pci_irq_vector(rvu->pdev, offset), rvu 2102 drivers/net/ethernet/marvell/octeontx2/af/rvu.c &rvu->irq_name[offset * NAME_SIZE], rvu 2103 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu); rvu 2105 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2108 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated[offset] = true; rvu 2114 drivers/net/ethernet/marvell/octeontx2/af/rvu.c sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); rvu 2115 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = request_irq(pci_irq_vector(rvu->pdev, offset), rvu 2117 drivers/net/ethernet/marvell/octeontx2/af/rvu.c &rvu->irq_name[offset * NAME_SIZE], rvu 2118 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu); rvu 2120 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2123 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated[offset] = true; rvu 2127 drivers/net/ethernet/marvell/octeontx2/af/rvu.c sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); rvu 2128 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = request_irq(pci_irq_vector(rvu->pdev, offset), rvu 2130 drivers/net/ethernet/marvell/octeontx2/af/rvu.c &rvu->irq_name[offset * NAME_SIZE], rvu); rvu 2132 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2136 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated[offset] = true; rvu 2139 drivers/net/ethernet/marvell/octeontx2/af/rvu.c sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); rvu 2140 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = request_irq(pci_irq_vector(rvu->pdev, offset), rvu 2142 drivers/net/ethernet/marvell/octeontx2/af/rvu.c &rvu->irq_name[offset * NAME_SIZE], rvu); rvu 2144 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2148 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated[offset] = true; rvu 2152 drivers/net/ethernet/marvell/octeontx2/af/rvu.c sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); rvu 2153 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = request_irq(pci_irq_vector(rvu->pdev, offset), rvu 2155 drivers/net/ethernet/marvell/octeontx2/af/rvu.c &rvu->irq_name[offset * NAME_SIZE], rvu); rvu 2157 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2161 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated[offset] = true; rvu 2164 drivers/net/ethernet/marvell/octeontx2/af/rvu.c sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); rvu 2165 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = request_irq(pci_irq_vector(rvu->pdev, offset), rvu 2167 drivers/net/ethernet/marvell/octeontx2/af/rvu.c &rvu->irq_name[offset * NAME_SIZE], rvu); rvu 2169 drivers/net/ethernet/marvell/octeontx2/af/rvu.c dev_err(rvu->dev, rvu 2173 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->irq_allocated[offset] = true; rvu 2177 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_unregister_interrupts(rvu); rvu 2181 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_flr_wq_destroy(struct rvu *rvu) rvu 2183 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (rvu->flr_wq) { rvu 2184 drivers/net/ethernet/marvell/octeontx2/af/rvu.c flush_workqueue(rvu->flr_wq); rvu 2185 drivers/net/ethernet/marvell/octeontx2/af/rvu.c destroy_workqueue(rvu->flr_wq); rvu 2186 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->flr_wq = NULL; rvu 2190 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_flr_init(struct rvu *rvu) rvu 2197 drivers/net/ethernet/marvell/octeontx2/af/rvu.c for (pf = 0; pf < rvu->hw->total_pfs; pf++) { rvu 2198 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); rvu 2199 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), rvu 2203 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", rvu 2206 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu->flr_wq) rvu 2209 drivers/net/ethernet/marvell/octeontx2/af/rvu.c num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); rvu 2210 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, rvu 2212 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu->flr_wrk) { rvu 2213 drivers/net/ethernet/marvell/octeontx2/af/rvu.c destroy_workqueue(rvu->flr_wq); rvu 2218 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->flr_wrk[dev].rvu = rvu; rvu 2219 drivers/net/ethernet/marvell/octeontx2/af/rvu.c INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); rvu 2222 drivers/net/ethernet/marvell/octeontx2/af/rvu.c mutex_init(&rvu->flr_lock); rvu 2227 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_disable_afvf_intr(struct rvu *rvu) rvu 2229 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int vfs = rvu->vfs; rvu 2231 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); rvu 2232 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); rvu 2233 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); rvu 2237 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), rvu 2239 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); rvu 2240 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); rvu 2243 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_enable_afvf_intr(struct rvu *rvu) rvu 2245 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int vfs = rvu->vfs; rvu 2251 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); rvu 2252 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); rvu 2255 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); rvu 2256 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); rvu 2257 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); rvu 2263 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); rvu 2264 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), rvu 2267 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); rvu 2268 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); rvu 2269 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); rvu 2298 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static int rvu_enable_sriov(struct rvu *rvu) rvu 2300 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct pci_dev *pdev = rvu->pdev; rvu 2303 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu_afvf_msix_vectors_num_ok(rvu)) { rvu 2338 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->vfs = vfs; rvu 2340 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, rvu 2345 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_enable_afvf_intr(rvu); rvu 2351 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_disable_afvf_intr(rvu); rvu 2352 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_mbox_destroy(&rvu->afvf_wq_info); rvu 2359 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_disable_sriov(struct rvu *rvu) rvu 2361 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_disable_afvf_intr(rvu); rvu 2362 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_mbox_destroy(&rvu->afvf_wq_info); rvu 2363 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pci_disable_sriov(rvu->pdev); rvu 2366 drivers/net/ethernet/marvell/octeontx2/af/rvu.c static void rvu_update_module_params(struct rvu *rvu) rvu 2370 drivers/net/ethernet/marvell/octeontx2/af/rvu.c strscpy(rvu->mkex_pfl_name, rvu 2377 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu; rvu 2380 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); rvu 2381 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu) rvu 2384 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); rvu 2385 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu->hw) { rvu 2386 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devm_kfree(dev, rvu); rvu 2390 drivers/net/ethernet/marvell/octeontx2/af/rvu.c pci_set_drvdata(pdev, rvu); rvu 2391 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->pdev = pdev; rvu 2392 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->dev = &pdev->dev; rvu 2419 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); rvu 2420 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); rvu 2421 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!rvu->afreg_base || !rvu->pfreg_base) { rvu 2428 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_update_module_params(rvu); rvu 2431 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_check_block_implemented(rvu); rvu 2433 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_reset_all_blocks(rvu); rvu 2435 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_setup_hw_resources(rvu); rvu 2440 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, rvu 2441 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu->hw->total_pfs, rvu_afpf_mbox_handler, rvu 2446 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_flr_init(rvu); rvu 2450 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_register_interrupts(rvu); rvu 2455 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = rvu_enable_sriov(rvu); rvu 2461 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_unregister_interrupts(rvu); rvu 2463 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_flr_wq_destroy(rvu); rvu 2465 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_mbox_destroy(&rvu->afpf_wq_info); rvu 2467 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_cgx_exit(rvu); rvu 2468 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_reset_all_blocks(rvu); rvu 2469 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_free_hw_resources(rvu); rvu 2476 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devm_kfree(&pdev->dev, rvu->hw); rvu 2477 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devm_kfree(dev, rvu); rvu 2483 drivers/net/ethernet/marvell/octeontx2/af/rvu.c struct rvu *rvu = pci_get_drvdata(pdev); rvu 2485 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_unregister_interrupts(rvu); rvu 2486 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_flr_wq_destroy(rvu); rvu 2487 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_cgx_exit(rvu); rvu 2488 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_mbox_destroy(&rvu->afpf_wq_info); rvu 2489 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_disable_sriov(rvu); rvu 2490 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_reset_all_blocks(rvu); rvu 2491 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_free_hw_resources(rvu); rvu 2497 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devm_kfree(&pdev->dev, rvu->hw); rvu 2498 drivers/net/ethernet/marvell/octeontx2/af/rvu.c devm_kfree(&pdev->dev, rvu); rvu 40 drivers/net/ethernet/marvell/octeontx2/af/rvu.h struct rvu *rvu; rvu 268 drivers/net/ethernet/marvell/octeontx2/af/rvu.h static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) rvu 270 drivers/net/ethernet/marvell/octeontx2/af/rvu.h writeq(val, rvu->afreg_base + ((block << 28) | offset)); rvu 273 drivers/net/ethernet/marvell/octeontx2/af/rvu.h static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) rvu 275 drivers/net/ethernet/marvell/octeontx2/af/rvu.h return readq(rvu->afreg_base + ((block << 28) | offset)); rvu 278 drivers/net/ethernet/marvell/octeontx2/af/rvu.h static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) rvu 280 drivers/net/ethernet/marvell/octeontx2/af/rvu.h writeq(val, rvu->pfreg_base + offset); rvu 283 drivers/net/ethernet/marvell/octeontx2/af/rvu.h static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) rvu 285 drivers/net/ethernet/marvell/octeontx2/af/rvu.h return readq(rvu->pfreg_base + offset); rvu 288 drivers/net/ethernet/marvell/octeontx2/af/rvu.h static inline bool is_rvu_9xxx_A0(struct rvu *rvu) rvu 290 drivers/net/ethernet/marvell/octeontx2/af/rvu.h struct pci_dev *pdev = rvu->pdev; rvu 311 drivers/net/ethernet/marvell/octeontx2/af/rvu.h struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); rvu 312 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); rvu 314 drivers/net/ethernet/marvell/octeontx2/af/rvu.h bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); rvu 315 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); rvu 316 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); rvu 317 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); rvu 318 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); rvu 329 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, rvu 331 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); rvu 334 drivers/net/ethernet/marvell/octeontx2/af/rvu.h static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) rvu 336 drivers/net/ethernet/marvell/octeontx2/af/rvu.h return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs); rvu 345 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_cgx_init(struct rvu *rvu); rvu 346 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_cgx_exit(struct rvu *rvu); rvu 347 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); rvu 348 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); rvu 349 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req, rvu 351 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req, rvu 353 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req, rvu 355 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu, rvu 358 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu, rvu 361 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req, rvu 363 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req, rvu 365 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req, rvu 367 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req, rvu 369 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req, rvu 371 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req, rvu 373 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req, rvu 377 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_npa_init(struct rvu *rvu); rvu 378 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npa_freemem(struct rvu *rvu); rvu 379 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); rvu 380 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npa_aq_enq(struct rvu *rvu, rvu 383 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npa_hwctx_disable(struct rvu *rvu, rvu 386 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu, rvu 389 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req, rvu 393 drivers/net/ethernet/marvell/octeontx2/af/rvu.h bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); rvu 394 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_nix_init(struct rvu *rvu); rvu 395 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, rvu 397 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_nix_freemem(struct rvu *rvu); rvu 398 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_get_nixlf_count(struct rvu *rvu); rvu 399 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); rvu 400 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, rvu 403 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct msg_req *req, rvu 405 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, rvu 408 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu, rvu 411 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu, rvu 414 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu, rvu 417 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu, rvu 420 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req, rvu 422 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu, rvu 425 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_rxvlan_alloc(struct rvu *rvu, struct msg_req *req, rvu 427 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu, rvu 430 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, rvu 433 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req, rvu 435 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req, rvu 437 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req, rvu 439 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req, rvu 441 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu, rvu 444 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req, rvu 446 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu, rvu 451 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_npc_init(struct rvu *rvu); rvu 452 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_freemem(struct rvu *rvu); rvu 453 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); rvu 454 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); rvu 455 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, rvu 457 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, rvu 459 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); rvu 460 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); rvu 461 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, rvu 463 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf); rvu 464 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); rvu 465 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); rvu 466 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); rvu 467 drivers/net/ethernet/marvell/octeontx2/af/rvu.h void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, rvu 469 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, rvu 472 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu, rvu 475 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu, rvu 478 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu, rvu 481 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu, rvu 484 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu, rvu 487 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, rvu 490 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, rvu 492 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu, rvu 494 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, rvu 496 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu, rvu 499 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu, rvu 502 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req, rvu 25 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \ rvu 30 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \ rvu 43 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c static inline u16 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id) rvu 45 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id]; rvu 53 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu) rvu 55 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (cgx_id >= rvu->cgx_cnt_max) rvu 58 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c return rvu->cgx_idmap[cgx_id]; rvu 61 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c static int rvu_map_cgx_lmac_pf(struct rvu *rvu) rvu 63 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c struct npc_pkind *pkind = &rvu->hw->pkind; rvu 64 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int cgx_cnt_max = rvu->cgx_cnt_max; rvu 80 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL); rvu 81 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (!rvu->pf2cgxlmac_map) rvu 85 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c memset(rvu->pf2cgxlmac_map, 0xFF, size); rvu 88 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->cgxlmac2pf_map = devm_kzalloc(rvu->dev, rvu 91 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (!rvu->cgxlmac2pf_map) rvu 94 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->cgx_mapped_pfs = 0; rvu 96 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (!rvu_cgx_pdata(cgx, rvu)) rvu 98 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); rvu 100 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac); rvu 101 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf; rvu 104 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->cgx_mapped_pfs++; rvu 110 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu) rvu 121 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c spin_lock_irqsave(&rvu->cgx_evq_lock, flags); rvu 122 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id, rvu 128 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head); rvu 130 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags); rvu 133 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work); rvu 142 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c struct rvu *rvu = data; rvu 149 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c spin_lock(&rvu->cgx_evq_lock); rvu 150 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head); rvu 151 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c spin_unlock(&rvu->cgx_evq_lock); rvu 154 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work); rvu 159 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu) rvu 167 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id); rvu 174 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (!test_bit(pfid, &rvu->pf_notify_bmap)) { rvu 175 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n", rvu 182 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid); rvu 186 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c otx2_mbox_msg_send(&rvu->afpf_wq_info.mbox_up, pfid); rvu 187 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c err = otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pfid); rvu 189 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c dev_warn(rvu->dev, "notification to pf %d failed\n", rvu 196 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work); rvu 203 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c spin_lock_irqsave(&rvu->cgx_evq_lock, flags); rvu 204 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c qentry = list_first_entry_or_null(&rvu->cgx_evq_head, rvu 209 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags); rvu 216 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c cgx_notify_pfs(event, rvu); rvu 221 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c static int cgx_lmac_event_handler_init(struct rvu *rvu) rvu 227 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c spin_lock_init(&rvu->cgx_evq_lock); rvu 228 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c INIT_LIST_HEAD(&rvu->cgx_evq_head); rvu 229 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task); rvu 230 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0); rvu 231 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (!rvu->cgx_evh_wq) { rvu 232 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c dev_err(rvu->dev, "alloc workqueue failed"); rvu 237 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c cb.data = rvu; rvu 239 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) { rvu 240 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c cgxd = rvu_cgx_pdata(cgx, rvu); rvu 246 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c dev_err(rvu->dev, rvu 255 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c static void rvu_cgx_wq_destroy(struct rvu *rvu) rvu 257 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (rvu->cgx_evh_wq) { rvu 258 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c flush_workqueue(rvu->cgx_evh_wq); rvu 259 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c destroy_workqueue(rvu->cgx_evh_wq); rvu 260 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->cgx_evh_wq = NULL; rvu 264 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_cgx_init(struct rvu *rvu) rvu 272 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->cgx_cnt_max = cgx_get_cgxcnt_max(); rvu 273 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (!rvu->cgx_cnt_max) { rvu 274 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c dev_info(rvu->dev, "No CGX devices found!\n"); rvu 278 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max * rvu 280 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (!rvu->cgx_idmap) rvu 284 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++) rvu 285 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx); rvu 288 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c err = rvu_map_cgx_lmac_pf(rvu); rvu 293 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c err = cgx_lmac_event_handler_init(rvu); rvu 303 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) { rvu 304 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c cgxd = rvu_cgx_pdata(cgx, rvu); rvu 309 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c dev_err(rvu->dev, rvu 317 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_cgx_exit(struct rvu *rvu) rvu 322 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) { rvu 323 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c cgxd = rvu_cgx_pdata(cgx, rvu); rvu 333 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_cgx_wq_destroy(rvu); rvu 337 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start) rvu 345 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if ((pcifunc & RVU_PFVF_FUNC_MASK) || !is_pf_cgxmapped(rvu, pf)) rvu 348 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); rvu 350 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c cgx_lmac_rx_tx_enable(rvu_cgx_pdata(cgx_id, rvu), lmac_id, start); rvu 355 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req, rvu 358 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true); rvu 362 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req, rvu 365 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false); rvu 369 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req, rvu 379 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c !is_pf_cgxmapped(rvu, pf)) rvu 382 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); rvu 383 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c cgxd = rvu_cgx_pdata(cgx_idx, rvu); rvu 406 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu, rvu 413 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); rvu 420 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu, rvu 429 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); rvu 439 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req, rvu 450 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c !is_pf_cgxmapped(rvu, pf)) rvu 453 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); rvu 459 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req, rvu 470 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c !is_pf_cgxmapped(rvu, pf)) rvu 473 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); rvu 479 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en) rvu 487 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if ((pcifunc & RVU_PFVF_FUNC_MASK) || !is_pf_cgxmapped(rvu, pf)) rvu 490 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); rvu 493 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c set_bit(pf, &rvu->pf_notify_bmap); rvu 495 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_cgx_send_link_info(cgx_id, lmac_id, rvu); rvu 497 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c clear_bit(pf, &rvu->pf_notify_bmap); rvu 503 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req, rvu 506 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true); rvu 510 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req, rvu 513 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false); rvu 517 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req, rvu 525 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if (!is_pf_cgxmapped(rvu, pf)) rvu 528 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); rvu 530 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id, rvu 535 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en) rvu 543 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c if ((pcifunc & RVU_PFVF_FUNC_MASK) || !is_pf_cgxmapped(rvu, pf)) rvu 546 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); rvu 548 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c return cgx_lmac_internal_loopback(rvu_cgx_pdata(cgx_id, rvu), rvu 552 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req, rvu 555 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true); rvu 559 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req, rvu 562 drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false); rvu 20 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add); rvu 71 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc) rvu 73 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 76 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 82 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_get_nixlf_count(struct rvu *rvu) rvu 87 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0); rvu 90 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c block = &rvu->hw->block[blkaddr]; rvu 121 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_rx_sync(struct rvu *rvu, int blkaddr) rvu 126 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); rvu 127 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); rvu 129 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "NIX RX software sync failed\n"); rvu 134 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (is_rvu_9xxx_A0(rvu)) rvu 138 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static bool is_valid_txschq(struct rvu *rvu, int blkaddr, rvu 145 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 154 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_lock(&rvu->rsrc_lock); rvu 156 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_unlock(&rvu->rsrc_lock); rvu 170 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf) rvu 172 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 178 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK) rvu 183 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf->cgx_lmac = rvu->pf2cgxlmac_map[pf]; rvu 186 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pkind = rvu_npc_get_pkind(rvu, pf); rvu 188 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, rvu 196 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, pkind); rvu 197 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_set_pkind(rvu, pkind, pfvf); rvu 206 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, rvu 214 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, rvu 218 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_update_bcast_mce_list(rvu, pcifunc, true); rvu 220 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, rvu 226 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_install_bcast_match_entry(rvu, pcifunc, rvu 234 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf) rvu 236 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 244 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_update_bcast_mce_list(rvu, pcifunc, false); rvu 246 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, rvu 252 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); rvu 255 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr, rvu 266 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 279 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 284 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_setup_lso_tso_l4(struct rvu *rvu, int blkaddr, rvu 294 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 303 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 308 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) rvu 313 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF; rvu 317 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG); rvu 323 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LSO_CFG, cfg | BIT_ULL(63)); rvu 330 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_setup_lso_tso_l3(rvu, blkaddr, idx, true, &fidx); rvu 331 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); rvu 335 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 343 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_setup_lso_tso_l3(rvu, blkaddr, idx, false, &fidx); rvu 344 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); rvu 348 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 354 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf) rvu 360 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c qmem_free(rvu->dev, pfvf->rq_ctx); rvu 362 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c qmem_free(rvu->dev, pfvf->sq_ctx); rvu 364 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c qmem_free(rvu->dev, pfvf->cq_ctx); rvu 366 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c qmem_free(rvu->dev, pfvf->rss_ctx); rvu 368 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c qmem_free(rvu->dev, pfvf->nix_qints_ctx); rvu 370 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c qmem_free(rvu->dev, pfvf->cq_ints_ctx); rvu 383 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nixlf_rss_ctx_init(struct rvu *rvu, int blkaddr, rvu 395 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = qmem_alloc(rvu->dev, &pfvf->rss_ctx, num_indices, hwctx_size); rvu 399 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_BASE(nixlf), rvu 403 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf), rvu 408 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_GRPX(nixlf, grp), rvu 413 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, rvu 424 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS); rvu 434 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, block->addr, NIX_AF_AQ_DOOR, 1); rvu 450 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req, rvu 453 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 464 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 471 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_warn(rvu->dev, "%s: NIX AQ not initialized\n", __func__); rvu 475 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 476 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, block, pcifunc, 0); rvu 500 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf)); rvu 506 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG); rvu 530 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (!is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_SMQ, rvu 595 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = nix_aq_enqueue_wait(rvu, block, &inst); rvu 666 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req) rvu 668 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); rvu 706 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = rvu_nix_aq_enq_inst(rvu, &aq_req, NULL); rvu 709 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "Failed to disable %s:%d context\n", rvu 719 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, rvu 723 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c return rvu_nix_aq_enq_inst(rvu, req, rsp); rvu 726 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu, rvu 730 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c return nix_lf_hwctx_disable(rvu, req); rvu 733 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, rvu 738 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 748 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 749 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 754 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, block, pcifunc, 0); rvu 763 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (!is_pffunc_map_valid(rvu, req->npa_func, BLKTYPE_NPA)) rvu 772 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (!is_pffunc_map_valid(rvu, req->sso_func, BLKTYPE_SSO)) rvu 790 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_lf_reset(rvu, block, nixlf); rvu 792 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", rvu 797 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3); rvu 801 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size); rvu 809 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_BASE(nixlf), rvu 814 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_CFG(nixlf), cfg); rvu 818 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size); rvu 826 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_BASE(nixlf), rvu 829 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_CFG(nixlf), cfg); rvu 833 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size); rvu 841 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_BASE(nixlf), rvu 844 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_CFG(nixlf), cfg); rvu 848 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, rvu 854 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); rvu 857 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size); rvu 861 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf), rvu 863 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_CFG(nixlf), BIT_ULL(36)); rvu 866 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); rvu 869 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size); rvu 873 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf), rvu 875 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_CFG(nixlf), BIT_ULL(36)); rvu 882 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg); rvu 885 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG2(nixlf), BIT_ULL(0)); rvu 894 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf), cfg); rvu 897 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), req->rx_cfg); rvu 900 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_interface_init(rvu, pcifunc, intf, nixlf); rvu 905 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); rvu 910 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_ctx_free(rvu, pfvf); rvu 918 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQ_CONST); rvu 927 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); rvu 931 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); rvu 937 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct msg_req *req, rvu 940 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 946 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 947 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 952 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, block, pcifunc, 0); rvu 956 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_interface_deinit(rvu, pcifunc, nixlf); rvu 959 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_lf_reset(rvu, block, nixlf); rvu 961 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", rvu 966 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_ctx_free(rvu, pfvf); rvu 971 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu, rvu 981 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 982 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 986 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 995 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfg); rvu 997 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "No mark_format_ctl for (pf:%d, vf:%d)", rvu 1009 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_reset_tx_shaping(struct rvu *rvu, int blkaddr, rvu 1036 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, cir_reg); rvu 1037 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, cir_reg, cfg & ~BIT_ULL(0)); rvu 1041 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, pir_reg); rvu 1042 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, pir_reg, cfg & ~BIT_ULL(0)); rvu 1045 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr, rvu 1048 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 1053 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_TL4X_SDP_LINK_CFG(schq), 0x00); rvu 1060 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 1065 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_get_tl1_schqs(struct rvu *rvu, int blkaddr, u16 pcifunc, rvu 1076 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 1080 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 1094 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c schq_base = rvu->cgx_cnt_max * MAX_LMAC_PER_CGX * 2; rvu 1111 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_reset_tx_linkcfg(rvu, blkaddr, rvu 1113 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_reset_tx_shaping(rvu, blkaddr, rvu 1116 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_reset_tx_linkcfg(rvu, blkaddr, rvu 1118 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_reset_tx_shaping(rvu, blkaddr, rvu 1131 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu, rvu 1144 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 1145 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 1149 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 1153 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_lock(&rvu->rsrc_lock); rvu 1166 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_get_tl1_schqs(rvu, blkaddr, rvu 1202 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_get_tl1_schqs(rvu, blkaddr, pcifunc, rvu 1215 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); rvu 1216 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_reset_tx_shaping(rvu, blkaddr, lvl, schq); rvu 1226 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); rvu 1227 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_reset_tx_shaping(rvu, blkaddr, lvl, schq); rvu 1235 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_unlock(&rvu->rsrc_lock); rvu 1239 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_txschq_free(struct rvu *rvu, u16 pcifunc) rvu 1242 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 1247 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 1251 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 1255 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); rvu 1260 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_lock(&rvu->rsrc_lock); rvu 1269 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); rvu 1278 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq)); rvu 1281 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg); rvu 1284 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_poll_reg(rvu, blkaddr, rvu 1287 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, rvu 1308 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_unlock(&rvu->rsrc_lock); rvu 1311 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12) | nixlf); rvu 1312 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_poll_reg(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12), true); rvu 1314 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "NDC-TX sync failed for NIXLF %d\n", nixlf); rvu 1319 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_txschq_free_one(struct rvu *rvu, rvu 1323 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 1330 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 1334 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 1338 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); rvu 1352 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_lock(&rvu->rsrc_lock); rvu 1355 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_unlock(&rvu->rsrc_lock); rvu 1363 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq)); rvu 1366 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg); rvu 1369 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = rvu_poll_reg(rvu, blkaddr, rvu 1372 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, rvu 1380 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_unlock(&rvu->rsrc_lock); rvu 1386 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu, rvu 1391 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c return nix_txschq_free(rvu, req->hdr.pcifunc); rvu 1393 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c return nix_txschq_free_one(rvu, req); rvu 1396 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static bool is_txschq_config_valid(struct rvu *rvu, u16 pcifunc, int blkaddr, rvu 1407 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (!is_valid_txschq(rvu, blkaddr, lvl, pcifunc, schq)) rvu 1413 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL4, pcifunc, parent)) rvu 1418 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL3, pcifunc, parent)) rvu 1423 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL2, pcifunc, parent)) rvu 1428 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL1, pcifunc, parent)) rvu 1435 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_tl1_default_cfg(struct rvu *rvu, u16 pcifunc) rvu 1444 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 1448 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 1454 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_lock(&rvu->rsrc_lock); rvu 1456 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_get_tl1_schqs(rvu, blkaddr, rvu 1473 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); rvu 1476 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); rvu 1479 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); rvu 1485 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_unlock(&rvu->rsrc_lock); rvu 1489 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu, rvu 1494 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 1507 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 1511 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 1515 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); rvu 1527 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c return nix_tl1_default_cfg(rvu, pcifunc); rvu 1535 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (!is_txschq_config_valid(rvu, pcifunc, blkaddr, rvu 1541 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], rvu 1552 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_lock(&rvu->rsrc_lock); rvu 1559 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_unlock(&rvu->rsrc_lock); rvu 1562 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); rvu 1567 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_poll_reg(rvu, blkaddr, rvu 1576 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_rx_vtag_cfg(struct rvu *rvu, int nixlf, int blkaddr, rvu 1589 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 1594 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu, rvu 1598 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 1602 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 1606 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); rvu 1611 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_rx_vtag_cfg(rvu, nixlf, blkaddr, req); rvu 1622 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_setup_mce(struct rvu *rvu, int mce, u8 op, rvu 1643 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_nix_aq_enq_inst(rvu, &aq_req, NULL); rvu 1645 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "Failed to setup Bcast MCE for PF%d:VF%d\n", rvu 1692 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add) rvu 1706 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 1710 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 1717 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); rvu 1722 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, rvu 1751 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_setup_mce(rvu, mce->idx, rvu 1763 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_setup_bcast_tables(struct rvu *rvu, struct nix_hw *nix_hw) rvu 1772 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c for (pf = 1; pf < (rvu->cgx_mapped_pfs + 1); pf++) { rvu 1773 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); rvu 1780 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = &rvu->pf[pf]; rvu 1795 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_setup_mce(rvu, pfvf->bcast_mce_idx + idx, rvu 1805 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) rvu 1808 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 1811 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c size = (rvu_read64(rvu, blkaddr, NIX_AF_CONST3) >> 16) & 0x0F; rvu 1815 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = qmem_alloc(rvu->dev, &mcast->mce_ctx, rvu 1820 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BASE, rvu 1824 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG, rvu 1828 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c size = rvu_read64(rvu, blkaddr, NIX_AF_MC_MIRROR_CONST) & 0xFFFF; rvu 1829 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = qmem_alloc(rvu->dev, &mcast->mcast_buf, rvu 1834 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_BASE, rvu 1840 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_CFG, rvu 1846 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c return nix_setup_bcast_tables(rvu, nix_hw); rvu 1849 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_setup_txschq(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) rvu 1878 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, reg); rvu 1887 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c txsch->pfvf_map = devm_kcalloc(rvu->dev, txsch->schq.max, rvu 1896 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, rvu 1908 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_MARK_FORMATX_CTL(fmt_idx), cfg); rvu 1914 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_af_mark_format_setup(struct rvu *rvu, struct nix_hw *nix_hw, rvu 1931 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c total = (rvu_read64(rvu, blkaddr, NIX_AF_PSE_CONST) & 0xFF00) >> 8; rvu 1933 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw->mark_format.cfg = devm_kcalloc(rvu->dev, total, sizeof(u32), rvu 1938 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfgs[i]); rvu 1940 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "Err %d in setup mark format %d\n", rvu 1947 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req, rvu 1950 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 1955 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 1959 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); rvu 1964 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c stats = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); rvu 1968 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, i), 0); rvu 1972 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, i), 0); rvu 2121 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int reserve_flowkey_alg_idx(struct rvu *rvu, int blkaddr, u32 flow_cfg) rvu 2127 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c hw = get_nix_hw(rvu->hw, blkaddr); rvu 2142 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 2154 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu, rvu 2158 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 2163 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 2167 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); rvu 2171 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 2178 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c alg_idx = reserve_flowkey_alg_idx(rvu, blkaddr, rvu 2184 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_update_flowkey_alg_idx(rvu, pcifunc, nixlf, req->group, rvu 2189 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_rx_flowkey_alg_cfg(struct rvu *rvu, int blkaddr) rvu 2197 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 2204 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); rvu 2211 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); rvu 2217 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); rvu 2223 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); rvu 2230 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); rvu 2237 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); rvu 2244 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); rvu 2251 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); rvu 2258 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, rvu 2262 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 2267 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 2268 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 2272 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); rvu 2278 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, rvu 2281 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_update_rxvlan(rvu, pcifunc, nixlf); rvu 2286 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req, rvu 2290 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 2295 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 2296 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 2300 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); rvu 2312 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf); rvu 2314 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, rvu 2317 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_update_rxvlan(rvu, pcifunc, nixlf); rvu 2322 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_find_link_frs(struct rvu *rvu, rvu 2332 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 2341 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); rvu 2345 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = &rvu->hwvf[hwvf + vf]; rvu 2354 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = &rvu->pf[pf]; rvu 2367 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req, rvu 2370 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 2379 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 2383 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 2399 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_lock(&rvu->rsrc_lock); rvu 2403 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq)); rvu 2407 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg); rvu 2409 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mutex_unlock(&rvu->rsrc_lock); rvu 2421 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (is_pf_cgxmapped(rvu, pf)) { rvu 2423 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac); rvu 2433 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_find_link_frs(rvu, req, pcifunc); rvu 2436 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link)); rvu 2440 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), cfg); rvu 2447 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c CGX_FIFO_LEN / cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); rvu 2448 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_TX_LINKX_NORM_CREDIT(link)); rvu 2451 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg); rvu 2452 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_TX_LINKX_EXPR_CREDIT(link), cfg); rvu 2457 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_rxvlan_alloc(struct rvu *rvu, struct msg_req *req, rvu 2473 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 2481 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, &alloc_req, rvu 2487 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 2493 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr], pcifunc, 0); rvu 2503 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_npc_update_rxvlan(rvu, pcifunc, nixlf); rvu 2511 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_mbox_handler_npc_mcam_free_entry(rvu, &free_req, rsp); rvu 2516 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req, rvu 2519 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 2526 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 2527 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 2532 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nixlf = rvu_get_lf(rvu, block, pcifunc, 0); rvu 2536 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf)); rvu 2553 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), cfg); rvu 2558 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static void nix_link_config(struct rvu *rvu, int blkaddr) rvu 2560 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 2571 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), rvu 2577 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), rvu 2585 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); rvu 2591 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 2594 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 2606 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 2608 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 2613 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr) rvu 2619 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_CFG, rvu 2620 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_read64(rvu, blkaddr, NIX_AF_CFG) | BIT_ULL(9)); rvu 2622 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_poll_reg(rvu, blkaddr, rvu 2625 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "NIX X2P bus calibration failed\n"); rvu 2629 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c status = rvu_read64(rvu, blkaddr, NIX_AF_STATUS); rvu 2631 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c for (idx = 0; idx < rvu->cgx_cnt_max; idx++) { rvu 2633 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (!rvu_cgx_pdata(idx, rvu) || rvu 2636 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, rvu 2643 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, rvu 2649 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_CFG, rvu 2650 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_read64(rvu, blkaddr, NIX_AF_CFG) & ~BIT_ULL(9)); rvu 2652 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, rvu 2659 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_aq_init(struct rvu *rvu, struct rvu_block *block) rvu 2665 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, block->addr, NIX_AF_CFG); rvu 2668 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); rvu 2671 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); rvu 2675 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, block->addr, NIX_AF_NDC_CFG); rvu 2677 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, block->addr, NIX_AF_NDC_CFG, cfg); rvu 2683 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = rvu_aq_alloc(rvu, &block->aq, rvu 2689 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, block->addr, NIX_AF_AQ_CFG, AQ_SIZE); rvu 2690 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, block->addr, rvu 2695 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_nix_init(struct rvu *rvu) rvu 2697 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 2702 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0); rvu 2711 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (is_rvu_9xxx_A0(rvu)) rvu 2712 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_CFG, rvu 2713 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_read64(rvu, blkaddr, NIX_AF_CFG) | 0x5EULL); rvu 2716 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_calibrate_x2p(rvu, blkaddr); rvu 2721 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); rvu 2729 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_aq_init(rvu, block); rvu 2734 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_CINT_DELAY, 0x0ULL); rvu 2737 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c hw->nix0 = devm_kzalloc(rvu->dev, rvu 2742 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_setup_txschq(rvu, hw->nix0, blkaddr); rvu 2746 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_af_mark_format_setup(rvu, hw->nix0, blkaddr); rvu 2750 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_setup_mcast(rvu, hw->nix0, blkaddr); rvu 2755 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_setup_lso(rvu, hw->nix0, blkaddr); rvu 2761 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OL2, rvu 2763 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4, rvu 2765 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4, rvu 2767 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6, rvu 2769 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6, rvu 2771 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OTCP, rvu 2773 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ITCP, rvu 2775 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OUDP, rvu 2777 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IUDP, rvu 2779 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OSCTP, rvu 2781 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ISCTP, rvu 2785 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_rx_flowkey_alg_cfg(rvu, blkaddr); rvu 2790 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_link_config(rvu, blkaddr); rvu 2795 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c void rvu_nix_freemem(struct rvu *rvu) rvu 2797 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 2804 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0); rvu 2809 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_aq_free(rvu, block->aq); rvu 2812 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 2822 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c qmem_free(rvu->dev, mcast->mce_ctx); rvu 2823 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c qmem_free(rvu->dev, mcast->mcast_buf); rvu 2828 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c static int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf) rvu 2830 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 2831 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_hwinfo *hw = rvu->hw; rvu 2834 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 2838 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c *nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); rvu 2845 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req, rvu 2851 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_get_nixlf(rvu, pcifunc, &nixlf); rvu 2855 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_enable_default_entries(rvu, pcifunc, nixlf); rvu 2859 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req, rvu 2865 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_get_nixlf(rvu, pcifunc, &nixlf); rvu 2869 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); rvu 2873 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int nixlf) rvu 2875 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 2882 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_interface_deinit(rvu, pcifunc, nixlf); rvu 2883 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_rx_sync(rvu, blkaddr); rvu 2884 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_txschq_free(rvu, pcifunc); rvu 2888 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_lf_hwctx_disable(rvu, &ctx_req); rvu 2890 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "SQ ctx disable failed\n"); rvu 2895 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_lf_hwctx_disable(rvu, &ctx_req); rvu 2897 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "RQ ctx disable failed\n"); rvu 2902 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c err = nix_lf_hwctx_disable(rvu, &ctx_req); rvu 2904 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c dev_err(rvu->dev, "CQ ctx disable failed\n"); rvu 2907 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_ctx_free(rvu, pfvf); rvu 2910 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu, rvu 2920 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 2921 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); rvu 2925 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c nix_hw = get_nix_hw(rvu->hw, blkaddr); rvu 2932 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = rvu_read64(rvu, blkaddr, rvu 2954 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, rvu 18 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c static int npa_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, rvu 29 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c reg = rvu_read64(rvu, block->addr, NPA_AF_AQ_STATUS); rvu 39 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, block->addr, NPA_AF_AQ_DOOR, 1); rvu 55 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c static int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, rvu 58 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c struct rvu_hwinfo *hw = rvu->hw; rvu 68 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 72 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); rvu 79 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c dev_warn(rvu->dev, "%s: NPA AQ not initialized\n", __func__); rvu 83 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c npalf = rvu_get_lf(rvu, block, pcifunc, 0); rvu 147 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rc = npa_aq_enqueue_wait(rvu, block, &inst); rvu 199 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c static int npa_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req) rvu 201 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); rvu 232 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rc = rvu_npa_aq_enq_inst(rvu, &aq_req, NULL); rvu 235 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c dev_err(rvu->dev, "Failed to disable %s:%d context\n", rvu 244 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c int rvu_mbox_handler_npa_aq_enq(struct rvu *rvu, rvu 248 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c return rvu_npa_aq_enq_inst(rvu, req, rsp); rvu 251 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c int rvu_mbox_handler_npa_hwctx_disable(struct rvu *rvu, rvu 255 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c return npa_lf_hwctx_disable(rvu, req); rvu 258 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c static void npa_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf) rvu 263 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c qmem_free(rvu->dev, pfvf->aura_ctx); rvu 269 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c qmem_free(rvu->dev, pfvf->pool_ctx); rvu 272 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c qmem_free(rvu->dev, pfvf->npa_qints_ctx); rvu 276 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu, rvu 281 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c struct rvu_hwinfo *hw = rvu->hw; rvu 292 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 293 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); rvu 298 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c npalf = rvu_get_lf(rvu, block, pcifunc, 0); rvu 303 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c err = rvu_lf_reset(rvu, block, npalf); rvu 305 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c dev_err(rvu->dev, "Failed to reset NPALF%d\n", npalf); rvu 309 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c ctx_cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST1); rvu 313 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c err = qmem_alloc(rvu->dev, &pfvf->aura_ctx, rvu 325 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c err = qmem_alloc(rvu->dev, &pfvf->pool_ctx, req->nr_pools, hwctx_size); rvu 335 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST); rvu 340 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c err = qmem_alloc(rvu->dev, &pfvf->npa_qints_ctx, qints, hwctx_size); rvu 344 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c cfg = rvu_read64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf)); rvu 349 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf), cfg); rvu 352 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, blkaddr, NPA_AF_LFX_LOC_AURAS_BASE(npalf), rvu 356 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_CFG(npalf), BIT_ULL(36)); rvu 357 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_BASE(npalf), rvu 363 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c npa_ctx_free(rvu, pfvf); rvu 368 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST); rvu 375 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req, rvu 378 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c struct rvu_hwinfo *hw = rvu->hw; rvu 385 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 386 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); rvu 391 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c npalf = rvu_get_lf(rvu, block, pcifunc, 0); rvu 396 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c err = rvu_lf_reset(rvu, block, npalf); rvu 398 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c dev_err(rvu->dev, "Failed to reset NPALF%d\n", npalf); rvu 402 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c npa_ctx_free(rvu, pfvf); rvu 407 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c static int npa_aq_init(struct rvu *rvu, struct rvu_block *block) rvu 413 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c cfg = rvu_read64(rvu, block->addr, NPA_AF_GEN_CFG); rvu 416 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); rvu 419 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); rvu 423 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG); rvu 425 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg); rvu 431 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c err = rvu_aq_alloc(rvu, &block->aq, rvu 437 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, block->addr, NPA_AF_AQ_CFG, AQ_SIZE); rvu 438 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_write64(rvu, block->addr, rvu 443 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c int rvu_npa_init(struct rvu *rvu) rvu 445 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c struct rvu_hwinfo *hw = rvu->hw; rvu 448 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); rvu 453 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c err = npa_aq_init(rvu, &hw->block[blkaddr]); rvu 460 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c void rvu_npa_freemem(struct rvu *rvu) rvu 462 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c struct rvu_hwinfo *hw = rvu->hw; rvu 466 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); rvu 471 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c rvu_aq_free(rvu, block->aq); rvu 474 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf) rvu 476 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 482 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c npa_lf_hwctx_disable(rvu, &ctx_req); rvu 486 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c npa_lf_hwctx_disable(rvu, &ctx_req); rvu 488 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c npa_ctx_free(rvu, pfvf); rvu 31 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, rvu 33 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, rvu 36 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf) rvu 41 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 47 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); rvu 50 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_npc_get_pkind(struct rvu *rvu, u16 pf) rvu 52 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_pkind *pkind = &rvu->hw->pkind; rvu 98 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, rvu 105 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); rvu 109 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, rvu 117 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 202 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, rvu 222 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 225 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 231 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 233 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 237 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 239 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 244 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 248 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank), rvu 253 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true); rvu 255 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false); rvu 258 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, rvu 274 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8)); rvu 275 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg); rvu 280 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = rvu_read64(rvu, blkaddr, rvu 282 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 286 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = rvu_read64(rvu, blkaddr, rvu 288 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 292 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = rvu_read64(rvu, blkaddr, rvu 294 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 298 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, rvu 304 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c return rvu_read64(rvu, blkaddr, rvu 308 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, rvu 311 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 312 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 322 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 343 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) { rvu 344 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c *(u64 *)&action = npc_get_mcam_action(rvu, mcam, rvu 353 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_mcam_entry(rvu, mcam, blkaddr, index, rvu 368 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, rvu 371 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 380 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 402 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx)) rvu 403 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c *(u64 *)&action = npc_get_mcam_action(rvu, mcam, rvu 413 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_mcam_entry(rvu, mcam, blkaddr, index, rvu 417 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_enadis_promisc_entry(struct rvu *rvu, u16 pcifunc, rvu 420 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 423 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 433 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); rvu 436 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf) rvu 438 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enadis_promisc_entry(rvu, pcifunc, nixlf, false); rvu 441 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf) rvu 443 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enadis_promisc_entry(rvu, pcifunc, nixlf, true); rvu 446 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, rvu 449 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 457 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 465 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); rvu 509 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_mcam_entry(rvu, mcam, blkaddr, index, rvu 513 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, rvu 516 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 520 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 541 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c *(u64 *)&action = rvu_read64(rvu, blkaddr, rvu 552 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 561 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) { rvu 565 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 570 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_npc_update_rxvlan(rvu, pcifunc, nixlf); rvu 573 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc, rvu 576 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 580 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 587 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); rvu 601 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c *(u64 *)&action = rvu_read64(rvu, blkaddr, rvu 604 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, rvu 607 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf); rvu 609 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf); rvu 611 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_npc_update_rxvlan(rvu, pcifunc, nixlf); rvu 614 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) rvu 616 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enadis_default_entries(rvu, pcifunc, nixlf, false); rvu 619 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) rvu 621 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enadis_default_entries(rvu, pcifunc, nixlf, true); rvu 624 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) rvu 626 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 629 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 636 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); rvu 639 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_mcam_free_all_counters(rvu, mcam, pcifunc); rvu 643 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); rvu 647 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, \ rvu 651 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, \ rvu 658 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_config_ldata_extract(struct rvu *rvu, int blkaddr) rvu 660 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 665 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST); rvu 735 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr, rvu 740 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX), rvu 742 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX), rvu 746 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld), rvu 780 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr) rvu 782 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c const char *mkex_profile = rvu->mkex_pfl_name; rvu 783 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct device *dev = &rvu->pdev->dev; rvu 813 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c if (is_rvu_9xxx_A0(rvu) && rvu 819 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_program_mkex_profile(rvu, blkaddr, mcam_kex); rvu 828 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu->mkex_pfl_name); rvu 831 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c dev_info(rvu->dev, "Using default mkex profile\n"); rvu 833 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_ldata_extract(rvu, blkaddr); rvu 840 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_config_kpuaction(struct rvu *rvu, int blkaddr, rvu 859 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1); rvu 879 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0); rvu 882 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_config_kpucam(struct rvu *rvu, int blkaddr, rvu 899 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 901 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 910 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu, rvu 916 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c dev_err(rvu->dev, rvu 921 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c max_entries = rvu_read64(rvu, blkaddr, NPC_AF_CONST1) & 0xFFF; rvu 926 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_kpucam(rvu, blkaddr, rvu 932 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_kpuaction(rvu, blkaddr, &profile->action[entry], rvu 937 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 940 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 946 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01); rvu 949 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_parser_profile_init(struct rvu *rvu, int blkaddr) rvu 951 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct rvu_hwinfo *hw = rvu->hw; rvu 956 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c hw->npc_kpus = (rvu_read64(rvu, blkaddr, NPC_AF_CONST) >> 8) & 0x1F; rvu 960 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 962 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 964 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00); rvu 976 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_kpuaction(rvu, blkaddr, rvu 984 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_program_kpu_profile(rvu, blkaddr, rvu 988 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr) rvu 990 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int nixlf_count = rvu_get_nixlf_count(rvu); rvu 991 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 996 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST); rvu 1002 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = (rvu_read64(rvu, blkaddr, rvu 1023 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF); rvu 1025 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c dev_warn(rvu->dev, rvu 1036 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries), rvu 1041 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c mcam->bmap_reverse = devm_kcalloc(rvu->dev, rvu 1050 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries, rvu 1074 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max, rvu 1082 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries, rvu 1087 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max, rvu 1101 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_npc_init(struct rvu *rvu) rvu 1103 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_pkind *pkind = &rvu->hw->pkind; rvu 1108 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 1110 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); rvu 1115 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST); rvu 1118 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 1123 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c pkind->rsrc.max = (rvu_read64(rvu, blkaddr, rvu 1130 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max, rvu 1136 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_parser_profile_init(rvu, blkaddr); rvu 1139 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2, rvu 1141 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4, rvu 1145 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4, rvu 1154 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG, rvu 1155 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) | rvu 1163 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX), rvu 1168 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c if (!is_rvu_9xxx_A0(rvu)) rvu 1170 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX), rvu 1173 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c err = npc_mcam_rsrcs_init(rvu, blkaddr); rvu 1178 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_load_mkex_profile(rvu, blkaddr); rvu 1183 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_TX), rvu 1187 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_RX), rvu 1193 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c void rvu_npc_freemem(struct rvu *rvu) rvu 1195 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_pkind *pkind = &rvu->hw->pkind; rvu 1196 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1233 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam, rvu 1243 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 1248 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu, rvu 1259 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, rvu 1295 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, rvu 1307 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); rvu 1312 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_unmap_mcam_entry_and_cntr(rvu, mcam, rvu 1319 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, rvu 1634 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, rvu 1638 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1642 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 1668 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c if (!is_nixlf_attached(rvu, pcifunc)) rvu 1674 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu, rvu 1678 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1683 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 1688 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c if (!is_nixlf_attached(rvu, pcifunc)) rvu 1702 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); rvu 1707 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, rvu 1714 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); rvu 1720 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu, rvu 1724 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1728 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 1748 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, req->intf, rvu 1752 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, rvu 1761 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu, rvu 1765 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1769 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 1779 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true); rvu 1784 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu, rvu 1788 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1792 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 1802 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); rvu 1807 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu, rvu 1811 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1817 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 1847 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false); rvu 1850 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry); rvu 1855 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, rvu 1857 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, rvu 1862 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true); rvu 1863 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false); rvu 1876 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, rvu 1880 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1885 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 1890 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c if (!is_nixlf_attached(rvu, pcifunc)) rvu 1940 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, rvu 1943 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1947 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 1974 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, rvu 1982 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, rvu 1985 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 1989 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 2003 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, rvu 2020 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, rvu 2028 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu, rvu 2031 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 2034 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 2044 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00); rvu 2049 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu, rvu 2053 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 2056 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 2066 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr)); rvu 2072 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu, rvu 2080 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 2085 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 2099 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, rvu 2117 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); rvu 2131 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_mcam_entry(rvu, mcam, blkaddr, entry, req->intf, rvu 2135 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr); rvu 2145 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf)) rvu 2148 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld)) rvu 2151 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_read64(rvu, BLKADDR_NPC, \ rvu 2155 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_read64(rvu, BLKADDR_NPC, \ rvu 2158 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req, rvu 2186 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN); rvu 2190 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf) rvu 2192 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); rvu 2193 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c struct npc_mcam *mcam = &rvu->hw->mcam; rvu 2197 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); rvu 2206 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c pfvf->entry.action = npc_get_mcam_action(rvu, mcam, blkaddr, index); rvu 2207 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, index); rvu 2208 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c npc_config_mcam_entry(rvu, mcam, blkaddr, pfvf->rxvlan_index,