CSR 59 arch/arm/mach-omap1/dma.c [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT }, CSR 219 arch/arm/mach-omap1/dma.c l = dma_read(CSR, lch); CSR 60 arch/arm/mach-omap2/dma.c [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT }, CSR 491 arch/arm/plat-omap/dma.c p->dma_read(CSR, lch); CSR 493 arch/arm/plat-omap/dma.c p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); CSR 505 arch/arm/plat-omap/dma.c p->dma_read(CSR, lch); CSR 507 arch/arm/plat-omap/dma.c p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); CSR 1091 arch/arm/plat-omap/dma.c csr = p->dma_read(CSR, ch); CSR 1143 arch/arm/plat-omap/dma.c u32 status = p->dma_read(CSR, ch); CSR 1179 arch/arm/plat-omap/dma.c p->dma_write(status, CSR, ch); CSR 1198 arch/arm/plat-omap/dma.c status = p->dma_read(CSR, ch); CSR 1199 arch/arm/plat-omap/dma.c p->dma_write(status, CSR, ch); CSR 113 arch/c6x/kernel/setup.c csr = get_creg(CSR); CSR 364 drivers/dma/ti/omap-dma.c omap_dma_chan_read(c, CSR); CSR 366 drivers/dma/ti/omap-dma.c omap_dma_chan_write(c, CSR, ~0); CSR 371 drivers/dma/ti/omap-dma.c unsigned val = omap_dma_chan_read(c, CSR); CSR 374 drivers/dma/ti/omap-dma.c omap_dma_chan_write(c, CSR, val); CSR 296 drivers/dma/txx9dmac.c channel64_readl(dc, CSR)); CSR 308 drivers/dma/txx9dmac.c channel32_readl(dc, CSR)); CSR 339 drivers/dma/txx9dmac.c if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { CSR 349 drivers/dma/txx9dmac.c channel64_writel(dc, CSR, 0xffffffff); CSR 370 drivers/dma/txx9dmac.c channel32_writel(dc, CSR, 0xffffffff); CSR 480 drivers/dma/txx9dmac.c desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); CSR 493 drivers/dma/txx9dmac.c d->SAIR, d->DAIR, d->CCR, d->CSR); CSR 519 drivers/dma/txx9dmac.c channel_writel(dc, CSR, errors); CSR 545 drivers/dma/txx9dmac.c csr = channel64_readl(dc, CSR); CSR 546 drivers/dma/txx9dmac.c channel64_writel(dc, CSR, csr); CSR 549 drivers/dma/txx9dmac.c csr = channel32_readl(dc, CSR); CSR 550 drivers/dma/txx9dmac.c channel32_writel(dc, CSR, csr); CSR 611 drivers/dma/txx9dmac.c csr = channel_readl(dc, CSR); CSR 629 drivers/dma/txx9dmac.c channel_readl(dc, CSR)); CSR 656 drivers/dma/txx9dmac.c csr = channel_readl(dc, CSR); CSR 953 drivers/dma/txx9dmac.c if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) && CSR 994 drivers/dma/txx9dmac.c if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { CSR 1056 drivers/dma/txx9dmac.c BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT); CSR 78 drivers/dma/txx9dmac.h TXX9_DMA_REG32(CSR); /* Channel Status Register */ CSR 88 drivers/dma/txx9dmac.h u32 CSR; CSR 78 drivers/net/ethernet/renesas/ravb_main.c error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); CSR 671 drivers/net/ethernet/renesas/ravb_main.c error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, CSR 680 drivers/net/ethernet/renesas/ravb_main.c error = ravb_wait(ndev, CSR, CSR_RPO, 0); CSR 1080 drivers/scsi/aacraid/aacraid.h #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) CSR 1081 drivers/scsi/aacraid/aacraid.h #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) CSR 1082 drivers/scsi/aacraid/aacraid.h #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) CSR 1083 drivers/scsi/aacraid/aacraid.h #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) CSR 1142 drivers/scsi/aacraid/aacraid.h #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) CSR 1143 drivers/scsi/aacraid/aacraid.h #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) CSR 1144 drivers/scsi/aacraid/aacraid.h #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) CSR 1145 drivers/scsi/aacraid/aacraid.h #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) CSR 1160 drivers/scsi/aacraid/aacraid.h #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) CSR 1161 drivers/scsi/aacraid/aacraid.h #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) CSR 1162 drivers/scsi/aacraid/aacraid.h #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR)) CSR 1163 drivers/scsi/aacraid/aacraid.h #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR)) CSR 1208 drivers/scsi/aacraid/aacraid.h #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR)) CSR 1209 drivers/scsi/aacraid/aacraid.h #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR)) CSR 1210 drivers/scsi/aacraid/aacraid.h #define src_writeb(AEP, CSR, value) writeb(value, \ CSR 1211 drivers/scsi/aacraid/aacraid.h &((AEP)->regs.src.bar0->CSR)) CSR 1212 drivers/scsi/aacraid/aacraid.h #define src_writel(AEP, CSR, value) writel(value, \ CSR 1213 drivers/scsi/aacraid/aacraid.h &((AEP)->regs.src.bar0->CSR)) CSR 1215 drivers/scsi/aacraid/aacraid.h #define src_writeq(AEP, CSR, value) writeq(value, \ CSR 1216 drivers/scsi/aacraid/aacraid.h &((AEP)->regs.src.bar0->CSR)) CSR 294 drivers/spi/spi-at91-usart.c aus->status = at91_usart_spi_readl(aus, CSR); CSR 1471 drivers/staging/qlge/qlge_dbg.c DUMP_REG(qdev, CSR); CSR 9 drivers/staging/qlge/qlge_mpi.c tmp = ql_read32(qdev, CSR); CSR 13 drivers/staging/qlge/qlge_mpi.c ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); CSR 23 drivers/staging/qlge/qlge_mpi.c ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE); CSR 25 drivers/staging/qlge/qlge_mpi.c tmp = ql_read32(qdev, CSR); CSR 40 drivers/staging/qlge/qlge_mpi.c ql_write32(qdev, CSR, CSR_CMD_SET_RST); CSR 42 drivers/staging/qlge/qlge_mpi.c tmp = ql_read32(qdev, CSR); CSR 44 drivers/staging/qlge/qlge_mpi.c ql_write32(qdev, CSR, CSR_CMD_CLR_RST); CSR 175 drivers/staging/qlge/qlge_mpi.c if (ql_read32(qdev, CSR) & CSR_HRI) CSR 194 drivers/staging/qlge/qlge_mpi.c ql_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); CSR 516 drivers/staging/qlge/qlge_mpi.c ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); CSR 596 drivers/staging/qlge/qlge_mpi.c ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);