rt_sysc_r32       135 arch/mips/include/asm/mach-ralink/mt7620.h 	return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
rt_sysc_r32        47 arch/mips/include/asm/mach-ralink/ralink_regs.h 	u32 val = rt_sysc_r32(reg) & ~clr;
rt_sysc_r32       242 arch/mips/pci/pci-mt7620.c 	if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
rt_sysc_r32       312 arch/mips/pci/pci-rt3883.c 	rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
rt_sysc_r32       313 arch/mips/pci/pci-rt3883.c 	syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
rt_sysc_r32       314 arch/mips/pci/pci-rt3883.c 	clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
rt_sysc_r32       325 arch/mips/pci/pci-rt3883.c 		t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
rt_sysc_r32       329 arch/mips/pci/pci-rt3883.c 		t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
rt_sysc_r32       333 arch/mips/pci/pci-rt3883.c 		t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
rt_sysc_r32       337 arch/mips/pci/pci-rt3883.c 		t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
rt_sysc_r32       387 arch/mips/pci/pci-rt3883.c 			t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
rt_sysc_r32       394 arch/mips/pci/pci-rt3883.c 			t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
rt_sysc_r32       398 arch/mips/pci/pci-rt3883.c 			t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
rt_sysc_r32       386 arch/mips/ralink/mt7620.c 	reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
rt_sysc_r32       398 arch/mips/ralink/mt7620.c 	reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
rt_sysc_r32       414 arch/mips/ralink/mt7620.c 	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
rt_sysc_r32       440 arch/mips/ralink/mt7620.c 	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
rt_sysc_r32       457 arch/mips/ralink/mt7620.c 	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
rt_sysc_r32       490 arch/mips/ralink/mt7620.c 	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
rt_sysc_r32       578 arch/mips/ralink/mt7620.c 		u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
rt_sysc_r32       125 arch/mips/ralink/mt7621.c 	if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
rt_sysc_r32       130 arch/mips/ralink/mt7621.c 		clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
rt_sysc_r32       137 arch/mips/ralink/mt7621.c 		fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
rt_sysc_r32       138 arch/mips/ralink/mt7621.c 		syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
rt_sysc_r32        33 arch/mips/ralink/reset.c 	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
rt_sysc_r32        48 arch/mips/ralink/reset.c 	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
rt_sysc_r32        43 arch/mips/ralink/rt288x.c 	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
rt_sysc_r32       135 arch/mips/ralink/rt305x.c 	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
rt_sysc_r32       188 arch/mips/ralink/rt305x.c 		u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
rt_sysc_r32        70 arch/mips/ralink/rt3883.c 	syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
rt_sysc_r32       140 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c 	u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
rt_sysc_r32       141 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c 	mode = rt_sysc_r32(reg);
rt_sysc_r32       100 drivers/watchdog/mt7621_wdt.c 	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
rt_sysc_r32       114 drivers/watchdog/rt2880_wdt.c 	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)